2016-06-10 03:59:01 +03:00
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/*
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* sPAPR CPU core device, acts as container of CPU thread devices.
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*
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* Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw/cpu/core.h"
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#include "hw/ppc/spapr_cpu_core.h"
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#include "target-ppc/cpu.h"
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#include "hw/ppc/spapr.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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2016-06-22 20:11:19 +03:00
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#include "sysemu/cpus.h"
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2016-06-10 03:59:01 +03:00
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#include "target-ppc/kvm_ppc.h"
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2016-06-10 03:59:02 +03:00
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#include "hw/ppc/ppc.h"
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#include "target-ppc/mmu-hash64.h"
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2016-06-22 20:11:19 +03:00
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#include "sysemu/numa.h"
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2016-06-10 03:59:02 +03:00
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static void spapr_cpu_reset(void *opaque)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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PowerPCCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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cpu_reset(cs);
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/* All CPUs start halted. CPU0 is unhalted from the machine level
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* reset code and the rest are explicitly started up by the guest
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* using an RTAS call */
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cs->halted = 1;
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env->spr[SPR_HIOR] = 0;
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ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
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&error_fatal);
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}
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2016-06-10 03:59:05 +03:00
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static void spapr_cpu_destroy(PowerPCCPU *cpu)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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2016-06-28 22:05:15 +03:00
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xics_cpu_destroy(spapr->xics, cpu);
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2016-06-10 03:59:05 +03:00
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qemu_unregister_reset(spapr_cpu_reset, cpu);
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}
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2016-06-10 03:59:02 +03:00
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void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
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{
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CPUPPCState *env = &cpu->env;
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2016-06-10 03:59:04 +03:00
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CPUState *cs = CPU(cpu);
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int i;
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2016-06-10 03:59:02 +03:00
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
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/* Enable PAPR mode in TCG or KVM */
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cpu_ppc_set_papr(cpu);
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if (cpu->max_compat) {
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Error *local_err = NULL;
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ppc_set_compat(cpu, cpu->max_compat, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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2016-06-10 03:59:04 +03:00
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/* Set NUMA node for the added CPUs */
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2016-10-05 18:51:23 +03:00
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i = numa_get_node_for_cpu(cs->cpu_index);
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if (i < nb_numa_nodes) {
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2016-06-10 03:59:04 +03:00
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cs->numa_node = i;
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}
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2016-06-28 22:05:15 +03:00
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xics_cpu_setup(spapr->xics, cpu);
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2016-06-10 03:59:02 +03:00
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qemu_register_reset(spapr_cpu_reset, cpu);
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2016-06-10 03:59:04 +03:00
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spapr_cpu_reset(cpu);
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2016-06-10 03:59:02 +03:00
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}
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2016-06-10 03:59:01 +03:00
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2016-06-10 03:59:03 +03:00
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/*
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* Return the sPAPR CPU core type for @model which essentially is the CPU
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* model specified with -cpu cmdline option.
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*/
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char *spapr_get_cpu_core_type(const char *model)
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{
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char *core_type;
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gchar **model_pieces = g_strsplit(model, ",", 2);
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core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE);
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2016-08-09 19:59:59 +03:00
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/* Check whether it exists or whether we have to look up an alias name */
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if (!object_class_by_name(core_type)) {
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const char *realmodel;
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g_free(core_type);
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2016-10-03 15:13:20 +03:00
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core_type = NULL;
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realmodel = ppc_cpu_lookup_alias(model_pieces[0]);
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2016-08-09 19:59:59 +03:00
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if (realmodel) {
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2016-10-03 15:13:20 +03:00
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core_type = spapr_get_cpu_core_type(realmodel);
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2016-08-09 19:59:59 +03:00
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}
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}
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2016-10-03 15:13:20 +03:00
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g_strfreev(model_pieces);
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2016-06-10 03:59:03 +03:00
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return core_type;
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}
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2016-06-10 03:59:05 +03:00
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static void spapr_core_release(DeviceState *dev, void *opaque)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
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2016-09-12 10:57:20 +03:00
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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const char *typename = object_class_get_name(scc->cpu_class);
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2016-06-10 03:59:05 +03:00
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size_t size = object_type_get_instance_size(typename);
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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CPUCore *cc = CPU_CORE(dev);
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int i;
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for (i = 0; i < cc->nr_threads; i++) {
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void *obj = sc->threads + i * size;
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DeviceState *dev = DEVICE(obj);
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CPUState *cs = CPU(dev);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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spapr_cpu_destroy(cpu);
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cpu_remove_sync(cs);
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object_unparent(obj);
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}
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2016-07-22 14:10:36 +03:00
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spapr->cores[cc->core_id / smp_threads] = NULL;
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2016-06-10 03:59:05 +03:00
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2016-06-29 23:50:45 +03:00
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g_free(sc->threads);
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2016-06-10 03:59:05 +03:00
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object_unparent(OBJECT(dev));
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}
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void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp)
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{
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2016-07-08 16:12:07 +03:00
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CPUCore *cc = CPU_CORE(dev);
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2016-07-22 14:10:36 +03:00
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int smt = kvmppc_smt_threads();
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int index = cc->core_id / smp_threads;
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2016-06-10 03:59:05 +03:00
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sPAPRDRConnector *drc =
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2016-07-22 14:10:36 +03:00
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spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
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2016-06-10 03:59:05 +03:00
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sPAPRDRConnectorClass *drck;
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Error *local_err = NULL;
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2016-07-27 08:14:42 +03:00
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if (index == 0) {
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error_setg(errp, "Boot CPU core may not be unplugged");
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return;
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}
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2016-06-10 03:59:05 +03:00
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g_assert(drc);
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drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
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drck->detach(drc, dev, spapr_core_release, NULL, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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spapr_hotplug_req_remove_by_index(drc);
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}
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2016-06-10 03:59:04 +03:00
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void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp)
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{
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sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
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sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
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CPUCore *cc = CPU_CORE(dev);
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CPUState *cs = CPU(core->threads);
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sPAPRDRConnector *drc;
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sPAPRDRConnectorClass *drck;
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Error *local_err = NULL;
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void *fdt = NULL;
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int fdt_offset = 0;
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2016-07-22 14:10:36 +03:00
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int index = cc->core_id / smp_threads;
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2016-06-10 03:59:04 +03:00
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int smt = kvmppc_smt_threads();
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2016-07-22 14:10:36 +03:00
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drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
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2016-06-10 03:59:04 +03:00
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spapr->cores[index] = OBJECT(dev);
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g_assert(drc);
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/*
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* Setup CPU DT entries only for hotplugged CPUs. For boot time or
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2016-10-25 03:51:33 +03:00
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* coldplugged CPUs DT entries are setup in spapr_build_fdt().
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2016-06-10 03:59:04 +03:00
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*/
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if (dev->hotplugged) {
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fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
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}
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drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
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drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
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if (local_err) {
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g_free(fdt);
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spapr->cores[index] = NULL;
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error_propagate(errp, local_err);
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return;
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}
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if (dev->hotplugged) {
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/*
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* Send hotplug notification interrupt to the guest only in case
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* of hotplugged CPUs.
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*/
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spapr_hotplug_req_add_by_index(drc);
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} else {
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/*
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* Set the right DRC states for cold plugged CPU.
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*/
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drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
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drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
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}
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}
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2016-06-10 03:59:03 +03:00
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void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp)
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{
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MachineState *machine = MACHINE(OBJECT(hotplug_dev));
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2016-08-05 09:25:33 +03:00
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MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
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2016-06-10 03:59:03 +03:00
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sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
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int spapr_max_cores = max_cpus / smp_threads;
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2016-07-26 06:37:20 +03:00
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int index;
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2016-06-10 03:59:03 +03:00
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Error *local_err = NULL;
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CPUCore *cc = CPU_CORE(dev);
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char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
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const char *type = object_get_typename(OBJECT(dev));
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2016-08-05 09:25:33 +03:00
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if (!mc->query_hotpluggable_cpus) {
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2016-08-03 06:08:23 +03:00
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error_setg(&local_err, "CPU hotplug not supported for this machine");
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2016-06-10 03:59:03 +03:00
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goto out;
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}
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2016-08-03 06:08:23 +03:00
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if (strcmp(base_core_type, type)) {
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error_setg(&local_err, "CPU core type should be %s", base_core_type);
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2016-06-10 03:59:04 +03:00
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goto out;
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}
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2016-06-10 03:59:03 +03:00
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if (cc->nr_threads != smp_threads) {
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error_setg(&local_err, "threads must be %d", smp_threads);
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goto out;
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}
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2016-07-22 14:10:36 +03:00
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if (cc->core_id % smp_threads) {
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2016-08-03 14:37:51 +03:00
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error_setg(&local_err, "invalid core id %d", cc->core_id);
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2016-06-10 03:59:03 +03:00
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goto out;
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}
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2016-07-22 14:10:36 +03:00
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index = cc->core_id / smp_threads;
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2016-06-10 03:59:03 +03:00
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if (index < 0 || index >= spapr_max_cores) {
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error_setg(&local_err, "core id %d out of range", cc->core_id);
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goto out;
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}
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if (spapr->cores[index]) {
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error_setg(&local_err, "core %d already populated", cc->core_id);
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goto out;
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}
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out:
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g_free(base_core_type);
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error_propagate(errp, local_err);
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}
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2016-07-01 08:14:39 +03:00
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static void spapr_cpu_core_realize_child(Object *child, Error **errp)
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2016-06-10 03:59:01 +03:00
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{
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2016-07-01 08:14:39 +03:00
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Error *local_err = NULL;
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2016-06-10 03:59:01 +03:00
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sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
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CPUState *cs = CPU(child);
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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2016-06-29 23:50:32 +03:00
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object_property_set_bool(child, true, "realized", &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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2016-07-01 08:14:39 +03:00
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return;
|
2016-06-10 03:59:01 +03:00
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}
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2016-06-29 23:50:32 +03:00
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spapr_cpu_init(spapr, cpu, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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2016-07-01 08:14:39 +03:00
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return;
|
2016-06-10 03:59:01 +03:00
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}
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}
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static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
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{
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sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
|
2016-09-12 10:57:20 +03:00
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sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev));
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2016-06-10 03:59:01 +03:00
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CPUCore *cc = CPU_CORE(OBJECT(dev));
|
2016-09-12 10:57:20 +03:00
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const char *typename = object_class_get_name(scc->cpu_class);
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2016-06-10 03:59:01 +03:00
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size_t size = object_type_get_instance_size(typename);
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Error *local_err = NULL;
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2016-07-01 08:14:39 +03:00
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void *obj;
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int i, j;
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2016-06-10 03:59:01 +03:00
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sc->threads = g_malloc0(size * cc->nr_threads);
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for (i = 0; i < cc->nr_threads; i++) {
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|
|
char id[32];
|
2016-07-21 18:54:37 +03:00
|
|
|
CPUState *cs;
|
|
|
|
|
2016-07-01 08:14:39 +03:00
|
|
|
obj = sc->threads + i * size;
|
2016-06-10 03:59:01 +03:00
|
|
|
|
|
|
|
object_initialize(obj, size, typename);
|
2016-07-21 18:54:37 +03:00
|
|
|
cs = CPU(obj);
|
|
|
|
cs->cpu_index = cc->core_id + i;
|
2016-06-10 03:59:01 +03:00
|
|
|
snprintf(id, sizeof(id), "thread[%d]", i);
|
|
|
|
object_property_add_child(OBJECT(sc), id, obj, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
goto err;
|
|
|
|
}
|
2016-06-29 23:50:20 +03:00
|
|
|
object_unref(obj);
|
2016-06-10 03:59:01 +03:00
|
|
|
}
|
2016-07-01 08:14:39 +03:00
|
|
|
|
|
|
|
for (j = 0; j < cc->nr_threads; j++) {
|
|
|
|
obj = sc->threads + j * size;
|
|
|
|
|
|
|
|
spapr_cpu_core_realize_child(obj, &local_err);
|
|
|
|
if (local_err) {
|
|
|
|
goto err;
|
|
|
|
}
|
2016-06-10 03:59:01 +03:00
|
|
|
}
|
2016-07-01 08:14:39 +03:00
|
|
|
return;
|
2016-06-10 03:59:01 +03:00
|
|
|
|
|
|
|
err:
|
2016-06-27 19:28:15 +03:00
|
|
|
while (--i >= 0) {
|
2016-06-10 03:59:01 +03:00
|
|
|
obj = sc->threads + i * size;
|
|
|
|
object_unparent(obj);
|
|
|
|
}
|
|
|
|
g_free(sc->threads);
|
|
|
|
error_propagate(errp, local_err);
|
|
|
|
}
|
|
|
|
|
2016-09-12 10:57:20 +03:00
|
|
|
static const char *spapr_core_models[] = {
|
2016-08-09 19:59:59 +03:00
|
|
|
/* 970 */
|
2016-09-12 10:57:20 +03:00
|
|
|
"970_v2.2",
|
2016-06-28 18:05:02 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* 970MP variants */
|
2016-09-12 10:57:20 +03:00
|
|
|
"970MP_v1.0",
|
|
|
|
"970mp_v1.0",
|
|
|
|
"970MP_v1.1",
|
|
|
|
"970mp_v1.1",
|
2016-06-29 14:37:26 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER5+ */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER5+_v2.1",
|
2016-06-28 18:05:02 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER7 */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER7_v2.3",
|
2016-06-10 03:59:01 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER7+ */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER7+_v2.1",
|
2016-06-10 03:59:01 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER8 */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER8_v2.0",
|
2016-06-10 03:59:01 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER8E */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER8E_v2.1",
|
2016-06-10 03:59:01 +03:00
|
|
|
|
2016-08-09 19:59:59 +03:00
|
|
|
/* POWER8NVL */
|
2016-09-12 10:57:20 +03:00
|
|
|
"POWER8NVL_v1.0",
|
2016-06-10 03:59:01 +03:00
|
|
|
};
|
|
|
|
|
2016-09-12 10:57:20 +03:00
|
|
|
void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
|
2016-06-10 03:59:01 +03:00
|
|
|
{
|
2016-09-12 10:57:20 +03:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = spapr_cpu_core_realize;
|
|
|
|
scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data);
|
|
|
|
g_assert(scc->cpu_class);
|
2016-06-10 03:59:01 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo spapr_cpu_core_type_info = {
|
|
|
|
.name = TYPE_SPAPR_CPU_CORE,
|
|
|
|
.parent = TYPE_CPU_CORE,
|
|
|
|
.abstract = true,
|
|
|
|
.instance_size = sizeof(sPAPRCPUCore),
|
2016-09-12 10:57:20 +03:00
|
|
|
.class_size = sizeof(sPAPRCPUCoreClass),
|
2016-06-10 03:59:01 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
static void spapr_cpu_core_register_types(void)
|
|
|
|
{
|
2016-09-12 10:57:20 +03:00
|
|
|
int i;
|
2016-06-10 03:59:01 +03:00
|
|
|
|
|
|
|
type_register_static(&spapr_cpu_core_type_info);
|
2016-09-12 10:57:20 +03:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) {
|
|
|
|
TypeInfo type_info = {
|
|
|
|
.parent = TYPE_SPAPR_CPU_CORE,
|
|
|
|
.instance_size = sizeof(sPAPRCPUCore),
|
|
|
|
.class_init = spapr_cpu_core_class_init,
|
|
|
|
.class_data = (void *) spapr_core_models[i],
|
|
|
|
};
|
|
|
|
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE,
|
|
|
|
spapr_core_models[i]);
|
|
|
|
type_register(&type_info);
|
|
|
|
g_free((void *)type_info.name);
|
2016-06-10 03:59:01 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(spapr_cpu_core_register_types)
|