mirror of https://gitlab.com/qemu-project/qemu
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2015 Imagination Technologies
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*
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*/
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#ifndef _MIPS_GCR_H
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#define _MIPS_GCR_H
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#define TYPE_MIPS_GCR "mips-gcr"
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#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
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#define GCR_BASE_ADDR 0x1fbf8000ULL
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#define GCR_ADDRSPACE_SZ 0x8000
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/* Offsets to register blocks */
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#define MIPS_GCB_OFS 0x0000 /* Global Control Block */
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#define MIPS_CLCB_OFS 0x2000 /* Core Local Control Block */
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#define MIPS_COCB_OFS 0x4000 /* Core Other Control Block */
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#define MIPS_GDB_OFS 0x6000 /* Global Debug Block */
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/* Global Control Block Register Map */
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#define GCR_CONFIG_OFS 0x0000
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#define GCR_BASE_OFS 0x0008
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#define GCR_REV_OFS 0x0030
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#define GCR_L2_CONFIG_OFS 0x0130
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/* Core Local and Core Other Block Register Map */
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#define GCR_CL_CONFIG_OFS 0x0010
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#define GCR_CL_OTHER_OFS 0x0018
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/* GCR_L2_CONFIG register fields */
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#define GCR_L2_CONFIG_BYPASS_SHF 20
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#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
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typedef struct MIPSGCRState MIPSGCRState;
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struct MIPSGCRState {
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SysBusDevice parent_obj;
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int32_t gcr_rev;
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int32_t num_vps;
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hwaddr gcr_base;
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MemoryRegion iomem;
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};
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#endif /* _MIPS_GCR_H */
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