2012-04-03 01:20:08 +04:00
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/*
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* QEMU x86 CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_I386_CPU_QOM_H
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#define QEMU_I386_CPU_QOM_H
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2012-12-17 21:19:50 +04:00
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#include "qom/cpu.h"
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2015-03-31 15:12:25 +03:00
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#include "qemu/notify.h"
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2012-04-03 01:20:08 +04:00
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#ifdef TARGET_X86_64
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#define TYPE_X86_CPU "x86_64-cpu"
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#else
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#define TYPE_X86_CPU "i386-cpu"
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#endif
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#define X86_CPU_CLASS(klass) \
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OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
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#define X86_CPU(obj) \
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OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
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#define X86_CPU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
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2019-06-28 03:28:39 +03:00
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typedef struct X86CPUModel X86CPUModel;
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2014-02-10 14:21:30 +04:00
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2012-04-03 01:20:08 +04:00
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/**
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* X86CPUClass:
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2014-02-10 14:21:30 +04:00
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* @cpu_def: CPU model definition
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2017-09-13 12:05:19 +03:00
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* @host_cpuid_required: Whether CPU model requires cpuid from host.
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2017-01-20 00:04:45 +03:00
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* @ordering: Ordering on the "-cpu help" CPU model list.
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2017-01-16 21:12:12 +03:00
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* @migration_safe: See CpuDefinitionInfo::migration_safe
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i386: Define static "base" CPU model
The query-cpu-model-expand QMP command needs at least one static
model, to allow the "static" expansion mode to be implemented.
Instead of defining static versions of every CPU model, define a
"base" CPU model that has absolutely no feature flag enabled.
Despite having no CPUID data set at all, "-cpu base" is even a
functional CPU:
* It can boot a Slackware Linux 1.01 image with a Linux 0.99.12
kernel[1].
* It is even possible to boot[2] a modern Fedora x86_64 guest by
manually enabling the following CPU features:
-cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr
[1] http://www.qemu-advent-calendar.org/2014/#day-1
[2] This is what can be seen in the guest:
[root@localhost ~]# cat /proc/cpuinfo
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : 00/00
stepping : 0
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl
bugs :
bogomips : 5832.70
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
[root@localhost ~]# x86info -v -a
x86info v1.30. Dave Jones 2001-2011
Feedback to <davej@redhat.com>.
No TSC, MHz calculation cannot be performed.
Unknown vendor (0)
MP Table:
Family: 0 Model: 0 Stepping: 0
CPU Model (x86info's best guess):
eax in: 0x00000000, eax = 00000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000001, eax = 00000000 ebx = 00000800 ecx = 00000000 edx = 07008161
eax in: 0x80000000, eax = 80000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 20000000
Feature flags:
fpu Onboard FPU
msr Model-Specific Registers
pae Physical Address Extensions
cx8 CMPXCHG8 instruction
cmov CMOV instruction
fxsr FXSAVE and FXRSTOR instructions
sse SSE support
sse2 SSE2 support
Long NOPs supported: yes
Address sizes : 0 bits physical, 0 bits virtual
0MHz processor (estimate).
running at an estimated 0MHz
[root@localhost ~]#
Message-Id: <20170222190029.17243-2-ehabkost@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-02-22 22:00:27 +03:00
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* @static_model: See CpuDefinitionInfo::static
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2013-01-16 06:41:47 +04:00
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* @parent_realize: The parent class' realize handler.
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2012-04-03 01:20:08 +04:00
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* @parent_reset: The parent class' reset handler.
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*
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* An x86 CPU model or family.
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*/
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typedef struct X86CPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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2017-02-22 21:39:19 +03:00
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/* CPU definition, automatically loaded by instance_init if not NULL.
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* Should be eventually replaced by subclass-specific property defaults.
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*/
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2019-06-28 03:28:39 +03:00
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X86CPUModel *model;
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2014-02-10 14:21:30 +04:00
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2017-09-13 12:05:19 +03:00
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bool host_cpuid_required;
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2017-01-20 00:04:45 +03:00
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int ordering;
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2017-01-16 21:12:12 +03:00
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bool migration_safe;
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i386: Define static "base" CPU model
The query-cpu-model-expand QMP command needs at least one static
model, to allow the "static" expansion mode to be implemented.
Instead of defining static versions of every CPU model, define a
"base" CPU model that has absolutely no feature flag enabled.
Despite having no CPUID data set at all, "-cpu base" is even a
functional CPU:
* It can boot a Slackware Linux 1.01 image with a Linux 0.99.12
kernel[1].
* It is even possible to boot[2] a modern Fedora x86_64 guest by
manually enabling the following CPU features:
-cpu base,+lm,+msr,+pae,+fpu,+cx8,+cmov,+sse,+sse2,+fxsr
[1] http://www.qemu-advent-calendar.org/2014/#day-1
[2] This is what can be seen in the guest:
[root@localhost ~]# cat /proc/cpuinfo
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : 00/00
stepping : 0
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu msr pae cx8 cmov fxsr sse sse2 lm nopl
bugs :
bogomips : 5832.70
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
[root@localhost ~]# x86info -v -a
x86info v1.30. Dave Jones 2001-2011
Feedback to <davej@redhat.com>.
No TSC, MHz calculation cannot be performed.
Unknown vendor (0)
MP Table:
Family: 0 Model: 0 Stepping: 0
CPU Model (x86info's best guess):
eax in: 0x00000000, eax = 00000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x00000001, eax = 00000000 ebx = 00000800 ecx = 00000000 edx = 07008161
eax in: 0x80000000, eax = 80000001 ebx = 00000000 ecx = 00000000 edx = 00000000
eax in: 0x80000001, eax = 00000000 ebx = 00000000 ecx = 00000000 edx = 20000000
Feature flags:
fpu Onboard FPU
msr Model-Specific Registers
pae Physical Address Extensions
cx8 CMPXCHG8 instruction
cmov CMOV instruction
fxsr FXSAVE and FXRSTOR instructions
sse SSE support
sse2 SSE2 support
Long NOPs supported: yes
Address sizes : 0 bits physical, 0 bits virtual
0MHz processor (estimate).
running at an estimated 0MHz
[root@localhost ~]#
Message-Id: <20170222190029.17243-2-ehabkost@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: Jiri Denemark <jdenemar@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-02-22 22:00:27 +03:00
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bool static_model;
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2014-02-10 14:21:30 +04:00
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2016-09-30 21:49:36 +03:00
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/* Optional description of CPU model.
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* If unavailable, cpu_def->model_id is used */
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const char *model_description;
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2013-01-16 06:41:47 +04:00
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DeviceRealize parent_realize;
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2016-10-20 14:26:04 +03:00
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DeviceUnrealize parent_unrealize;
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2012-04-03 01:20:08 +04:00
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void (*parent_reset)(CPUState *cpu);
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} X86CPUClass;
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2016-03-15 15:49:25 +03:00
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typedef struct X86CPU X86CPU;
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2014-09-13 20:45:14 +04:00
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2012-04-03 01:20:08 +04:00
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#endif
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