267 lines
8.4 KiB
C
267 lines
8.4 KiB
C
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/*
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* STM32L4x5 SYSCFG (System Configuration Controller)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This work is based on the stm32f4xx_syscfg by Alistair Francis.
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* Original code is licensed under the MIT License:
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*/
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/*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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* https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32l4x5_syscfg.h"
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#define SYSCFG_MEMRMP 0x00
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#define SYSCFG_CFGR1 0x04
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#define SYSCFG_EXTICR1 0x08
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#define SYSCFG_EXTICR2 0x0C
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#define SYSCFG_EXTICR3 0x10
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#define SYSCFG_EXTICR4 0x14
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#define SYSCFG_SCSR 0x18
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#define SYSCFG_CFGR2 0x1C
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#define SYSCFG_SWPR 0x20
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#define SYSCFG_SKR 0x24
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#define SYSCFG_SWPR2 0x28
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/* 00000000_00000000_00000001_00000111 */
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#define ACTIVABLE_BITS_MEMRP 0x00000107
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/* 11111100_11111111_00000001_00000000 */
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#define ACTIVABLE_BITS_CFGR1 0xFCFF0100
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/* 00000000_00000000_00000000_00000001 */
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#define FIREWALL_DISABLE_CFGR1 0x00000001
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/* 00000000_00000000_11111111_11111111 */
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#define ACTIVABLE_BITS_EXTICR 0x0000FFFF
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/* 00000000_00000000_00000000_00000011 */
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/* #define ACTIVABLE_BITS_SCSR 0x00000003 */
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/* 00000000_00000000_00000000_00001111 */
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#define ECC_LOCK_CFGR2 0x0000000F
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/* 00000000_00000000_00000001_00000000 */
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#define SRAM2_PARITY_ERROR_FLAG_CFGR2 0x00000100
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/* 00000000_00000000_00000000_11111111 */
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#define ACTIVABLE_BITS_SKR 0x000000FF
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#define NUM_LINES_PER_EXTICR_REG 4
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static void stm32l4x5_syscfg_hold_reset(Object *obj)
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{
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Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
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s->memrmp = 0x00000000;
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s->cfgr1 = 0x7C000001;
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s->exticr[0] = 0x00000000;
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s->exticr[1] = 0x00000000;
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s->exticr[2] = 0x00000000;
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s->exticr[3] = 0x00000000;
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s->scsr = 0x00000000;
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s->cfgr2 = 0x00000000;
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s->swpr = 0x00000000;
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s->skr = 0x00000000;
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s->swpr2 = 0x00000000;
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}
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static void stm32l4x5_syscfg_set_irq(void *opaque, int irq, int level)
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{
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Stm32l4x5SyscfgState *s = opaque;
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const uint8_t gpio = irq / GPIO_NUM_PINS;
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const int line = irq % GPIO_NUM_PINS;
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const int exticr_reg = line / NUM_LINES_PER_EXTICR_REG;
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const int startbit = (line % NUM_LINES_PER_EXTICR_REG) * 4;
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g_assert(gpio < NUM_GPIOS);
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trace_stm32l4x5_syscfg_set_irq(gpio, line, level);
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if (extract32(s->exticr[exticr_reg], startbit, 4) == gpio) {
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trace_stm32l4x5_syscfg_forward_exti(line);
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qemu_set_irq(s->gpio_out[line], level);
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}
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}
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static uint64_t stm32l4x5_syscfg_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Stm32l4x5SyscfgState *s = opaque;
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trace_stm32l4x5_syscfg_read(addr);
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switch (addr) {
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case SYSCFG_MEMRMP:
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return s->memrmp;
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case SYSCFG_CFGR1:
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return s->cfgr1;
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case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
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return s->exticr[(addr - SYSCFG_EXTICR1) / 4];
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case SYSCFG_SCSR:
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return s->scsr;
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case SYSCFG_CFGR2:
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return s->cfgr2;
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case SYSCFG_SWPR:
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return s->swpr;
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case SYSCFG_SKR:
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return s->skr;
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case SYSCFG_SWPR2:
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return s->swpr2;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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return 0;
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}
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}
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static void stm32l4x5_syscfg_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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Stm32l4x5SyscfgState *s = opaque;
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trace_stm32l4x5_syscfg_write(addr, value);
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switch (addr) {
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case SYSCFG_MEMRMP:
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qemu_log_mask(LOG_UNIMP,
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"%s: Changing the memory mapping isn't supported\n",
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__func__);
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s->memrmp = value & ACTIVABLE_BITS_MEMRP;
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return;
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case SYSCFG_CFGR1:
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qemu_log_mask(LOG_UNIMP,
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"%s: Functions in CFGRx aren't supported\n",
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__func__);
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/* bit 0 (firewall dis.) is cleared by software, set only by reset. */
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s->cfgr1 = (s->cfgr1 & value & FIREWALL_DISABLE_CFGR1) |
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(value & ACTIVABLE_BITS_CFGR1);
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return;
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case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
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s->exticr[(addr - SYSCFG_EXTICR1) / 4] =
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(value & ACTIVABLE_BITS_EXTICR);
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return;
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case SYSCFG_SCSR:
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qemu_log_mask(LOG_UNIMP,
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"%s: Erasing SRAM2 isn't supported\n",
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__func__);
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/*
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* only non reserved bits are :
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* bit 0 (write-protected by a passkey), bit 1 (meant to be read)
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* so it serves no purpose yet to add :
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* s->scsr = value & 0x3;
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*/
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return;
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case SYSCFG_CFGR2:
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qemu_log_mask(LOG_UNIMP,
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"%s: Functions in CFGRx aren't supported\n",
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__func__);
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/* bit 8 (SRAM2 PEF) is cleared by software by writing a '1'.*/
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/* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/
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s->cfgr2 = (s->cfgr2 | (value & ECC_LOCK_CFGR2)) &
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~(value & SRAM2_PARITY_ERROR_FLAG_CFGR2);
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return;
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case SYSCFG_SWPR:
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qemu_log_mask(LOG_UNIMP,
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"%s: Write protecting SRAM2 isn't supported\n",
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__func__);
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/* These bits are set by software and cleared only by reset.*/
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s->swpr |= value;
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return;
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case SYSCFG_SKR:
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qemu_log_mask(LOG_UNIMP,
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"%s: Erasing SRAM2 isn't supported\n",
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__func__);
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s->skr = value & ACTIVABLE_BITS_SKR;
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return;
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case SYSCFG_SWPR2:
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qemu_log_mask(LOG_UNIMP,
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"%s: Write protecting SRAM2 isn't supported\n",
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__func__);
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/* These bits are set by software and cleared only by reset.*/
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s->swpr2 |= value;
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32l4x5_syscfg_ops = {
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.read = stm32l4x5_syscfg_read,
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.write = stm32l4x5_syscfg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.impl.unaligned = false,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void stm32l4x5_syscfg_init(Object *obj)
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{
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Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
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memory_region_init_io(&s->mmio, obj, &stm32l4x5_syscfg_ops, s,
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TYPE_STM32L4X5_SYSCFG, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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qdev_init_gpio_in(DEVICE(obj), stm32l4x5_syscfg_set_irq,
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GPIO_NUM_PINS * NUM_GPIOS);
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qdev_init_gpio_out(DEVICE(obj), s->gpio_out, GPIO_NUM_PINS);
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}
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static const VMStateDescription vmstate_stm32l4x5_syscfg = {
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.name = TYPE_STM32L4X5_SYSCFG,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(memrmp, Stm32l4x5SyscfgState),
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VMSTATE_UINT32(cfgr1, Stm32l4x5SyscfgState),
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VMSTATE_UINT32_ARRAY(exticr, Stm32l4x5SyscfgState,
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SYSCFG_NUM_EXTICR),
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VMSTATE_UINT32(scsr, Stm32l4x5SyscfgState),
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VMSTATE_UINT32(cfgr2, Stm32l4x5SyscfgState),
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VMSTATE_UINT32(swpr, Stm32l4x5SyscfgState),
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VMSTATE_UINT32(skr, Stm32l4x5SyscfgState),
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VMSTATE_UINT32(swpr2, Stm32l4x5SyscfgState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void stm32l4x5_syscfg_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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dc->vmsd = &vmstate_stm32l4x5_syscfg;
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rc->phases.hold = stm32l4x5_syscfg_hold_reset;
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}
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static const TypeInfo stm32l4x5_syscfg_info[] = {
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{
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.name = TYPE_STM32L4X5_SYSCFG,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Stm32l4x5SyscfgState),
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.instance_init = stm32l4x5_syscfg_init,
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.class_init = stm32l4x5_syscfg_class_init,
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}
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};
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DEFINE_TYPES(stm32l4x5_syscfg_info)
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