2018-02-12 04:14:10 +03:00
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#
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# HPPA instruction decode definitions.
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#
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# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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2018-02-12 05:22:38 +03:00
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####
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# Field definitions
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####
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%assemble_sr3 13:1 14:2
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2018-02-12 07:39:25 +03:00
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%assemble_sr3x 13:1 14:2 !function=expand_sr3x
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2018-02-12 05:22:38 +03:00
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2018-02-12 05:45:01 +03:00
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%sm_imm 16:10 !function=expand_sm_imm
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2018-02-12 09:48:03 +03:00
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%im5_0 0:s1 1:4
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%im5_16 16:s1 17:4
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%ma_to_m 5:1 13:1 !function=ma_to_m
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2018-02-12 07:39:25 +03:00
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####
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# Argument set definitions
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####
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# All insns that need to form a virtual address should use this set.
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&ldst t b x disp sp m scale size
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2018-02-12 08:44:41 +03:00
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&rr_cf t r cf
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&rrr_cf t r1 r2 cf
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&rrr_cf_sh t r1 r2 cf sh
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####
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# Format definitions
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####
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@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
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@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
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@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
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@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
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2018-02-12 04:14:10 +03:00
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####
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# System
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####
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break 000000 ----- ----- --- 00000000 -----
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2018-02-12 05:22:38 +03:00
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mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
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mtctl 000000 t:5 r:5 --- 11000010 00000
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mtsarcm 000000 01011 r:5 --- 11000110 00000
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mtsm 000000 00000 r:5 000 11000011 00000
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mfia 000000 ----- 00000 --- 10100101 t:5
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mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
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mfctl 000000 r:5 00000- e:1 -01000101 t:5
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2018-02-12 05:45:01 +03:00
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sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
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ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
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rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
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ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
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rfi 000000 ----- ----- --- 01100000 00000
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rfi_r 000000 ----- ----- --- 01100101 00000
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2018-02-12 07:39:25 +03:00
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####
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# Memory Management
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####
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@addrx ...... b:5 x:5 .. ........ m:1 ..... \
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&ldst disp=0 scale=0 t=0 sp=0 size=0
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nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
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nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
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nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
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nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
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nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
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nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
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nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
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probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
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ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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sp=%assemble_sr3x data=0
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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sp=%assemble_sr3x data=0
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lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
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&ldst disp=0 scale=0 size=0
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lci 000001 ----- ----- -- 01001100 0 t:5
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2018-02-12 08:44:41 +03:00
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####
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# Arith/Log
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####
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andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf
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and 000010 ..... ..... .... 001000 0 ..... @rrr_cf
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or 000010 ..... ..... .... 001001 0 ..... @rrr_cf
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xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
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uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
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ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
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cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
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uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf
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uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf
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dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf
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dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf
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add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh
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add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
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add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
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add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
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add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
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sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf
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sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
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sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
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sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
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sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
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sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
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2018-02-12 09:48:03 +03:00
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####
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# Index Mem
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####
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@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
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@ldim5 ...... b:5 ..... sp:2 ......... t:5 \
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&ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
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@stim5 ...... b:5 t:5 sp:2 ......... ..... \
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&ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
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ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
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ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
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st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
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ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
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ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
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lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
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lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
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sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
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stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
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