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qemu/target-sh4/helper.h

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TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
#include "def-helper.h"
SH4: add support for TCG helpers Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5096 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29 01:02:00 +04:00
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_0(ldtlb, void)
DEF_HELPER_0(raise_illegal_instruction, void)
DEF_HELPER_0(raise_slot_illegal_instruction, void)
SH4: Implement FD bit SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-08 01:46:31 +03:00
DEF_HELPER_0(raise_fpu_disable, void)
DEF_HELPER_0(raise_slot_fpu_disable, void)
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_0(debug, void)
DEF_HELPER_1(sleep, void, i32)
DEF_HELPER_1(trapa, void, i32)
SH4: convert some more arithmetics ops to TCG Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30 17:55:14 +04:00
SH: Improve movca.l/ocbi emulation. Author: Vladimir Prus <vladimir@codesourcery.com> Fix movcal.l/ocbi emulation. * target-sh4/cpu.h (memory_content): New. (CPUSH4State): New fields movcal_backup and movcal_backup_tail. * target-sh4/helper.h (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/op_helper.c (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/translate.c (DisasContext): New field has_movcal. (sh4_defs): Update CVS for SH7785. (cpu_sh4_init): Initialize env->movcal_backup_tail. (_decode_opc): Discard movca.l-backup. Make use of helper_movcal and helper_ocbi. (gen_intermediate_code_internal): Initialize has_movcal to 1. Thanks to Shin-ichiro KAWASAKI and Paul Mundt for valuable feedback. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6966 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-02 03:10:46 +04:00
DEF_HELPER_2(movcal, void, i32, i32)
DEF_HELPER_0(discard_movcal_backup, void)
DEF_HELPER_1(ocbi, void, i32)
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_2(addv, i32, i32, i32)
DEF_HELPER_2(addc, i32, i32, i32)
DEF_HELPER_2(subv, i32, i32, i32)
DEF_HELPER_2(subc, i32, i32, i32)
DEF_HELPER_2(div1, i32, i32, i32)
DEF_HELPER_2(macl, void, i32, i32)
DEF_HELPER_2(macw, void, i32, i32)
SH4: convert control/status register load/store to TCG Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-31 02:07:52 +04:00
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
DEF_HELPER_1(ld_fpscr, void, i32)
SH4: convert floating-point ops to TCG Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 02:11:56 +04:00
target-sh4: get rid of CPU_{Float,Double}U SH4 is always using softfloat, so it's possible to have helpers directly taking float32 or float64 value. This allow to get rid of conversions through CPU_{Float,Double}U. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 23:09:12 +04:00
DEF_HELPER_1(fabs_FT, f32, f32)
DEF_HELPER_1(fabs_DT, f64, f64)
DEF_HELPER_2(fadd_FT, f32, f32, f32)
DEF_HELPER_2(fadd_DT, f64, f64, f64)
DEF_HELPER_1(fcnvsd_FT_DT, f64, f32)
DEF_HELPER_1(fcnvds_DT_FT, f32, f64)
SH4: convert floating-point ops to TCG Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-02 02:11:56 +04:00
target-sh4: get rid of CPU_{Float,Double}U SH4 is always using softfloat, so it's possible to have helpers directly taking float32 or float64 value. This allow to get rid of conversions through CPU_{Float,Double}U. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10 23:09:12 +04:00
DEF_HELPER_2(fcmp_eq_FT, void, f32, f32)
DEF_HELPER_2(fcmp_eq_DT, void, f64, f64)
DEF_HELPER_2(fcmp_gt_FT, void, f32, f32)
DEF_HELPER_2(fcmp_gt_DT, void, f64, f64)
DEF_HELPER_2(fdiv_FT, f32, f32, f32)
DEF_HELPER_2(fdiv_DT, f64, f64, f64)
DEF_HELPER_1(float_FT, f32, i32)
DEF_HELPER_1(float_DT, f64, i32)
DEF_HELPER_3(fmac_FT, f32, f32, f32, f32)
DEF_HELPER_2(fmul_FT, f32, f32, f32)
DEF_HELPER_2(fmul_DT, f64, f64, f64)
DEF_HELPER_1(fneg_T, f32, f32)
DEF_HELPER_2(fsub_FT, f32, f32, f32)
DEF_HELPER_2(fsub_DT, f64, f64, f64)
DEF_HELPER_1(fsqrt_FT, f32, f32)
DEF_HELPER_1(fsqrt_DT, f64, f64)
DEF_HELPER_1(ftrc_FT, i32, f32)
DEF_HELPER_1(ftrc_DT, i32, f64)
target-sh4: add fipr instruction Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 22:39:18 +03:00
DEF_HELPER_2(fipr, void, i32, i32)
target-sh4: add ftrv instruction Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14 22:39:18 +03:00
DEF_HELPER_1(ftrv, void, i32)
TCG variable type checking. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17 17:43:54 +03:00
#include "def-helper.h"
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