qemu/tcg/loongarch64/tcg-target-con-str.h

/* SPDX-License-Identifier: MIT */
/*
 * Define LoongArch target-specific operand constraints.
 *
 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
 *
 * Based on tcg/riscv/tcg-target-con-str.h
 *
 * Copyright (c) 2021 Linaro
 */

/*
 * Define constraint letters for register sets:
 * REGS(letter, register_mask)
 */
REGS('r', ALL_GENERAL_REGS)
REGS('w', ALL_VECTOR_REGS)

/*
 * Define constraint letters for constants:
 * CONST(letter, TCG_CT_CONST_* bit set)
 */
CONST('I', TCG_CT_CONST_S12)
CONST('J', TCG_CT_CONST_S32)
CONST('U', TCG_CT_CONST_U12)
CONST('Z', TCG_CT_CONST_ZERO)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ)
tcg/loongarch64: Define the operand constraints Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-7-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-12-21 08:40:40 +03:00			`/* SPDX-License-Identifier: MIT */`
			`/*`
			`* Define LoongArch target-specific operand constraints.`
			`*`
			`* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>`
			`*`
			`* Based on tcg/riscv/tcg-target-con-str.h`
			`*`
			`* Copyright (c) 2021 Linaro`
			`*/`

			`/*`
			`* Define constraint letters for register sets:`
			`* REGS(letter, register_mask)`
			`*/`
			`REGS('r', ALL_GENERAL_REGS)`
tcg/loongarch64: Lower basic tcg vec ops to LSX LSX support on host cpu is detected via hwcap. Lower the following ops to LSX: - dup_vec - dupi_vec - dupm_vec - ld_vec - st_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-3-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-09-08 05:21:09 +03:00			`REGS('w', ALL_VECTOR_REGS)`
tcg/loongarch64: Define the operand constraints Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-7-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-12-21 08:40:40 +03:00
			`/*`
			`* Define constraint letters for constants:`
			`* CONST(letter, TCG_CT_CONST_* bit set)`
			`*/`
			`CONST('I', TCG_CT_CONST_S12)`
tcg/loongarch64: Introduce tcg_out_addi Adjust the constraints to allow any int32_t for immediate addition. Split immediate adds into addu16i + addi, which covers quite a lot of the immediate space. For the hole in the middle, load the constant into TMP0 instead. Reviewed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-11-29 09:46:52 +03:00			`CONST('J', TCG_CT_CONST_S32)`
tcg/loongarch64: Define the operand constraints Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-7-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2021-12-21 08:40:40 +03:00			`CONST('U', TCG_CT_CONST_U12)`
			`CONST('Z', TCG_CT_CONST_ZERO)`
			`CONST('C', TCG_CT_CONST_C12)`
			`CONST('W', TCG_CT_CONST_WSZ)`