2015-12-07 19:23:44 +03:00
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#include "qemu/osdep.h"
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2008-05-04 17:11:44 +04:00
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#include "hw/hw.h"
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#include "hw/boards.h"
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2015-09-24 03:29:37 +03:00
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#include "qemu/error-report.h"
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2013-06-25 21:16:07 +04:00
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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2014-09-12 17:06:49 +04:00
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#include "internals.h"
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static bool vfp_needed(void *opaque)
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2008-05-04 17:11:44 +04:00
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{
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2013-04-19 15:24:19 +04:00
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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return arm_feature(env, ARM_FEATURE_VFP);
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}
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val = qemu_get_be32(f);
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vfp_set_fpscr(env, val);
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return 0;
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}
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static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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qemu_put_be32(f, vfp_get_fpscr(env));
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}
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static const VMStateInfo vmstate_fpscr = {
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.name = "fpscr",
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.get = get_fpscr,
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.put = put_fpscr,
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};
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2013-04-19 15:24:19 +04:00
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static const VMStateDescription vmstate_vfp = {
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.name = "cpu/vfp",
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2013-09-03 23:12:09 +04:00
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.version_id = 3,
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.minimum_version_id = 3,
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2014-09-23 16:09:54 +04:00
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.needed = vfp_needed,
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2013-04-19 15:24:19 +04:00
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.fields = (VMStateField[]) {
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2013-09-03 23:12:09 +04:00
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VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
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2013-04-19 15:24:19 +04:00
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/* The xregs array is a little awkward because element 1 (FPSCR)
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* requires a specific accessor, so we have to split it up in
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* the vmstate:
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*/
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VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
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VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
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{
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.name = "fpscr",
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.version_id = 0,
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.size = sizeof(uint32_t),
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.info = &vmstate_fpscr,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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2013-04-19 15:24:19 +04:00
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VMSTATE_END_OF_LIST()
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2008-05-04 17:11:44 +04:00
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}
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2013-04-19 15:24:19 +04:00
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};
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static bool iwmmxt_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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return arm_feature(env, ARM_FEATURE_IWMMXT);
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}
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2009-07-30 16:33:47 +04:00
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2013-04-19 15:24:19 +04:00
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static const VMStateDescription vmstate_iwmmxt = {
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.name = "cpu/iwmmxt",
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.version_id = 1,
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.minimum_version_id = 1,
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2014-09-23 16:09:54 +04:00
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.needed = iwmmxt_needed,
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2013-04-19 15:24:19 +04:00
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
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VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
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VMSTATE_END_OF_LIST()
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2009-07-30 16:33:47 +04:00
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}
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2013-04-19 15:24:19 +04:00
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};
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static bool m_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_M);
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2008-05-04 17:11:44 +04:00
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}
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2014-03-16 22:07:55 +04:00
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static const VMStateDescription vmstate_m = {
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2013-04-19 15:24:19 +04:00
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.name = "cpu/m",
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.version_id = 1,
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.minimum_version_id = 1,
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2014-09-23 16:09:54 +04:00
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.needed = m_needed,
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2013-04-19 15:24:19 +04:00
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
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VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
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VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
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VMSTATE_UINT32(env.v7m.control, ARMCPU),
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VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
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VMSTATE_INT32(env.v7m.exception, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool thumb2ee_needed(void *opaque)
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2008-05-04 17:11:44 +04:00
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{
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2013-04-19 15:24:19 +04:00
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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return arm_feature(env, ARM_FEATURE_THUMB2EE);
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}
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static const VMStateDescription vmstate_thumb2ee = {
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.name = "cpu/thumb2ee",
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.version_id = 1,
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.minimum_version_id = 1,
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2014-09-23 16:09:54 +04:00
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.needed = thumb2ee_needed,
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2013-04-19 15:24:19 +04:00
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(env.teecr, ARMCPU),
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VMSTATE_UINT32(env.teehbr, ARMCPU),
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VMSTATE_END_OF_LIST()
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2008-05-04 17:11:44 +04:00
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}
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2013-04-19 15:24:19 +04:00
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};
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2015-06-19 16:17:44 +03:00
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static bool pmsav7_needed(void *opaque)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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return arm_feature(env, ARM_FEATURE_MPU) &&
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arm_feature(env, ARM_FEATURE_V7);
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}
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static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id)
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{
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ARMCPU *cpu = opaque;
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return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
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}
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static const VMStateDescription vmstate_pmsav7 = {
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.name = "cpu/pmsav7",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = pmsav7_needed,
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.fields = (VMStateField[]) {
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VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0,
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vmstate_info_uint32, uint32_t),
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VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate),
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VMSTATE_END_OF_LIST()
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}
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};
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2013-04-19 15:24:19 +04:00
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static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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uint32_t val = qemu_get_be32(f);
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2014-12-11 15:07:53 +03:00
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env->aarch64 = ((val & PSTATE_nRW) == 0);
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if (is_a64(env)) {
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pstate_write(env, val);
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return 0;
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}
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2013-04-19 15:24:19 +04:00
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/* Avoid mode switch when restoring CPSR */
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2009-07-30 16:33:47 +04:00
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env->uncached_cpsr = val & CPSR_M;
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cpsr_write(env, val, 0xffffffff);
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2013-04-19 15:24:19 +04:00
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return 0;
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}
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
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{
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ARMCPU *cpu = opaque;
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CPUARMState *env = &cpu->env;
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2014-12-11 15:07:53 +03:00
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uint32_t val;
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if (is_a64(env)) {
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val = pstate_read(env);
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} else {
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val = cpsr_read(env);
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}
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2008-05-04 17:11:44 +04:00
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2014-12-11 15:07:53 +03:00
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qemu_put_be32(f, val);
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2013-04-19 15:24:19 +04:00
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}
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2008-05-04 17:11:44 +04:00
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2013-04-19 15:24:19 +04:00
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static const VMStateInfo vmstate_cpsr = {
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.name = "cpsr",
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.get = get_cpsr,
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.put = put_cpsr,
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};
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2013-06-25 21:16:07 +04:00
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static void cpu_pre_save(void *opaque)
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{
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ARMCPU *cpu = opaque;
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2013-06-25 21:16:07 +04:00
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if (kvm_enabled()) {
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if (!write_kvmstate_to_list(cpu)) {
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/* This should never fail */
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abort();
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}
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} else {
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if (!write_cpustate_to_list(cpu)) {
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/* This should never fail. */
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abort();
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}
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2013-06-25 21:16:07 +04:00
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}
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cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
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memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
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cpu->cpreg_array_len * sizeof(uint64_t));
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memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
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cpu->cpreg_array_len * sizeof(uint64_t));
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}
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static int cpu_post_load(void *opaque, int version_id)
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{
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ARMCPU *cpu = opaque;
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int i, v;
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/* Update the values list from the incoming migration data.
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* Anything in the incoming data which we don't know about is
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* a migration failure; anything we know about but the incoming
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* data doesn't specify retains its current (reset) value.
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* The indexes list remains untouched -- we only inspect the
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* incoming migration index list so we can match the values array
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* entries with the right slots in our own values array.
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*/
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for (i = 0, v = 0; i < cpu->cpreg_array_len
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&& v < cpu->cpreg_vmstate_array_len; i++) {
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if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
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/* register in our list but not incoming : skip it */
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continue;
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}
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if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
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/* register in their list but not ours: fail migration */
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return -1;
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}
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/* matching register, copy the value over */
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cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
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v++;
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}
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2013-06-25 21:16:07 +04:00
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if (kvm_enabled()) {
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2015-07-21 13:18:45 +03:00
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if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {
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2013-06-25 21:16:07 +04:00
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return -1;
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}
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/* Note that it's OK for the TCG side not to know about
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* every register in the list; KVM is authoritative if
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* we're using it.
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*/
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write_list_to_cpustate(cpu);
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} else {
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if (!write_list_to_cpustate(cpu)) {
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return -1;
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}
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2013-06-25 21:16:07 +04:00
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}
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2014-09-29 21:48:46 +04:00
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hw_breakpoint_update_all(cpu);
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2014-09-12 17:06:49 +04:00
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hw_watchpoint_update_all(cpu);
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2013-06-25 21:16:07 +04:00
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return 0;
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}
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2013-04-19 15:24:19 +04:00
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const VMStateDescription vmstate_arm_cpu = {
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.name = "cpu",
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2014-12-11 15:07:53 +03:00
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.version_id = 22,
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.minimum_version_id = 22,
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2013-06-25 21:16:07 +04:00
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.pre_save = cpu_pre_save,
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.post_load = cpu_post_load,
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2013-04-19 15:24:19 +04:00
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
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2014-12-11 15:07:53 +03:00
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VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32),
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VMSTATE_UINT64(env.pc, ARMCPU),
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2013-04-19 15:24:19 +04:00
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{
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.name = "cpsr",
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.version_id = 0,
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.size = sizeof(uint32_t),
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.info = &vmstate_cpsr,
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.flags = VMS_SINGLE,
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.offset = 0,
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},
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VMSTATE_UINT32(env.spsr, ARMCPU),
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2014-05-27 20:09:52 +04:00
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VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
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2014-10-24 15:19:14 +04:00
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VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8),
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VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8),
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2013-04-19 15:24:19 +04:00
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VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
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VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
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2014-05-27 20:09:52 +04:00
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VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
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2014-05-27 20:09:52 +04:00
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VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
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2013-06-25 21:16:07 +04:00
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/* The length-check must come before the arrays to avoid
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* incoming data possibly overflowing the array.
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*/
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2014-04-03 20:52:21 +04:00
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VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
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2013-06-25 21:16:07 +04:00
|
|
|
VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
|
|
|
|
cpreg_vmstate_array_len,
|
|
|
|
0, vmstate_info_uint64, uint64_t),
|
|
|
|
VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
|
|
|
|
cpreg_vmstate_array_len,
|
|
|
|
0, vmstate_info_uint64, uint64_t),
|
2014-01-05 02:15:47 +04:00
|
|
|
VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
|
|
|
|
VMSTATE_UINT64(env.exclusive_val, ARMCPU),
|
|
|
|
VMSTATE_UINT64(env.exclusive_high, ARMCPU),
|
2013-04-19 15:24:19 +04:00
|
|
|
VMSTATE_UINT64(env.features, ARMCPU),
|
target-arm: Define exception record for AArch64 exceptions
For AArch32 exceptions, the only information provided about
the cause of an exception is the individual exception type (data
abort, undef, etc), which we store in cs->exception_index. For
AArch64, the CPU provides much more detail about the cause of
the exception, which can be found in the syndrome register.
Create a set of fields in CPUARMState which must be filled in
whenever an exception is raised, so that exception entry can
correctly fill in the syndrome register for the guest.
This includes the information which in AArch32 appears in
the DFAR and IFAR (fault address registers) and the DFSR
and IFSR (fault status registers) for data aborts and
prefetch aborts, since if we end up taking the MMU fault
to AArch64 rather than AArch32 this will need to end up
in different system registers.
This patch does a refactoring which moves the setting of the
AArch32 DFAR/DFSR/IFAR/IFSR from the point where the exception
is raised to the point where it is taken. (This is no change
for cores with an MMU, retains the existing clearly incorrect
behaviour for ARM946 of trashing the MP access permissions
registers which share the c5_data and c5_insn state fields,
and has no effect for v7M because we don't implement its
MPU fault status or address registers.)
As a side effect of the cleanup we fix a bug in the AArch64
linux-user mode code where we were passing a 64 bit fault
address through the 32 bit c6_data/c6_insn fields: it now
goes via the always-64-bit exception.vaddress.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2014-04-15 22:18:38 +04:00
|
|
|
VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
|
|
|
|
VMSTATE_UINT32(env.exception.fsr, ARMCPU),
|
|
|
|
VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
|
2015-01-08 12:18:59 +03:00
|
|
|
VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU),
|
|
|
|
VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU),
|
2014-10-24 15:19:12 +04:00
|
|
|
VMSTATE_BOOL(powered_off, ARMCPU),
|
2013-04-19 15:24:19 +04:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
},
|
2014-09-23 16:09:54 +04:00
|
|
|
.subsections = (const VMStateDescription*[]) {
|
|
|
|
&vmstate_vfp,
|
|
|
|
&vmstate_iwmmxt,
|
|
|
|
&vmstate_m,
|
|
|
|
&vmstate_thumb2ee,
|
2015-06-19 16:17:44 +03:00
|
|
|
&vmstate_pmsav7,
|
2014-09-23 16:09:54 +04:00
|
|
|
NULL
|
2009-07-30 16:33:47 +04:00
|
|
|
}
|
2013-04-19 15:24:19 +04:00
|
|
|
};
|
2015-09-24 03:29:37 +03:00
|
|
|
|
|
|
|
const char *gicv3_class_name(void)
|
|
|
|
{
|
|
|
|
if (kvm_irqchip_in_kernel()) {
|
|
|
|
#ifdef TARGET_AARCH64
|
|
|
|
return "kvm-arm-gicv3";
|
|
|
|
#else
|
|
|
|
error_report("KVM GICv3 acceleration is not supported on this "
|
2015-12-18 18:35:19 +03:00
|
|
|
"platform");
|
2015-09-24 03:29:37 +03:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
/* TODO: Software emulation is not implemented yet */
|
2015-12-18 18:35:19 +03:00
|
|
|
error_report("KVM is currently required for GICv3 emulation");
|
2015-09-24 03:29:37 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
exit(1);
|
|
|
|
}
|