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qemu/tests/tcg/xtensa/test_cache.S

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target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
#include "macros.inc"
.purgem test_init
.macro test_init
call0 cache_unlock_invalidate
.endm
test_suite cache
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_HAVE_PTP_MMU
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
.macro pf_op op
\op a2, 0
\op a3, 0
\op a4, 0
.endm
test prefetch
movi a2, 0xd0000000 /* cacheable */
movi a3, 0xd8000000 /* non-cacheable */
movi a4, 0x00001235 /* unmapped */
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_DCACHE_SIZE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
pf_op dpfr
pf_op dpfro
pf_op dpfw
pf_op dpfwo
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#ifdef XCHAL_ICACHE_SIZE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
pf_op ipf
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_DCACHE_LINE_LOCKABLE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
dpfl a2, 0
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#if XCHAL_ICACHE_LINE_LOCKABLE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
ipfl a2, 0
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test_end
.macro cache_fault op, addr, exc_code
set_vector kernel, 2f
movi a4, \addr
1:
\op a4, 0
test_fail
2:
rsr a2, epc1
movi a3, 1b
assert eq, a2, a3
rsr a2, excvaddr
assert eq, a2, a4
rsr a2, exccause
movi a3, \exc_code
assert eq, a2, a3
.endm
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#if XCHAL_DCACHE_LINE_LOCKABLE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test dpfl_tlb_miss
cache_fault dpfl, 0x00002345, 24
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_DCACHE_SIZE
#if XCHAL_DCACHE_IS_WRITEBACK
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test dhwb_tlb_miss
cache_fault dhwb, 0x00002345, 24
test_end
test dhwbi_tlb_miss
cache_fault dhwbi, 0x00002345, 24
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test dhi_tlb_miss
cache_fault dhi, 0x00002345, 24
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_DCACHE_LINE_LOCKABLE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test dhu_tlb_miss
cache_fault dhu, 0x00002345, 24
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_ICACHE_SIZE
#if XCHAL_ICACHE_LINE_LOCKABLE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test ipfl_tlb_miss
cache_fault ipfl, 0x00002345, 16
test_end
test ihu_tlb_miss
cache_fault ihu, 0x00002345, 16
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test ihi_tlb_miss
cache_fault ihi, 0x00002345, 16
test_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#endif
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
test_suite_end
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
cache_unlock_invalidate:
#if XCHAL_DCACHE_SIZE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
movi a2, 0
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
movi a3, XCHAL_DCACHE_SIZE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
1:
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#if XCHAL_DCACHE_LINE_LOCKABLE
diu a2, 0
#endif
dii a2, 0
addi a2, a2, XCHAL_DCACHE_LINESIZE
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
bltu a2, a3, 1b
tests/tcg/xtensa: conditionalize cache option tests Make data/instruction tests conditional on the presence of data/instruction cache, whether they're lockable and whether data cache is writeback. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-18 17:32:45 +03:00
#endif
#if XCHAL_ICACHE_SIZE
movi a2, 0
movi a3, XCHAL_ICACHE_SIZE
1:
#if XCHAL_ICACHE_LINE_LOCKABLE
iiu a2, 0
#endif
iii a2, 0
addi a2, a2, XCHAL_ICACHE_LINESIZE
bltu a2, a3, 1b
#endif
target-xtensa: add basic tests for cache opcodes Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-11 12:22:19 +04:00
ret
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