2015-09-23 22:04:44 +03:00
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/*
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* vfio based device assignment support - PCI devices
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*
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* Copyright Red Hat, Inc. 2012-2015
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*
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* Authors:
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* Alex Williamson <alex.williamson@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef HW_VFIO_VFIO_PCI_H
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#define HW_VFIO_VFIO_PCI_H
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#include "exec/memory.h"
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2022-12-22 13:03:28 +03:00
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#include "hw/pci/pci_device.h"
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2015-09-23 22:04:44 +03:00
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#include "hw/vfio/vfio-common.h"
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#include "qemu/event_notifier.h"
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#include "qemu/queue.h"
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#include "qemu/timer.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2022-03-26 09:02:26 +03:00
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#include "sysemu/kvm.h"
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2015-09-23 22:04:44 +03:00
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2015-09-23 22:04:49 +03:00
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#define PCI_ANY_ID (~0)
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2015-09-23 22:04:44 +03:00
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struct VFIOPCIDevice;
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vfio/quirks: ioeventfd quirk acceleration
The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found
in device MMIO space. Normally PCI config space is considered a slow
path and further optimization is unnecessary, however NVIDIA uses a
register here to enable the MSI interrupt to re-trigger. Exiting to
QEMU for this MSI-ACK handling can therefore rate limit our interrupt
handling. Fortunately the MSI-ACK write is easily detected since the
quirk MemoryRegion otherwise has very few accesses, so simply looking
for consecutive writes with the same data is sufficient, in this case
10 consecutive writes with the same data and size is arbitrarily
chosen. We configure the KVM ioeventfd with data match, so there's
no risk of triggering for the wrong data or size, but we do risk that
pathological driver behavior might consume all of QEMU's file
descriptors, so we cap ourselves to 10 ioeventfds for this purpose.
In support of the above, generic ioeventfd infrastructure is added
for vfio quirks. This automatically initializes an ioeventfd list
per quirk, disables and frees ioeventfds on exit, and allows
ioeventfds marked as dynamic to be dropped on device reset. The
rationale for this latter feature is that useful ioeventfds may
depend on specific driver behavior and since we necessarily place a
cap on our use of ioeventfds, a machine reset is a reasonable point
at which to assume a new driver and re-profile.
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-06-05 17:23:17 +03:00
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typedef struct VFIOIOEventFD {
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QLIST_ENTRY(VFIOIOEventFD) next;
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MemoryRegion *mr;
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hwaddr addr;
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unsigned size;
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uint64_t data;
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EventNotifier e;
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VFIORegion *region;
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hwaddr region_addr;
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bool dynamic; /* Added runtime, removed on device reset */
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2018-06-05 17:23:17 +03:00
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bool vfio;
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vfio/quirks: ioeventfd quirk acceleration
The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found
in device MMIO space. Normally PCI config space is considered a slow
path and further optimization is unnecessary, however NVIDIA uses a
register here to enable the MSI interrupt to re-trigger. Exiting to
QEMU for this MSI-ACK handling can therefore rate limit our interrupt
handling. Fortunately the MSI-ACK write is easily detected since the
quirk MemoryRegion otherwise has very few accesses, so simply looking
for consecutive writes with the same data is sufficient, in this case
10 consecutive writes with the same data and size is arbitrarily
chosen. We configure the KVM ioeventfd with data match, so there's
no risk of triggering for the wrong data or size, but we do risk that
pathological driver behavior might consume all of QEMU's file
descriptors, so we cap ourselves to 10 ioeventfds for this purpose.
In support of the above, generic ioeventfd infrastructure is added
for vfio quirks. This automatically initializes an ioeventfd list
per quirk, disables and frees ioeventfds on exit, and allows
ioeventfds marked as dynamic to be dropped on device reset. The
rationale for this latter feature is that useful ioeventfds may
depend on specific driver behavior and since we necessarily place a
cap on our use of ioeventfds, a machine reset is a reasonable point
at which to assume a new driver and re-profile.
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-06-05 17:23:17 +03:00
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} VFIOIOEventFD;
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2015-09-23 22:04:46 +03:00
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typedef struct VFIOQuirk {
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QLIST_ENTRY(VFIOQuirk) next;
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void *data;
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vfio/quirks: ioeventfd quirk acceleration
The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found
in device MMIO space. Normally PCI config space is considered a slow
path and further optimization is unnecessary, however NVIDIA uses a
register here to enable the MSI interrupt to re-trigger. Exiting to
QEMU for this MSI-ACK handling can therefore rate limit our interrupt
handling. Fortunately the MSI-ACK write is easily detected since the
quirk MemoryRegion otherwise has very few accesses, so simply looking
for consecutive writes with the same data is sufficient, in this case
10 consecutive writes with the same data and size is arbitrarily
chosen. We configure the KVM ioeventfd with data match, so there's
no risk of triggering for the wrong data or size, but we do risk that
pathological driver behavior might consume all of QEMU's file
descriptors, so we cap ourselves to 10 ioeventfds for this purpose.
In support of the above, generic ioeventfd infrastructure is added
for vfio quirks. This automatically initializes an ioeventfd list
per quirk, disables and frees ioeventfds on exit, and allows
ioeventfds marked as dynamic to be dropped on device reset. The
rationale for this latter feature is that useful ioeventfds may
depend on specific driver behavior and since we necessarily place a
cap on our use of ioeventfds, a machine reset is a reasonable point
at which to assume a new driver and re-profile.
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-06-05 17:23:17 +03:00
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QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
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2015-09-23 22:04:46 +03:00
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int nr_mem;
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MemoryRegion *mem;
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2018-06-05 17:23:17 +03:00
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void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
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2015-09-23 22:04:44 +03:00
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} VFIOQuirk;
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typedef struct VFIOBAR {
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VFIORegion region;
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2018-02-06 21:08:25 +03:00
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MemoryRegion *mr;
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size_t size;
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uint8_t type;
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2015-09-23 22:04:44 +03:00
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bool ioport;
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bool mem64;
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QLIST_HEAD(, VFIOQuirk) quirks;
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} VFIOBAR;
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typedef struct VFIOVGARegion {
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MemoryRegion mem;
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off_t offset;
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int nr;
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QLIST_HEAD(, VFIOQuirk) quirks;
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} VFIOVGARegion;
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typedef struct VFIOVGA {
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off_t fd_offset;
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int fd;
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VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
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} VFIOVGA;
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typedef struct VFIOINTx {
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bool pending; /* interrupt pending */
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bool kvm_accel; /* set when QEMU bypass through KVM enabled */
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uint8_t pin; /* which pin to pull for qemu_set_irq */
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EventNotifier interrupt; /* eventfd triggered on interrupt */
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EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
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PCIINTxRoute route; /* routing info for QEMU bypass */
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uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
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QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
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} VFIOINTx;
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typedef struct VFIOMSIVector {
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/*
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* Two interrupt paths are configured per vector. The first, is only used
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* for interrupts injected via QEMU. This is typically the non-accel path,
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* but may also be used when we want QEMU to handle masking and pending
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* bits. The KVM path bypasses QEMU and is therefore higher performance,
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* but requires masking at the device. virq is used to track the MSI route
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* through KVM, thus kvm_interrupt is only available when virq is set to a
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* valid (>= 0) value.
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*/
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EventNotifier interrupt;
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EventNotifier kvm_interrupt;
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struct VFIOPCIDevice *vdev; /* back pointer to device */
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int virq;
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bool use;
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} VFIOMSIVector;
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enum {
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VFIO_INT_NONE = 0,
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VFIO_INT_INTx = 1,
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VFIO_INT_MSI = 2,
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VFIO_INT_MSIX = 3,
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};
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2018-02-06 21:08:25 +03:00
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/* Cache of MSI-X setup */
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2015-09-23 22:04:44 +03:00
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typedef struct VFIOMSIXInfo {
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uint8_t table_bar;
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uint8_t pba_bar;
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uint16_t entries;
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uint32_t table_offset;
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uint32_t pba_offset;
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2016-01-19 21:33:42 +03:00
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unsigned long *pending;
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2015-09-23 22:04:44 +03:00
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} VFIOMSIXInfo;
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2020-08-25 22:20:38 +03:00
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#define TYPE_VFIO_PCI "vfio-pci"
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2020-09-16 21:25:19 +03:00
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OBJECT_DECLARE_SIMPLE_TYPE(VFIOPCIDevice, VFIO_PCI)
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2020-08-25 22:20:38 +03:00
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2020-09-03 23:43:22 +03:00
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struct VFIOPCIDevice {
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2015-09-23 22:04:44 +03:00
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PCIDevice pdev;
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VFIODevice vbasedev;
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VFIOINTx intx;
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unsigned int config_size;
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uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
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off_t config_offset; /* Offset of config space region within device fd */
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unsigned int rom_size;
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off_t rom_offset; /* Offset of ROM region within device fd */
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void *rom;
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int msi_cap_size;
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VFIOMSIVector *msi_vectors;
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VFIOMSIXInfo *msix;
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int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
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int interrupt; /* Current interrupt type */
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VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
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2016-03-10 19:39:08 +03:00
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VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */
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vfio/pci: Intel graphics legacy mode assignment
Enable quirks to support SandyBridge and newer IGD devices as primary
VM graphics. This requires new vfio-pci device specific regions added
in kernel v4.6 to expose the IGD OpRegion, the shadow ROM, and config
space access to the PCI host bridge and LPC/ISA bridge. VM firmware
support, SeaBIOS only so far, is also required for reserving memory
regions for IGD specific use. In order to enable this mode, IGD must
be assigned to the VM at PCI bus address 00:02.0, it must have a ROM,
it must be able to enable VGA, it must have or be able to create on
its own an LPC/ISA bridge of the proper type at PCI bus address
00:1f.0 (sorry, not compatible with Q35 yet), and it must have the
above noted vfio-pci kernel features and BIOS. The intention is that
to enable this mode, a user simply needs to assign 00:02.0 from the
host to 00:02.0 in the VM:
-device vfio-pci,host=0000:00:02.0,bus=pci.0,addr=02.0
and everything either happens automatically or it doesn't. In the
case that it doesn't, we leave error reports, but assume the device
will operate in universal passthrough mode (UPT), which doesn't
require any of this, but has a much more narrow window of supported
devices, supported use cases, and supported guest drivers.
When using IGD in this mode, the VM firmware is required to reserve
some VM RAM for the OpRegion (on the order or several 4k pages) and
stolen memory for the GTT (up to 8MB for the latest GPUs). An
additional option, x-igd-gms allows the user to specify some amount
of additional memory (value is number of 32MB chunks up to 512MB) that
is pre-allocated for graphics use. TBH, I don't know of anything that
requires this or makes use of this memory, which is why we don't
allocate any by default, but the specification suggests this is not
actually a valid combination, so the option exists as a workaround.
Please report if it's actually necessary in some environment.
See code comments for further discussion about the actual operation
of the quirks necessary to assign these devices.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
2016-05-26 18:43:21 +03:00
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void *igd_opregion;
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2015-09-23 22:04:44 +03:00
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PCIHostDeviceAddress host;
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EventNotifier err_notifier;
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EventNotifier req_notifier;
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int (*resetfn)(struct VFIOPCIDevice *);
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2015-09-23 22:04:49 +03:00
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uint32_t vendor_id;
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uint32_t device_id;
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uint32_t sub_vendor_id;
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uint32_t sub_device_id;
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2015-09-23 22:04:44 +03:00
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uint32_t features;
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#define VFIO_FEATURE_ENABLE_VGA_BIT 0
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#define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
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#define VFIO_FEATURE_ENABLE_REQ_BIT 1
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#define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
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2016-05-26 18:43:22 +03:00
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#define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
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#define VFIO_FEATURE_ENABLE_IGD_OPREGION \
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(1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
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2018-03-13 20:17:29 +03:00
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OnOffAuto display;
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2019-03-11 20:14:40 +03:00
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uint32_t display_xres;
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uint32_t display_yres;
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2015-09-23 22:04:44 +03:00
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int32_t bootindex;
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vfio/pci: Intel graphics legacy mode assignment
Enable quirks to support SandyBridge and newer IGD devices as primary
VM graphics. This requires new vfio-pci device specific regions added
in kernel v4.6 to expose the IGD OpRegion, the shadow ROM, and config
space access to the PCI host bridge and LPC/ISA bridge. VM firmware
support, SeaBIOS only so far, is also required for reserving memory
regions for IGD specific use. In order to enable this mode, IGD must
be assigned to the VM at PCI bus address 00:02.0, it must have a ROM,
it must be able to enable VGA, it must have or be able to create on
its own an LPC/ISA bridge of the proper type at PCI bus address
00:1f.0 (sorry, not compatible with Q35 yet), and it must have the
above noted vfio-pci kernel features and BIOS. The intention is that
to enable this mode, a user simply needs to assign 00:02.0 from the
host to 00:02.0 in the VM:
-device vfio-pci,host=0000:00:02.0,bus=pci.0,addr=02.0
and everything either happens automatically or it doesn't. In the
case that it doesn't, we leave error reports, but assume the device
will operate in universal passthrough mode (UPT), which doesn't
require any of this, but has a much more narrow window of supported
devices, supported use cases, and supported guest drivers.
When using IGD in this mode, the VM firmware is required to reserve
some VM RAM for the OpRegion (on the order or several 4k pages) and
stolen memory for the GTT (up to 8MB for the latest GPUs). An
additional option, x-igd-gms allows the user to specify some amount
of additional memory (value is number of 32MB chunks up to 512MB) that
is pre-allocated for graphics use. TBH, I don't know of anything that
requires this or makes use of this memory, which is why we don't
allocate any by default, but the specification suggests this is not
actually a valid combination, so the option exists as a workaround.
Please report if it's actually necessary in some environment.
See code comments for further discussion about the actual operation
of the quirks necessary to assign these devices.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
2016-05-26 18:43:21 +03:00
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uint32_t igd_gms;
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vfio/pci: Allow relocating MSI-X MMIO
Recently proposed vfio-pci kernel changes (v4.16) remove the
restriction preventing userspace from mmap'ing PCI BARs in areas
overlapping the MSI-X vector table. This change is primarily intended
to benefit host platforms which make use of system page sizes larger
than the PCI spec recommendation for alignment of MSI-X data
structures (ie. not x86_64). In the case of POWER systems, the SPAPR
spec requires the VM to program MSI-X using hypercalls, rendering the
MSI-X vector table unused in the VM view of the device. However,
ARM64 platforms also support 64KB pages and rely on QEMU emulation of
MSI-X. Regardless of the kernel driver allowing mmaps overlapping
the MSI-X vector table, emulation of the MSI-X vector table also
prevents direct mapping of device MMIO spaces overlapping this page.
Thanks to the fact that PCI devices have a standard self discovery
mechanism, we can try to resolve this by relocating the MSI-X data
structures, either by creating a new PCI BAR or extending an existing
BAR and updating the MSI-X capability for the new location. There's
even a very slim chance that this could benefit devices which do not
adhere to the PCI spec alignment guidelines on x86_64 systems.
This new x-msix-relocation option accepts the following choices:
off: Disable MSI-X relocation, use native device config (default)
auto: Use a known good combination for the platform/device (none yet)
bar0..bar5: Specify the target BAR for MSI-X data structures
If compatible, the target BAR will either be created or extended and
the new portion will be used for MSI-X emulation.
The first obvious user question with this option is how to determine
whether a given platform and device might benefit from this option.
In most cases, the answer is that it won't, especially on x86_64.
Devices often dedicate an entire BAR to MSI-X and therefore no
performance sensitive registers overlap the MSI-X area. Take for
example:
# lspci -vvvs 0a:00.0
0a:00.0 Ethernet controller: Intel Corporation I350 Gigabit Network Connection
...
Region 0: Memory at db680000 (32-bit, non-prefetchable) [size=512K]
Region 3: Memory at db7f8000 (32-bit, non-prefetchable) [size=16K]
...
Capabilities: [70] MSI-X: Enable+ Count=10 Masked-
Vector table: BAR=3 offset=00000000
PBA: BAR=3 offset=00002000
This device uses the 16K bar3 for MSI-X with the vector table at
offset zero and the pending bits arrary at offset 8K, fully honoring
the PCI spec alignment guidance. The data sheet specifically refers
to this as an MSI-X BAR. This device would not see a benefit from
MSI-X relocation regardless of the platform, regardless of the page
size.
However, here's another example:
# lspci -vvvs 02:00.0
02:00.0 Serial Attached SCSI controller: xxxxxxxx
...
Region 0: I/O ports at c000 [size=256]
Region 1: Memory at ef640000 (64-bit, non-prefetchable) [size=64K]
Region 3: Memory at ef600000 (64-bit, non-prefetchable) [size=256K]
...
Capabilities: [c0] MSI-X: Enable+ Count=16 Masked-
Vector table: BAR=1 offset=0000e000
PBA: BAR=1 offset=0000f000
Here the MSI-X data structures are placed on separate 4K pages at the
end of a 64KB BAR. If our host page size is 4K, we're likely fine,
but at 64KB page size, MSI-X emulation at that location prevents the
entire BAR from being directly mapped into the VM address space.
Overlapping performance sensitive registers then starts to be a very
likely scenario on such a platform. At this point, the user could
enable tracing on vfio_region_read and vfio_region_write to determine
more conclusively if device accesses are being trapped through QEMU.
Upon finding a device and platform in need of MSI-X relocation, the
next problem is how to choose target PCI BAR to host the MSI-X data
structures. A few key rules to keep in mind for this selection
include:
* There are only 6 BAR slots, bar0..bar5
* 64-bit BARs occupy two BAR slots, 'lspci -vvv' lists the first slot
* PCI BARs are always a power of 2 in size, extending == doubling
* The maximum size of a 32-bit BAR is 2GB
* MSI-X data structures must reside in an MMIO BAR
Using these rules, we can evaluate each BAR of the second example
device above as follows:
bar0: I/O port BAR, incompatible with MSI-X tables
bar1: BAR could be extended, incurring another 64KB of MMIO
bar2: Unavailable, bar1 is 64-bit, this register is used by bar1
bar3: BAR could be extended, incurring another 256KB of MMIO
bar4: Unavailable, bar3 is 64bit, this register is used by bar3
bar5: Available, empty BAR, minimum additional MMIO
A secondary optimization we might wish to make in relocating MSI-X
is to minimize the additional MMIO required for the device, therefore
we might test the available choices in order of preference as bar5,
bar1, and finally bar3. The original proposal for this feature
included an 'auto' option which would choose bar5 in this case, but
various drivers have been found that make assumptions about the
properties of the "first" BAR or the size of BARs such that there
appears to be no foolproof automatic selection available, requiring
known good combinations to be sourced from users. This patch is
pre-enabled for an 'auto' selection making use of a validated lookup
table, but no entries are yet identified.
Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-02-06 21:08:26 +03:00
|
|
|
OffAutoPCIBAR msix_relo;
|
2015-09-23 22:04:44 +03:00
|
|
|
uint8_t pm_cap;
|
2017-08-30 01:05:47 +03:00
|
|
|
uint8_t nv_gpudirect_clique;
|
2015-09-23 22:04:44 +03:00
|
|
|
bool pci_aer;
|
|
|
|
|
bool req_enabled;
|
|
|
|
|
bool has_flr;
|
|
|
|
|
bool has_pm_reset;
|
|
|
|
|
bool rom_read_failed;
|
|
|
|
|
bool no_kvm_intx;
|
|
|
|
|
bool no_kvm_msi;
|
|
|
|
|
bool no_kvm_msix;
|
2018-02-06 21:08:27 +03:00
|
|
|
bool no_geforce_quirks;
|
vfio/quirks: ioeventfd quirk acceleration
The NVIDIA BAR0 quirks virtualize the PCI config space mirrors found
in device MMIO space. Normally PCI config space is considered a slow
path and further optimization is unnecessary, however NVIDIA uses a
register here to enable the MSI interrupt to re-trigger. Exiting to
QEMU for this MSI-ACK handling can therefore rate limit our interrupt
handling. Fortunately the MSI-ACK write is easily detected since the
quirk MemoryRegion otherwise has very few accesses, so simply looking
for consecutive writes with the same data is sufficient, in this case
10 consecutive writes with the same data and size is arbitrarily
chosen. We configure the KVM ioeventfd with data match, so there's
no risk of triggering for the wrong data or size, but we do risk that
pathological driver behavior might consume all of QEMU's file
descriptors, so we cap ourselves to 10 ioeventfds for this purpose.
In support of the above, generic ioeventfd infrastructure is added
for vfio quirks. This automatically initializes an ioeventfd list
per quirk, disables and frees ioeventfds on exit, and allows
ioeventfds marked as dynamic to be dropped on device reset. The
rationale for this latter feature is that useful ioeventfds may
depend on specific driver behavior and since we necessarily place a
cap on our use of ioeventfds, a machine reset is a reasonable point
at which to assume a new driver and re-profile.
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2018-06-05 17:23:17 +03:00
|
|
|
bool no_kvm_ioeventfd;
|
2018-06-05 17:23:17 +03:00
|
|
|
bool no_vfio_ioeventfd;
|
2018-10-15 19:52:09 +03:00
|
|
|
bool enable_ramfb;
|
2022-03-26 09:02:26 +03:00
|
|
|
bool defer_kvm_irq_routing;
|
2018-03-13 20:17:30 +03:00
|
|
|
VFIODisplay *dpy;
|
2019-10-17 04:38:30 +03:00
|
|
|
Notifier irqchip_change_notifier;
|
2020-09-03 23:43:22 +03:00
|
|
|
};
|
2015-09-23 22:04:44 +03:00
|
|
|
|
2020-02-06 21:55:42 +03:00
|
|
|
/* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
|
|
|
|
|
static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
|
|
|
|
|
{
|
|
|
|
|
return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) &&
|
|
|
|
|
(device == PCI_ANY_ID || device == vdev->device_id);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
|
|
|
|
|
{
|
|
|
|
|
PCIDevice *pdev = &vdev->pdev;
|
|
|
|
|
uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
|
|
|
|
|
|
|
|
|
|
return class == PCI_CLASS_DISPLAY_VGA;
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-23 22:04:45 +03:00
|
|
|
uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
|
|
|
|
|
void vfio_pci_write_config(PCIDevice *pdev,
|
|
|
|
|
uint32_t addr, uint32_t val, int len);
|
|
|
|
|
|
|
|
|
|
uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
|
|
|
|
|
void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
|
|
|
|
|
|
2021-02-05 20:18:17 +03:00
|
|
|
bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev);
|
2015-09-23 22:04:45 +03:00
|
|
|
void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
|
2016-03-10 19:39:08 +03:00
|
|
|
void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
|
|
|
|
|
void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
|
2015-09-23 22:04:45 +03:00
|
|
|
void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
|
2016-03-10 19:39:08 +03:00
|
|
|
void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
|
|
|
|
|
void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
|
2015-09-23 22:04:49 +03:00
|
|
|
void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
|
2017-08-30 01:05:39 +03:00
|
|
|
int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
|
2018-06-05 17:23:17 +03:00
|
|
|
void vfio_quirk_reset(VFIOPCIDevice *vdev);
|
2020-02-06 21:55:42 +03:00
|
|
|
VFIOQuirk *vfio_quirk_alloc(int nr_mem);
|
|
|
|
|
void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr);
|
2015-09-23 22:04:45 +03:00
|
|
|
|
2017-08-30 01:05:47 +03:00
|
|
|
extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
|
|
|
|
|
|
2016-10-17 19:57:57 +03:00
|
|
|
int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
|
2016-03-10 19:39:08 +03:00
|
|
|
|
2016-05-26 18:43:22 +03:00
|
|
|
int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
|
2016-10-17 19:57:59 +03:00
|
|
|
struct vfio_region_info *info,
|
|
|
|
|
Error **errp);
|
spapr: Support NVIDIA V100 GPU with NVLink2
NVIDIA V100 GPUs have on-board RAM which is mapped into the host memory
space and accessible as normal RAM via an NVLink bus. The VFIO-PCI driver
implements special regions for such GPUs and emulates an NVLink bridge.
NVLink2-enabled POWER9 CPUs also provide address translation services
which includes an ATS shootdown (ATSD) register exported via the NVLink
bridge device.
This adds a quirk to VFIO to map the GPU memory and create an MR;
the new MR is stored in a PCI device as a QOM link. The sPAPR PCI uses
this to get the MR and map it to the system address space.
Another quirk does the same for ATSD.
This adds additional steps to sPAPR PHB setup:
1. Search for specific GPUs and NPUs, collect findings in
sPAPRPHBState::nvgpus, manage system address space mappings;
2. Add device-specific properties such as "ibm,npu", "ibm,gpu",
"memory-block", "link-speed" to advertise the NVLink2 function to
the guest;
3. Add "mmio-atsd" to vPHB to advertise the ATSD capability;
4. Add new memory blocks (with extra "linux,memory-usable" to prevent
the guest OS from accessing the new memory until it is onlined) and
npuphb# nodes representing an NPU unit for every vPHB as the GPU driver
uses it for link discovery.
This allocates space for GPU RAM and ATSD like we do for MMIOs by
adding 2 new parameters to the phb_placement() hook. Older machine types
set these to zero.
This puts new memory nodes in a separate NUMA node to as the GPU RAM
needs to be configured equally distant from any other node in the system.
Unlike the host setup which assigns numa ids from 255 downwards, this
adds new NUMA nodes after the user configures nodes or from 1 if none
were configured.
This adds requirement similar to EEH - one IOMMU group per vPHB.
The reason for this is that ATSD registers belong to a physical NPU
so they cannot invalidate translations on GPUs attached to another NPU.
It is guaranteed by the host platform as it does not mix NVLink bridges
or GPUs from different NPU in the same IOMMU group. If more than one
IOMMU group is detected on a vPHB, this disables ATSD support for that
vPHB and prints a warning.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
[aw: for vfio portions]
Acked-by: Alex Williamson <alex.williamson@redhat.com>
Message-Id: <20190312082103.130561-1-aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-12 11:21:03 +03:00
|
|
|
int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp);
|
|
|
|
|
int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp);
|
2016-05-26 18:43:22 +03:00
|
|
|
|
2018-04-27 12:11:06 +03:00
|
|
|
void vfio_display_reset(VFIOPCIDevice *vdev);
|
2018-03-13 20:17:29 +03:00
|
|
|
int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
|
|
|
|
|
void vfio_display_finalize(VFIOPCIDevice *vdev);
|
|
|
|
|
|
2015-09-23 22:04:44 +03:00
|
|
|
#endif /* HW_VFIO_VFIO_PCI_H */
|