2021-06-14 22:32:18 +03:00
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/*
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* QEMU Floppy disk emulator (Intel 82078)
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*
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* Copyright (c) 2003, 2007 Jocelyn Mayer
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* Copyright (c) 2008 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* The controller is used in Sun4m systems in a slightly different
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* way. There are changes in DOR register and DMA is not available.
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*/
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#include "qemu/osdep.h"
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#include "hw/block/fdc.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/timer.h"
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2022-06-08 16:53:08 +03:00
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#include "hw/acpi/acpi_aml_interface.h"
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2021-06-14 22:32:18 +03:00
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#include "hw/irq.h"
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#include "hw/isa/isa.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "migration/vmstate.h"
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#include "hw/block/block.h"
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#include "sysemu/block-backend.h"
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#include "sysemu/blockdev.h"
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#include "sysemu/sysemu.h"
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2024-01-14 15:39:01 +03:00
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#include "exec/ioport.h"
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2021-06-14 22:32:18 +03:00
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qom/object.h"
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#include "fdc-internal.h"
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OBJECT_DECLARE_SIMPLE_TYPE(FDCtrlISABus, ISA_FDC)
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struct FDCtrlISABus {
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/*< private >*/
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ISADevice parent_obj;
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/*< public >*/
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uint32_t iobase;
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uint32_t irq;
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uint32_t dma;
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struct FDCtrl state;
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2024-01-14 15:39:01 +03:00
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PortioList portio_list;
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2021-06-14 22:32:18 +03:00
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int32_t bootindexA;
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int32_t bootindexB;
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};
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static void fdctrl_external_reset_isa(DeviceState *d)
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{
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FDCtrlISABus *isa = ISA_FDC(d);
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FDCtrl *s = &isa->state;
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fdctrl_reset(s, 0);
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}
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void isa_fdc_init_drives(ISADevice *fdc, DriveInfo **fds)
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{
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fdctrl_init_drives(&ISA_FDC(fdc)->state.bus, fds);
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}
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static const MemoryRegionPortio fdc_portio_list[] = {
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{ 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
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{ 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
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PORTIO_END_OF_LIST(),
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};
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static void isabus_fdc_realize(DeviceState *dev, Error **errp)
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{
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ISADevice *isadev = ISA_DEVICE(dev);
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2023-02-15 17:36:42 +03:00
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ISABus *bus = isa_bus_from_device(isadev);
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2021-06-14 22:32:18 +03:00
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FDCtrlISABus *isa = ISA_FDC(dev);
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FDCtrl *fdctrl = &isa->state;
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Error *err = NULL;
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2024-01-14 15:39:01 +03:00
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isa_register_portio_list(isadev, &isa->portio_list,
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2021-06-14 22:32:18 +03:00
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isa->iobase, fdc_portio_list, fdctrl,
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"fdc");
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2023-02-15 17:36:42 +03:00
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fdctrl->irq = isa_bus_get_irq(bus, isa->irq);
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2021-06-14 22:32:18 +03:00
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fdctrl->dma_chann = isa->dma;
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if (fdctrl->dma_chann != -1) {
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IsaDmaClass *k;
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2023-02-15 17:36:42 +03:00
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fdctrl->dma = isa_bus_get_dma(bus, isa->dma);
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2021-06-14 22:32:18 +03:00
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if (!fdctrl->dma) {
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error_setg(errp, "ISA controller does not support DMA");
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return;
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}
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k = ISADMA_GET_CLASS(fdctrl->dma);
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k->register_channel(fdctrl->dma, fdctrl->dma_chann,
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&fdctrl_transfer_handler, fdctrl);
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}
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qdev_set_legacy_instance_id(dev, isa->iobase, 2);
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fdctrl_realize_common(dev, fdctrl, &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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}
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FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
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{
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FDCtrlISABus *isa = ISA_FDC(fdc);
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return isa->state.drives[i].drive;
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}
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static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc,
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uint8_t *maxh, uint8_t *maxs)
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{
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const FDFormat *fdf;
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*maxc = *maxh = *maxs = 0;
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for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
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if (fdf->drive != type) {
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continue;
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}
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if (*maxc < fdf->max_track) {
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*maxc = fdf->max_track;
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}
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if (*maxh < fdf->max_head) {
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*maxh = fdf->max_head;
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}
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if (*maxs < fdf->last_sect) {
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*maxs = fdf->last_sect;
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}
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}
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(*maxc)--;
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}
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static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
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{
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Aml *dev, *fdi;
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uint8_t maxc, maxh, maxs;
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isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
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dev = aml_device("FLP%c", 'A' + idx);
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aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
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fdi = aml_package(16);
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aml_append(fdi, aml_int(idx)); /* Drive Number */
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aml_append(fdi,
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aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
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/*
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* the values below are the limits of the drive, and are thus independent
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* of the inserted media
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*/
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aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
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aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
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aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
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/*
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* SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
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* the drive type, so shall we
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*/
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aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
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aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
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aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
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aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
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aml_append(fdi, aml_int(0x12)); /* disk_eot */
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aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
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aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
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aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
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aml_append(fdi, aml_int(0xF6)); /* disk_fill */
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aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
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aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
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aml_append(dev, aml_name_decl("_FDI", fdi));
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return dev;
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}
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2024-01-14 15:39:07 +03:00
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void isa_fdc_set_iobase(ISADevice *fdc, hwaddr iobase)
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{
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FDCtrlISABus *isa = ISA_FDC(fdc);
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fdc->ioport_id = iobase;
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isa->iobase = iobase;
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portio_list_set_address(&isa->portio_list, isa->iobase);
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}
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void isa_fdc_set_enabled(ISADevice *fdc, bool enabled)
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{
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portio_list_set_enabled(&ISA_FDC(fdc)->portio_list, enabled);
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}
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2021-06-14 22:32:18 +03:00
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int cmos_get_fd_drive_type(FloppyDriveType fd0)
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{
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int val;
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switch (fd0) {
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case FLOPPY_DRIVE_TYPE_144:
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case FLOPPY_DRIVE_TYPE_288:
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case FLOPPY_DRIVE_TYPE_120:
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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case FLOPPY_DRIVE_TYPE_NONE:
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default:
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val = 0;
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break;
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}
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return val;
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}
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2022-06-08 16:53:08 +03:00
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static void build_fdc_aml(AcpiDevAmlIf *adev, Aml *scope)
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2021-06-14 22:32:18 +03:00
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{
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2022-06-08 16:53:08 +03:00
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FDCtrlISABus *isa = ISA_FDC(adev);
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2021-06-14 22:32:18 +03:00
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Aml *dev;
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Aml *crs;
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int i;
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#define ACPI_FDE_MAX_FD 4
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uint32_t fde_buf[5] = {
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0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
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cpu_to_le32(2) /* tape presence (2 == never present) */
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};
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crs = aml_resource_template();
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aml_append(crs,
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2022-02-09 22:15:58 +03:00
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aml_io(AML_DECODE16, isa->iobase + 2, isa->iobase + 2, 0x00, 0x04));
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aml_append(crs,
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aml_io(AML_DECODE16, isa->iobase + 7, isa->iobase + 7, 0x00, 0x01));
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aml_append(crs, aml_irq_no_flags(isa->irq));
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aml_append(crs,
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aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, isa->dma));
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2021-06-14 22:32:18 +03:00
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dev = aml_device("FDC0");
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aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
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aml_append(dev, aml_name_decl("_CRS", crs));
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for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
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2022-06-08 16:53:08 +03:00
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FloppyDriveType type = isa_fdc_get_drive_type(ISA_DEVICE(adev), i);
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2021-06-14 22:32:18 +03:00
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if (type < FLOPPY_DRIVE_TYPE_NONE) {
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fde_buf[i] = cpu_to_le32(1); /* drive present */
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aml_append(dev, build_fdinfo_aml(i, type));
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}
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}
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aml_append(dev, aml_name_decl("_FDE",
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aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
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aml_append(scope, dev);
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}
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static const VMStateDescription vmstate_isa_fdc = {
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.name = "fdc",
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.version_id = 2,
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.minimum_version_id = 2,
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2023-12-21 06:16:05 +03:00
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.fields = (const VMStateField[]) {
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2021-06-14 22:32:18 +03:00
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VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property isa_fdc_properties[] = {
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DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
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DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
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DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
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DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
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FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
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FloppyDriveType),
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DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
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FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
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FloppyDriveType),
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DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
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FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
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FloppyDriveType),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void isabus_fdc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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2022-06-08 16:53:08 +03:00
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AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
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2021-06-14 22:32:18 +03:00
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2021-06-14 22:32:20 +03:00
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dc->desc = "virtual floppy controller";
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2021-06-14 22:32:18 +03:00
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dc->realize = isabus_fdc_realize;
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dc->fw_name = "fdc";
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dc->reset = fdctrl_external_reset_isa;
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dc->vmsd = &vmstate_isa_fdc;
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2022-06-08 16:53:08 +03:00
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adevc->build_dev_aml = build_fdc_aml;
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2021-06-14 22:32:18 +03:00
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device_class_set_props(dc, isa_fdc_properties);
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static void isabus_fdc_instance_init(Object *obj)
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{
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FDCtrlISABus *isa = ISA_FDC(obj);
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device_add_bootindex_property(obj, &isa->bootindexA,
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"bootindexA", "/floppy@0",
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DEVICE(obj));
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device_add_bootindex_property(obj, &isa->bootindexB,
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"bootindexB", "/floppy@1",
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DEVICE(obj));
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}
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static const TypeInfo isa_fdc_info = {
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.name = TYPE_ISA_FDC,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(FDCtrlISABus),
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.class_init = isabus_fdc_class_init,
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.instance_init = isabus_fdc_instance_init,
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2022-06-08 16:53:08 +03:00
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_ACPI_DEV_AML_IF },
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{ },
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},
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2021-06-14 22:32:18 +03:00
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};
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static void isa_fdc_register_types(void)
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{
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type_register_static(&isa_fdc_info);
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}
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type_init(isa_fdc_register_types)
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