2010-10-20 12:18:53 +04:00
|
|
|
/*
|
|
|
|
* ioh3420.c
|
|
|
|
* Intel X58 north bridge IOH
|
|
|
|
* PCI Express root port device id 3420
|
|
|
|
*
|
|
|
|
* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
|
|
|
|
* VA Linux Systems Japan K.K.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License along
|
|
|
|
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
2016-01-26 21:17:15 +03:00
|
|
|
#include "qemu/osdep.h"
|
2013-02-04 18:40:22 +04:00
|
|
|
#include "hw/pci/pci_ids.h"
|
|
|
|
#include "hw/pci/msi.h"
|
|
|
|
#include "hw/pci/pcie.h"
|
2018-10-11 00:53:54 +03:00
|
|
|
#include "hw/pci/pcie_port.h"
|
2010-10-20 12:18:53 +04:00
|
|
|
|
|
|
|
#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */
|
|
|
|
#define PCI_DEVICE_ID_IOH_REV 0x2
|
|
|
|
#define IOH_EP_SSVID_OFFSET 0x40
|
|
|
|
#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
|
|
|
|
#define IOH_EP_SSVID_SSID 0
|
|
|
|
#define IOH_EP_MSI_OFFSET 0x60
|
|
|
|
#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
|
|
|
|
#define IOH_EP_MSI_NR_VECTOR 2
|
|
|
|
#define IOH_EP_EXP_OFFSET 0x90
|
|
|
|
#define IOH_EP_AER_OFFSET 0x100
|
|
|
|
|
2010-11-16 11:26:10 +03:00
|
|
|
/*
|
|
|
|
* If two MSI vector are allocated, Advanced Error Interrupt Message Number
|
|
|
|
* is 1. otherwise 0.
|
|
|
|
* 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
|
|
|
|
*/
|
|
|
|
static uint8_t ioh3420_aer_vector(const PCIDevice *d)
|
|
|
|
{
|
|
|
|
switch (msi_nr_vectors_allocated(d)) {
|
|
|
|
case 1:
|
|
|
|
return 0;
|
|
|
|
case 2:
|
|
|
|
return 1;
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
case 16:
|
|
|
|
case 32:
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
abort();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-01-23 22:20:19 +03:00
|
|
|
static int ioh3420_interrupts_init(PCIDevice *d, Error **errp)
|
2010-11-16 11:26:10 +03:00
|
|
|
{
|
2010-10-20 12:18:53 +04:00
|
|
|
int rc;
|
2016-06-10 12:54:23 +03:00
|
|
|
|
2010-10-20 12:18:53 +04:00
|
|
|
rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
|
|
|
|
IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
|
2017-01-23 22:20:19 +03:00
|
|
|
IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
|
2017-09-09 09:22:26 +03:00
|
|
|
errp);
|
2010-10-20 12:18:53 +04:00
|
|
|
if (rc < 0) {
|
2016-06-20 09:13:39 +03:00
|
|
|
assert(rc == -ENOTSUP);
|
2010-10-20 12:18:53 +04:00
|
|
|
}
|
2016-06-10 12:54:23 +03:00
|
|
|
|
2010-11-16 11:26:10 +03:00
|
|
|
return rc;
|
2010-10-20 12:18:53 +04:00
|
|
|
}
|
|
|
|
|
2017-01-23 22:20:19 +03:00
|
|
|
static void ioh3420_interrupts_uninit(PCIDevice *d)
|
2010-10-20 12:18:53 +04:00
|
|
|
{
|
2010-11-16 11:26:10 +03:00
|
|
|
msi_uninit(d);
|
2010-10-20 12:18:53 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_ioh3420 = {
|
|
|
|
.name = "ioh-3240-express-root-port",
|
pci/bus: let it has higher migration priority
In the past, we prioritized IOMMU migration so that we have such a
priority order:
IOMMU > PCI Devices
When migrating a guest with both vIOMMU and a pcie-root-port, we'll
always migrate vIOMMU first, since pci buses will be seen to have the
same priority of general PCI devices.
That's problematic.
The thing is that PCI bus number information is stored in the root port,
and that is needed by vIOMMU during post_load(), e.g., to figure out
context entry for a device. If we don't have correct bus numbers for
devices, we won't be able to recover device state of the DMAR memory
regions, and things will be messed up.
So let's boost the PCIe root ports to be even with higher priority:
PCIe Root Port > IOMMU > PCI Devices
A smoke test shows that this patch fixes bug 1538953.
Also, apply this rule to all the PCI bus/bridge devices: ioh3420,
xio3130_downstream, xio3130_upstream, pcie_pci_bridge, pci-pci bridge,
i82801b11.
I noted that we set pcie_pci_bridge_dev_vmstate twice. Clean that up
together.
CC: Alex Williamson <alex.williamson@redhat.com>
CC: Marcel Apfelbaum <marcel@redhat.com>
CC: Michael S. Tsirkin <mst@redhat.com>
CC: Dr. David Alan Gilbert <dgilbert@redhat.com>
CC: Juan Quintela <quintela@redhat.com>
CC: Laurent Vivier <lvivier@redhat.com>
Bug: https://bugzilla.redhat.com/show_bug.cgi?id=1538953
Reported-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2018-02-06 10:39:33 +03:00
|
|
|
.priority = MIG_PRI_PCI_BUS,
|
2010-10-20 12:18:53 +04:00
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2010-10-25 09:46:47 +04:00
|
|
|
.post_load = pcie_cap_slot_post_load,
|
2010-10-20 12:18:53 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2016-12-14 22:58:29 +03:00
|
|
|
VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
|
2013-07-12 21:56:00 +04:00
|
|
|
VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
|
|
|
|
PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
|
2010-10-20 12:18:53 +04:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2011-12-04 22:22:06 +04:00
|
|
|
static void ioh3420_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2017-01-23 22:20:19 +03:00
|
|
|
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
|
2011-12-04 22:22:06 +04:00
|
|
|
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_INTEL;
|
|
|
|
k->device_id = PCI_DEVICE_ID_IOH_EPORT;
|
|
|
|
k->revision = PCI_DEVICE_ID_IOH_REV;
|
2011-12-08 07:34:16 +04:00
|
|
|
dc->desc = "Intel IOH device id 3420 PCIE Root Port";
|
|
|
|
dc->vmsd = &vmstate_ioh3420;
|
2017-01-23 22:20:19 +03:00
|
|
|
rpc->aer_vector = ioh3420_aer_vector;
|
|
|
|
rpc->interrupts_init = ioh3420_interrupts_init;
|
|
|
|
rpc->interrupts_uninit = ioh3420_interrupts_uninit;
|
|
|
|
rpc->exp_offset = IOH_EP_EXP_OFFSET;
|
|
|
|
rpc->aer_offset = IOH_EP_AER_OFFSET;
|
|
|
|
rpc->ssvid_offset = IOH_EP_SSVID_OFFSET;
|
|
|
|
rpc->ssid = IOH_EP_SSVID_SSID;
|
2011-12-04 22:22:06 +04:00
|
|
|
}
|
|
|
|
|
2013-01-10 19:19:07 +04:00
|
|
|
static const TypeInfo ioh3420_info = {
|
2011-12-08 07:34:16 +04:00
|
|
|
.name = "ioh3420",
|
2017-01-23 22:20:19 +03:00
|
|
|
.parent = TYPE_PCIE_ROOT_PORT,
|
2011-12-08 07:34:16 +04:00
|
|
|
.class_init = ioh3420_class_init,
|
2010-10-20 12:18:53 +04:00
|
|
|
};
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
static void ioh3420_register_types(void)
|
2010-10-20 12:18:53 +04:00
|
|
|
{
|
2011-12-08 07:34:16 +04:00
|
|
|
type_register_static(&ioh3420_info);
|
2010-10-20 12:18:53 +04:00
|
|
|
}
|
|
|
|
|
2012-02-09 18:20:55 +04:00
|
|
|
type_init(ioh3420_register_types)
|