mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
0bbf0f7acf
qemu/tcg/s390x/tcg-target-con-set.h

43 lines
905 B
C
Raw Normal View History

tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
/* SPDX-License-Identifier: MIT */
/*
* Define S390 target-specific constraint sets.
* Copyright (c) 2021 Linaro
*/
/*
* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
* Each operand should be a sequence of constraint letters as defined by
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(L, L)
C_O0_I2(r, r)
C_O0_I2(r, ri)
tcg/s390x: Add host vector framework Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 02:33:14 +03:00
C_O0_I2(v, r)
tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
C_O1_I1(r, L)
C_O1_I1(r, r)
tcg/s390x: Add host vector framework Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 02:33:14 +03:00
C_O1_I1(v, r)
tcg/s390x: Implement andc, orc, abs, neg, not vector operations These logical and arithmetic operations are optional but trivial. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 04:23:16 +03:00
C_O1_I1(v, v)
tcg/s390x: Add host vector framework Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 02:33:14 +03:00
C_O1_I1(v, vr)
tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
C_O1_I2(r, 0, ri)
C_O1_I2(r, 0, rI)
C_O1_I2(r, 0, rJ)
tcg/s390x: Support MIE3 logical operations This is andc, orc, nand, nor, eqv. We can use nor for implementing not. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-24 03:04:25 +03:00
C_O1_I2(r, r, r)
tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
C_O1_I2(r, r, ri)
tcg/s390x: Support MIE2 multiply single instructions The MIE2 facility adds 3-operand versions of multiply. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-24 04:28:44 +03:00
C_O1_I2(r, r, rJ)
tcg/s390x: Tighten constraints for or_i64 and xor_i64 Drop support for sequential OR and XOR, as the serial dependency is slower than loading the constant first. Let the register allocator handle such immediates by matching only what one insn can achieve. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-08 20:28:19 +03:00
C_O1_I2(r, r, rK)
tcg/s390x: Support MIE3 logical operations This is andc, orc, nand, nor, eqv. We can use nor for implementing not. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-24 03:04:25 +03:00
C_O1_I2(r, r, rKR)
C_O1_I2(r, r, rNK)
tcg/s390x: Tighten constraints for and_i64 Let the register allocator handle such immediates by matching only what one insn can achieve. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-12-08 21:06:03 +03:00
C_O1_I2(r, r, rNKR)
tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
C_O1_I2(r, rZ, r)
tcg/s390x: Implement vector shift operations Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 05:00:38 +03:00
C_O1_I2(v, v, r)
tcg/s390x: Add host vector framework Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 02:33:14 +03:00
C_O1_I2(v, v, v)
tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-15 06:36:36 +03:00
C_O1_I3(v, v, v, v)
tcg/s390x: Generalize movcond implementation Generalize movcond to support pre-computed conditions, and the same set of arguments at all times. This will be assumed by a following patch, which needs to reuse tgen_movcond_int. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-24 03:24:05 +03:00
C_O1_I4(r, r, ri, rI, r)
tcg/s390x: Use register pair allocation for div and mulu2 Previously we hard-coded R2 and R3. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-10 18:41:15 +03:00
C_O2_I2(o, m, 0, r)
tcg/s390x: Support MIE2 MGRK instruction The MIE2 facility adds a 3-operand signed 64x64->128 multiply. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-24 04:35:43 +03:00
C_O2_I2(o, m, r, r)
tcg/s390x: Use register pair allocation for div and mulu2 Previously we hard-coded R2 and R3. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-10-10 18:41:15 +03:00
C_O2_I3(o, m, 0, 1, r)
tcg/s390: Split out constraint sets to tcg-target-con-set.h Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-17 21:15:40 +03:00
C_O2_I4(r, r, 0, 1, rA, r)
C_O2_I4(r, r, 0, 1, ri, r)
C_O2_I4(r, r, 0, 1, r, r)
Reference in New Issue Copy Permalink