2022-06-16 17:51:24 +03:00
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/*
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* Emulated CXL Switch Upstream Port
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*
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* Copyright (c) 2022 Huawei Technologies.
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*
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* Based on xio3130_upstream.c
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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2022-10-14 18:10:45 +03:00
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#include "hw/qdev-properties.h"
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2022-06-16 17:51:24 +03:00
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_port.h"
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2022-10-14 18:10:45 +03:00
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#define CXL_UPSTREAM_PORT_MSI_NR_VECTOR 2
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2022-06-16 17:51:24 +03:00
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#define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70
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#define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90
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#define CXL_UPSTREAM_PORT_AER_OFFSET 0x100
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#define CXL_UPSTREAM_PORT_DVSEC_OFFSET \
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(CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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typedef struct CXLUpstreamPort {
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/*< private >*/
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PCIEPort parent_obj;
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/*< public >*/
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CXLComponentState cxl_cstate;
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2022-10-14 18:10:45 +03:00
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DOECap doe_cdat;
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2022-06-16 17:51:24 +03:00
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} CXLUpstreamPort;
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CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp)
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{
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return &usp->cxl_cstate;
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}
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static void cxl_usp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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CXLUpstreamPort *usp = CXL_USP(dev);
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if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
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uint8_t *reg = &dev->config[addr];
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addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
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if (addr == PORT_CONTROL_OFFSET) {
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if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
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/* unmask SBR */
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qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
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}
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if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
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/* Alt Memory & ID Space Enable */
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qemu_log_mask(LOG_UNIMP,
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"Alt Memory & ID space is not supported\n");
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}
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}
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}
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}
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static void cxl_usp_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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2022-10-14 18:10:45 +03:00
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CXLUpstreamPort *usp = CXL_USP(d);
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pcie_doe_write_config(&usp->doe_cdat, address, val, len);
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2022-06-16 17:51:24 +03:00
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pci_bridge_write_config(d, address, val, len);
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pcie_cap_flr_write_config(d, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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cxl_usp_dvsec_write_config(d, address, val, len);
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}
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2022-10-14 18:10:45 +03:00
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static uint32_t cxl_usp_read_config(PCIDevice *d, uint32_t address, int len)
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{
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CXLUpstreamPort *usp = CXL_USP(d);
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uint32_t val;
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if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) {
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return val;
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}
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return pci_default_read_config(d, address, len);
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}
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2022-06-16 17:51:24 +03:00
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static void latch_registers(CXLUpstreamPort *usp)
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{
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uint32_t *reg_state = usp->cxl_cstate.crb.cache_mem_registers;
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uint32_t *write_msk = usp->cxl_cstate.crb.cache_mem_regs_write_mask;
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cxl_component_register_init_common(reg_state, write_msk,
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CXL2_UPSTREAM_PORT);
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ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8);
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}
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static void cxl_usp_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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CXLUpstreamPort *usp = CXL_USP(qdev);
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pci_bridge_reset(qdev);
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pcie_cap_deverr_reset(d);
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latch_registers(usp);
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}
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static void build_dvsecs(CXLComponentState *cxl)
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{
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uint8_t *dvsec;
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dvsec = (uint8_t *)&(CXLDVSECPortExtensions){
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.status = 0x1, /* Port Power Management Init Complete */
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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EXTENSIONS_PORT_DVSEC_LENGTH,
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EXTENSIONS_PORT_DVSEC,
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EXTENSIONS_PORT_DVSEC_REVID, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
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.cap = 0x27, /* Cache, IO, Mem, non-MLD */
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.ctrl = 0x27, /* Cache, IO, Mem */
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.status = 0x26, /* same */
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.rcvd_mod_ts_data_phase1 = 0xef, /* WTF? */
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
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PCIE_FLEXBUS_PORT_DVSEC,
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PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
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dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
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.rsvd = 0,
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.reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
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.reg0_base_hi = 0,
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};
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cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
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REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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REG_LOC_DVSEC_REVID, dvsec);
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}
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2022-10-14 18:10:45 +03:00
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static bool cxl_doe_cdat_rsp(DOECap *doe_cap)
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{
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CDATObject *cdat = &CXL_USP(doe_cap->pdev)->cxl_cstate.cdat;
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uint16_t ent;
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void *base;
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uint32_t len;
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CDATReq *req = pcie_doe_get_write_mbox_ptr(doe_cap);
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CDATRsp rsp;
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cxl_doe_cdat_update(&CXL_USP(doe_cap->pdev)->cxl_cstate, &error_fatal);
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assert(cdat->entry_len);
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/* Discard if request length mismatched */
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if (pcie_doe_get_obj_len(req) <
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DIV_ROUND_UP(sizeof(CDATReq), sizeof(uint32_t))) {
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return false;
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}
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ent = req->entry_handle;
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base = cdat->entry[ent].base;
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len = cdat->entry[ent].length;
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rsp = (CDATRsp) {
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.header = {
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.vendor_id = CXL_VENDOR_ID,
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.data_obj_type = CXL_DOE_TABLE_ACCESS,
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.reserved = 0x0,
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.length = DIV_ROUND_UP((sizeof(rsp) + len), sizeof(uint32_t)),
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},
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.rsp_code = CXL_DOE_TAB_RSP,
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.table_type = CXL_DOE_TAB_TYPE_CDAT,
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.entry_handle = (ent < cdat->entry_len - 1) ?
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ent + 1 : CXL_DOE_TAB_ENT_MAX,
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};
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memcpy(doe_cap->read_mbox, &rsp, sizeof(rsp));
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memcpy(doe_cap->read_mbox + DIV_ROUND_UP(sizeof(rsp), sizeof(uint32_t)),
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base, len);
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doe_cap->read_mbox_len += rsp.header.length;
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return true;
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}
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static DOEProtocol doe_cdat_prot[] = {
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{ CXL_VENDOR_ID, CXL_DOE_TABLE_ACCESS, cxl_doe_cdat_rsp },
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{ }
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};
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enum {
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CXL_USP_CDAT_SSLBIS_LAT,
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CXL_USP_CDAT_SSLBIS_BW,
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CXL_USP_CDAT_NUM_ENTRIES
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};
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static int build_cdat_table(CDATSubHeader ***cdat_table, void *priv)
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{
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g_autofree CDATSslbis *sslbis_latency = NULL;
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g_autofree CDATSslbis *sslbis_bandwidth = NULL;
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CXLUpstreamPort *us = CXL_USP(priv);
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PCIBus *bus = &PCI_BRIDGE(us)->sec_bus;
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int devfn, sslbis_size, i;
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int count = 0;
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uint16_t port_ids[256];
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for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
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PCIDevice *d = bus->devices[devfn];
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PCIEPort *port;
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if (!d || !pci_is_express(d) || !d->exp.exp_cap) {
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continue;
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}
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/*
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* Whilst the PCI express spec doesn't allow anything other than
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* downstream ports on this bus, let us be a little paranoid
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*/
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if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) {
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continue;
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}
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port = PCIE_PORT(d);
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port_ids[count] = port->port;
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count++;
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}
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/* May not yet have any ports - try again later */
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if (count == 0) {
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return 0;
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}
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sslbis_size = sizeof(CDATSslbis) + sizeof(*sslbis_latency->sslbe) * count;
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sslbis_latency = g_malloc(sslbis_size);
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if (!sslbis_latency) {
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return -ENOMEM;
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}
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*sslbis_latency = (CDATSslbis) {
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.sslbis_header = {
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.header = {
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.type = CDAT_TYPE_SSLBIS,
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.length = sslbis_size,
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},
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.data_type = HMATLB_DATA_TYPE_ACCESS_LATENCY,
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.entry_base_unit = 10000,
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},
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};
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for (i = 0; i < count; i++) {
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sslbis_latency->sslbe[i] = (CDATSslbe) {
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.port_x_id = CDAT_PORT_ID_USP,
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.port_y_id = port_ids[i],
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.latency_bandwidth = 15, /* 150ns */
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};
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}
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sslbis_bandwidth = g_malloc(sslbis_size);
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if (!sslbis_bandwidth) {
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return 0;
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}
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*sslbis_bandwidth = (CDATSslbis) {
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.sslbis_header = {
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.header = {
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.type = CDAT_TYPE_SSLBIS,
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.length = sslbis_size,
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},
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.data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH,
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.entry_base_unit = 1000,
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},
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};
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for (i = 0; i < count; i++) {
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sslbis_bandwidth->sslbe[i] = (CDATSslbe) {
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.port_x_id = CDAT_PORT_ID_USP,
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.port_y_id = port_ids[i],
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.latency_bandwidth = 16, /* 16 GB/s */
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};
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}
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*cdat_table = g_malloc0(sizeof(*cdat_table) * CXL_USP_CDAT_NUM_ENTRIES);
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if (!*cdat_table) {
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return -ENOMEM;
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}
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/* Header always at start of structure */
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(*cdat_table)[CXL_USP_CDAT_SSLBIS_LAT] = g_steal_pointer(&sslbis_latency);
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(*cdat_table)[CXL_USP_CDAT_SSLBIS_BW] = g_steal_pointer(&sslbis_bandwidth);
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return CXL_USP_CDAT_NUM_ENTRIES;
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}
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static void free_default_cdat_table(CDATSubHeader **cdat_table, int num,
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void *priv)
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{
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int i;
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for (i = 0; i < num; i++) {
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g_free(cdat_table[i]);
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}
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g_free(cdat_table);
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}
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2022-06-16 17:51:24 +03:00
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static void cxl_usp_realize(PCIDevice *d, Error **errp)
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{
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PCIEPort *p = PCIE_PORT(d);
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CXLUpstreamPort *usp = CXL_USP(d);
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CXLComponentState *cxl_cstate = &usp->cxl_cstate;
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ComponentRegisters *cregs = &cxl_cstate->crb;
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MemoryRegion *component_bar = &cregs->component_registers;
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int rc;
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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pcie_port_init_reg(d);
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rc = msi_init(d, CXL_UPSTREAM_PORT_MSI_OFFSET,
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CXL_UPSTREAM_PORT_MSI_NR_VECTOR, true, true, errp);
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if (rc) {
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assert(rc == -ENOTSUP);
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goto err_bridge;
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}
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rc = pcie_cap_init(d, CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET,
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PCI_EXP_TYPE_UPSTREAM, p->port, errp);
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if (rc < 0) {
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goto err_msi;
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}
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pcie_cap_flr_init(d);
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pcie_cap_deverr_init(d);
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rc = pcie_aer_init(d, PCI_ERR_VER, CXL_UPSTREAM_PORT_AER_OFFSET,
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PCI_ERR_SIZEOF, errp);
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if (rc) {
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goto err_cap;
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}
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cxl_cstate->dvsec_offset = CXL_UPSTREAM_PORT_DVSEC_OFFSET;
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cxl_cstate->pdev = d;
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build_dvsecs(cxl_cstate);
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cxl_component_register_block_init(OBJECT(d), cxl_cstate, TYPE_CXL_USP);
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pci_register_bar(d, CXL_COMPONENT_REG_BAR_IDX,
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64,
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component_bar);
|
|
|
|
|
2022-10-14 18:10:45 +03:00
|
|
|
pcie_doe_init(d, &usp->doe_cdat, cxl_cstate->dvsec_offset, doe_cdat_prot,
|
|
|
|
true, 1);
|
|
|
|
|
|
|
|
cxl_cstate->cdat.build_cdat_table = build_cdat_table;
|
|
|
|
cxl_cstate->cdat.free_cdat_table = free_default_cdat_table;
|
|
|
|
cxl_cstate->cdat.private = d;
|
|
|
|
cxl_doe_cdat_init(cxl_cstate, errp);
|
|
|
|
|
2022-06-16 17:51:24 +03:00
|
|
|
return;
|
|
|
|
|
|
|
|
err_cap:
|
|
|
|
pcie_cap_exit(d);
|
|
|
|
err_msi:
|
|
|
|
msi_uninit(d);
|
|
|
|
err_bridge:
|
|
|
|
pci_bridge_exitfn(d);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cxl_usp_exitfn(PCIDevice *d)
|
|
|
|
{
|
|
|
|
pcie_aer_exit(d);
|
|
|
|
pcie_cap_exit(d);
|
|
|
|
msi_uninit(d);
|
|
|
|
pci_bridge_exitfn(d);
|
|
|
|
}
|
|
|
|
|
2022-10-14 18:10:45 +03:00
|
|
|
static Property cxl_upstream_props[] = {
|
|
|
|
DEFINE_PROP_STRING("cdat", CXLUpstreamPort, cxl_cstate.cdat.filename),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2022-06-16 17:51:24 +03:00
|
|
|
static void cxl_upstream_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
k->is_bridge = true;
|
|
|
|
k->config_write = cxl_usp_write_config;
|
2022-10-14 18:10:45 +03:00
|
|
|
k->config_read = cxl_usp_read_config;
|
2022-06-16 17:51:24 +03:00
|
|
|
k->realize = cxl_usp_realize;
|
|
|
|
k->exit = cxl_usp_exitfn;
|
|
|
|
k->vendor_id = 0x19e5; /* Huawei */
|
|
|
|
k->device_id = 0xa128; /* Emulated CXL Switch Upstream Port */
|
|
|
|
k->revision = 0;
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
|
|
dc->desc = "CXL Switch Upstream Port";
|
|
|
|
dc->reset = cxl_usp_reset;
|
2022-10-14 18:10:45 +03:00
|
|
|
device_class_set_props(dc, cxl_upstream_props);
|
2022-06-16 17:51:24 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo cxl_usp_info = {
|
|
|
|
.name = TYPE_CXL_USP,
|
|
|
|
.parent = TYPE_PCIE_PORT,
|
|
|
|
.instance_size = sizeof(CXLUpstreamPort),
|
|
|
|
.class_init = cxl_upstream_class_init,
|
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_PCIE_DEVICE },
|
|
|
|
{ INTERFACE_CXL_DEVICE },
|
|
|
|
{ }
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void cxl_usp_register_type(void)
|
|
|
|
{
|
|
|
|
type_register_static(&cxl_usp_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(cxl_usp_register_type);
|