2006-05-13 20:11:23 +04:00
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/*
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* QEMU Common PCI Host bridge configuration data space access routines.
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*
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* Copyright (c) 2006 Fabrice Bellard
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2007-09-17 01:08:06 +04:00
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*
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2006-05-13 20:11:23 +04:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* Worker routines for a PCI host controller that uses an {address,data}
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register pair to access PCI configuration space. */
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2009-10-30 15:21:06 +03:00
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#ifndef PCI_HOST_H
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#define PCI_HOST_H
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2009-01-08 21:52:52 +03:00
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2012-12-13 01:05:42 +04:00
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#include "hw/sysbus.h"
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2020-09-03 23:43:22 +03:00
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#include "qom/object.h"
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2009-07-22 17:17:01 +04:00
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2012-08-20 21:08:07 +04:00
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#define TYPE_PCI_HOST_BRIDGE "pci-host-bridge"
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2020-09-16 21:25:18 +03:00
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OBJECT_DECLARE_TYPE(PCIHostState, PCIHostBridgeClass, PCI_HOST_BRIDGE)
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2012-08-20 21:08:07 +04:00
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2009-11-12 08:58:41 +03:00
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struct PCIHostState {
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2009-07-22 17:17:01 +04:00
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SysBusDevice busdev;
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2012-08-20 21:08:07 +04:00
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2011-07-24 18:47:18 +04:00
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MemoryRegion conf_mem;
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MemoryRegion data_mem;
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2011-11-21 19:16:57 +04:00
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MemoryRegion mmcfg;
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2006-05-13 20:11:23 +04:00
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uint32_t config_reg;
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hw/pci-host: save/restore pci host config register
The pci host config register is used to save PCI address for
read/write config data. If guest writes a value to config register,
and then QEMU pauses the vcpu to migrate, after the migration, the guest
will continue to write pci config data, and the write data will be ignored
because of new qemu process losing the config register state.
To trigger the bug:
1. guest is booting in seabios.
2. guest enables the SMRAM in seabios:piix4_apmc_smm_setup, and then
expects to disable the SMRAM by pci_config_writeb.
3. after guest writes the pci host config register, QEMU pauses vcpu
to finish migration.
4. guest write of config data(0x0A) fails to disable the SMRAM because
the config register state is lost.
5. guest continues to boot and crashes in ipxe option ROM due to SMRAM
in enabled state.
Example Reproducer:
step 1. Make modifications to seabios and qemu for increase reproduction
efficiency, write 0xf0 to 0x402 port notify qemu to stop vcpu after
0x0cf8 port wrote i440 configure register. qemu stop vcpu when catch
0x402 port wrote 0xf0.
seabios:/src/hw/pci.c
@@ -52,6 +52,11 @@ void pci_config_writeb(u16 bdf, u32 addr, u8 val)
writeb(mmconfig_addr(bdf, addr), val);
} else {
outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD);
+ if (bdf == 0 && addr == 0x72 && val == 0xa) {
+ dprintf(1, "stop vcpu\n");
+ outb(0xf0, 0x402); // notify qemu to stop vcpu
+ dprintf(1, "resume vcpu\n");
+ }
outb(val, PORT_PCI_DATA + (addr & 3));
}
}
qemu:hw/char/debugcon.c
@@ -60,6 +61,9 @@ static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
printf(" [debugcon: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val);
#endif
+ if (ch == 0xf0) {
+ vm_stop(RUN_STATE_PAUSED);
+ }
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(&s->chr, &ch, 1);
step 2. start vm1 by the following command line, and then vm stopped.
$ qemu-system-x86_64 -machine pc-i440fx-5.0,accel=kvm\
-netdev tap,ifname=tap-test,id=hostnet0,vhost=on,downscript=no,script=no\
-device virtio-net-pci,netdev=hostnet0,id=net0,bus=pci.0,addr=0x13,bootindex=3\
-device cirrus-vga,id=video0,vgamem_mb=16,bus=pci.0,addr=0x2\
-chardev file,id=seabios,path=/var/log/test.seabios,append=on\
-device isa-debugcon,iobase=0x402,chardev=seabios\
-monitor stdio
step 3. start vm2 to accept vm1 state.
$ qemu-system-x86_64 -machine pc-i440fx-5.0,accel=kvm\
-netdev tap,ifname=tap-test1,id=hostnet0,vhost=on,downscript=no,script=no\
-device virtio-net-pci,netdev=hostnet0,id=net0,bus=pci.0,addr=0x13,bootindex=3\
-device cirrus-vga,id=video0,vgamem_mb=16,bus=pci.0,addr=0x2\
-chardev file,id=seabios,path=/var/log/test.seabios,append=on\
-device isa-debugcon,iobase=0x402,chardev=seabios\
-monitor stdio \
-incoming tcp:127.0.0.1:8000
step 4. execute the following qmp command in vm1 to migrate.
(qemu) migrate tcp:127.0.0.1:8000
step 5. execute the following qmp command in vm2 to resume vcpu.
(qemu) cont
Before this patch, we get KVM "emulation failure" error on vm2.
This patch fixes it.
Cc: qemu-stable@nongnu.org
Signed-off-by: Hogan Wang <hogan.wang@huawei.com>
Message-Id: <20200727084621.3279-1-hogan.wang@huawei.com>
Reported-by: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2020-07-27 11:46:20 +03:00
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bool mig_enabled;
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2006-05-13 20:11:23 +04:00
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PCIBus *bus;
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2021-07-08 15:55:11 +03:00
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bool bypass_iommu;
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2013-06-06 12:48:54 +04:00
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QLIST_ENTRY(PCIHostState) next;
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2009-11-12 08:58:41 +03:00
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};
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2006-05-13 20:11:23 +04:00
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2020-09-03 23:43:22 +03:00
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struct PCIHostBridgeClass {
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2013-06-06 12:48:49 +04:00
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SysBusDeviceClass parent_class;
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const char *(*root_bus_path)(PCIHostState *, PCIBus *);
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2020-09-03 23:43:22 +03:00
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};
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2013-06-06 12:48:49 +04:00
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2011-07-22 13:05:01 +04:00
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/* common internal helpers for PCI/PCIe hosts, cut off overflows */
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void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t val, uint32_t len);
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uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t len);
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2019-12-16 03:21:34 +03:00
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void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len);
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uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len);
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2009-11-12 08:58:30 +03:00
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2011-07-24 18:47:18 +04:00
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extern const MemoryRegionOps pci_host_conf_le_ops;
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extern const MemoryRegionOps pci_host_conf_be_ops;
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extern const MemoryRegionOps pci_host_data_le_ops;
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extern const MemoryRegionOps pci_host_data_be_ops;
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2006-05-13 20:11:23 +04:00
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2009-10-30 15:21:06 +03:00
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#endif /* PCI_HOST_H */
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