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qemu/target/arm/sve.decode

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target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# AArch64 SVE instruction descriptions
#
# Copyright (c) 2017 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
target/arm: Implement SVE load vector/predicate Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
###########################################################################
# Named fields. These are primarily for disjoint fields.
%imm9_16_10 16:s6 10:3
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Either a copy of rd (at bit 0), or a different source
# as propagated via the MOVPRFX instruction.
%reg_movprfx 0:5
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
###########################################################################
# Named attribute sets. These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.
target/arm: Implement SVE Predicate Misc Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rr_esz rd rn esz
target/arm: Implement SVE load vector/predicate Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rri rd rn imm
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rrr_esz rd rn rm esz
target/arm: Implement SVE Integer Reduction Group Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rpr_esz rd pg rn esz
target/arm: Implement SVE Predicate Logical Operations Group Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rprr_s rd pg rn rm s
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
&rprr_esz rd pg rn rm esz
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
target/arm: Implement SVE Predicate Misc Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Three operand with unused vector element size
@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
target/arm: Implement SVE Predicate Logical Operations Group Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
&rprr_esz rm=%reg_movprfx
target/arm: Implement SVE Integer Reduction Group Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# One register operand, with governing predicate, vector element size
@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
target/arm: Implement SVE load vector/predicate Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# Basic Load/Store with 9-bit immediate offset
@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
&rri imm=%imm9_16_10
@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
&rri imm=%imm9_16_10
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Integer Arithmetic - Binary Predicated Group
# SVE bitwise logical vector operations (predicated)
ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
# SVE integer add/subtract vectors (predicated)
ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
# SVE integer min/max/difference (predicated)
SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
# SVE integer multiply/divide (predicated)
MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
# Note that divide requires size >= 2; below 2 is unallocated.
SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
target/arm: Implement SVE Integer Reduction Group Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Integer Reduction Group
# SVE bitwise logical reduction (predicated)
ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
# SVE integer add reduction (predicated)
# Note that saddv requires size != 3.
UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
# SVE integer min/max reduction (predicated)
SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
target/arm: Add SVE decode skeleton Including only 4, as-yet unimplemented, instruction patterns so that the whole thing compiles. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)
AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
target/arm: Implement SVE load vector/predicate Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
target/arm: Implement SVE Predicate Logical Operations Group Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Predicate Logical Operations Group
# SVE predicate logical operations
AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
target/arm: Implement SVE predicate test Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Predicate Misc Group
# SVE predicate test
PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
target/arm: Implement SVE Predicate Misc Group Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
# SVE predicate initialize
PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
# SVE initialize FFR
SETFFR 00100101 0010 1100 1001 0000 0000 0000
# SVE zero predicate register
PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
# SVE predicate read from FFR (predicated)
RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
# SVE predicate read from FFR (unpredicated)
RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
# SVE FFR write from predicate (WRFFR)
WRFFR 00100101 0010 1000 1001 000 rn:4 00000
# SVE predicate first active
PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
# SVE predicate next active
PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
target/arm: Implement SVE load vector/predicate Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-18 19:48:08 +03:00
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register
LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
# SVE load vector register
LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
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