866 lines
28 KiB
C
866 lines
28 KiB
C
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/*
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* QEMU ATI SVGA emulation
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*
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* Copyright (c) 2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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/*
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* WARNING:
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* This is very incomplete and only enough for Linux console and some
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* unaccelerated X output at the moment.
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* Currently it's little more than a frame buffer with minimal functions,
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* other more advanced features of the hardware are yet to be implemented.
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* We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
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* No 3D at all yet (maybe after 2D works, but feel free to improve it)
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*/
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#include "ati_int.h"
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#include "ati_regs.h"
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#include "vga_regs.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "ui/console.h"
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#include "trace.h"
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#define ATI_DEBUG_HW_CURSOR 0
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static const struct {
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const char *name;
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uint16_t dev_id;
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} ati_model_aliases[] = {
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{ "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF },
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{ "rv100", PCI_DEVICE_ID_ATI_RADEON_QY },
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};
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enum { VGA_MODE, EXT_MODE };
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static void ati_vga_switch_mode(ATIVGAState *s)
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{
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DPRINTF("%d -> %d\n",
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s->mode, !!(s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN));
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if (s->regs.crtc_gen_cntl & CRTC2_EXT_DISP_EN) {
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/* Extended mode enabled */
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s->mode = EXT_MODE;
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if (s->regs.crtc_gen_cntl & CRTC2_EN) {
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/* CRT controller enabled, use CRTC values */
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uint32_t offs = s->regs.crtc_offset & 0x07ffffff;
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int stride = (s->regs.crtc_pitch & 0x7ff) * 8;
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int bpp = 0;
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int h, v;
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if (s->regs.crtc_h_total_disp == 0) {
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s->regs.crtc_h_total_disp = ((640 / 8) - 1) << 16;
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}
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if (s->regs.crtc_v_total_disp == 0) {
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s->regs.crtc_v_total_disp = (480 - 1) << 16;
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}
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h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
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v = (s->regs.crtc_v_total_disp >> 16) + 1;
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switch (s->regs.crtc_gen_cntl & CRTC_PIX_WIDTH_MASK) {
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case CRTC_PIX_WIDTH_4BPP:
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bpp = 4;
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break;
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case CRTC_PIX_WIDTH_8BPP:
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bpp = 8;
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break;
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case CRTC_PIX_WIDTH_15BPP:
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bpp = 15;
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break;
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case CRTC_PIX_WIDTH_16BPP:
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bpp = 16;
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break;
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case CRTC_PIX_WIDTH_24BPP:
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bpp = 24;
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break;
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case CRTC_PIX_WIDTH_32BPP:
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bpp = 32;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Unsupported bpp value\n");
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}
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assert(bpp != 0);
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DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs);
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
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vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
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/* reset VBE regs then set up mode */
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s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h;
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s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v;
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s->vga.vbe_regs[VBE_DISPI_INDEX_BPP] = bpp;
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/* enable mode via ioport so it updates vga regs */
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
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vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED |
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VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM |
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(s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));
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/* now set offset and stride after enable as that resets these */
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if (stride) {
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);
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vbe_ioport_write_data(&s->vga, 0, stride);
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if (offs % stride == 0) {
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);
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vbe_ioport_write_data(&s->vga, 0, offs / stride);
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} else {
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/* FIXME what to do with this? */
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error_report("VGA offset is not multiple of pitch, "
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"expect bad picture");
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}
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}
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}
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} else {
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/* VGA mode enabled */
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s->mode = VGA_MODE;
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vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE);
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vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED);
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}
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}
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/* Used by host side hardware cursor */
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static void ati_cursor_define(ATIVGAState *s)
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{
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uint8_t data[1024];
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uint8_t *src;
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int i, j, idx = 0;
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if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) {
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return; /* Do not update cursor if locked or rendered by guest */
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}
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/* FIXME handle cur_hv_offs correctly */
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src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
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s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
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(s->regs.cur_hv_offs & 0xffff) * 16;
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for (i = 0; i < 64; i++) {
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for (j = 0; j < 8; j++, idx++) {
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data[idx] = src[i * 16 + j];
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data[512 + idx] = src[i * 16 + j + 8];
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}
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}
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if (!s->cursor) {
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s->cursor = cursor_alloc(64, 64);
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}
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cursor_set_mono(s->cursor, s->regs.cur_color1, s->regs.cur_color0,
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&data[512], 1, &data[0]);
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dpy_cursor_define(s->vga.con, s->cursor);
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}
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/* Alternatively support guest rendered hardware cursor */
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static void ati_cursor_invalidate(VGACommonState *vga)
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{
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ATIVGAState *s = container_of(vga, ATIVGAState, vga);
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int size = (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ? 64 : 0;
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if (s->regs.cur_offset & BIT(31)) {
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return; /* Do not update cursor if locked */
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}
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if (s->cursor_size != size ||
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vga->hw_cursor_x != s->regs.cur_hv_pos >> 16 ||
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vga->hw_cursor_y != (s->regs.cur_hv_pos & 0xffff) ||
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s->cursor_offset != s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
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(s->regs.cur_hv_offs & 0xffff) * 16) {
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/* Remove old cursor then update and show new one if needed */
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vga_invalidate_scanlines(vga, vga->hw_cursor_y, vga->hw_cursor_y + 63);
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vga->hw_cursor_x = s->regs.cur_hv_pos >> 16;
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vga->hw_cursor_y = s->regs.cur_hv_pos & 0xffff;
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s->cursor_offset = s->regs.cur_offset - (s->regs.cur_hv_offs >> 16) -
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(s->regs.cur_hv_offs & 0xffff) * 16;
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s->cursor_size = size;
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if (size) {
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vga_invalidate_scanlines(vga,
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vga->hw_cursor_y, vga->hw_cursor_y + 63);
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}
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}
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}
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static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y)
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{
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ATIVGAState *s = container_of(vga, ATIVGAState, vga);
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uint8_t *src;
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uint32_t *dp = (uint32_t *)d;
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int i, j, h;
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if (!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) ||
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scr_y < vga->hw_cursor_y || scr_y >= vga->hw_cursor_y + 64 ||
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scr_y > s->regs.crtc_v_total_disp >> 16) {
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return;
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}
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/* FIXME handle cur_hv_offs correctly */
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src = s->vga.vram_ptr + (s->regs.crtc_offset & 0x07ffffff) +
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s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16;
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dp = &dp[vga->hw_cursor_x];
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h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8;
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for (i = 0; i < 8; i++) {
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uint32_t color;
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uint8_t abits = src[i];
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uint8_t xbits = src[i + 8];
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for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) {
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if (abits & BIT(7)) {
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if (xbits & BIT(7)) {
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color = dp[i * 8 + j] ^ 0xffffffff; /* complement */
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} else {
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continue; /* transparent, no change */
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}
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} else {
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color = (xbits & BIT(7) ? s->regs.cur_color1 :
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s->regs.cur_color0) << 8 | 0xff;
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}
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if (vga->hw_cursor_x + i * 8 + j >= h) {
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return; /* end of screen, don't span to next line */
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}
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dp[i * 8 + j] = color;
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}
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}
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}
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static inline uint64_t ati_reg_read_offs(uint32_t reg, int offs,
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unsigned int size)
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{
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if (offs == 0 && size == 4) {
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return reg;
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} else {
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return extract32(reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE);
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}
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}
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static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size)
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{
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ATIVGAState *s = opaque;
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uint64_t val = 0;
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switch (addr) {
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case MM_INDEX:
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val = s->regs.mm_index;
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break;
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case MM_DATA ... MM_DATA + 3:
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/* indexed access to regs or memory */
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if (s->regs.mm_index & BIT(31)) {
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if (s->regs.mm_index <= s->vga.vram_size - size) {
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int i = size - 1;
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while (i >= 0) {
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val <<= 8;
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val |= s->vga.vram_ptr[s->regs.mm_index + i--];
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}
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}
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} else {
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val = ati_mm_read(s, s->regs.mm_index + addr - MM_DATA, size);
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}
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break;
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case BIOS_0_SCRATCH ... BUS_CNTL - 1:
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{
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int i = (addr - BIOS_0_SCRATCH) / 4;
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if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
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break;
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}
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val = ati_reg_read_offs(s->regs.bios_scratch[i],
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addr - (BIOS_0_SCRATCH + i * 4), size);
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break;
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}
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case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
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val = ati_reg_read_offs(s->regs.crtc_gen_cntl,
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addr - CRTC_GEN_CNTL, size);
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break;
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case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
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val = ati_reg_read_offs(s->regs.crtc_ext_cntl,
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addr - CRTC_EXT_CNTL, size);
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break;
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case DAC_CNTL:
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val = s->regs.dac_cntl;
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break;
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/* case GPIO_MONID: FIXME hook up DDC I2C here */
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case PALETTE_INDEX:
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/* FIXME unaligned access */
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val = vga_ioport_read(&s->vga, VGA_PEL_IR) << 16;
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val |= vga_ioport_read(&s->vga, VGA_PEL_IW) & 0xff;
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break;
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case PALETTE_DATA:
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val = vga_ioport_read(&s->vga, VGA_PEL_D);
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break;
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case CNFG_MEMSIZE:
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val = s->vga.vram_size;
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break;
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case MC_STATUS:
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val = 5;
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break;
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case RBBM_STATUS:
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case GUI_STAT:
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val = 64; /* free CMDFIFO entries */
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break;
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case CRTC_H_TOTAL_DISP:
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val = s->regs.crtc_h_total_disp;
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break;
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case CRTC_H_SYNC_STRT_WID:
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val = s->regs.crtc_h_sync_strt_wid;
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break;
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case CRTC_V_TOTAL_DISP:
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val = s->regs.crtc_v_total_disp;
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break;
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case CRTC_V_SYNC_STRT_WID:
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val = s->regs.crtc_v_sync_strt_wid;
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break;
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case CRTC_OFFSET:
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val = s->regs.crtc_offset;
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break;
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case CRTC_OFFSET_CNTL:
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val = s->regs.crtc_offset_cntl;
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break;
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case CRTC_PITCH:
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val = s->regs.crtc_pitch;
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break;
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case 0xf00 ... 0xfff:
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val = pci_default_read_config(&s->dev, addr - 0xf00, size);
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break;
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case CUR_OFFSET:
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val = s->regs.cur_offset;
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break;
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case CUR_HORZ_VERT_POSN:
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val = s->regs.cur_hv_pos;
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val |= s->regs.cur_offset & BIT(31);
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break;
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case CUR_HORZ_VERT_OFF:
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val = s->regs.cur_hv_offs;
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val |= s->regs.cur_offset & BIT(31);
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break;
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case CUR_CLR0:
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val = s->regs.cur_color0;
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break;
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case CUR_CLR1:
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val = s->regs.cur_color1;
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break;
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case DST_OFFSET:
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||
|
|
val = s->regs.dst_offset;
|
||
|
|
break;
|
||
|
|
case DST_PITCH:
|
||
|
|
val = s->regs.dst_pitch;
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
val &= s->regs.dst_tile << 16;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DST_WIDTH:
|
||
|
|
val = s->regs.dst_width;
|
||
|
|
break;
|
||
|
|
case DST_HEIGHT:
|
||
|
|
val = s->regs.dst_height;
|
||
|
|
break;
|
||
|
|
case SRC_X:
|
||
|
|
val = s->regs.src_x;
|
||
|
|
break;
|
||
|
|
case SRC_Y:
|
||
|
|
val = s->regs.src_y;
|
||
|
|
break;
|
||
|
|
case DST_X:
|
||
|
|
val = s->regs.dst_x;
|
||
|
|
break;
|
||
|
|
case DST_Y:
|
||
|
|
val = s->regs.dst_y;
|
||
|
|
break;
|
||
|
|
case DP_GUI_MASTER_CNTL:
|
||
|
|
val = s->regs.dp_gui_master_cntl;
|
||
|
|
break;
|
||
|
|
case SRC_OFFSET:
|
||
|
|
val = s->regs.src_offset;
|
||
|
|
break;
|
||
|
|
case SRC_PITCH:
|
||
|
|
val = s->regs.src_pitch;
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
val &= s->regs.src_tile << 16;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DP_BRUSH_BKGD_CLR:
|
||
|
|
val = s->regs.dp_brush_bkgd_clr;
|
||
|
|
break;
|
||
|
|
case DP_BRUSH_FRGD_CLR:
|
||
|
|
val = s->regs.dp_brush_frgd_clr;
|
||
|
|
break;
|
||
|
|
case DP_SRC_FRGD_CLR:
|
||
|
|
val = s->regs.dp_src_frgd_clr;
|
||
|
|
break;
|
||
|
|
case DP_SRC_BKGD_CLR:
|
||
|
|
val = s->regs.dp_src_bkgd_clr;
|
||
|
|
break;
|
||
|
|
case DP_CNTL:
|
||
|
|
val = s->regs.dp_cntl;
|
||
|
|
break;
|
||
|
|
case DP_DATATYPE:
|
||
|
|
val = s->regs.dp_datatype;
|
||
|
|
break;
|
||
|
|
case DP_MIX:
|
||
|
|
val = s->regs.dp_mix;
|
||
|
|
break;
|
||
|
|
case DP_WRITE_MASK:
|
||
|
|
val = s->regs.dp_write_mask;
|
||
|
|
break;
|
||
|
|
case DEFAULT_OFFSET:
|
||
|
|
val = s->regs.default_offset;
|
||
|
|
break;
|
||
|
|
case DEFAULT_PITCH:
|
||
|
|
val = s->regs.default_pitch;
|
||
|
|
break;
|
||
|
|
case DEFAULT_SC_BOTTOM_RIGHT:
|
||
|
|
val = s->regs.default_sc_bottom_right;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
|
||
|
|
trace_ati_mm_read(size, addr, ati_reg_name(addr & ~3ULL), val);
|
||
|
|
}
|
||
|
|
return val;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void ati_reg_write_offs(uint32_t *reg, int offs,
|
||
|
|
uint64_t data, unsigned int size)
|
||
|
|
{
|
||
|
|
if (offs == 0 && size == 4) {
|
||
|
|
*reg = data;
|
||
|
|
} else {
|
||
|
|
*reg = deposit32(*reg, offs * BITS_PER_BYTE, size * BITS_PER_BYTE,
|
||
|
|
data);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ati_mm_write(void *opaque, hwaddr addr,
|
||
|
|
uint64_t data, unsigned int size)
|
||
|
|
{
|
||
|
|
ATIVGAState *s = opaque;
|
||
|
|
|
||
|
|
if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
|
||
|
|
trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
|
||
|
|
}
|
||
|
|
switch (addr) {
|
||
|
|
case MM_INDEX:
|
||
|
|
s->regs.mm_index = data;
|
||
|
|
break;
|
||
|
|
case MM_DATA ... MM_DATA + 3:
|
||
|
|
/* indexed access to regs or memory */
|
||
|
|
if (s->regs.mm_index & BIT(31)) {
|
||
|
|
if (s->regs.mm_index <= s->vga.vram_size - size) {
|
||
|
|
int i = 0;
|
||
|
|
while (i < size) {
|
||
|
|
s->vga.vram_ptr[s->regs.mm_index + i] = data & 0xff;
|
||
|
|
data >>= 8;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case BIOS_0_SCRATCH ... BUS_CNTL - 1:
|
||
|
|
{
|
||
|
|
int i = (addr - BIOS_0_SCRATCH) / 4;
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
ati_reg_write_offs(&s->regs.bios_scratch[i],
|
||
|
|
addr - (BIOS_0_SCRATCH + i * 4), data, size);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
|
||
|
|
{
|
||
|
|
uint32_t val = s->regs.crtc_gen_cntl;
|
||
|
|
ati_reg_write_offs(&s->regs.crtc_gen_cntl,
|
||
|
|
addr - CRTC_GEN_CNTL, data, size);
|
||
|
|
if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
|
||
|
|
if (s->cursor_guest_mode) {
|
||
|
|
s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN);
|
||
|
|
} else {
|
||
|
|
if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) {
|
||
|
|
ati_cursor_define(s);
|
||
|
|
}
|
||
|
|
dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
|
||
|
|
s->regs.cur_hv_pos & 0xffff,
|
||
|
|
(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) !=
|
||
|
|
(s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) {
|
||
|
|
ati_vga_switch_mode(s);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
|
||
|
|
{
|
||
|
|
uint32_t val = s->regs.crtc_ext_cntl;
|
||
|
|
ati_reg_write_offs(&s->regs.crtc_ext_cntl,
|
||
|
|
addr - CRTC_EXT_CNTL, data, size);
|
||
|
|
if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) {
|
||
|
|
DPRINTF("Display disabled\n");
|
||
|
|
s->vga.ar_index &= ~BIT(5);
|
||
|
|
} else {
|
||
|
|
DPRINTF("Display enabled\n");
|
||
|
|
s->vga.ar_index |= BIT(5);
|
||
|
|
ati_vga_switch_mode(s);
|
||
|
|
}
|
||
|
|
if ((val & CRT_CRTC_DISPLAY_DIS) !=
|
||
|
|
(s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) {
|
||
|
|
ati_vga_switch_mode(s);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case DAC_CNTL:
|
||
|
|
s->regs.dac_cntl = data & 0xffffe3ff;
|
||
|
|
s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
|
||
|
|
break;
|
||
|
|
/* case GPIO_MONID: FIXME hook up DDC I2C here */
|
||
|
|
case PALETTE_INDEX ... PALETTE_INDEX + 3:
|
||
|
|
if (size == 4) {
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
|
||
|
|
} else {
|
||
|
|
if (addr == PALETTE_INDEX) {
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
|
||
|
|
} else {
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case PALETTE_DATA ... PALETTE_DATA + 3:
|
||
|
|
data <<= addr - PALETTE_DATA;
|
||
|
|
data = bswap32(data) >> 8;
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
|
||
|
|
data >>= 8;
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
|
||
|
|
data >>= 8;
|
||
|
|
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
|
||
|
|
break;
|
||
|
|
case CRTC_H_TOTAL_DISP:
|
||
|
|
s->regs.crtc_h_total_disp = data & 0x07ff07ff;
|
||
|
|
break;
|
||
|
|
case CRTC_H_SYNC_STRT_WID:
|
||
|
|
s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff;
|
||
|
|
break;
|
||
|
|
case CRTC_V_TOTAL_DISP:
|
||
|
|
s->regs.crtc_v_total_disp = data & 0x0fff0fff;
|
||
|
|
break;
|
||
|
|
case CRTC_V_SYNC_STRT_WID:
|
||
|
|
s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;
|
||
|
|
break;
|
||
|
|
case CRTC_OFFSET:
|
||
|
|
s->regs.crtc_offset = data & 0xc7ffffff;
|
||
|
|
break;
|
||
|
|
case CRTC_OFFSET_CNTL:
|
||
|
|
s->regs.crtc_offset_cntl = data; /* FIXME */
|
||
|
|
break;
|
||
|
|
case CRTC_PITCH:
|
||
|
|
s->regs.crtc_pitch = data & 0x07ff07ff;
|
||
|
|
break;
|
||
|
|
case 0xf00 ... 0xfff:
|
||
|
|
/* read-only copy of PCI config space so ignore writes */
|
||
|
|
break;
|
||
|
|
case CUR_OFFSET:
|
||
|
|
if (s->regs.cur_offset != (data & 0x87fffff0)) {
|
||
|
|
s->regs.cur_offset = data & 0x87fffff0;
|
||
|
|
ati_cursor_define(s);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case CUR_HORZ_VERT_POSN:
|
||
|
|
s->regs.cur_hv_pos = data & 0x3fff0fff;
|
||
|
|
if (data & BIT(31)) {
|
||
|
|
s->regs.cur_offset |= data & BIT(31);
|
||
|
|
} else if (s->regs.cur_offset & BIT(31)) {
|
||
|
|
s->regs.cur_offset &= ~BIT(31);
|
||
|
|
ati_cursor_define(s);
|
||
|
|
}
|
||
|
|
if (!s->cursor_guest_mode &&
|
||
|
|
(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(data & BIT(31))) {
|
||
|
|
dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
|
||
|
|
s->regs.cur_hv_pos & 0xffff, 1);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case CUR_HORZ_VERT_OFF:
|
||
|
|
s->regs.cur_hv_offs = data & 0x3f003f;
|
||
|
|
if (data & BIT(31)) {
|
||
|
|
s->regs.cur_offset |= data & BIT(31);
|
||
|
|
} else if (s->regs.cur_offset & BIT(31)) {
|
||
|
|
s->regs.cur_offset &= ~BIT(31);
|
||
|
|
ati_cursor_define(s);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case CUR_CLR0:
|
||
|
|
if (s->regs.cur_color0 != (data & 0xffffff)) {
|
||
|
|
s->regs.cur_color0 = data & 0xffffff;
|
||
|
|
ati_cursor_define(s);
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case CUR_CLR1:
|
||
|
|
/*
|
||
|
|
* Update cursor unconditionally here because some clients set up
|
||
|
|
* other registers before actually writing cursor data to memory at
|
||
|
|
* offset so we would miss cursor change unless always updating here
|
||
|
|
*/
|
||
|
|
s->regs.cur_color1 = data & 0xffffff;
|
||
|
|
ati_cursor_define(s);
|
||
|
|
break;
|
||
|
|
case DST_OFFSET:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.dst_offset = data & 0xfffffff0;
|
||
|
|
} else {
|
||
|
|
s->regs.dst_offset = data & 0xfffffc00;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DST_PITCH:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.dst_pitch = data & 0x3fff;
|
||
|
|
s->regs.dst_tile = (data >> 16) & 1;
|
||
|
|
} else {
|
||
|
|
s->regs.dst_pitch = data & 0x3ff0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DST_TILE:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) {
|
||
|
|
s->regs.dst_tile = data & 3;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DST_WIDTH:
|
||
|
|
s->regs.dst_width = data & 0x3fff;
|
||
|
|
ati_2d_blt(s);
|
||
|
|
break;
|
||
|
|
case DST_HEIGHT:
|
||
|
|
s->regs.dst_height = data & 0x3fff;
|
||
|
|
break;
|
||
|
|
case SRC_X:
|
||
|
|
s->regs.src_x = data & 0x3fff;
|
||
|
|
break;
|
||
|
|
case SRC_Y:
|
||
|
|
s->regs.src_y = data & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_X:
|
||
|
|
s->regs.dst_x = data & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_Y:
|
||
|
|
s->regs.dst_y = data & 0x3fff;
|
||
|
|
break;
|
||
|
|
case SRC_PITCH_OFFSET:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.src_offset = (data & 0x1fffff) << 5;
|
||
|
|
s->regs.src_pitch = (data >> 21) & 0x3ff;
|
||
|
|
s->regs.src_tile = data >> 31;
|
||
|
|
} else {
|
||
|
|
s->regs.src_offset = (data & 0x3fffff) << 11;
|
||
|
|
s->regs.src_pitch = (data & 0x3fc00000) >> 16;
|
||
|
|
s->regs.src_tile = (data >> 30) & 1;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DST_PITCH_OFFSET:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.dst_offset = (data & 0x1fffff) << 5;
|
||
|
|
s->regs.dst_pitch = (data >> 21) & 0x3ff;
|
||
|
|
s->regs.dst_tile = data >> 31;
|
||
|
|
} else {
|
||
|
|
s->regs.dst_offset = (data & 0x3fffff) << 11;
|
||
|
|
s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
|
||
|
|
s->regs.dst_tile = data >> 30;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case SRC_Y_X:
|
||
|
|
s->regs.src_x = data & 0x3fff;
|
||
|
|
s->regs.src_y = (data >> 16) & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_Y_X:
|
||
|
|
s->regs.dst_x = data & 0x3fff;
|
||
|
|
s->regs.dst_y = (data >> 16) & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_HEIGHT_WIDTH:
|
||
|
|
s->regs.dst_width = data & 0x3fff;
|
||
|
|
s->regs.dst_height = (data >> 16) & 0x3fff;
|
||
|
|
ati_2d_blt(s);
|
||
|
|
break;
|
||
|
|
case DP_GUI_MASTER_CNTL:
|
||
|
|
s->regs.dp_gui_master_cntl = data & 0xf800000f;
|
||
|
|
s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
|
||
|
|
(data & 0x4000) << 16;
|
||
|
|
s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
|
||
|
|
break;
|
||
|
|
case DST_WIDTH_X:
|
||
|
|
s->regs.dst_x = data & 0x3fff;
|
||
|
|
s->regs.dst_width = (data >> 16) & 0x3fff;
|
||
|
|
ati_2d_blt(s);
|
||
|
|
break;
|
||
|
|
case SRC_X_Y:
|
||
|
|
s->regs.src_y = data & 0x3fff;
|
||
|
|
s->regs.src_x = (data >> 16) & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_X_Y:
|
||
|
|
s->regs.dst_y = data & 0x3fff;
|
||
|
|
s->regs.dst_x = (data >> 16) & 0x3fff;
|
||
|
|
break;
|
||
|
|
case DST_WIDTH_HEIGHT:
|
||
|
|
s->regs.dst_height = data & 0x3fff;
|
||
|
|
s->regs.dst_width = (data >> 16) & 0x3fff;
|
||
|
|
ati_2d_blt(s);
|
||
|
|
break;
|
||
|
|
case DST_HEIGHT_Y:
|
||
|
|
s->regs.dst_y = data & 0x3fff;
|
||
|
|
s->regs.dst_height = (data >> 16) & 0x3fff;
|
||
|
|
break;
|
||
|
|
case SRC_OFFSET:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.src_offset = data & 0xfffffff0;
|
||
|
|
} else {
|
||
|
|
s->regs.src_offset = data & 0xfffffc00;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case SRC_PITCH:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.src_pitch = data & 0x3fff;
|
||
|
|
s->regs.src_tile = (data >> 16) & 1;
|
||
|
|
} else {
|
||
|
|
s->regs.src_pitch = data & 0x3ff0;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DP_BRUSH_BKGD_CLR:
|
||
|
|
s->regs.dp_brush_bkgd_clr = data;
|
||
|
|
break;
|
||
|
|
case DP_BRUSH_FRGD_CLR:
|
||
|
|
s->regs.dp_brush_frgd_clr = data;
|
||
|
|
break;
|
||
|
|
case DP_CNTL:
|
||
|
|
s->regs.dp_cntl = data;
|
||
|
|
break;
|
||
|
|
case DP_DATATYPE:
|
||
|
|
s->regs.dp_datatype = data & 0xe0070f0f;
|
||
|
|
break;
|
||
|
|
case DP_MIX:
|
||
|
|
s->regs.dp_mix = data & 0x00ff0700;
|
||
|
|
break;
|
||
|
|
case DP_WRITE_MASK:
|
||
|
|
s->regs.dp_write_mask = data;
|
||
|
|
break;
|
||
|
|
case DEFAULT_OFFSET:
|
||
|
|
data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
|
||
|
|
0x03fffc00 : 0xfffffc00);
|
||
|
|
s->regs.default_offset = data;
|
||
|
|
break;
|
||
|
|
case DEFAULT_PITCH:
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
|
||
|
|
s->regs.default_pitch = data & 0x103ff;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case DEFAULT_SC_BOTTOM_RIGHT:
|
||
|
|
s->regs.default_sc_bottom_right = data & 0x3fff3fff;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps ati_mm_ops = {
|
||
|
|
.read = ati_mm_read,
|
||
|
|
.write = ati_mm_write,
|
||
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ati_vga_realize(PCIDevice *dev, Error **errp)
|
||
|
|
{
|
||
|
|
ATIVGAState *s = ATI_VGA(dev);
|
||
|
|
VGACommonState *vga = &s->vga;
|
||
|
|
|
||
|
|
if (s->model) {
|
||
|
|
int i;
|
||
|
|
for (i = 0; i < ARRAY_SIZE(ati_model_aliases); i++) {
|
||
|
|
if (!strcmp(s->model, ati_model_aliases[i].name)) {
|
||
|
|
s->dev_id = ati_model_aliases[i].dev_id;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (i >= ARRAY_SIZE(ati_model_aliases)) {
|
||
|
|
warn_report("Unknown ATI VGA model name, "
|
||
|
|
"using default rage128p");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF &&
|
||
|
|
s->dev_id != PCI_DEVICE_ID_ATI_RADEON_QY) {
|
||
|
|
error_setg(errp, "Unknown ATI VGA device id, "
|
||
|
|
"only 0x5046 and 0x5159 are supported");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
pci_set_word(dev->config + PCI_DEVICE_ID, s->dev_id);
|
||
|
|
|
||
|
|
if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY &&
|
||
|
|
s->vga.vram_size_mb < 16) {
|
||
|
|
warn_report("Too small video memory for device id");
|
||
|
|
s->vga.vram_size_mb = 16;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* init vga bits */
|
||
|
|
vga_common_init(vga, OBJECT(s));
|
||
|
|
vga_init(vga, OBJECT(s), pci_address_space(dev),
|
||
|
|
pci_address_space_io(dev), true);
|
||
|
|
vga->con = graphic_console_init(DEVICE(s), 0, s->vga.hw_ops, &s->vga);
|
||
|
|
if (s->cursor_guest_mode) {
|
||
|
|
vga->cursor_invalidate = ati_cursor_invalidate;
|
||
|
|
vga->cursor_draw_line = ati_cursor_draw_line;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* mmio register space */
|
||
|
|
memory_region_init_io(&s->mm, OBJECT(s), &ati_mm_ops, s,
|
||
|
|
"ati.mmregs", 0x4000);
|
||
|
|
/* io space is alias to beginning of mmregs */
|
||
|
|
memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100);
|
||
|
|
|
||
|
|
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
|
||
|
|
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
||
|
|
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ati_vga_reset(DeviceState *dev)
|
||
|
|
{
|
||
|
|
ATIVGAState *s = ATI_VGA(dev);
|
||
|
|
|
||
|
|
/* reset vga */
|
||
|
|
vga_common_reset(&s->vga);
|
||
|
|
s->mode = VGA_MODE;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ati_vga_exit(PCIDevice *dev)
|
||
|
|
{
|
||
|
|
ATIVGAState *s = ATI_VGA(dev);
|
||
|
|
|
||
|
|
graphic_console_close(s->vga.con);
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property ati_vga_properties[] = {
|
||
|
|
DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState, vga.vram_size_mb, 16),
|
||
|
|
DEFINE_PROP_STRING("model", ATIVGAState, model),
|
||
|
|
DEFINE_PROP_UINT16("x-device-id", ATIVGAState, dev_id,
|
||
|
|
PCI_DEVICE_ID_ATI_RAGE128_PF),
|
||
|
|
DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false),
|
||
|
|
DEFINE_PROP_END_OF_LIST()
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ati_vga_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->reset = ati_vga_reset;
|
||
|
|
dc->props = ati_vga_properties;
|
||
|
|
dc->hotpluggable = false;
|
||
|
|
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
||
|
|
|
||
|
|
k->class_id = PCI_CLASS_DISPLAY_VGA;
|
||
|
|
k->vendor_id = PCI_VENDOR_ID_ATI;
|
||
|
|
k->device_id = PCI_DEVICE_ID_ATI_RAGE128_PF;
|
||
|
|
k->romfile = "vgabios-stdvga.bin";
|
||
|
|
k->realize = ati_vga_realize;
|
||
|
|
k->exit = ati_vga_exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo ati_vga_info = {
|
||
|
|
.name = TYPE_ATI_VGA,
|
||
|
|
.parent = TYPE_PCI_DEVICE,
|
||
|
|
.instance_size = sizeof(ATIVGAState),
|
||
|
|
.class_init = ati_vga_class_init,
|
||
|
|
.interfaces = (InterfaceInfo[]) {
|
||
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
||
|
|
{ },
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ati_vga_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&ati_vga_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(ati_vga_register_types)
|