2009-11-20 03:21:33 +03:00
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/*
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* MAXIM DS1338 I2C RTC+NVRAM
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*
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* Copyright (c) 2009 CodeSourcery.
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* Written by Paul Brook
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*
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2011-06-26 06:21:35 +04:00
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* This code is licensed under the GNU GPL v2.
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2012-01-13 20:44:23 +04:00
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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2009-11-20 03:21:33 +03:00
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*/
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2016-01-26 21:17:18 +03:00
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#include "qemu/osdep.h"
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2016-01-19 23:51:44 +03:00
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#include "qemu-common.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/i2c/i2c.h"
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2016-03-20 20:16:19 +03:00
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#include "qemu/bcd.h"
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2019-05-23 17:35:07 +03:00
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#include "qemu/module.h"
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2009-11-20 03:21:33 +03:00
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2012-10-12 14:54:38 +04:00
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/* Size of NVRAM including both the user-accessible area and the
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* secondary register area.
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*/
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#define NVRAM_SIZE 64
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2012-12-13 18:05:27 +04:00
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/* Flags definitions */
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#define SECONDS_CH 0x80
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#define HOURS_12 0x40
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#define HOURS_PM 0x20
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#define CTRL_OSF 0x20
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2013-12-20 01:34:05 +04:00
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#define TYPE_DS1338 "ds1338"
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#define DS1338(obj) OBJECT_CHECK(DS1338State, (obj), TYPE_DS1338)
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typedef struct DS1338State {
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I2CSlave parent_obj;
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2012-10-12 14:54:38 +04:00
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int64_t offset;
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2012-12-13 18:05:28 +04:00
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uint8_t wday_offset;
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2012-10-12 14:54:38 +04:00
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uint8_t nvram[NVRAM_SIZE];
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2012-10-12 14:54:38 +04:00
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int32_t ptr;
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bool addr_byte;
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2009-11-20 03:21:33 +03:00
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} DS1338State;
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2012-10-12 14:54:38 +04:00
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static const VMStateDescription vmstate_ds1338 = {
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.name = "ds1338",
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2012-12-13 18:05:28 +04:00
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.version_id = 2,
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2012-10-12 14:54:38 +04:00
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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2013-12-20 01:34:05 +04:00
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VMSTATE_I2C_SLAVE(parent_obj, DS1338State),
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2012-10-12 14:54:38 +04:00
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VMSTATE_INT64(offset, DS1338State),
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2012-12-13 18:05:28 +04:00
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VMSTATE_UINT8_V(wday_offset, DS1338State, 2),
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2012-10-12 14:54:38 +04:00
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VMSTATE_UINT8_ARRAY(nvram, DS1338State, NVRAM_SIZE),
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VMSTATE_INT32(ptr, DS1338State),
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VMSTATE_BOOL(addr_byte, DS1338State),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-10-12 14:54:38 +04:00
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static void capture_current_time(DS1338State *s)
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{
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/* Capture the current time into the secondary registers
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* which will be actually read by the data transfer operation.
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*/
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2012-10-12 14:54:38 +04:00
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struct tm now;
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qemu_get_timedate(&now, s->offset);
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s->nvram[0] = to_bcd(now.tm_sec);
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s->nvram[1] = to_bcd(now.tm_min);
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2012-12-13 18:05:27 +04:00
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if (s->nvram[2] & HOURS_12) {
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int tmp = now.tm_hour;
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2013-02-28 22:23:12 +04:00
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if (tmp % 12 == 0) {
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tmp += 12;
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2012-12-13 18:05:27 +04:00
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}
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if (tmp <= 12) {
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s->nvram[2] = HOURS_12 | to_bcd(tmp);
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} else {
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s->nvram[2] = HOURS_12 | HOURS_PM | to_bcd(tmp - 12);
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2012-10-12 14:54:38 +04:00
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}
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} else {
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2012-10-12 14:54:38 +04:00
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s->nvram[2] = to_bcd(now.tm_hour);
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2012-10-12 14:54:38 +04:00
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}
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2012-12-13 18:05:28 +04:00
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s->nvram[3] = (now.tm_wday + s->wday_offset) % 7 + 1;
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2012-10-12 14:54:38 +04:00
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s->nvram[4] = to_bcd(now.tm_mday);
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2012-12-13 18:05:27 +04:00
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s->nvram[5] = to_bcd(now.tm_mon + 1);
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2012-10-12 14:54:38 +04:00
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s->nvram[6] = to_bcd(now.tm_year - 100);
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2012-10-12 14:54:38 +04:00
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}
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static void inc_regptr(DS1338State *s)
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{
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/* The register pointer wraps around after 0x3F; wraparound
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* causes the current time/date to be retransferred into
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* the secondary registers.
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*/
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s->ptr = (s->ptr + 1) & (NVRAM_SIZE - 1);
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if (!s->ptr) {
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capture_current_time(s);
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}
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}
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2017-01-09 14:40:20 +03:00
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static int ds1338_event(I2CSlave *i2c, enum i2c_event event)
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2009-11-20 03:21:33 +03:00
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{
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2013-12-20 01:34:05 +04:00
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DS1338State *s = DS1338(i2c);
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2009-11-20 03:21:33 +03:00
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switch (event) {
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case I2C_START_RECV:
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2012-10-12 14:54:38 +04:00
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/* In h/w, capture happens on any START condition, not just a
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* START_RECV, but there is no need to actually capture on
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* START_SEND, because the guest can't get at that data
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* without going through a START_RECV which would overwrite it.
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*/
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capture_current_time(s);
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2009-11-20 03:21:33 +03:00
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break;
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case I2C_START_SEND:
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2012-10-12 14:54:38 +04:00
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s->addr_byte = true;
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2009-11-20 03:21:33 +03:00
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break;
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default:
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break;
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}
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2017-01-09 14:40:20 +03:00
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return 0;
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2009-11-20 03:21:33 +03:00
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}
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2018-11-14 20:50:50 +03:00
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static uint8_t ds1338_recv(I2CSlave *i2c)
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2009-11-20 03:21:33 +03:00
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{
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2013-12-20 01:34:05 +04:00
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DS1338State *s = DS1338(i2c);
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2009-11-20 03:21:33 +03:00
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uint8_t res;
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res = s->nvram[s->ptr];
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2012-10-12 14:54:38 +04:00
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inc_regptr(s);
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2009-11-20 03:21:33 +03:00
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return res;
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}
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2011-12-05 06:28:27 +04:00
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static int ds1338_send(I2CSlave *i2c, uint8_t data)
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2009-11-20 03:21:33 +03:00
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{
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2013-12-20 01:34:05 +04:00
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DS1338State *s = DS1338(i2c);
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2009-11-20 03:21:33 +03:00
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if (s->addr_byte) {
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2012-10-12 14:54:38 +04:00
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s->ptr = data & (NVRAM_SIZE - 1);
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2012-10-12 14:54:38 +04:00
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s->addr_byte = false;
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2009-11-20 03:21:33 +03:00
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return 0;
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}
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2012-12-13 18:05:28 +04:00
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if (s->ptr < 7) {
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/* Time register. */
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2012-10-12 14:54:38 +04:00
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struct tm now;
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qemu_get_timedate(&now, s->offset);
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2012-10-12 14:54:38 +04:00
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switch(s->ptr) {
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2009-11-20 03:21:33 +03:00
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case 0:
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/* TODO: Implement CH (stop) bit. */
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2012-10-12 14:54:38 +04:00
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now.tm_sec = from_bcd(data & 0x7f);
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2009-11-20 03:21:33 +03:00
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break;
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case 1:
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2012-10-12 14:54:38 +04:00
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now.tm_min = from_bcd(data & 0x7f);
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2009-11-20 03:21:33 +03:00
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break;
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case 2:
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2012-12-13 18:05:27 +04:00
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if (data & HOURS_12) {
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int tmp = from_bcd(data & (HOURS_PM - 1));
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if (data & HOURS_PM) {
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tmp += 12;
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}
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2013-02-28 22:23:12 +04:00
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if (tmp % 12 == 0) {
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tmp -= 12;
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2009-11-20 03:21:33 +03:00
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}
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2012-12-13 18:05:27 +04:00
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now.tm_hour = tmp;
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2009-11-20 03:21:33 +03:00
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} else {
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2012-12-13 18:05:27 +04:00
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now.tm_hour = from_bcd(data & (HOURS_12 - 1));
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2009-11-20 03:21:33 +03:00
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}
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break;
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case 3:
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2012-12-13 18:05:28 +04:00
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{
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/* The day field is supposed to contain a value in
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the range 1-7. Otherwise behavior is undefined.
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*/
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int user_wday = (data & 7) - 1;
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s->wday_offset = (user_wday - now.tm_wday + 7) % 7;
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}
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2009-11-20 03:21:33 +03:00
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break;
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case 4:
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2012-10-12 14:54:38 +04:00
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now.tm_mday = from_bcd(data & 0x3f);
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2009-11-20 03:21:33 +03:00
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break;
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case 5:
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2012-10-12 14:54:38 +04:00
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now.tm_mon = from_bcd(data & 0x1f) - 1;
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2012-02-25 17:50:25 +04:00
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break;
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2009-11-20 03:21:33 +03:00
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case 6:
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2012-10-12 14:54:38 +04:00
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now.tm_year = from_bcd(data) + 100;
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2009-11-20 03:21:33 +03:00
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break;
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}
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2012-10-12 14:54:38 +04:00
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s->offset = qemu_timedate_diff(&now);
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2012-12-13 18:05:28 +04:00
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} else if (s->ptr == 7) {
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/* Control register. */
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/* Ensure bits 2, 3 and 6 will read back as zero. */
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data &= 0xB3;
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/* Attempting to write the OSF flag to logic 1 leaves the
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value unchanged. */
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data = (data & ~CTRL_OSF) | (data & s->nvram[s->ptr] & CTRL_OSF);
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s->nvram[s->ptr] = data;
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2012-10-12 14:54:38 +04:00
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} else {
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s->nvram[s->ptr] = data;
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2009-11-20 03:21:33 +03:00
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}
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2012-10-12 14:54:38 +04:00
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inc_regptr(s);
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2009-11-20 03:21:33 +03:00
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return 0;
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}
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2012-12-13 18:05:28 +04:00
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static void ds1338_reset(DeviceState *dev)
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{
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2013-12-20 01:34:05 +04:00
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DS1338State *s = DS1338(dev);
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2012-12-13 18:05:28 +04:00
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/* The clock is running and synchronized with the host */
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s->offset = 0;
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2012-12-13 18:05:28 +04:00
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s->wday_offset = 0;
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2012-12-13 18:05:28 +04:00
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memset(s->nvram, 0, NVRAM_SIZE);
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s->ptr = 0;
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s->addr_byte = false;
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}
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2011-12-05 06:39:20 +04:00
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static void ds1338_class_init(ObjectClass *klass, void *data)
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{
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2012-10-12 14:54:38 +04:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-05 06:39:20 +04:00
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I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
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k->event = ds1338_event;
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k->recv = ds1338_recv;
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k->send = ds1338_send;
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2012-12-13 18:05:28 +04:00
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dc->reset = ds1338_reset;
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2012-10-12 14:54:38 +04:00
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dc->vmsd = &vmstate_ds1338;
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2011-12-05 06:39:20 +04:00
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}
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2013-01-10 19:19:07 +04:00
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static const TypeInfo ds1338_info = {
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2013-12-20 01:34:05 +04:00
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.name = TYPE_DS1338,
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2011-12-08 07:34:16 +04:00
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.parent = TYPE_I2C_SLAVE,
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.instance_size = sizeof(DS1338State),
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.class_init = ds1338_class_init,
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2009-11-20 03:21:33 +03:00
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};
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2012-02-09 18:20:55 +04:00
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static void ds1338_register_types(void)
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2009-11-20 03:21:33 +03:00
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{
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2011-12-08 07:34:16 +04:00
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type_register_static(&ds1338_info);
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2009-11-20 03:21:33 +03:00
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}
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2012-02-09 18:20:55 +04:00
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type_init(ds1338_register_types)
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