2021-02-08 08:46:10 +03:00
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#!/usr/bin/env python3
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##
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2024-03-07 06:23:27 +03:00
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## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
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2021-02-08 08:46:10 +03:00
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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import sys
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import re
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import string
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import hex_common
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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##
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## Generate the TCG code to call the helper
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## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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## We produce:
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2022-11-08 19:28:56 +03:00
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## static void generate_A2_add(DisasContext *ctx)
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## {
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2023-12-11 01:07:05 +03:00
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## Insn *insn G_GNUC_UNUSED = ctx->insn;
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## const int RdN = insn->regno[0];
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## TCGv RdV = get_result_gpr(ctx, RdN);
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## TCGv RsV = hex_gpr[insn->regno[1]];
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## TCGv RtV = hex_gpr[insn->regno[2]];
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## <GEN>
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2023-04-28 01:59:53 +03:00
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## gen_log_reg_write(ctx, RdN, RdV);
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Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-07 05:58:26 +03:00
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## }
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2021-02-08 08:46:10 +03:00
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##
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## where <GEN> depends on hex_common.skip_qemu_helper(tag)
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## if hex_common.skip_qemu_helper(tag) is True
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## <GEN> is fGEN_TCG_A2_add({ RdV=RsV+RtV;});
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## if hex_common.skip_qemu_helper(tag) is False
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2023-09-14 02:37:36 +03:00
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## <GEN> is gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
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2021-02-08 08:46:10 +03:00
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##
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def gen_tcg_func(f, tag, regs, imms):
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2023-03-20 12:25:32 +03:00
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f.write(f"static void generate_{tag}(DisasContext *ctx)\n")
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2023-03-20 12:25:33 +03:00
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f.write("{\n")
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2022-11-08 19:28:56 +03:00
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2023-12-11 01:07:05 +03:00
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f.write(" Insn *insn G_GNUC_UNUSED = ctx->insn;\n")
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2022-11-08 19:28:56 +03:00
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2023-03-20 12:25:33 +03:00
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if hex_common.need_ea(tag):
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2023-12-11 01:07:05 +03:00
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f.write(" TCGv EA G_GNUC_UNUSED = tcg_temp_new();\n")
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2021-02-08 08:46:10 +03:00
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## Declare all the operands (regs and immediates)
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2023-12-11 01:07:05 +03:00
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i = 0
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2023-05-24 17:41:47 +03:00
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for regtype, regid in regs:
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2023-12-11 01:07:05 +03:00
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reg = hex_common.get_register(tag, regtype, regid)
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reg.decl_tcg(f, tag, i)
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2021-02-08 08:46:10 +03:00
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i += 1
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2023-03-20 12:25:33 +03:00
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for immlett, bits, immshift in imms:
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2023-12-11 01:07:05 +03:00
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i = 1 if immlett.isupper() else 0
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f.write(f" int {hex_common.imm_name(immlett)} = insn->immed[{i}];\n")
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2021-02-08 08:46:10 +03:00
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2022-09-23 20:38:30 +03:00
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if hex_common.is_idef_parser_enabled(tag):
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declared = []
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## Handle registers
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2023-05-24 17:41:47 +03:00
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for regtype, regid in regs:
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2023-12-11 01:07:05 +03:00
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reg = hex_common.get_register(tag, regtype, regid)
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reg.idef_arg(declared)
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2022-09-23 20:38:30 +03:00
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## Handle immediates
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2023-03-20 12:25:33 +03:00
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for immlett, bits, immshift in imms:
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2022-09-23 20:38:30 +03:00
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declared.append(hex_common.imm_name(immlett))
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arguments = ", ".join(["ctx", "ctx->insn", "ctx->pkt"] + declared)
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2023-03-20 12:25:32 +03:00
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f.write(f" emit_{tag}({arguments});\n")
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2022-09-23 20:38:30 +03:00
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2023-03-20 12:25:33 +03:00
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elif hex_common.skip_qemu_helper(tag):
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2023-03-20 12:25:32 +03:00
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f.write(f" fGEN_TCG_{tag}({hex_common.semdict[tag]});\n")
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2021-02-08 08:46:10 +03:00
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else:
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## Generate the call to the helper
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2023-12-11 01:07:05 +03:00
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declared = []
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ret_type = hex_common.helper_ret_type(tag, regs).call_arg
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if ret_type != "void":
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declared.append(ret_type)
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for arg in hex_common.helper_args(tag, regs, imms):
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declared.append(arg.call_arg)
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2021-02-08 08:46:10 +03:00
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2023-12-11 01:07:05 +03:00
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arguments = ", ".join(declared)
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f.write(f" gen_helper_{tag}({arguments});\n")
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2021-02-08 08:46:10 +03:00
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## Write all the outputs
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2023-05-24 17:41:47 +03:00
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for regtype, regid in regs:
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2023-12-11 01:07:05 +03:00
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reg = hex_common.get_register(tag, regtype, regid)
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if reg.is_written():
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reg.log_write(f, tag)
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2021-02-08 08:46:10 +03:00
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f.write("}\n\n")
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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def gen_def_tcg_func(f, tag, tagregs, tagimms):
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regs = tagregs[tag]
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imms = tagimms[tag]
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gen_tcg_func(f, tag, regs, imms)
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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def main():
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2024-03-07 06:23:27 +03:00
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is_idef_parser_enabled = hex_common.read_common_files()
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2021-02-08 08:46:10 +03:00
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tagregs = hex_common.get_tagregs()
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tagimms = hex_common.get_tagimms()
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2022-09-23 20:38:30 +03:00
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output_file = sys.argv[-1]
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2023-03-20 12:25:33 +03:00
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with open(output_file, "w") as f:
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2021-02-08 08:46:10 +03:00
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f.write("#ifndef HEXAGON_TCG_FUNCS_H\n")
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f.write("#define HEXAGON_TCG_FUNCS_H\n\n")
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2022-09-23 20:38:30 +03:00
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if is_idef_parser_enabled:
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2023-03-20 12:25:33 +03:00
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f.write('#include "idef-generated-emitter.h.inc"\n\n')
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2021-02-08 08:46:10 +03:00
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for tag in hex_common.tags:
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## Skip the priv instructions
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2023-03-20 12:25:33 +03:00
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if "A_PRIV" in hex_common.attribdict[tag]:
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2021-02-08 08:46:10 +03:00
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continue
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## Skip the guest instructions
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2023-03-20 12:25:33 +03:00
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if "A_GUEST" in hex_common.attribdict[tag]:
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2021-02-08 08:46:10 +03:00
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continue
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## Skip the diag instructions
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2023-03-20 12:25:33 +03:00
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if tag == "Y6_diag":
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2021-02-08 08:46:10 +03:00
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continue
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2023-03-20 12:25:33 +03:00
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if tag == "Y6_diag0":
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2021-02-08 08:46:10 +03:00
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continue
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2023-03-20 12:25:33 +03:00
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if tag == "Y6_diag1":
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2021-02-08 08:46:10 +03:00
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continue
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gen_def_tcg_func(f, tag, tagregs, tagimms)
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f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n")
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2023-03-20 12:25:33 +03:00
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2021-02-08 08:46:10 +03:00
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if __name__ == "__main__":
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main()
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