2021-07-19 14:21:07 +03:00
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/*
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* SGX EPC device
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*
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* Copyright (C) 2019 Intel Corporation
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*
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* Authors:
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* Sean Christopherson <sean.j.christopherson@intel.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/i386/pc.h"
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#include "hw/i386/sgx-epc.h"
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#include "hw/mem/memory-device.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "target/i386/cpu.h"
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#include "exec/address-spaces.h"
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static Property sgx_epc_properties[] = {
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DEFINE_PROP_UINT64(SGX_EPC_ADDR_PROP, SGXEPCDevice, addr, 0),
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numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 19:20:05 +03:00
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DEFINE_PROP_UINT32(SGX_EPC_NUMA_NODE_PROP, SGXEPCDevice, node, 0),
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2021-07-19 14:21:07 +03:00
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DEFINE_PROP_LINK(SGX_EPC_MEMDEV_PROP, SGXEPCDevice, hostmem,
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TYPE_MEMORY_BACKEND_EPC, HostMemoryBackendEpc *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void sgx_epc_get_size(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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Error *local_err = NULL;
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uint64_t value;
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value = memory_device_get_region_size(MEMORY_DEVICE(obj), &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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visit_type_uint64(v, name, &value, errp);
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}
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static void sgx_epc_init(Object *obj)
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{
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object_property_add(obj, SGX_EPC_SIZE_PROP, "uint64", sgx_epc_get_size,
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NULL, NULL, NULL);
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}
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static void sgx_epc_realize(DeviceState *dev, Error **errp)
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{
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PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
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X86MachineState *x86ms = X86_MACHINE(pcms);
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vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-28 11:40:58 +03:00
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MemoryDeviceState *md = MEMORY_DEVICE(dev);
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SGXEPCState *sgx_epc = &pcms->sgx_epc;
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2021-07-19 14:21:07 +03:00
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SGXEPCDevice *epc = SGX_EPC(dev);
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HostMemoryBackend *hostmem;
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const char *path;
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if (x86ms->boot_cpus != 0) {
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error_setg(errp, "'" TYPE_SGX_EPC "' can't be created after vCPUs,"
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"e.g. via -device");
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return;
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}
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if (!epc->hostmem) {
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error_setg(errp, "'" SGX_EPC_MEMDEV_PROP "' property is not set");
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return;
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}
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hostmem = MEMORY_BACKEND(epc->hostmem);
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if (host_memory_backend_is_mapped(hostmem)) {
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path = object_get_canonical_path_component(OBJECT(hostmem));
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error_setg(errp, "can't use already busy memdev: %s", path);
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return;
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}
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vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-09-28 11:40:58 +03:00
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epc->addr = sgx_epc->base + sgx_epc->size;
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memory_region_add_subregion(&sgx_epc->mr, epc->addr - sgx_epc->base,
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host_memory_backend_get_memory(hostmem));
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host_memory_backend_set_mapped(hostmem, true);
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sgx_epc->sections = g_renew(SGXEPCDevice *, sgx_epc->sections,
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sgx_epc->nr_sections + 1);
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sgx_epc->sections[sgx_epc->nr_sections++] = epc;
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sgx_epc->size += memory_device_get_region_size(md, errp);
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2021-07-19 14:21:07 +03:00
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}
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static void sgx_epc_unrealize(DeviceState *dev)
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{
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SGXEPCDevice *epc = SGX_EPC(dev);
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HostMemoryBackend *hostmem = MEMORY_BACKEND(epc->hostmem);
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host_memory_backend_set_mapped(hostmem, false);
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}
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static uint64_t sgx_epc_md_get_addr(const MemoryDeviceState *md)
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{
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const SGXEPCDevice *epc = SGX_EPC(md);
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return epc->addr;
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}
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static void sgx_epc_md_set_addr(MemoryDeviceState *md, uint64_t addr,
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Error **errp)
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{
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object_property_set_uint(OBJECT(md), SGX_EPC_ADDR_PROP, addr, errp);
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}
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static uint64_t sgx_epc_md_get_plugged_size(const MemoryDeviceState *md,
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Error **errp)
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{
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return 0;
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}
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static MemoryRegion *sgx_epc_md_get_memory_region(MemoryDeviceState *md,
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Error **errp)
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{
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SGXEPCDevice *epc = SGX_EPC(md);
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HostMemoryBackend *hostmem;
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if (!epc->hostmem) {
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error_setg(errp, "'" SGX_EPC_MEMDEV_PROP "' property must be set");
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return NULL;
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}
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hostmem = MEMORY_BACKEND(epc->hostmem);
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return host_memory_backend_get_memory(hostmem);
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}
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static void sgx_epc_md_fill_device_info(const MemoryDeviceState *md,
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MemoryDeviceInfo *info)
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{
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2021-07-19 14:21:35 +03:00
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SgxEPCDeviceInfo *se = g_new0(SgxEPCDeviceInfo, 1);
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SGXEPCDevice *epc = SGX_EPC(md);
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se->memaddr = epc->addr;
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se->size = object_property_get_uint(OBJECT(epc), SGX_EPC_SIZE_PROP,
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NULL);
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numa: Enable numa for SGX EPC sections
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20211101162009.62161-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-11-01 19:20:05 +03:00
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se->node = object_property_get_uint(OBJECT(epc), SGX_EPC_NUMA_NODE_PROP,
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NULL);
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2021-07-19 14:21:35 +03:00
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se->memdev = object_get_canonical_path(OBJECT(epc->hostmem));
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info->u.sgx_epc.data = se;
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info->type = MEMORY_DEVICE_INFO_KIND_SGX_EPC;
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2021-07-19 14:21:07 +03:00
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}
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static void sgx_epc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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MemoryDeviceClass *mdc = MEMORY_DEVICE_CLASS(oc);
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dc->hotpluggable = false;
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dc->realize = sgx_epc_realize;
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dc->unrealize = sgx_epc_unrealize;
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dc->desc = "SGX EPC section";
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2021-11-09 20:50:14 +03:00
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dc->user_creatable = false;
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2021-07-19 14:21:07 +03:00
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device_class_set_props(dc, sgx_epc_properties);
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mdc->get_addr = sgx_epc_md_get_addr;
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mdc->set_addr = sgx_epc_md_set_addr;
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mdc->get_plugged_size = sgx_epc_md_get_plugged_size;
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mdc->get_memory_region = sgx_epc_md_get_memory_region;
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mdc->fill_device_info = sgx_epc_md_fill_device_info;
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}
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2022-01-17 17:58:04 +03:00
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static const TypeInfo sgx_epc_info = {
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2021-07-19 14:21:07 +03:00
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.name = TYPE_SGX_EPC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SGXEPCDevice),
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.instance_init = sgx_epc_init,
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.class_init = sgx_epc_class_init,
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.class_size = sizeof(DeviceClass),
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_MEMORY_DEVICE },
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{ }
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},
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};
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static void sgx_epc_register_types(void)
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{
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type_register_static(&sgx_epc_info);
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}
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type_init(sgx_epc_register_types)
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