mirror of https://github.com/dzavalishin/oskit/
235 lines
7.4 KiB
C
Executable File
235 lines
7.4 KiB
C
Executable File
/*
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* Copyright (c) 1994-1999 University of Utah and the Flux Group.
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* All rights reserved.
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*
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* This file is part of the Flux OSKit. The OSKit is free software, also known
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* as "open source;" you can redistribute it and/or modify it under the terms
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* of the GNU General Public License (GPL), version 2, as published by the Free
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* Software Foundation (FSF). To explore alternate licensing terms, contact
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* the University of Utah at csl-dist@cs.utah.edu or +1-801-585-3271.
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*
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* The OSKit is distributed in the hope that it will be useful, but WITHOUT ANY
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* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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* FOR A PARTICULAR PURPOSE. See the GPL for more details. You should have
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* received a copy of the GPL along with the OSKit; see the file COPYING. If
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* not, write to the FSF, 59 Temple Place #330, Boston, MA 02111-1307, USA.
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*/
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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Copyright (c) 1988,1989 Prime Computer, Inc. Natick, MA 01760
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All Rights Reserved.
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Permission to use, copy, modify, and distribute this
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software and its documentation for any purpose and
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without fee is hereby granted, provided that the above
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copyright notice appears in all copies and that both the
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copyright notice and this permission notice appear in
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supporting documentation, and that the name of Prime
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Computer, Inc. not be used in advertising or publicity
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pertaining to distribution of the software without
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specific, written prior permission.
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THIS SOFTWARE IS PROVIDED "AS IS", AND PRIME COMPUTER,
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INC. DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
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SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN
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NO EVENT SHALL PRIME COMPUTER, INC. BE LIABLE FOR ANY
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SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY
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DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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PROFITS, WHETHER IN ACTION OF CONTRACT, NEGLIGENCE, OR
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OTHER TORTIOUS ACTION, ARISING OUR OF OR IN CONNECTION
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WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Routines for manipulating the 8259A Programmable Interrupt
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* Controller (PIC)
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*/
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#include <sys/types.h>
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#include <oskit/arm32/pio.h>
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#include <oskit/arm32/proc_reg.h>
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#include <oskit/arm32/shark/pic.h>
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#include <assert.h>
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/*
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* Initialize the PIC,
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* Note that we don't disable all intrs here, you can call pic_disable_all.
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*
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* XXX the original Mach version put delays after the outb's in this
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* function, so we do the same thing (FreeBSD doesn't.) Don't know if
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* this is still required, the enable/disable functions below work
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* like champs without it.
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*/
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void
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pic_init(unsigned char master_base, unsigned char slave_base)
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{
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/* Initialize the master. */
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outb_p(MASTER_ICW, PICM_ICW1|LEVL_TRIGGER);
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outb_p(MASTER_OCW, master_base);
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outb_p(MASTER_OCW, PICM_ICW3);
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outb_p(MASTER_OCW, PICM_ICW4|AUTO_EOI_MOD);
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outb_p(MASTER_ICW, 0x68); /* special mask mode (if available) */
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outb_p(MASTER_ICW, 0x0a); /* Read IRR, not ISR */
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/* Initialize the slave. */
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outb_p(SLAVES_ICW, PICS_ICW1|LEVL_TRIGGER);
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outb_p(SLAVES_OCW, slave_base);
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outb_p(SLAVES_OCW, PICS_ICW3);
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outb_p(SLAVES_OCW, PICS_ICW4|AUTO_EOI_MOD);
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outb_p(SLAVES_ICW, 0x68); /* special mask mode (if available) */
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outb_p(SLAVES_ICW, 0x0a); /* Read IRR, not ISR */
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/* Ack any bogus intrs by setting the End Of Interrupt bit. */
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outb_p(MASTER_ICW, NON_SPEC_EOI);
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outb_p(SLAVES_ICW, NON_SPEC_EOI);
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}
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/*
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* Enable the irq by clearing the appropriate bit in the PIC.
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*/
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void
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pic_enable_irq(unsigned char irq)
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{
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unsigned int enabled = interrupts_enabled();
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assert(irq < 16);
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disable_interrupts();
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if (irq < 8)
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outb(MASTER_OCW, inb(MASTER_OCW) & ~(1 << irq));
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else {
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/* Enable the cascade line on the master. */
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outb(MASTER_OCW, inb(MASTER_OCW) & ~(1 << 2));
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irq -= 8;
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outb(SLAVES_OCW, inb(SLAVES_OCW) & ~(1 << irq));
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}
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if (enabled)
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enable_interrupts();
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}
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/*
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* Disable the irq by setting the appropriate bit in the PIC.
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*/
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void
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pic_disable_irq(unsigned char irq)
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{
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unsigned int enabled = interrupts_enabled();
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assert(irq < 16);
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disable_interrupts();
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if (irq < 8)
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outb(MASTER_OCW, inb(MASTER_OCW) | (1 << irq));
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else {
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irq -= 8;
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outb(SLAVES_OCW, inb(SLAVES_OCW) | (1 << irq));
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}
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if (enabled)
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enable_interrupts();
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}
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/*
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* Check to see if the specified irq is currently pending.
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*/
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int
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pic_test_irq(unsigned char irq)
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{
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assert(irq < 16);
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if (irq < 8)
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return inb(MASTER_ICW) & (1 << irq);
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else {
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irq -= 8;
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return inb(SLAVES_ICW) & (1 << irq);
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}
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}
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int
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pic_get_irqmask(void)
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{
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return (inb(SLAVES_OCW) << 8) | inb(MASTER_OCW);
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}
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void
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pic_set_irqmask(int mask)
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{
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unsigned int enabled, m, s;
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m = mask & 0xff;
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s = (mask >> 8) & 0xff;
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/* ensure that slave PIC is enabled if necessary */
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if (s != PICS_MASK)
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m &= ~(1 << 2);
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enabled = interrupts_enabled();
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disable_interrupts();
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outb(MASTER_OCW, m);
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outb(SLAVES_OCW, s);
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if (enabled)
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enable_interrupts();
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}
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