mirror of https://github.com/dzavalishin/oskit/
103 lines
3.2 KiB
C
Executable File
103 lines
3.2 KiB
C
Executable File
/*
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* Copyright (c) 1999 University of Utah and the Flux Group.
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* All rights reserved.
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*
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* This file is part of the Flux OSKit. The OSKit is free software, also known
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* as "open source;" you can redistribute it and/or modify it under the terms
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* of the GNU General Public License (GPL), version 2, as published by the Free
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* Software Foundation (FSF). To explore alternate licensing terms, contact
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* the University of Utah at csl-dist@cs.utah.edu or +1-801-585-3271.
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*
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* The OSKit is distributed in the hope that it will be useful, but WITHOUT ANY
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* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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* FOR A PARTICULAR PURPOSE. See the GPL for more details. You should have
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* received a copy of the GPL along with the OSKit; see the file COPYING. If
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* not, write to the FSF, 59 Temple Place #330, Boston, MA 02111-1307, USA.
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*/
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/*
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* Code to enable the basic paged memory environment on a SHARK. Much of
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* this stuff would also need to be done when changing the TTB pointer.
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*/
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#include <oskit/debug.h>
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#include <oskit/arm32/proc_reg.h>
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#include <oskit/arm32/base_paging.h>
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#include <oskit/arm32/base_vm.h>
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#include <oskit/arm32/base_trap.h>
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#include <oskit/arm32/trap.h>
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pd_entry_t *mypde;
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void base_paging_load(void)
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{
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int i;
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/* What about FIQs? */
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disable_interrupts();
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/*
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* Well, this is a major pain in the ass. I have not figured out
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* how to clean/flush individual lines from the cache, so changes
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* to the page directory and tables made through the virtual address,
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* do not get flushed to main memory where the TLB walker scans them.
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* So, go through and change all the page tables describing the
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* page directory and page tables (:-)) to non cacheable/bufferable
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* so that there is no cache coherence problem. Note that the pdir
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* functions arrange for newly allocated page tables to have the
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* proper bits changed.
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*
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* First do the page directory itself.
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*/
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pdir_prot_range(base_pdir_pa,
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phystokv(base_pdir_pa), ARM32_PD_SIZE,
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PT_AP(ARM32_AP_KRWURW) | ARM32_PTE_TYPE_SPAGE);
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/*
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* Now go through the page directory, and for each valid page
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* table, changes it bits.
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*/
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for (i = 0; i < ARM32_PD_SIZE / sizeof(pd_entry_t); i++) {
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mypde = (&((pd_entry_t*)phystokv(base_pdir_pa))[i]);
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if (! *mypde)
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continue;
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pdir_prot_range(base_pdir_pa,
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phystokv(pde_to_pa(*mypde)), PAGE_SIZE,
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PT_AP(ARM32_AP_KRWURW) | ARM32_PTE_TYPE_SPAGE);
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}
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/*
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* According to the SA110 spec, the only way to properly clean/flush
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* the data cache is to read from a special location in I/O space
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* in a loop that causes the entire D cache to be cleaned before
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* the write buffers are drained. Totally silly.
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*/
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arm32_cache_clean();
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flush_cache_I();
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drain_write_buffer();
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/* Set the translation table base register */
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set_ttb(base_pdir_pa);
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/* Flush the I+D TLBs! */
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flush_tlb_ID();
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/* Flush the I cache */
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flush_cache_I();
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/* Turn on the S bit so we get read-only pages! Must turn off R bit. */
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set_cpuctrl(get_cpuctrl() & ~CPU_CTRL_R);
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set_cpuctrl(get_cpuctrl() | CPU_CTRL_S);
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/* Set the domain control register to do access permission checks. */
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set_domctrl(ARM32_DOMAIN_CLIENT);
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/* Turn on the M bit (MMU enable) */
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set_cpuctrl(get_cpuctrl() | CPU_CTRL_M);
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enable_interrupts();
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}
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