170 lines
6.0 KiB
C
170 lines
6.0 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "nvidia-drm-conftest.h" /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
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#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
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#if defined(NV_DRM_DRMP_H_PRESENT)
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#include <drm/drmP.h>
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#endif
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#include <linux/kernel.h>
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#include <linux/bitmap.h>
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#include "nvidia-drm-format.h"
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#include "nvidia-drm-os-interface.h"
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static const u32 nvkms_to_drm_format[] = {
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/* RGB formats */
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[NvKmsSurfaceMemoryFormatA1R5G5B5] = DRM_FORMAT_ARGB1555,
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[NvKmsSurfaceMemoryFormatX1R5G5B5] = DRM_FORMAT_XRGB1555,
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[NvKmsSurfaceMemoryFormatR5G6B5] = DRM_FORMAT_RGB565,
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[NvKmsSurfaceMemoryFormatA8R8G8B8] = DRM_FORMAT_ARGB8888,
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[NvKmsSurfaceMemoryFormatX8R8G8B8] = DRM_FORMAT_XRGB8888,
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[NvKmsSurfaceMemoryFormatX8B8G8R8] = DRM_FORMAT_XBGR8888,
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[NvKmsSurfaceMemoryFormatA2B10G10R10] = DRM_FORMAT_ABGR2101010,
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[NvKmsSurfaceMemoryFormatX2B10G10R10] = DRM_FORMAT_XBGR2101010,
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[NvKmsSurfaceMemoryFormatA8B8G8R8] = DRM_FORMAT_ABGR8888,
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#if defined(DRM_FORMAT_ABGR16161616F)
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[NvKmsSurfaceMemoryFormatRF16GF16BF16AF16] = DRM_FORMAT_ABGR16161616F,
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#endif
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#if defined(DRM_FORMAT_XBGR16161616F)
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[NvKmsSurfaceMemoryFormatRF16GF16BF16XF16] = DRM_FORMAT_XBGR16161616F,
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#endif
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[NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422] = DRM_FORMAT_YUYV,
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[NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422] = DRM_FORMAT_UYVY,
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/* YUV semi-planar formats
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*
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* NVKMS YUV semi-planar formats are MSB aligned. Yx__UxVx means
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* that the UV components are packed like UUUUUVVVVV (MSB to LSB)
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* and Yx_VxUx means VVVVVUUUUU (MSB to LSB).
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*/
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/*
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* 2 plane YCbCr
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* index 0 = Y plane, [7:0] Y
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* index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
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* or
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* index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
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*/
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[NvKmsSurfaceMemoryFormatY8___V8U8_N444] = DRM_FORMAT_NV24, /* non-subsampled Cr:Cb plane */
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[NvKmsSurfaceMemoryFormatY8___U8V8_N444] = DRM_FORMAT_NV42, /* non-subsampled Cb:Cr plane */
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[NvKmsSurfaceMemoryFormatY8___V8U8_N422] = DRM_FORMAT_NV16, /* 2x1 subsampled Cr:Cb plane */
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[NvKmsSurfaceMemoryFormatY8___U8V8_N422] = DRM_FORMAT_NV61, /* 2x1 subsampled Cb:Cr plane */
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[NvKmsSurfaceMemoryFormatY8___V8U8_N420] = DRM_FORMAT_NV12, /* 2x2 subsampled Cr:Cb plane */
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[NvKmsSurfaceMemoryFormatY8___U8V8_N420] = DRM_FORMAT_NV21, /* 2x2 subsampled Cb:Cr plane */
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#if defined(DRM_FORMAT_P210)
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
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*
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* 2x1 subsampled Cr:Cb plane, 10 bit per channel
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*/
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[NvKmsSurfaceMemoryFormatY10___V10U10_N422] = DRM_FORMAT_P210,
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#endif
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#if defined(DRM_FORMAT_P010)
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
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*
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* 2x2 subsampled Cr:Cb plane 10 bits per channel
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*/
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[NvKmsSurfaceMemoryFormatY10___V10U10_N420] = DRM_FORMAT_P010,
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#endif
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#if defined(DRM_FORMAT_P012)
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [12:4] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
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*
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* 2x2 subsampled Cr:Cb plane 12 bits per channel
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*/
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[NvKmsSurfaceMemoryFormatY12___V12U12_N420] = DRM_FORMAT_P012,
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#endif
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};
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bool nv_drm_format_to_nvkms_format(u32 format,
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enum NvKmsSurfaceMemoryFormat *nvkms_format)
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{
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enum NvKmsSurfaceMemoryFormat i;
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for (i = 0; i < ARRAY_SIZE(nvkms_to_drm_format); i++) {
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/*
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* Note nvkms_to_drm_format[] is sparsely populated: it doesn't
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* handle all NvKmsSurfaceMemoryFormat values, so be sure to skip 0
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* entries when iterating through it.
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*/
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if (nvkms_to_drm_format[i] != 0 && nvkms_to_drm_format[i] == format) {
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*nvkms_format = i;
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return true;
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}
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}
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return false;
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}
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uint32_t *nv_drm_format_array_alloc(
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unsigned int *count,
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const long unsigned int nvkms_format_mask)
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{
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enum NvKmsSurfaceMemoryFormat i;
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unsigned int max_count = hweight64(nvkms_format_mask);
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uint32_t *array = nv_drm_calloc(1, sizeof(uint32_t) * max_count);
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if (array == NULL) {
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return NULL;
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}
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*count = 0;
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for_each_set_bit(i, &nvkms_format_mask,
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sizeof(nvkms_format_mask) * BITS_PER_BYTE) {
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if (i >= ARRAY_SIZE(nvkms_to_drm_format)) {
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break;
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}
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/*
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* Note nvkms_to_drm_format[] is sparsely populated: it doesn't
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* handle all NvKmsSurfaceMemoryFormat values, so be sure to skip 0
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* entries when iterating through it.
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*/
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if (nvkms_to_drm_format[i] == 0) {
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continue;
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}
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array[(*count)++] = nvkms_to_drm_format[i];
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}
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if (*count == 0) {
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nv_drm_free(array);
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return NULL;
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}
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return array;
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}
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#endif
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