341 lines
16 KiB
C
341 lines
16 KiB
C
/*******************************************************************************
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Copyright (c) 2016-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_global.h"
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "uvm_user_channel.h"
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#include "clc36f.h"
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void uvm_hal_volta_host_write_gpu_put(uvm_channel_t *channel, NvU32 gpu_put)
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{
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// We need to add a BAR1 read if GPPut is located in sysmem. This
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// guarantees that any in-flight BAR1 writes from the CPU will have reached
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// the GPU by the time the GPU reads the updated GPPut. Read the provided
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// BAR1 mapping in channel_info.
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if (channel->channel_info.dummyBar1Mapping)
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UVM_GPU_READ_ONCE(*channel->channel_info.dummyBar1Mapping);
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UVM_GPU_WRITE_ONCE(*channel->channel_info.gpPut, gpu_put);
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wmb();
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UVM_GPU_WRITE_ONCE(*channel->channel_info.workSubmissionOffset, channel->channel_info.workSubmissionToken);
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}
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static NvU32 fault_cancel_va_mode_to_cancel_access_type(uvm_fault_cancel_va_mode_t cancel_va_mode)
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{
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// There are only two logical cases from the perspective of UVM. Accesses to
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// an invalid address, which will cancel all accesses on the page, and
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// accesses with an invalid type on a read-only page, which will cancel all
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// write/atomic accesses on the page.
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switch (cancel_va_mode)
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{
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case UVM_FAULT_CANCEL_VA_MODE_ALL:
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return HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_ACCESS_TYPE, VIRT_ALL);
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case UVM_FAULT_CANCEL_VA_MODE_WRITE_AND_ATOMIC:
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return HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_ACCESS_TYPE, VIRT_WRITE_AND_ATOMIC);
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default:
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UVM_ASSERT_MSG(false, "Invalid cancel_va_mode %d\n", cancel_va_mode);
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}
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return 0;
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}
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void uvm_hal_volta_cancel_faults_va(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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const uvm_fault_buffer_entry_t *fault_entry,
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uvm_fault_cancel_va_mode_t cancel_va_mode)
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{
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NvU32 aperture_value;
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NvU32 pdb_lo;
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NvU32 pdb_hi;
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NvU32 addr_lo;
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NvU32 addr_hi;
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NvU32 access_type_value;
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NvU64 addr = fault_entry->fault_address;
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NvU32 mmu_engine_id = fault_entry->fault_source.mmu_engine_id;
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UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture);
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx not aligned to 4KB\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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access_type_value = fault_cancel_va_mode_to_cancel_access_type(cancel_va_mode);
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UVM_ASSERT_MSG(IS_ALIGNED(addr, 1 << 12), "addr 0x%llx not aligned to 4KB\n", addr);
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addr >>= 12;
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addr_lo = addr & HWMASK(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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addr_hi = addr >> HWSIZE(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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NV_PUSH_4U(C36F, MEM_OP_A, HWCONST(C36F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, addr_lo) |
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HWVALUE(C36F, MEM_OP_A, TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID, mmu_engine_id),
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MEM_OP_B, HWVALUE(C36F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, addr_hi),
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MEM_OP_C, HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_REPLAY, CANCEL_VA_GLOBAL) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, NONE) |
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access_type_value |
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aperture_value,
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C36F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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void uvm_hal_volta_host_clear_faulted_channel_method(uvm_push_t *push,
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uvm_user_channel_t *user_channel,
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const uvm_fault_buffer_entry_t *fault)
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{
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NvU32 clear_type_value = 0;
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UVM_ASSERT(user_channel->gpu->parent->has_clear_faulted_channel_method);
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if (fault->fault_source.mmu_engine_type == UVM_MMU_ENGINE_TYPE_HOST) {
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clear_type_value = HWCONST(C36F, CLEAR_FAULTED, TYPE, PBDMA_FAULTED);
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}
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else if (fault->fault_source.mmu_engine_type == UVM_MMU_ENGINE_TYPE_CE) {
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clear_type_value = HWCONST(C36F, CLEAR_FAULTED, TYPE, ENG_FAULTED);
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}
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else {
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UVM_ASSERT_MSG(false, "Unsupported MMU engine type %s\n",
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uvm_mmu_engine_type_string(fault->fault_source.mmu_engine_type));
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}
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NV_PUSH_1U(C36F, CLEAR_FAULTED, HWVALUE(C36F, CLEAR_FAULTED, CHID, user_channel->hw_channel_id) |
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clear_type_value);
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}
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void uvm_hal_volta_access_counter_clear_all(uvm_push_t *push)
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{
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NV_PUSH_4U(C36F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, 0,
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, ACCESS_COUNTER_CLR) |
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HWCONST(C36F, MEM_OP_D, ACCESS_COUNTER_CLR_TYPE, ALL));
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}
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static NvU32 get_access_counter_type_value(uvm_access_counter_type_t type)
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{
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if (type == UVM_ACCESS_COUNTER_TYPE_MIMC)
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return NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC;
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else if (type == UVM_ACCESS_COUNTER_TYPE_MOMC)
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return NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC;
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else
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UVM_ASSERT_MSG(false, "Invalid access counter type %u\n", type);
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return 0;
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}
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static NvU32 get_access_counter_targeted_type_value(uvm_access_counter_type_t type)
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{
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if (type == UVM_ACCESS_COUNTER_TYPE_MIMC)
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return NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC;
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else if (type == UVM_ACCESS_COUNTER_TYPE_MOMC)
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return NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC;
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else
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UVM_ASSERT_MSG(false, "Invalid access counter type %u\n", type);
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return 0;
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}
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void uvm_hal_volta_access_counter_clear_type(uvm_push_t *push, uvm_access_counter_type_t type)
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{
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NvU32 type_value = get_access_counter_type_value(type);
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NV_PUSH_4U(C36F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, 0,
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, ACCESS_COUNTER_CLR) |
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HWVALUE(C36F, MEM_OP_D, ACCESS_COUNTER_CLR_TYPE, type_value));
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}
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void uvm_hal_volta_access_counter_clear_targeted(uvm_push_t *push,
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const uvm_access_counter_buffer_entry_t *buffer_entry)
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{
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NvU32 targeted_type_value = get_access_counter_targeted_type_value(buffer_entry->counter_type);
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NV_PUSH_4U(C36F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, HWVALUE(C36F, MEM_OP_C, ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG, buffer_entry->tag),
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, ACCESS_COUNTER_CLR) |
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HWCONST(C36F, MEM_OP_D, ACCESS_COUNTER_CLR_TYPE, TARGETED) |
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HWVALUE(C36F, MEM_OP_D, ACCESS_COUNTER_CLR_TARGETED_TYPE, targeted_type_value) |
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HWVALUE(C36F, MEM_OP_D, ACCESS_COUNTER_CLR_TARGETED_BANK, buffer_entry->bank));
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}
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void uvm_hal_volta_host_tlb_invalidate_va(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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NvU32 depth,
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NvU64 base,
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NvU64 size,
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NvU64 page_size,
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uvm_membar_t membar)
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{
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NvU32 aperture_value;
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NvU32 page_table_level;
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NvU32 pdb_lo;
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NvU32 pdb_hi;
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NvU32 ack_value = 0;
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NvU32 va_lo;
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NvU32 va_hi;
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NvU64 end;
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NvU64 actual_base;
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NvU64 actual_size;
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NvU64 actual_end;
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NvU32 log2_invalidation_size;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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UVM_ASSERT_MSG(IS_ALIGNED(page_size, 1 << 12), "page_size 0x%llx\n", page_size);
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UVM_ASSERT_MSG(IS_ALIGNED(base, page_size), "base 0x%llx page_size 0x%llx\n", base, page_size);
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UVM_ASSERT_MSG(IS_ALIGNED(size, page_size), "size 0x%llx page_size 0x%llx\n", size, page_size);
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UVM_ASSERT_MSG(size > 0, "size 0x%llx\n", size);
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// The invalidation size must be a power-of-two number of pages containing
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// the passed interval
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end = base + size - 1;
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log2_invalidation_size = __fls((unsigned long)(end ^ base)) + 1;
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if (log2_invalidation_size == 64) {
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// Invalidate everything
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gpu->parent->host_hal->tlb_invalidate_all(push, pdb, depth, membar);
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return;
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}
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// The hardware aligns the target address down to the invalidation size.
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actual_size = 1ULL << log2_invalidation_size;
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actual_base = UVM_ALIGN_DOWN(base, actual_size);
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actual_end = actual_base + actual_size - 1;
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UVM_ASSERT(actual_end >= end);
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// The invalidation size field expects log2(invalidation size in 4K), not
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// log2(invalidation size in bytes)
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log2_invalidation_size -= 12;
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// Address to invalidate, as a multiple of 4K.
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base >>= 12;
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va_lo = base & HWMASK(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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va_hi = base >> HWSIZE(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture);
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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// PDE3 is the highest level on Pascal and Volta, see the comment in
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// uvm_pascal_mmu.c for details.
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UVM_ASSERT_MSG(depth < NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3, "depth %u", depth);
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page_table_level = NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 - depth;
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if (membar != UVM_MEMBAR_NONE) {
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// If a GPU or SYS membar is needed, ACK_TYPE needs to be set to
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// GLOBALLY to make sure all the pending accesses can be picked up by
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// the membar.
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ack_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY);
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}
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NV_PUSH_4U(C36F, MEM_OP_A, HWVALUE(C36F, MEM_OP_A, TLB_INVALIDATE_INVALIDATION_SIZE, log2_invalidation_size) |
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HWCONST(C36F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo),
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MEM_OP_B, HWVALUE(C36F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi),
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MEM_OP_C, HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) |
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HWVALUE(C36F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) |
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aperture_value |
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ack_value,
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C36F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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uvm_hal_tlb_invalidate_membar(push, membar);
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}
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void uvm_hal_volta_replay_faults(uvm_push_t *push, uvm_fault_replay_type_t type)
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{
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NvU32 replay_value = 0;
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const NvU32 va_lo = 0;
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const NvU32 va_hi = 0;
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const NvU32 pdb_lo = 0;
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const NvU32 pdb_hi = 0;
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// On Volta+ the MMU will forward the replay to the uTLBs even if the PDB
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// is not in the MMU PDB_ID cache. Therefore, we target a dummy PDB to
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// avoid any VA invalidation, which could impact on the performance.
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UVM_ASSERT_MSG(type == UVM_FAULT_REPLAY_TYPE_START || type == UVM_FAULT_REPLAY_TYPE_START_ACK_ALL,
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"replay_type: %u\n", type);
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if (type == UVM_FAULT_REPLAY_TYPE_START)
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replay_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_REPLAY, START);
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else if (type == UVM_FAULT_REPLAY_TYPE_START_ACK_ALL)
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replay_value = HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_REPLAY, START_ACK_ALL);
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NV_PUSH_4U(C36F, MEM_OP_A, HWCONST(C36F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C36F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo),
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MEM_OP_B, HWVALUE(C36F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi),
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MEM_OP_C, HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, PTE_ONLY) |
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HWCONST(C36F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM) |
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replay_value,
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MEM_OP_D, HWCONST(C36F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C36F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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void uvm_hal_volta_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
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{
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NvU32 sem_lo;
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UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C36F, SEM_ADDR_LO, OFFSET)));
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sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C36F, SEM_ADDR_LO, OFFSET);
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uvm_hal_wfi_membar(push, uvm_push_get_and_reset_membar_flag(push));
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NV_PUSH_5U(C36F, SEM_ADDR_LO, HWVALUE(C36F, SEM_ADDR_LO, OFFSET, sem_lo),
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SEM_ADDR_HI, HWVALUE(C36F, SEM_ADDR_HI, OFFSET, NvOffset_HI32(gpu_va)),
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SEM_PAYLOAD_LO, 0xdeadbeef,
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SEM_PAYLOAD_HI, 0,
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SEM_EXECUTE, HWCONST(C36F, SEM_EXECUTE, OPERATION, RELEASE) |
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HWCONST(C36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
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HWCONST(C36F, SEM_EXECUTE, RELEASE_TIMESTAMP, EN) |
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HWCONST(C36F, SEM_EXECUTE, RELEASE_WFI, DIS));
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}
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