124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/*******************************************************************************
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Copyright (c) 2021-2024 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_global.h"
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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#include "hwref/turing/tu102/dev_fault.h"
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static void clear_replayable_faults_interrupt(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->fault_buffer_info.rm_info.replayable.pPmcIntr;
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mask = parent_gpu->fault_buffer_info.rm_info.replayable.replayableFaultMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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}
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void uvm_hal_turing_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get)
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{
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clear_replayable_faults_interrupt(parent_gpu);
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wmb();
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// Write GET to force the re-evaluation of the interrupt condition after the
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// interrupt bit has been cleared.
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parent_gpu->fault_buffer_hal->write_get(parent_gpu, get);
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}
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void uvm_hal_turing_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu)
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{
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volatile NvU32 *reg;
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NvU32 mask;
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reg = parent_gpu->fault_buffer_info.rm_info.replayable.pPmcIntrEnClear;
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mask = parent_gpu->fault_buffer_info.rm_info.replayable.replayableFaultMask;
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UVM_GPU_WRITE_ONCE(*reg, mask);
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wmb();
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// We clear the interrupts right after disabling them in order to avoid
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// triggering unnecessary new interrupts after re-enabling them if the
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// interrupt condition is no longer true.
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clear_replayable_faults_interrupt(parent_gpu);
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}
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static bool client_id_ce(NvU16 client_id)
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{
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if (client_id >= NV_PFAULT_CLIENT_HUB_HSCE0 && client_id <= NV_PFAULT_CLIENT_HUB_HSCE9)
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return true;
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switch (client_id) {
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case NV_PFAULT_CLIENT_HUB_CE0:
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case NV_PFAULT_CLIENT_HUB_CE1:
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case NV_PFAULT_CLIENT_HUB_CE2:
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return true;
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}
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return false;
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}
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static bool client_id_host(NvU16 client_id)
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{
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switch (client_id) {
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case NV_PFAULT_CLIENT_HUB_HOST:
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case NV_PFAULT_CLIENT_HUB_HOST_CPU:
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return true;
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}
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return false;
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}
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uvm_mmu_engine_type_t uvm_hal_turing_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id)
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{
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// Servicing CE and Host (HUB clients) faults.
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if (client_type == UVM_FAULT_CLIENT_TYPE_HUB) {
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if (client_id_ce(client_id)) {
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UVM_ASSERT(mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_CE0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_CE8);
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return UVM_MMU_ENGINE_TYPE_CE;
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}
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if (client_id_host(client_id)) {
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UVM_ASSERT(mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_HOST0 && mmu_engine_id <= NV_PFAULT_MMU_ENG_ID_HOST14);
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return UVM_MMU_ENGINE_TYPE_HOST;
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}
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}
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// We shouldn't be servicing faults from any other engines other than GR.
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UVM_ASSERT_MSG(client_id <= NV_PFAULT_CLIENT_GPC_T1_39, "Unexpected client ID: 0x%x\n", client_id);
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UVM_ASSERT_MSG(mmu_engine_id >= NV_PFAULT_MMU_ENG_ID_GRAPHICS && mmu_engine_id < NV_PFAULT_MMU_ENG_ID_BAR1,
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"Unexpected engine ID: 0x%x\n",
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mmu_engine_id);
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UVM_ASSERT(client_type == UVM_FAULT_CLIENT_TYPE_GPC);
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return UVM_MMU_ENGINE_TYPE_GRAPHICS;
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}
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