365 lines
18 KiB
C
365 lines
18 KiB
C
/*******************************************************************************
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Copyright (c) 2015-2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_linux.h"
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#include "uvm_hal_types.h"
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "uvm_channel.h"
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#include "clc06f.h"
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#include "clc076.h"
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void uvm_hal_pascal_host_membar_sys(uvm_push_t *push)
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{
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NV_PUSH_4U(C06F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR),
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MEMBAR));
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}
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void uvm_hal_pascal_host_membar_gpu(uvm_push_t *push)
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{
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NV_PUSH_4U(C06F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, MEMBAR_TYPE, MEMBAR),
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MEMBAR));
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}
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void uvm_hal_pascal_host_tlb_invalidate_all(uvm_push_t *push, uvm_gpu_phys_address_t pdb, NvU32 depth, uvm_membar_t membar)
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{
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NvU32 aperture_value;
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NvU32 page_table_level;
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NvU32 pdb_lo;
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NvU32 pdb_hi;
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NvU32 ack_value = 0;
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UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture);
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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// PDE3 is the highest level on Pascal, see the comment in uvm_pascal_mmu.c for details.
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UVM_ASSERT_MSG(depth < NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3, "depth %u", depth);
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page_table_level = NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 - depth;
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if (membar != UVM_MEMBAR_NONE) {
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// If a GPU or SYS membar is needed, ACK_TYPE needs to be set to
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// GLOBALLY to make sure all the pending accesses can be picked up by
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// the membar.
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ack_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY);
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}
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NV_PUSH_4U(C06F, MEM_OP_A, HWCONST(C06F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS),
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MEM_OP_B, 0,
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) |
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aperture_value |
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ack_value,
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE) |
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HWVALUE(C06F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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uvm_hal_tlb_invalidate_membar(push, membar);
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}
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void uvm_hal_pascal_host_tlb_invalidate_va(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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NvU32 depth,
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NvU64 base,
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NvU64 size,
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NvU64 page_size,
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uvm_membar_t membar)
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{
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NvU32 aperture_value;
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NvU32 page_table_level;
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NvU32 pdb_lo;
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NvU32 pdb_hi;
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NvU32 ack_value = 0;
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NvU64 va;
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NvU32 va_lo;
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NvU32 va_hi;
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UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture);
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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// PDE3 is the highest level on Pascal, see the comment in uvm_pascal_mmu.c for details.
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UVM_ASSERT_MSG(depth < NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3, "depth %u", depth);
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page_table_level = NVC06F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 - depth;
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if (membar != UVM_MEMBAR_NONE) {
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// If a GPU or SYS membar is needed, ACK_TYPE needs to be set to
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// GLOBALLY to make sure all the pending accesses can be picked up by
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// the membar.
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ack_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY);
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}
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UVM_ASSERT_MSG(IS_ALIGNED(page_size, 1 << 12), "page_size 0x%llx\n", page_size);
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UVM_ASSERT_MSG(IS_ALIGNED(base, page_size), "base 0x%llx page_size 0x%llx\n", base, page_size);
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UVM_ASSERT_MSG(IS_ALIGNED(size, page_size), "size 0x%llx page_size 0x%llx\n", size, page_size);
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UVM_ASSERT_MSG(size > 0, "size 0x%llx\n", size);
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base >>= 12;
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size >>= 12;
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page_size >>= 12;
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for (va = base; va < base + size; va += page_size) {
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va_lo = va & HWMASK(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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va_hi = va >> HWSIZE(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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NV_PUSH_4U(C06F, MEM_OP_A, HWCONST(C06F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo),
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MEM_OP_B, HWVALUE(C06F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi),
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) |
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aperture_value |
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ack_value,
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C06F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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uvm_hal_tlb_invalidate_membar(push, membar);
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}
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void uvm_hal_pascal_host_tlb_invalidate_test(uvm_push_t *push, uvm_gpu_phys_address_t pdb,
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UVM_TEST_INVALIDATE_TLB_PARAMS *params)
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{
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NvU32 ack_value = 0;
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NvU32 invalidate_gpc_value = 0;
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NvU32 aperture_value = 0;
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NvU32 pdb_lo = 0;
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NvU32 pdb_hi = 0;
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NvU32 page_table_level = 0;
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uvm_membar_t membar;
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UVM_ASSERT_MSG(pdb.aperture == UVM_APERTURE_VID || pdb.aperture == UVM_APERTURE_SYS, "aperture: %u", pdb.aperture);
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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if (params->page_table_level != UvmInvalidatePageTableLevelAll) {
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// PDE3 is the highest level on Pascal, see the comment in
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// uvm_pascal_mmu.c for details.
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page_table_level = min((NvU32)UvmInvalidatePageTableLevelPde3, params->page_table_level) - 1;
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}
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if (params->membar != UvmInvalidateTlbMemBarNone) {
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// If a GPU or SYS membar is needed, ack_value needs to be set to
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// GLOBALLY to make sure all the pending accesses can be picked up by
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// the membar.
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ack_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_ACK_TYPE, GLOBALLY);
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}
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if (params->disable_gpc_invalidate)
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invalidate_gpc_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_GPC, DISABLE);
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else
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invalidate_gpc_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE);
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if (params->target_va_mode == UvmTargetVaModeTargeted) {
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NvU64 va = params->va >> 12;
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NvU32 va_lo = va & HWMASK(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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NvU32 va_hi = va >> HWSIZE(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO);
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NV_PUSH_4U(C06F, MEM_OP_A, HWCONST(C06F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo),
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MEM_OP_B, HWVALUE(C06F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi),
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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invalidate_gpc_value |
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aperture_value |
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ack_value,
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C06F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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else {
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NV_PUSH_4U(C06F, MEM_OP_A, HWCONST(C06F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS),
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MEM_OP_B, 0,
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, NONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, page_table_level) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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invalidate_gpc_value |
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aperture_value |
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ack_value,
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE) |
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HWVALUE(C06F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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if (params->membar == UvmInvalidateTlbMemBarSys)
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membar = UVM_MEMBAR_SYS;
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else if (params->membar == UvmInvalidateTlbMemBarLocal)
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membar = UVM_MEMBAR_GPU;
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else
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membar = UVM_MEMBAR_NONE;
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uvm_hal_tlb_invalidate_membar(push, membar);
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}
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void uvm_hal_pascal_replay_faults(uvm_push_t *push, uvm_fault_replay_type_t type)
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{
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NvU32 aperture_value;
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NvU32 replay_value = 0;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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uvm_gpu_phys_address_t pdb;
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NvU32 va_lo = 0;
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NvU32 va_hi = 0;
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NvU32 pdb_lo;
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NvU32 pdb_hi;
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// MMU will not forward the replay to the uTLBs if the PDB is not in the MMU PDB_ID cache. If
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// we have stale entries filling the fault buffer and a context switch has happened, the new
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// context may have faulted without writing its entries into the buffer. To force a replay
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// regardless of which faults happen to be in the uTLB replay lists, we use the PDB of the
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// channel used to push the replay, which is guaranteed to be in the cache as it is required
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// to be resident for the channel to push the method. In order to minimize the performance hit
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// of the invalidation, we just invalidate PTEs for address 0x0.
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UVM_ASSERT_MSG(type == UVM_FAULT_REPLAY_TYPE_START || type == UVM_FAULT_REPLAY_TYPE_START_ACK_ALL,
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"replay_type: %u\n", type);
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pdb = uvm_page_tree_pdb(&gpu->address_space_tree)->addr;
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if (pdb.aperture == UVM_APERTURE_VID)
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, VID_MEM);
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else
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aperture_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_APERTURE, SYS_MEM_COHERENT);
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UVM_ASSERT_MSG(IS_ALIGNED(pdb.address, 1 << 12), "pdb 0x%llx\n", pdb.address);
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pdb.address >>= 12;
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pdb_lo = pdb.address & HWMASK(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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pdb_hi = pdb.address >> HWSIZE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO);
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if (type == UVM_FAULT_REPLAY_TYPE_START)
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replay_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, START);
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else if (type == UVM_FAULT_REPLAY_TYPE_START_ACK_ALL)
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replay_value = HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_REPLAY, START_ACK_ALL);
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NV_PUSH_4U(C06F, MEM_OP_A, HWCONST(C06F, MEM_OP_A, TLB_INVALIDATE_SYSMEMBAR, DIS) |
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HWVALUE(C06F, MEM_OP_A, TLB_INVALIDATE_TARGET_ADDR_LO, va_lo),
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MEM_OP_B, HWVALUE(C06F, MEM_OP_B, TLB_INVALIDATE_TARGET_ADDR_HI, va_hi),
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MEM_OP_C, HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PDB, ONE) |
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HWVALUE(C06F, MEM_OP_C, TLB_INVALIDATE_PDB_ADDR_LO, pdb_lo) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_GPC, ENABLE) |
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HWCONST(C06F, MEM_OP_C, TLB_INVALIDATE_PAGE_TABLE_LEVEL, PTE_ONLY) |
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aperture_value |
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replay_value,
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MEM_OP_D, HWCONST(C06F, MEM_OP_D, OPERATION, MMU_TLB_INVALIDATE_TARGETED) |
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HWVALUE(C06F, MEM_OP_D, TLB_INVALIDATE_PDB_ADDR_HI, pdb_hi));
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}
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static NvU32 instance_ptr_aperture_type_to_hw_value(uvm_aperture_t aperture)
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{
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switch (aperture)
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{
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case UVM_APERTURE_SYS:
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return HWCONST(C076, FAULT_CANCEL_A, INST_APERTURE, SYS_MEM_COHERENT);
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case UVM_APERTURE_VID:
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return HWCONST(C076, FAULT_CANCEL_A, INST_APERTURE, VID_MEM);
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default:
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UVM_ASSERT_MSG(false, "Invalid aperture_type %d\n", aperture);
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}
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return 0;
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}
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void uvm_hal_pascal_host_init(uvm_push_t *push)
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{
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if (uvm_channel_is_ce(push->channel))
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NV_PUSH_1U(C076, SET_OBJECT, GP100_UVM_SW);
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}
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static void instance_ptr_address_to_hw_values(NvU64 instance_ptr_address,
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NvU32 *instance_ptr_lo,
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NvU32 *instance_ptr_hi)
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{
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// instance_ptr must be 4K aligned
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UVM_ASSERT_MSG(IS_ALIGNED(instance_ptr_address, 1 << 12), "instance_ptr 0x%llx\n", instance_ptr_address);
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instance_ptr_address >>= 12;
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*instance_ptr_lo = instance_ptr_address & HWMASK(C076, FAULT_CANCEL_A, INST_LOW);
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*instance_ptr_hi = instance_ptr_address >> HWSIZE(C076, FAULT_CANCEL_A, INST_LOW);
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}
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void uvm_hal_pascal_cancel_faults_global(uvm_push_t *push, uvm_gpu_phys_address_t instance_ptr)
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{
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NvU32 instance_ptr_lo, instance_ptr_hi;
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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// Global cancellations affect all MIG instances, not only the one that
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// originated the fault to be cancelled
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UVM_ASSERT(!gpu->parent->smc.enabled);
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instance_ptr_address_to_hw_values(instance_ptr.address, &instance_ptr_lo, &instance_ptr_hi);
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NV_PUSH_3U(C076, FAULT_CANCEL_A, HWVALUE(C076, FAULT_CANCEL_A, INST_LOW, instance_ptr_lo) |
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instance_ptr_aperture_type_to_hw_value(instance_ptr.aperture),
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FAULT_CANCEL_B, HWVALUE(C076, FAULT_CANCEL_B, INST_HI, instance_ptr_hi),
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FAULT_CANCEL_C, HWCONST(C076, FAULT_CANCEL_C, MODE, GLOBAL));
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}
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void uvm_hal_pascal_cancel_faults_targeted(uvm_push_t *push,
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uvm_gpu_phys_address_t instance_ptr,
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NvU32 gpc_id,
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NvU32 client_id)
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{
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NvU32 instance_ptr_lo, instance_ptr_hi;
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instance_ptr_address_to_hw_values(instance_ptr.address, &instance_ptr_lo, &instance_ptr_hi);
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NV_PUSH_3U(C076, FAULT_CANCEL_A, HWVALUE(C076, FAULT_CANCEL_A, INST_LOW, instance_ptr_lo) |
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instance_ptr_aperture_type_to_hw_value(instance_ptr.aperture),
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FAULT_CANCEL_B, HWVALUE(C076, FAULT_CANCEL_B, INST_HI, instance_ptr_hi),
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FAULT_CANCEL_C, HWVALUE(C076, FAULT_CANCEL_C, CLIENT_ID, client_id) |
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HWVALUE(C076, FAULT_CANCEL_C, GPC_ID, gpc_id) |
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HWCONST(C076, FAULT_CANCEL_C, MODE, TARGETED));
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}
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