124 lines
5.2 KiB
C
124 lines
5.2 KiB
C
/*******************************************************************************
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Copyright (c) 2016-2020 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_push.h"
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#include "clc0b5.h"
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void uvm_hal_pascal_ce_offset_out(uvm_push_t *push, NvU64 offset_out)
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{
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NV_PUSH_2U(C0B5, OFFSET_OUT_UPPER, HWVALUE(C0B5, OFFSET_OUT_UPPER, UPPER, NvOffset_HI32(offset_out)),
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OFFSET_OUT_LOWER, HWVALUE(C0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out)));
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}
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void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 offset_out)
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{
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NV_PUSH_4U(C0B5, OFFSET_IN_UPPER, HWVALUE(C0B5, OFFSET_IN_UPPER, UPPER, NvOffset_HI32(offset_in)),
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OFFSET_IN_LOWER, HWVALUE(C0B5, OFFSET_IN_LOWER, VALUE, NvOffset_LO32(offset_in)),
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OFFSET_OUT_UPPER, HWVALUE(C0B5, OFFSET_OUT_UPPER, UPPER, NvOffset_HI32(offset_out)),
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OFFSET_OUT_LOWER, HWVALUE(C0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out)));
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}
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void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 flush_value;
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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else
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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NV_PUSH_3U(C0B5, SET_SEMAPHORE_A, HWVALUE(C0B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C0B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, payload);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C0B5, LAUNCH_DMA, flush_value |
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HWCONST(C0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) |
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launch_dma_plc_mode);
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}
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void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 flush_value;
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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else
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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NV_PUSH_3U(C0B5, SET_SEMAPHORE_A, HWVALUE(C0B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C0B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, payload);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C0B5, LAUNCH_DMA, flush_value |
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HWCONST(C0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_ONE_WORD_SEMAPHORE) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_REDUCTION, INC) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_SIGN, UNSIGNED) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_REDUCTION_ENABLE, TRUE) |
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launch_dma_plc_mode);
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}
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void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
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{
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uvm_gpu_t *gpu;
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NvU32 flush_value;
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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else
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, FALSE);
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NV_PUSH_3U(C0B5, SET_SEMAPHORE_A, HWVALUE(C0B5, SET_SEMAPHORE_A, UPPER, NvOffset_HI32(gpu_va)),
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SET_SEMAPHORE_B, HWVALUE(C0B5, SET_SEMAPHORE_B, LOWER, NvOffset_LO32(gpu_va)),
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SET_SEMAPHORE_PAYLOAD, 0xdeadbeef);
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gpu = uvm_push_get_gpu(push);
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launch_dma_plc_mode = gpu->parent->ce_hal->plc_mode();
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NV_PUSH_1U(C0B5, LAUNCH_DMA, flush_value |
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HWCONST(C0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NONE) |
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HWCONST(C0B5, LAUNCH_DMA, SEMAPHORE_TYPE, RELEASE_FOUR_WORD_SEMAPHORE) |
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launch_dma_plc_mode);
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}
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