79 lines
3.0 KiB
C
79 lines
3.0 KiB
C
/*******************************************************************************
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Copyright (c) 2016-2023 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_hal.h"
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#include "uvm_gpu.h"
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#include "uvm_mem.h"
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void uvm_hal_maxwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu)
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{
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parent_gpu->tlb_batch.va_invalidate_supported = false;
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// 128 GB should be enough for all current RM allocations and leaves enough
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// space for UVM internal mappings.
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// A single top level PDE covers 64 or 128 MB on Maxwell so 128 GB is fine to use.
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parent_gpu->rm_va_base = 0;
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parent_gpu->rm_va_size = 128 * UVM_SIZE_1GB;
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parent_gpu->uvm_mem_va_base = 768 * UVM_SIZE_1GB;
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parent_gpu->uvm_mem_va_size = UVM_MEM_VA_SIZE;
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parent_gpu->ce_phys_vidmem_write_supported = true;
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// We don't have a compelling use case in UVM-Lite for direct peer
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// migrations between GPUs, so don't bother setting them up.
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parent_gpu->peer_copy_mode = UVM_GPU_PEER_COPY_MODE_UNSUPPORTED;
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parent_gpu->max_channel_va = 1ULL << 40;
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parent_gpu->max_host_va = 1ULL << 40;
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// Maxwell can only map sysmem with 4K pages
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parent_gpu->can_map_sysmem_with_large_pages = false;
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// Maxwell cannot place GPFIFO in vidmem
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parent_gpu->gpfifo_in_vidmem_supported = false;
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parent_gpu->replayable_faults_supported = false;
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parent_gpu->non_replayable_faults_supported = false;
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parent_gpu->access_counters_supported = false;
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parent_gpu->access_counters_can_use_physical_addresses = false;
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parent_gpu->fault_cancel_va_supported = false;
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parent_gpu->scoped_atomics_supported = false;
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parent_gpu->sparse_mappings_supported = false;
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parent_gpu->map_remap_larger_page_promotion = false;
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parent_gpu->smc.supported = false;
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parent_gpu->plc_supported = false;
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parent_gpu->no_ats_range_required = false;
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}
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