399 lines
17 KiB
C
399 lines
17 KiB
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _UAPI_NVIDIA_DRM_IOCTL_H_
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#define _UAPI_NVIDIA_DRM_IOCTL_H_
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#include <drm/drm.h>
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/*
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* We should do our best to keep these values constant. Any change to these will
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* be backwards incompatible with client applications that might be using them
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*/
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#define DRM_NVIDIA_GET_CRTC_CRC32 0x00
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#define DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY 0x01
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#define DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY 0x02
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#define DRM_NVIDIA_GET_DEV_INFO 0x03
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#define DRM_NVIDIA_FENCE_SUPPORTED 0x04
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#define DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE 0x05
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#define DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH 0x06
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#define DRM_NVIDIA_GET_CLIENT_CAPABILITY 0x08
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#define DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY 0x09
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#define DRM_NVIDIA_GEM_MAP_OFFSET 0x0a
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#define DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY 0x0b
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#define DRM_NVIDIA_GET_CRTC_CRC32_V2 0x0c
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#define DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY 0x0d
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#define DRM_NVIDIA_GEM_IDENTIFY_OBJECT 0x0e
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#define DRM_NVIDIA_DMABUF_SUPPORTED 0x0f
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#define DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID 0x10
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#define DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID 0x11
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#define DRM_NVIDIA_GRANT_PERMISSIONS 0x12
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#define DRM_NVIDIA_REVOKE_PERMISSIONS 0x13
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#define DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE 0x14
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#define DRM_NVIDIA_SEMSURF_FENCE_CREATE 0x15
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#define DRM_NVIDIA_SEMSURF_FENCE_WAIT 0x16
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#define DRM_NVIDIA_SEMSURF_FENCE_ATTACH 0x17
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#define DRM_NVIDIA_GET_DRM_FILE_UNIQUE_ID 0x18
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#define DRM_IOCTL_NVIDIA_GEM_IMPORT_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_NVKMS_MEMORY), \
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struct drm_nvidia_gem_import_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IMPORT_USERSPACE_MEMORY), \
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struct drm_nvidia_gem_import_userspace_memory_params)
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#define DRM_IOCTL_NVIDIA_GET_DEV_INFO \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DEV_INFO), \
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struct drm_nvidia_get_dev_info_params)
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/*
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* XXX Solaris compiler has issues with DRM_IO. None of this is supported on
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* Solaris anyway, so just skip it.
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*
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* 'warning: suggest parentheses around arithmetic in operand of |'
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*/
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#if defined(NV_LINUX) || defined(NV_BSD)
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#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED \
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DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_FENCE_SUPPORTED)
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#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED \
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DRM_IO(DRM_COMMAND_BASE + DRM_NVIDIA_DMABUF_SUPPORTED)
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#else
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#define DRM_IOCTL_NVIDIA_FENCE_SUPPORTED 0
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#define DRM_IOCTL_NVIDIA_DMABUF_SUPPORTED 0
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#endif
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#define DRM_IOCTL_NVIDIA_PRIME_FENCE_CONTEXT_CREATE \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_PRIME_FENCE_CONTEXT_CREATE),\
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struct drm_nvidia_prime_fence_context_create_params)
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#define DRM_IOCTL_NVIDIA_GEM_PRIME_FENCE_ATTACH \
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DRM_IOW((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_PRIME_FENCE_ATTACH), \
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struct drm_nvidia_gem_prime_fence_attach_params)
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#define DRM_IOCTL_NVIDIA_GET_CLIENT_CAPABILITY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CLIENT_CAPABILITY), \
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struct drm_nvidia_get_client_capability_params)
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#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32 \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32), \
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struct drm_nvidia_get_crtc_crc32_params)
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#define DRM_IOCTL_NVIDIA_GET_CRTC_CRC32_V2 \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CRTC_CRC32_V2), \
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struct drm_nvidia_get_crtc_crc32_v2_params)
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#define DRM_IOCTL_NVIDIA_GEM_EXPORT_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_NVKMS_MEMORY), \
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struct drm_nvidia_gem_export_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_MAP_OFFSET \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_MAP_OFFSET), \
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struct drm_nvidia_gem_map_offset_params)
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#define DRM_IOCTL_NVIDIA_GEM_ALLOC_NVKMS_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_ALLOC_NVKMS_MEMORY), \
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struct drm_nvidia_gem_alloc_nvkms_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_EXPORT_DMABUF_MEMORY \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_EXPORT_DMABUF_MEMORY), \
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struct drm_nvidia_gem_export_dmabuf_memory_params)
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#define DRM_IOCTL_NVIDIA_GEM_IDENTIFY_OBJECT \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GEM_IDENTIFY_OBJECT), \
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struct drm_nvidia_gem_identify_object_params)
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#define DRM_IOCTL_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_DPY_ID_FOR_CONNECTOR_ID),\
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struct drm_nvidia_get_dpy_id_for_connector_id_params)
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#define DRM_IOCTL_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GET_CONNECTOR_ID_FOR_DPY_ID),\
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struct drm_nvidia_get_connector_id_for_dpy_id_params)
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#define DRM_IOCTL_NVIDIA_GRANT_PERMISSIONS \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_GRANT_PERMISSIONS), \
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struct drm_nvidia_grant_permissions_params)
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#define DRM_IOCTL_NVIDIA_REVOKE_PERMISSIONS \
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DRM_IOWR((DRM_COMMAND_BASE + DRM_NVIDIA_REVOKE_PERMISSIONS), \
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struct drm_nvidia_revoke_permissions_params)
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#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CTX_CREATE \
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DRM_IOWR((DRM_COMMAND_BASE + \
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DRM_NVIDIA_SEMSURF_FENCE_CTX_CREATE), \
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struct drm_nvidia_semsurf_fence_ctx_create_params)
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#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_CREATE \
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DRM_IOWR((DRM_COMMAND_BASE + \
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DRM_NVIDIA_SEMSURF_FENCE_CREATE), \
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struct drm_nvidia_semsurf_fence_create_params)
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#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_WAIT \
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DRM_IOW((DRM_COMMAND_BASE + \
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DRM_NVIDIA_SEMSURF_FENCE_WAIT), \
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struct drm_nvidia_semsurf_fence_wait_params)
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#define DRM_IOCTL_NVIDIA_SEMSURF_FENCE_ATTACH \
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DRM_IOW((DRM_COMMAND_BASE + \
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DRM_NVIDIA_SEMSURF_FENCE_ATTACH), \
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struct drm_nvidia_semsurf_fence_attach_params)
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#define DRM_IOCTL_NVIDIA_GET_DRM_FILE_UNIQUE_ID \
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DRM_IOWR((DRM_COMMAND_BASE + \
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DRM_NVIDIA_GET_DRM_FILE_UNIQUE_ID), \
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struct drm_nvidia_get_drm_file_unique_id_params)
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struct drm_nvidia_gem_import_nvkms_memory_params {
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uint64_t mem_size; /* IN */
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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uint32_t handle; /* OUT */
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uint32_t __pad;
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};
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struct drm_nvidia_gem_import_userspace_memory_params {
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uint64_t size; /* IN Size of memory in bytes */
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uint64_t address; /* IN Virtual address of userspace memory */
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uint32_t handle; /* OUT Handle to gem object */
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};
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struct drm_nvidia_get_dev_info_params {
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uint32_t gpu_id; /* OUT */
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uint32_t primary_index; /* OUT; the "card%d" value */
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uint32_t supports_alloc; /* OUT */
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/* The generic_page_kind, page_kind_generation, and sector_layout
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* fields are only valid if supports_alloc is true.
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* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these. */
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uint32_t generic_page_kind; /* OUT */
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uint32_t page_kind_generation; /* OUT */
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uint32_t sector_layout; /* OUT */
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uint32_t supports_sync_fd; /* OUT */
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uint32_t supports_semsurf; /* OUT */
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};
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struct drm_nvidia_prime_fence_context_create_params {
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uint32_t handle; /* OUT GEM handle to fence context */
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uint32_t index; /* IN Index of semaphore to use for fencing */
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uint64_t size; /* IN Size of semaphore surface in bytes */
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/* Params for importing userspace semaphore surface */
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uint64_t import_mem_nvkms_params_ptr; /* IN */
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uint64_t import_mem_nvkms_params_size; /* IN */
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/* Params for creating software signaling event */
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uint64_t event_nvkms_params_ptr; /* IN */
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uint64_t event_nvkms_params_size; /* IN */
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};
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struct drm_nvidia_gem_prime_fence_attach_params {
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uint32_t handle; /* IN GEM handle to attach fence to */
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uint32_t fence_context_handle; /* IN GEM handle to fence context on which fence is run on */
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uint32_t sem_thresh; /* IN Semaphore value to reach before signal */
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uint32_t __pad;
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};
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struct drm_nvidia_get_client_capability_params {
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uint64_t capability; /* IN Client capability enum */
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uint64_t value; /* OUT Client capability value */
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};
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/* Struct that stores Crc value and if it is supported by hardware */
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struct drm_nvidia_crtc_crc32 {
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uint32_t value; /* Read value, undefined if supported is false */
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uint8_t supported; /* Supported boolean, true if readable by hardware */
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uint8_t __pad0;
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uint16_t __pad1;
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};
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struct drm_nvidia_crtc_crc32_v2_out {
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struct drm_nvidia_crtc_crc32 compositorCrc32; /* OUT compositor hardware CRC32 value */
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struct drm_nvidia_crtc_crc32 rasterGeneratorCrc32; /* OUT raster generator CRC32 value */
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struct drm_nvidia_crtc_crc32 outputCrc32; /* OUT SF/SOR CRC32 value */
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};
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struct drm_nvidia_get_crtc_crc32_v2_params {
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uint32_t crtc_id; /* IN CRTC identifier */
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struct drm_nvidia_crtc_crc32_v2_out crc32; /* OUT Crc32 output structure */
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};
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struct drm_nvidia_get_crtc_crc32_params {
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uint32_t crtc_id; /* IN CRTC identifier */
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uint32_t crc32; /* OUT CRC32 value */
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};
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struct drm_nvidia_gem_export_nvkms_memory_params {
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uint32_t handle; /* IN */
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uint32_t __pad;
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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};
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struct drm_nvidia_gem_map_offset_params {
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uint32_t handle; /* IN Handle to gem object */
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uint32_t __pad;
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uint64_t offset; /* OUT Fake offset */
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};
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#define NV_GEM_ALLOC_NO_SCANOUT (1 << 0)
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struct drm_nvidia_gem_alloc_nvkms_memory_params {
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uint32_t handle; /* OUT */
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uint8_t block_linear; /* IN */
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uint8_t compressible; /* IN/OUT */
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uint16_t __pad0;
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uint64_t memory_size; /* IN */
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uint32_t flags; /* IN */
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uint32_t __pad1;
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};
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struct drm_nvidia_gem_export_dmabuf_memory_params {
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uint32_t handle; /* IN GEM Handle*/
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uint32_t __pad;
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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};
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typedef enum {
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NV_GEM_OBJECT_NVKMS,
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NV_GEM_OBJECT_DMABUF,
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NV_GEM_OBJECT_USERMEMORY,
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NV_GEM_OBJECT_UNKNOWN = 0x7fffffff /* Force size of 32-bits. */
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} drm_nvidia_gem_object_type;
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struct drm_nvidia_gem_identify_object_params {
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uint32_t handle; /* IN GEM handle*/
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drm_nvidia_gem_object_type object_type; /* OUT GEM object type */
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};
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struct drm_nvidia_get_dpy_id_for_connector_id_params {
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uint32_t connectorId; /* IN */
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uint32_t dpyId; /* OUT */
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};
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struct drm_nvidia_get_connector_id_for_dpy_id_params {
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uint32_t dpyId; /* IN */
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uint32_t connectorId; /* OUT */
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};
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enum drm_nvidia_permissions_type {
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NV_DRM_PERMISSIONS_TYPE_MODESET = 2,
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NV_DRM_PERMISSIONS_TYPE_SUB_OWNER = 3
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};
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struct drm_nvidia_grant_permissions_params {
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int32_t fd; /* IN */
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uint32_t dpyId; /* IN */
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uint32_t type; /* IN */
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};
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struct drm_nvidia_revoke_permissions_params {
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uint32_t dpyId; /* IN */
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uint32_t type; /* IN */
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};
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struct drm_nvidia_semsurf_fence_ctx_create_params {
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uint64_t index; /* IN Index of the desired semaphore in the
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* fence context's semaphore surface */
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/* Params for importing userspace semaphore surface */
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uint64_t nvkms_params_ptr; /* IN */
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uint64_t nvkms_params_size; /* IN */
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uint32_t handle; /* OUT GEM handle to fence context */
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uint32_t __pad;
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};
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struct drm_nvidia_semsurf_fence_create_params {
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uint32_t fence_context_handle; /* IN GEM handle to fence context on which
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* fence is run on */
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uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence
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* after which the fence will be signaled
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* with its error status set to -ETIMEDOUT.
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* Default timeout value is 5000ms */
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uint64_t wait_value; /* IN Semaphore value to reach before signal */
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int32_t fd; /* OUT sync FD object representing the
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* semaphore at the specified index reaching
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* a value >= wait_value */
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uint32_t __pad;
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};
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/*
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* Note there is no provision for timeouts in this ioctl. The kernel
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* documentation asserts timeouts should be handled by fence producers, and
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* that waiters should not second-guess their logic, as it is producers rather
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* than consumers that have better information when it comes to determining a
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* reasonable timeout for a given workload.
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*/
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struct drm_nvidia_semsurf_fence_wait_params {
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uint32_t fence_context_handle; /* IN GEM handle to fence context which will
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* be used to wait on the sync FD. Need not
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* be the fence context used to create the
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* sync FD. */
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int32_t fd; /* IN sync FD object to wait on */
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uint64_t pre_wait_value; /* IN Wait for the semaphore represented by
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* fence_context to reach this value before
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* waiting for the sync file. */
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uint64_t post_wait_value; /* IN Signal the semaphore represented by
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* fence_context to this value after waiting
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* for the sync file */
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};
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struct drm_nvidia_semsurf_fence_attach_params {
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uint32_t handle; /* IN GEM handle of buffer */
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uint32_t fence_context_handle; /* IN GEM handle of fence context */
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uint32_t timeout_value_ms; /* IN Timeout value in ms for the fence
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* after which the fence will be signaled
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* with its error status set to -ETIMEDOUT.
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* Default timeout value is 5000ms */
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uint32_t shared; /* IN If true, fence will reserve shared
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* access to the buffer, otherwise it will
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* reserve exclusive access */
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uint64_t wait_value; /* IN Semaphore value to reach before signal */
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};
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struct drm_nvidia_get_drm_file_unique_id_params {
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uint64_t id; /* OUT Unique ID of the DRM file */
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};
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#endif /* _UAPI_NVIDIA_DRM_IOCTL_H_ */
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