687 lines
22 KiB
C
687 lines
22 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#if !defined(NVKMS_API_TYPES_H)
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#define NVKMS_API_TYPES_H
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#include <nvtypes.h>
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#include <nvmisc.h>
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#include <nvlimits.h>
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#define NVKMS_MAX_SUBDEVICES NV_MAX_SUBDEVICES
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#define NVKMS_MAX_HEADS_PER_DISP NV_MAX_HEADS
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#define NVKMS_LEFT 0
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#define NVKMS_RIGHT 1
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#define NVKMS_MAX_EYES 2
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#define NVKMS_MAIN_LAYER 0
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#define NVKMS_OVERLAY_LAYER 1
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#define NVKMS_MAX_LAYERS_PER_HEAD 8
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#define NVKMS_MAX_PLANES_PER_SURFACE 3
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#define NVKMS_DP_ADDRESS_STRING_LENGTH 64
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#define NVKMS_DEVICE_ID_TEGRA 0x0000ffff
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#define NVKMS_MAX_SUPERFRAME_VIEWS 4
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#define NVKMS_LOG2_LUT_ARRAY_SIZE 10
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#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE)
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typedef NvU32 NvKmsDeviceHandle;
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typedef NvU32 NvKmsDispHandle;
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typedef NvU32 NvKmsConnectorHandle;
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typedef NvU32 NvKmsSurfaceHandle;
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typedef NvU32 NvKmsFrameLockHandle;
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typedef NvU32 NvKmsDeferredRequestFifoHandle;
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typedef NvU32 NvKmsSwapGroupHandle;
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typedef NvU32 NvKmsVblankSyncObjectHandle;
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typedef NvU32 NvKmsVblankSemControlHandle;
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struct NvKmsSize {
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NvU16 width;
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NvU16 height;
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};
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struct NvKmsPoint {
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NvU16 x;
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NvU16 y;
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};
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struct NvKmsSignedPoint {
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NvS16 x;
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NvS16 y;
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};
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struct NvKmsRect {
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NvU16 x;
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NvU16 y;
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NvU16 width;
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NvU16 height;
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};
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/*
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* A 3x3 row-major matrix.
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*
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* The elements are 32-bit single-precision IEEE floating point values. The
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* floating point bit pattern should be stored in NvU32s to be passed into the
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* kernel.
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*/
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struct NvKmsMatrix {
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NvU32 m[3][3];
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};
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typedef enum {
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NVKMS_CONNECTOR_TYPE_DP = 0,
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NVKMS_CONNECTOR_TYPE_VGA = 1,
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NVKMS_CONNECTOR_TYPE_DVI_I = 2,
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NVKMS_CONNECTOR_TYPE_DVI_D = 3,
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NVKMS_CONNECTOR_TYPE_ADC = 4,
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NVKMS_CONNECTOR_TYPE_LVDS = 5,
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NVKMS_CONNECTOR_TYPE_HDMI = 6,
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NVKMS_CONNECTOR_TYPE_USBC = 7,
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NVKMS_CONNECTOR_TYPE_DSI = 8,
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NVKMS_CONNECTOR_TYPE_DP_SERIALIZER = 9,
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NVKMS_CONNECTOR_TYPE_UNKNOWN = 10,
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NVKMS_CONNECTOR_TYPE_MAX = NVKMS_CONNECTOR_TYPE_UNKNOWN,
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} NvKmsConnectorType;
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static inline
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const char *NvKmsConnectorTypeString(const NvKmsConnectorType connectorType)
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{
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switch (connectorType) {
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case NVKMS_CONNECTOR_TYPE_DP: return "DP";
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case NVKMS_CONNECTOR_TYPE_VGA: return "VGA";
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case NVKMS_CONNECTOR_TYPE_DVI_I: return "DVI-I";
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case NVKMS_CONNECTOR_TYPE_DVI_D: return "DVI-D";
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case NVKMS_CONNECTOR_TYPE_ADC: return "ADC";
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case NVKMS_CONNECTOR_TYPE_LVDS: return "LVDS";
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case NVKMS_CONNECTOR_TYPE_HDMI: return "HDMI";
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case NVKMS_CONNECTOR_TYPE_USBC: return "USB-C";
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case NVKMS_CONNECTOR_TYPE_DSI: return "DSI";
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case NVKMS_CONNECTOR_TYPE_DP_SERIALIZER: return "DP-SERIALIZER";
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default: break;
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}
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return "Unknown";
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}
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typedef enum {
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NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA = 0,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS = 1,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS = 2,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_DP = 3,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI = 4,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN = 5,
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NVKMS_CONNECTOR_SIGNAL_FORMAT_MAX =
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NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN,
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} NvKmsConnectorSignalFormat;
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/*!
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* Description of Notifiers and Semaphores (Non-isochronous (NISO) surfaces).
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*
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* When flipping, the client can optionally specify a notifier and/or
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* a semaphore to use with the flip. The surfaces used for these
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* should be registered with NVKMS to get an NvKmsSurfaceHandle.
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*
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* NvKmsNIsoSurface::offsetInWords indicates the starting location, in
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* 32-bit words, within the surface where EVO should write the
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* notifier or semaphore. Note that only the first 4096 bytes of a
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* surface can be used by semaphores or notifiers; offsetInWords must
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* allow for the semaphore or notifier to be written within the first
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* 4096 bytes of the surface. I.e., this must be satisfied:
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*
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* ((offsetInWords * 4) + elementSizeInBytes) <= 4096
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*
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* Where elementSizeInBytes is:
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*
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* if NISO_FORMAT_FOUR_WORD*, elementSizeInBytes = 16
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* if NISO_FORMAT_LEGACY,
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* if overlay && notifier, elementSizeInBytes = 16
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* else, elementSizeInBytes = 4
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*
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* Note that different GPUs support different semaphore and notifier formats.
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* Check NvKmsAllocDeviceReply::validNIsoFormatMask to determine which are
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* valid for the given device.
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*
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* Note also that FOUR_WORD and FOUR_WORD_NVDISPLAY are the same size, but
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* FOUR_WORD uses a format compatible with display class 907[ce], and
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* FOUR_WORD_NVDISPLAY uses a format compatible with c37e (actually defined by
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* the NV_DISP_NOTIFIER definition in clc37d.h).
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*/
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enum NvKmsNIsoFormat {
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NVKMS_NISO_FORMAT_LEGACY,
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NVKMS_NISO_FORMAT_FOUR_WORD,
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NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY,
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};
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enum NvKmsEventType {
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NVKMS_EVENT_TYPE_DPY_CHANGED,
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NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED,
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NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED,
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NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
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NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED,
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NVKMS_EVENT_TYPE_FLIP_OCCURRED,
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};
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enum NvKmsFlipResult {
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NV_KMS_FLIP_RESULT_SUCCESS = 0, /* Success */
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NV_KMS_FLIP_RESULT_INVALID_PARAMS, /* Parameter validation failed */
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NV_KMS_FLIP_RESULT_IN_PROGRESS, /* Flip would fail because an outstanding
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flip containing changes that cannot be
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queued is in progress */
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};
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typedef enum {
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NV_EVO_SCALER_1TAP = 0,
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NV_EVO_SCALER_2TAPS = 1,
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NV_EVO_SCALER_3TAPS = 2,
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NV_EVO_SCALER_5TAPS = 3,
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NV_EVO_SCALER_8TAPS = 4,
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NV_EVO_SCALER_TAPS_MIN = NV_EVO_SCALER_1TAP,
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NV_EVO_SCALER_TAPS_MAX = NV_EVO_SCALER_8TAPS,
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} NVEvoScalerTaps;
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/* This structure describes the scaling bounds for a given layer. */
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struct NvKmsScalingUsageBounds {
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/*
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* Maximum vertical downscale factor (scaled by 1024)
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*
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* For example, if the downscale factor is 1.5, then maxVDownscaleFactor
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* would be 1.5 x 1024 = 1536.
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*/
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NvU16 maxVDownscaleFactor;
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/*
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* Maximum horizontal downscale factor (scaled by 1024)
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*
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* See the example above for maxVDownscaleFactor.
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*/
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NvU16 maxHDownscaleFactor;
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/* Maximum vertical taps allowed */
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NVEvoScalerTaps vTaps;
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/* Whether vertical upscaling is allowed */
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NvBool vUpscalingAllowed;
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};
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struct NvKmsUsageBounds {
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struct {
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NvBool usable;
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struct NvKmsScalingUsageBounds scaling;
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NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
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} layer[NVKMS_MAX_LAYERS_PER_HEAD];
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};
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/*!
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* Per-component arrays of NvU16s describing the LUT; used for both the input
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* LUT and output LUT.
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*/
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struct NvKmsLutRamps {
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NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */
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NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */
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NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */
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};
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/*
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* A 3x4 row-major colorspace conversion matrix.
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*
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* The output color C' is the CSC matrix M times the column vector
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* [ R, G, B, 1 ].
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*
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* Each entry in the matrix is a signed 2's-complement fixed-point number with
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* 3 integer bits and 16 fractional bits.
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*/
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struct NvKmsCscMatrix {
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NvS32 m[3][4];
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};
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#define NVKMS_IDENTITY_CSC_MATRIX \
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(struct NvKmsCscMatrix){{ \
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{ 0x10000, 0, 0, 0 }, \
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{ 0, 0x10000, 0, 0 }, \
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{ 0, 0, 0x10000, 0 } \
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}}
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/*!
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* A color key match bit used in the blend equations and one can select the src
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* or dst Color Key when blending. Assert key bit means match, de-assert key
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* bit means nomatch.
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*
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* The src Color Key means using the key bit from the current layer, the dst
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* Color Key means using key bit from the previous layer composition stage. The
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* src or dst key bit will be inherited by blended pixel for the preparation of
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* next blending, as dst Color Key.
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*
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* src: Forward the color key match bit from the current layer pixel to next layer
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* composition stage.
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*
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* dst: Forward the color key match bit from the previous composition stage
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* pixel to next layer composition stage.
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*
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* disable: Forward “1” to the next layer composition stage as the color key.
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*/
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enum NvKmsCompositionColorKeySelect {
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NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE = 0,
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NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC,
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NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST,
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};
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#define NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS 3
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/*!
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* Composition modes used for surfaces in general.
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* The various types of composition are:
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*
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* Opaque: source pixels are opaque regardless of alpha,
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* and will occlude the destination pixel.
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*
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* Alpha blending: aka opacity, which could be specified
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* for a surface in its entirety, or on a per-pixel basis.
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*
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* Non-premultiplied: alpha value applies to source pixel,
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* and also counter-weighs the destination pixel.
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* Premultiplied: alpha already applied to source pixel,
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* so it only counter-weighs the destination pixel.
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*
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* Color keying: use a color key structure to decide
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* the criteria for matching and compositing.
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* (See NVColorKey below.)
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*/
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enum NvKmsCompositionBlendingMode {
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/*!
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* Modes that use no other parameters.
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*/
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NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE,
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/*!
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* Mode that ignores both per-pixel alpha provided
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* by client and the surfaceAlpha, makes source pixel
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* totally transparent.
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*/
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NVKMS_COMPOSITION_BLENDING_MODE_TRANSPARENT,
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/*!
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* Modes that use per-pixel alpha provided by client,
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* and the surfaceAlpha must be set to 0.
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*/
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NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA,
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NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA,
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/*!
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* These use both the surface-wide and per-pixel alpha values.
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* surfaceAlpha is treated as numerator ranging from 0 to 255
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* of a fraction whose denominator is 255.
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*/
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NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA,
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NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA,
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};
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static inline NvBool
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NvKmsIsCompositionModeUseAlpha(enum NvKmsCompositionBlendingMode mode)
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{
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return mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA ||
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mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA ||
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mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA ||
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mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA;
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}
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/*!
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* Abstract description of a color key.
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*
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* a, r, g, and b are component values in the same width as the framebuffer
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* values being scanned out.
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*
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* match[ARGB] defines whether that component is considered when matching the
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* color key -- TRUE means that the value of the corresponding component must
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* match the given value for the given pixel to be considered a 'key match';
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* FALSE means that the value of that component is not a key match criterion.
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*/
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typedef struct {
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NvU16 a, r, g, b;
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NvBool matchA, matchR, matchG, matchB;
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} NVColorKey;
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/*!
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* Describes the composition parameters for the single layer.
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*/
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struct NvKmsCompositionParams {
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enum NvKmsCompositionColorKeySelect colorKeySelect;
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NVColorKey colorKey;
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/*
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* It is possible to assign different blending mode for match pixels and
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* nomatch pixels. blendingMode[0] is used to blend a pixel with the color key
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* match bit "0", and blendingMode[1] is used to blend a pixel with the color
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* key match bit "1".
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*
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* But because of the hardware restrictions match and nomatch pixels can
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* not use blending mode PREMULT_ALPHA, NON_PREMULT_ALPHA,
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* PREMULT_SURFACE_ALPHA, and NON_PREMULT_SURFACE_ALPHA at once.
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*/
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enum NvKmsCompositionBlendingMode blendingMode[2];
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NvU8 surfaceAlpha; /* Applies to all pixels of entire surface */
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/*
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* Defines the composition order. A smaller value moves the layer closer to
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* the top (away from the background). No need to pick consecutive values,
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* requirements are that the value should be different for each of the
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* layers owned by the head and the value for the main layer should be
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* the greatest one.
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*
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* Cursor always remains at the top of all other layers, this parameter
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* has no effect on cursor. NVKMS assigns default depth to each of the
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* supported layers, by default depth of the layer is calculated as
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* (NVKMS_MAX_LAYERS_PER_HEAD - index of the layer). If depth is set to
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* '0' then default depth value will get used.
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*/
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NvU8 depth;
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};
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/*!
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* Describes the composition capabilities supported by the hardware for
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* cursor or layer. It describes supported the color key selects and for each
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* of the supported color key selects it describes supported blending modes
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* for match and nomatch pixles.
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*/
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struct NvKmsCompositionCapabilities {
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struct {
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/*
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* A bitmask of the supported blending modes for match and nomatch
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* pixels. It should be the bitwise 'or' of one or more
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* NVBIT(NVKMS_COMPOSITION_BLENDING_MODE_*) values.
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*/
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NvU32 supportedBlendModes[2];
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} colorKeySelect[NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS];
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/*
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* A bitmask of the supported color key selects.
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*
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* It should be the bitwise 'or' of one or more
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* NVBIT(NVKMS_COMPOSITION_COLOR_KEY_SELECT_*)
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* values.
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*/
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NvU32 supportedColorKeySelects;
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};
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struct NvKmsLayerCapabilities {
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/*!
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* Whether Layer supports the window mode. If window mode is supported,
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* then clients can set the layer's dimensions so that they're smaller than
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* the viewport, and can also change the output position of the layer to a
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* non-(0, 0) position.
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*
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* NOTE: Dimension changes are currently unsupported for the main layer,
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* and output position changes for the main layer are currently only
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* supported via IOCTL_SET_LAYER_POSITION but not via flips. Support for
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* these is coming soon, via changes to flip code.
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*/
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NvBool supportsWindowMode :1;
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/*!
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* Whether layer supports ICtCp pipe.
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*/
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NvBool supportsICtCp :1;
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/*!
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* Describes the supported Color Key selects and blending modes for
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* match and nomatch layer pixels.
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*/
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struct NvKmsCompositionCapabilities composition;
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/*!
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* Which NvKmsSurfaceMemoryFormat enum values are supported by the NVKMS
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* device on the given scanout surface layer.
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*
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* Iff a particular enum NvKmsSurfaceMemoryFormat 'value' is supported,
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* then (1 << value) will be set in the appropriate bitmask.
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*
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* Note that these bitmasks just report the static SW/HW capabilities,
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* and are a superset of the formats that IMP may allow. Clients are
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* still expected to honor the NvKmsUsageBounds for each head.
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*/
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NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
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};
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/*!
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* Surface layouts.
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*
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* BlockLinear is the NVIDIA GPU native tiling format, arranging pixels into
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* blocks or tiles for better locality during common GPU operations.
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*
|
|
* Pitch is the naive "linear" surface layout with pixels laid out sequentially
|
|
* in memory line-by-line, optionally with some padding at the end of each line
|
|
* for alignment purposes.
|
|
*/
|
|
enum NvKmsSurfaceMemoryLayout {
|
|
NvKmsSurfaceMemoryLayoutBlockLinear = 0,
|
|
NvKmsSurfaceMemoryLayoutPitch = 1,
|
|
};
|
|
|
|
static inline const char *NvKmsSurfaceMemoryLayoutToString(
|
|
enum NvKmsSurfaceMemoryLayout layout)
|
|
{
|
|
switch (layout) {
|
|
default:
|
|
return "Unknown";
|
|
case NvKmsSurfaceMemoryLayoutBlockLinear:
|
|
return "BlockLinear";
|
|
case NvKmsSurfaceMemoryLayoutPitch:
|
|
return "Pitch";
|
|
}
|
|
}
|
|
|
|
typedef enum {
|
|
MUX_STATE_GET = 0,
|
|
MUX_STATE_INTEGRATED = 1,
|
|
MUX_STATE_DISCRETE = 2,
|
|
MUX_STATE_UNKNOWN = 3,
|
|
} NvMuxState;
|
|
|
|
enum NvKmsRotation {
|
|
NVKMS_ROTATION_0 = 0,
|
|
NVKMS_ROTATION_90 = 1,
|
|
NVKMS_ROTATION_180 = 2,
|
|
NVKMS_ROTATION_270 = 3,
|
|
NVKMS_ROTATION_MIN = NVKMS_ROTATION_0,
|
|
NVKMS_ROTATION_MAX = NVKMS_ROTATION_270,
|
|
};
|
|
|
|
struct NvKmsRRParams {
|
|
enum NvKmsRotation rotation;
|
|
NvBool reflectionX;
|
|
NvBool reflectionY;
|
|
};
|
|
|
|
/*!
|
|
* Convert each possible NvKmsRRParams to a unique integer [0..15],
|
|
* so that we can describe possible NvKmsRRParams with an NvU16 bitmask.
|
|
*
|
|
* E.g.
|
|
* rotation = 0, reflectionX = F, reflectionY = F == 0|0|0 == 0
|
|
* ...
|
|
* rotation = 270, reflectionX = T, reflectionY = T == 3|4|8 == 15
|
|
*/
|
|
static inline NvU8 NvKmsRRParamsToCapBit(const struct NvKmsRRParams *rrParams)
|
|
{
|
|
NvU8 bitPosition = (NvU8)rrParams->rotation;
|
|
if (rrParams->reflectionX) {
|
|
bitPosition |= NVBIT(2);
|
|
}
|
|
if (rrParams->reflectionY) {
|
|
bitPosition |= NVBIT(3);
|
|
}
|
|
return bitPosition;
|
|
}
|
|
|
|
/*
|
|
* NVKMS_MEMORY_ISO is used to tag surface memory that will be accessed via
|
|
* display's isochronous interface. Examples of this type of memory are pixel
|
|
* data and LUT entries.
|
|
*
|
|
* NVKMS_MEMORY_NISO is used to tag surface memory that will be accessed via
|
|
* display's non-isochronous interface. Examples of this type of memory are
|
|
* semaphores and notifiers.
|
|
*/
|
|
typedef enum {
|
|
NVKMS_MEMORY_ISO = 0,
|
|
NVKMS_MEMORY_NISO = 1,
|
|
} NvKmsMemoryIsoType;
|
|
|
|
typedef struct {
|
|
NvBool coherent;
|
|
NvBool noncoherent;
|
|
} NvKmsDispIOCoherencyModes;
|
|
|
|
enum NvKmsInputColorRange {
|
|
/*
|
|
* If DEFAULT is provided, driver will assume full range for RGB formats
|
|
* and limited range for YUV formats.
|
|
*/
|
|
NVKMS_INPUT_COLORRANGE_DEFAULT = 0,
|
|
|
|
NVKMS_INPUT_COLORRANGE_LIMITED = 1,
|
|
|
|
NVKMS_INPUT_COLORRANGE_FULL = 2,
|
|
};
|
|
|
|
enum NvKmsInputColorSpace {
|
|
/* Unknown colorspace; no de-gamma will be applied */
|
|
NVKMS_INPUT_COLORSPACE_NONE = 0,
|
|
|
|
/* Linear, Rec.709 [-0.5, 7.5) */
|
|
NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1,
|
|
|
|
/* PQ, Rec.2020 unity */
|
|
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
|
|
};
|
|
|
|
enum NvKmsOutputColorimetry {
|
|
NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0,
|
|
|
|
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1,
|
|
};
|
|
|
|
enum NvKmsOutputTf {
|
|
/*
|
|
* NVKMS itself won't apply any OETF (clients are still
|
|
* free to provide a custom OLUT)
|
|
*/
|
|
NVKMS_OUTPUT_TF_NONE = 0,
|
|
NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR = 1,
|
|
NVKMS_OUTPUT_TF_PQ = 2,
|
|
};
|
|
|
|
/*!
|
|
* EOTF Data Byte 1 as per CTA-861-G spec.
|
|
* This is expected to match exactly with the spec.
|
|
*/
|
|
enum NvKmsInfoFrameEOTF {
|
|
NVKMS_INFOFRAME_EOTF_SDR_GAMMA = 0,
|
|
NVKMS_INFOFRAME_EOTF_HDR_GAMMA = 1,
|
|
NVKMS_INFOFRAME_EOTF_ST2084 = 2,
|
|
NVKMS_INFOFRAME_EOTF_HLG = 3,
|
|
};
|
|
|
|
/*!
|
|
* HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec.
|
|
* This is expected to match exactly with the spec.
|
|
*/
|
|
struct NvKmsHDRStaticMetadata {
|
|
/*!
|
|
* Color primaries of the data.
|
|
* These are coded as unsigned 16-bit values in units of 0.00002,
|
|
* where 0x0000 represents zero and 0xC350 represents 1.0000.
|
|
*/
|
|
struct {
|
|
NvU16 x, y;
|
|
} displayPrimaries[3];
|
|
|
|
/*!
|
|
* White point of colorspace data.
|
|
* These are coded as unsigned 16-bit values in units of 0.00002,
|
|
* where 0x0000 represents zero and 0xC350 represents 1.0000.
|
|
*/
|
|
struct {
|
|
NvU16 x, y;
|
|
} whitePoint;
|
|
|
|
/**
|
|
* Maximum mastering display luminance.
|
|
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
|
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
|
*/
|
|
NvU16 maxDisplayMasteringLuminance;
|
|
|
|
/*!
|
|
* Minimum mastering display luminance.
|
|
* This value is coded as an unsigned 16-bit value in units of
|
|
* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
|
|
* represents 6.5535 cd/m2.
|
|
*/
|
|
NvU16 minDisplayMasteringLuminance;
|
|
|
|
/*!
|
|
* Maximum content light level.
|
|
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
|
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
|
*/
|
|
NvU16 maxCLL;
|
|
|
|
/*!
|
|
* Maximum frame-average light level.
|
|
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
|
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
|
*/
|
|
NvU16 maxFALL;
|
|
};
|
|
|
|
/*!
|
|
* A superframe is made of two or more video streams that are combined in
|
|
* a specific way. A DP serializer (an external device connected to a Tegra
|
|
* ARM SOC over DP or HDMI) can receive a video stream comprising multiple
|
|
* videos combined into a single frame and then split it into multiple
|
|
* video streams. The following structure describes the number of views
|
|
* and dimensions of each view inside a superframe.
|
|
*/
|
|
struct NvKmsSuperframeInfo {
|
|
NvU8 numViews;
|
|
struct {
|
|
/* x offset inside superframe at which this view starts */
|
|
NvU16 x;
|
|
|
|
/* y offset inside superframe at which this view starts */
|
|
NvU16 y;
|
|
|
|
/* Horizontal active width in pixels for this view */
|
|
NvU16 width;
|
|
|
|
/* Vertical active height in lines for this view */
|
|
NvU16 height;
|
|
} view[NVKMS_MAX_SUPERFRAME_VIEWS];
|
|
};
|
|
|
|
#endif /* NVKMS_API_TYPES_H */
|