138 lines
5.4 KiB
C
138 lines
5.4 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NV_PGPROT_H__
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#define __NV_PGPROT_H__
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#include "cpuopsys.h"
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#include <linux/mm.h>
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#if !defined(NV_VMWARE)
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#if defined(NVCPU_X86_64)
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/* mark memory UC-, rather than UC (don't use _PAGE_PWT) */
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static inline pgprot_t pgprot_noncached_weak(pgprot_t old_prot)
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{
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pgprot_t new_prot = old_prot;
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if (boot_cpu_data.x86 > 3)
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new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_PCD);
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return new_prot;
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}
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#if !defined (pgprot_noncached)
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static inline pgprot_t pgprot_noncached(pgprot_t old_prot)
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{
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pgprot_t new_prot = old_prot;
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if (boot_cpu_data.x86 > 3)
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new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_PCD | _PAGE_PWT);
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return new_prot;
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}
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#endif
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static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot)
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{
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pgprot_t new_prot = old_prot;
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pgprot_val(new_prot) &= ~(_PAGE_PSE | _PAGE_PCD | _PAGE_PWT);
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new_prot = __pgprot(pgprot_val(new_prot) | _PAGE_PWT);
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return new_prot;
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}
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#endif /* defined(NVCPU_X86_64) */
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#endif /* !defined(NV_VMWARE) */
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#if defined(NVCPU_AARCH64)
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extern NvBool nvos_is_chipset_io_coherent(void);
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/*
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* Don't rely on the kernel's definition of pgprot_noncached(), as on 64-bit
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* ARM that's not for system memory, but device memory instead. For I/O cache
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* coherent systems, use cached mappings instead of uncached.
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*/
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#define NV_PGPROT_UNCACHED(old_prot) \
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((nvos_is_chipset_io_coherent()) ? \
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(old_prot) : \
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__pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)))
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#elif defined(NVCPU_PPC64LE)
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/* Don't attempt to mark sysmem pages as uncached on ppc64le */
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#define NV_PGPROT_UNCACHED(old_prot) old_prot
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#else
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#define NV_PGPROT_UNCACHED(old_prot) pgprot_noncached(old_prot)
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#endif
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#define NV_PGPROT_UNCACHED_DEVICE(old_prot) pgprot_noncached(old_prot)
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#if defined(NVCPU_AARCH64)
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#define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \
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PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
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__pgprot_modify(old_prot, PTE_ATTRINDX_MASK, NV_PROT_WRITE_COMBINED_DEVICE)
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#define NV_PGPROT_WRITE_COMBINED(old_prot) NV_PGPROT_UNCACHED(old_prot)
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#define NV_PGPROT_READ_ONLY(old_prot) \
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__pgprot_modify(old_prot, 0, PTE_RDONLY)
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#elif defined(NVCPU_X86_64)
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#define NV_PGPROT_UNCACHED_WEAK(old_prot) pgprot_noncached_weak(old_prot)
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#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
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pgprot_modify_writecombine(old_prot)
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#define NV_PGPROT_WRITE_COMBINED(old_prot) \
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NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
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#define NV_PGPROT_READ_ONLY(old_prot) \
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__pgprot(pgprot_val((old_prot)) & ~_PAGE_RW)
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#elif defined(NVCPU_PPC64LE)
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/*
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* Some kernels use H_PAGE instead of _PAGE
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*/
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#if defined(_PAGE_RW)
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#define NV_PAGE_RW _PAGE_RW
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#elif defined(H_PAGE_RW)
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#define NV_PAGE_RW H_PAGE_RW
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#else
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#warning "The kernel does not provide page protection defines!"
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#endif
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#if defined(_PAGE_4K_PFN)
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#define NV_PAGE_4K_PFN _PAGE_4K_PFN
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#elif defined(H_PAGE_4K_PFN)
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#define NV_PAGE_4K_PFN H_PAGE_4K_PFN
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#else
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#undef NV_PAGE_4K_PFN
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#endif
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#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
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pgprot_writecombine(old_prot)
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/* Don't attempt to mark sysmem pages as write combined on ppc64le */
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#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
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#define NV_PGPROT_READ_ONLY(old_prot) \
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__pgprot(pgprot_val((old_prot)) & ~NV_PAGE_RW)
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#elif defined(NVCPU_RISCV64)
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#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
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pgprot_writecombine(old_prot)
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/* Don't attempt to mark sysmem pages as write combined on riscv */
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#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
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#define NV_PGPROT_READ_ONLY(old_prot) \
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__pgprot(pgprot_val((old_prot)) & ~_PAGE_WRITE)
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#else
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/* Writecombine is not supported */
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#undef NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
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#undef NV_PGPROT_WRITE_COMBINED(old_prot)
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#define NV_PGPROT_READ_ONLY(old_prot)
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#endif
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#endif /* __NV_PGPROT_H__ */
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