79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/*******************************************************************************
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Copyright (c) 2021 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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#include "uvm_gpu.h"
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#include "uvm_hal.h"
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void uvm_hal_maxwell_enable_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu)
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{
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UVM_ASSERT_MSG(false,
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"enable_access_counter_notifications is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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}
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void uvm_hal_maxwell_disable_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu)
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{
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UVM_ASSERT_MSG(false,
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"disable_access_counter_notifications is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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}
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void uvm_hal_maxwell_clear_access_counter_notifications_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 get)
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{
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UVM_ASSERT_MSG(false,
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"clear_access_counter_notifications is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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}
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NvU32 uvm_hal_maxwell_access_counter_buffer_entry_size_unsupported(uvm_parent_gpu_t *parent_gpu)
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{
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UVM_ASSERT_MSG(false,
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"access_counter_buffer_entry_size is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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return 0;
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}
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bool uvm_hal_maxwell_access_counter_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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UVM_ASSERT_MSG(false,
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"access_counter_buffer_entry_is_valid is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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return false;
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}
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void uvm_hal_maxwell_access_counter_buffer_entry_clear_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index)
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{
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UVM_ASSERT_MSG(false,
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"access_counter_buffer_entry_clear_valid is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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}
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void uvm_hal_maxwell_access_counter_buffer_parse_entry_unsupported(uvm_parent_gpu_t *parent_gpu,
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NvU32 index,
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uvm_access_counter_buffer_entry_t *buffer_entry)
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{
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UVM_ASSERT_MSG(false,
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"access_counter_buffer_parse_entry is not supported on GPU: %s.\n",
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uvm_parent_gpu_name(parent_gpu));
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}
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