560.35.03
This commit is contained in:
parent
315fd96d2d
commit
ed4be64962
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@ -1,7 +1,7 @@
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# NVIDIA Linux Open GPU Kernel Module Source
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# NVIDIA Linux Open GPU Kernel Module Source
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This is the source release of the NVIDIA Linux open GPU kernel modules,
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This is the source release of the NVIDIA Linux open GPU kernel modules,
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version 560.31.02.
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version 560.35.03.
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## How to Build
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## How to Build
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@ -17,7 +17,7 @@ as root:
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Note that the kernel modules built here must be used with GSP
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Note that the kernel modules built here must be used with GSP
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firmware and user-space NVIDIA GPU driver components from a corresponding
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firmware and user-space NVIDIA GPU driver components from a corresponding
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560.31.02 driver release. This can be achieved by installing
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560.35.03 driver release. This can be achieved by installing
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the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
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the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
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option. E.g.,
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option. E.g.,
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@ -185,7 +185,7 @@ table below).
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For details on feature support and limitations, see the NVIDIA GPU driver
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For details on feature support and limitations, see the NVIDIA GPU driver
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end user README here:
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end user README here:
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https://us.download.nvidia.com/XFree86/Linux-x86_64/560.31.02/README/kernel_open.html
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https://us.download.nvidia.com/XFree86/Linux-x86_64/560.35.03/README/kernel_open.html
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For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
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For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
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Package for more details.
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Package for more details.
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@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
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EXTRA_CFLAGS += -I$(src)
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EXTRA_CFLAGS += -I$(src)
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EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
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EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
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EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
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EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.31.02\"
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.35.03\"
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ifneq ($(SYSSRCHOST1X),)
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ifneq ($(SYSSRCHOST1X),)
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EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
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EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
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@ -1425,7 +1425,7 @@ struct NvKmsKapiFunctionsTable {
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);
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);
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/*!
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/*!
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* Immediately reset the specified display semaphore to the pending state.
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* Immediately initialize the specified display semaphore to the pending state.
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*
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*
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* Must be called prior to applying a mode set that utilizes the specified
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* Must be called prior to applying a mode set that utilizes the specified
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* display semaphore for synchronization.
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* display semaphore for synchronization.
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@ -1438,7 +1438,7 @@ struct NvKmsKapiFunctionsTable {
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* for the specified device.
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* for the specified device.
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*/
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*/
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NvBool
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NvBool
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(*resetDisplaySemaphore)
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(*tryInitDisplaySemaphore)
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(
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(
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struct NvKmsKapiDevice *device,
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struct NvKmsKapiDevice *device,
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NvU32 semaphoreIndex
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NvU32 semaphoreIndex
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@ -1447,7 +1447,7 @@ struct NvKmsKapiFunctionsTable {
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/*!
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/*!
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* Immediately set the specified display semaphore to the displayable state.
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* Immediately set the specified display semaphore to the displayable state.
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*
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*
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* Must be called after \ref resetDisplaySemaphore to indicate a mode
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* Must be called after \ref tryInitDisplaySemaphore to indicate a mode
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* configuration change that utilizes the specified display semaphore for
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* configuration change that utilizes the specified display semaphore for
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* synchronization may proceed.
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* synchronization may proceed.
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*
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*
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@ -1471,7 +1471,7 @@ struct NvKmsKapiFunctionsTable {
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*
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*
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* This can be used by clients to restore a semaphore to a consistent state
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* This can be used by clients to restore a semaphore to a consistent state
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* when they have prepared it for use by previously calling
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* when they have prepared it for use by previously calling
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* \ref resetDisplaySemaphore() on it, but are then prevented from
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* \ref tryInitDisplaySemaphore() on it, but are then prevented from
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* submitting the associated hardware operations to consume it due to the
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* submitting the associated hardware operations to consume it due to the
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* subsequent failure of some software or hardware operation.
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* subsequent failure of some software or hardware operation.
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*
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*
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@ -192,6 +192,7 @@ static int __nv_drm_convert_in_fences(
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&to_nv_crtc_state(crtc_state)->req_config;
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&to_nv_crtc_state(crtc_state)->req_config;
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struct nv_drm_plane_fence_cb_data *fence_data;
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struct nv_drm_plane_fence_cb_data *fence_data;
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uint32_t semaphore_index;
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uint32_t semaphore_index;
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uint32_t idx_count;
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int ret, i;
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int ret, i;
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if (!crtc_state->active) {
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if (!crtc_state->active) {
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@ -244,9 +245,14 @@ static int __nv_drm_convert_in_fences(
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return -EINVAL;
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return -EINVAL;
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}
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}
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semaphore_index = nv_drm_next_display_semaphore(nv_dev);
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for (idx_count = 0; idx_count < nv_dev->display_semaphores.count; idx_count++) {
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semaphore_index = nv_drm_next_display_semaphore(nv_dev);
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if (nvKms->tryInitDisplaySemaphore(nv_dev->pDevice, semaphore_index)) {
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break;
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}
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}
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if (!nvKms->resetDisplaySemaphore(nv_dev->pDevice, semaphore_index)) {
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if (idx_count == nv_dev->display_semaphores.count) {
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NV_DRM_DEV_LOG_ERR(
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NV_DRM_DEV_LOG_ERR(
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nv_dev,
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nv_dev,
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"Failed to initialize semaphore for plane fence");
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"Failed to initialize semaphore for plane fence");
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@ -1,5 +1,5 @@
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/*******************************************************************************
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/*******************************************************************************
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Copyright (c) 2013-2023 NVIDIA Corporation
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Copyright (c) 2013-2024 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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of this software and associated documentation files (the "Software"), to
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UVM_ASSERT(first);
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UVM_ASSERT(first);
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UVM_ASSERT(outer);
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UVM_ASSERT(outer);
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if (uvm_platform_uses_canonical_form_address()) {
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// Maxwell GPUs (num_va_bits == 40b) do not support canonical form address
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// even when plugged into platforms using it.
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if (uvm_platform_uses_canonical_form_address() && num_va_bits > 40) {
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*first = 1ULL << (num_va_bits - 1);
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*first = 1ULL << (num_va_bits - 1);
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*outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits));
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*outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits));
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}
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}
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@ -137,6 +137,15 @@ NV_STATUS uvm_populate_pageable_vma(struct vm_area_struct *vma,
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if (status != NV_OK)
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if (status != NV_OK)
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goto out;
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goto out;
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// Kernel v6.6 introduced a bug in set_pte_range() around the handling of AF
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// bit. Instead of setting the AF bit, the bit is incorrectly being cleared
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// in set_pte_range() during first-touch fault handling. Calling
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// handle_mm_fault() again takes a different code path which correctly sets
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// the AF bit.
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status = handle_fault(vma, start, vma_num_pages, !!(gup_flags & FOLL_WRITE));
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if (status != NV_OK)
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goto out;
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if (touch)
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if (touch)
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ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL);
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ret = NV_PIN_USER_PAGES_REMOTE(mm, start, vma_num_pages, gup_flags, pages, NULL);
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else
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else
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@ -36,25 +36,25 @@
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// and then checked back in. You cannot make changes to these sections without
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// and then checked back in. You cannot make changes to these sections without
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// corresponding changes to the buildmeister script
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// corresponding changes to the buildmeister script
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#ifndef NV_BUILD_BRANCH
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#ifndef NV_BUILD_BRANCH
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#define NV_BUILD_BRANCH r560_78
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#define NV_BUILD_BRANCH r560_88
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#endif
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#endif
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#ifndef NV_PUBLIC_BRANCH
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#ifndef NV_PUBLIC_BRANCH
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#define NV_PUBLIC_BRANCH r560_78
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#define NV_PUBLIC_BRANCH r560_88
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#endif
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#endif
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r560/r560_78-120"
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r560/r560_88-137"
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#define NV_BUILD_CHANGELIST_NUM (34643855)
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#define NV_BUILD_CHANGELIST_NUM (34725486)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "rel/gpu_drv/r560/r560_78-120"
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#define NV_BUILD_NAME "rel/gpu_drv/r560/r560_88-137"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643855)
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34725486)
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#else /* Windows builds */
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#else /* Windows builds */
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#define NV_BUILD_BRANCH_VERSION "r560_78-2"
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#define NV_BUILD_BRANCH_VERSION "r560_88-4"
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#define NV_BUILD_CHANGELIST_NUM (34643068)
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#define NV_BUILD_CHANGELIST_NUM (34711266)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "560.81"
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#define NV_BUILD_NAME "560.94"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643068)
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34711266)
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#define NV_BUILD_BRANCH_BASE_VERSION R560
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#define NV_BUILD_BRANCH_BASE_VERSION R560
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#endif
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#endif
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// End buildmeister python edited section
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// End buildmeister python edited section
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@ -4,7 +4,7 @@
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
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(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
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(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
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#define NV_VERSION_STRING "560.31.02"
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#define NV_VERSION_STRING "560.35.03"
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#else
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#else
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@ -84,9 +84,11 @@ typedef NvUFXP32 NvUFXP25_7;
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typedef NvUFXP32 NvUFXP26_6;
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typedef NvUFXP32 NvUFXP26_6;
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typedef NvUFXP32 NvUFXP28_4;
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typedef NvUFXP32 NvUFXP28_4;
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typedef NvUFXP64 NvUFXP37_27;
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typedef NvUFXP64 NvUFXP40_24;
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typedef NvUFXP64 NvUFXP40_24;
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typedef NvUFXP64 NvUFXP48_16;
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typedef NvUFXP64 NvUFXP48_16;
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typedef NvUFXP64 NvUFXP52_12;
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typedef NvUFXP64 NvUFXP52_12;
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typedef NvUFXP64 NvUFXP54_10;
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typedef NvUFXP64 NvUFXP60_4;
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typedef NvUFXP64 NvUFXP60_4;
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/*!
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/*!
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@ -84,8 +84,8 @@ NvBool nvKmsKapiIsNotifierFinish(const struct NvKmsKapiDevice *device,
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void nvKmsKapiNotifierSetNotBegun(struct NvKmsKapiDevice *device,
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void nvKmsKapiNotifierSetNotBegun(struct NvKmsKapiDevice *device,
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NvU32 head, NvU32 layer, NvU32 index);
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NvU32 head, NvU32 layer, NvU32 index);
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|
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NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
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NvBool nvKmsKapiTryInitDisplaySemaphore(struct NvKmsKapiDevice *device,
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NvU32 index);
|
NvU32 index);
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|
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void nvKmsKapiSignalDisplaySemaphore(struct NvKmsKapiDevice *device,
|
void nvKmsKapiSignalDisplaySemaphore(struct NvKmsKapiDevice *device,
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NvU32 index);
|
NvU32 index);
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|
|
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@ -1425,7 +1425,7 @@ struct NvKmsKapiFunctionsTable {
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);
|
);
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|
|
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/*!
|
/*!
|
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* Immediately reset the specified display semaphore to the pending state.
|
* Immediately initialize the specified display semaphore to the pending state.
|
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*
|
*
|
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* Must be called prior to applying a mode set that utilizes the specified
|
* Must be called prior to applying a mode set that utilizes the specified
|
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* display semaphore for synchronization.
|
* display semaphore for synchronization.
|
||||||
|
@ -1438,7 +1438,7 @@ struct NvKmsKapiFunctionsTable {
|
||||||
* for the specified device.
|
* for the specified device.
|
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*/
|
*/
|
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NvBool
|
NvBool
|
||||||
(*resetDisplaySemaphore)
|
(*tryInitDisplaySemaphore)
|
||||||
(
|
(
|
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struct NvKmsKapiDevice *device,
|
struct NvKmsKapiDevice *device,
|
||||||
NvU32 semaphoreIndex
|
NvU32 semaphoreIndex
|
||||||
|
@ -1447,7 +1447,7 @@ struct NvKmsKapiFunctionsTable {
|
||||||
/*!
|
/*!
|
||||||
* Immediately set the specified display semaphore to the displayable state.
|
* Immediately set the specified display semaphore to the displayable state.
|
||||||
*
|
*
|
||||||
* Must be called after \ref resetDisplaySemaphore to indicate a mode
|
* Must be called after \ref tryInitDisplaySemaphore to indicate a mode
|
||||||
* configuration change that utilizes the specified display semaphore for
|
* configuration change that utilizes the specified display semaphore for
|
||||||
* synchronization may proceed.
|
* synchronization may proceed.
|
||||||
*
|
*
|
||||||
|
@ -1471,7 +1471,7 @@ struct NvKmsKapiFunctionsTable {
|
||||||
*
|
*
|
||||||
* This can be used by clients to restore a semaphore to a consistent state
|
* This can be used by clients to restore a semaphore to a consistent state
|
||||||
* when they have prepared it for use by previously calling
|
* when they have prepared it for use by previously calling
|
||||||
* \ref resetDisplaySemaphore() on it, but are then prevented from
|
* \ref tryInitDisplaySemaphore() on it, but are then prevented from
|
||||||
* submitting the associated hardware operations to consume it due to the
|
* submitting the associated hardware operations to consume it due to the
|
||||||
* subsequent failure of some software or hardware operation.
|
* subsequent failure of some software or hardware operation.
|
||||||
*
|
*
|
||||||
|
|
|
@ -286,8 +286,8 @@ NvBool nvKmsKapiAllocateSemaphores(struct NvKmsKapiDevice *device,
|
||||||
return NV_TRUE;
|
return NV_TRUE;
|
||||||
}
|
}
|
||||||
|
|
||||||
NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
|
NvBool nvKmsKapiTryInitDisplaySemaphore(struct NvKmsKapiDevice *device,
|
||||||
NvU32 index)
|
NvU32 index)
|
||||||
{
|
{
|
||||||
struct nvKmsParsedSemaphore semParsed;
|
struct nvKmsParsedSemaphore semParsed;
|
||||||
|
|
||||||
|
@ -297,12 +297,6 @@ NvBool nvKmsKapiResetDisplaySemaphore(struct NvKmsKapiDevice *device,
|
||||||
&semParsed);
|
&semParsed);
|
||||||
|
|
||||||
if (semParsed.payload != NVKMS_KAPI_SEMAPHORE_VALUE_DONE) {
|
if (semParsed.payload != NVKMS_KAPI_SEMAPHORE_VALUE_DONE) {
|
||||||
nvKmsKapiLogDeviceDebug(
|
|
||||||
device,
|
|
||||||
"Attempt to reuse semaphore at index %u with pending status 0x%08x",
|
|
||||||
index,
|
|
||||||
semParsed.payload);
|
|
||||||
|
|
||||||
return NV_FALSE;
|
return NV_FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -3607,7 +3607,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||||
nvKmsKapiSetSemaphoreSurfaceValue;
|
nvKmsKapiSetSemaphoreSurfaceValue;
|
||||||
funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback;
|
funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback;
|
||||||
|
|
||||||
funcsTable->resetDisplaySemaphore = nvKmsKapiResetDisplaySemaphore;
|
funcsTable->tryInitDisplaySemaphore = nvKmsKapiTryInitDisplaySemaphore;
|
||||||
funcsTable->signalDisplaySemaphore = nvKmsKapiSignalDisplaySemaphore;
|
funcsTable->signalDisplaySemaphore = nvKmsKapiSignalDisplaySemaphore;
|
||||||
funcsTable->cancelDisplaySemaphore = nvKmsKapiCancelDisplaySemaphore;
|
funcsTable->cancelDisplaySemaphore = nvKmsKapiCancelDisplaySemaphore;
|
||||||
funcsTable->signalVrrSemaphore = SignalVrrSemaphore;
|
funcsTable->signalVrrSemaphore = SignalVrrSemaphore;
|
||||||
|
|
|
@ -6716,7 +6716,8 @@ static NvBool GetDfpHdmiProtocol(const NVDpyEvoRec *pDpyEvo,
|
||||||
nvDpyGetOutputColorFormatInfo(pDpyEvo);
|
nvDpyGetOutputColorFormatInfo(pDpyEvo);
|
||||||
const NvBool forceHdmiFrlIsSupported = FALSE;
|
const NvBool forceHdmiFrlIsSupported = FALSE;
|
||||||
|
|
||||||
nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A ||
|
nvAssert(rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS ||
|
||||||
|
rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A ||
|
||||||
rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B);
|
rmProtocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B);
|
||||||
|
|
||||||
/* Override protocol if this mode requires HDMI FRL. */
|
/* Override protocol if this mode requires HDMI FRL. */
|
||||||
|
@ -6743,10 +6744,25 @@ static NvBool GetDfpHdmiProtocol(const NVDpyEvoRec *pDpyEvo,
|
||||||
if (nvHdmiGetEffectivePixelClockKHz(pDpyEvo, pTimings, pDpyColor) <=
|
if (nvHdmiGetEffectivePixelClockKHz(pDpyEvo, pTimings, pDpyColor) <=
|
||||||
pDpyEvo->maxSingleLinkPixelClockKHz) {
|
pDpyEvo->maxSingleLinkPixelClockKHz) {
|
||||||
|
|
||||||
*pTimingsProtocol = (rmProtocol ==
|
switch (rmProtocol) {
|
||||||
NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A) ?
|
case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DUAL_TMDS:
|
||||||
NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A :
|
/*
|
||||||
NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B;
|
* Force single link TMDS protocol. HDMI does not support
|
||||||
|
* physically support dual link TMDS.
|
||||||
|
*
|
||||||
|
* TMDS_A: "use A side of the link"
|
||||||
|
*/
|
||||||
|
*pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A;
|
||||||
|
break;
|
||||||
|
case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_A:
|
||||||
|
*pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_A;
|
||||||
|
break;
|
||||||
|
case NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_SINGLE_TMDS_B:
|
||||||
|
*pTimingsProtocol = NVKMS_PROTOCOL_SOR_SINGLE_TMDS_B;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
return TRUE;
|
return TRUE;
|
||||||
}
|
}
|
||||||
} while (nvDowngradeColorSpaceAndBpc(&colorFormatsInfo,
|
} while (nvDowngradeColorSpaceAndBpc(&colorFormatsInfo,
|
||||||
|
|
|
@ -110,7 +110,7 @@ NvBool nvHsIoctlMoveCursor(
|
||||||
{
|
{
|
||||||
NVHsChannelEvoRec *pHsChannel;
|
NVHsChannelEvoRec *pHsChannel;
|
||||||
|
|
||||||
if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) {
|
if (apiHead >= ARRAY_LEN(pDispEvo->pHsChannel)) {
|
||||||
return FALSE;
|
return FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -206,7 +206,7 @@ NvBool nvHsIoctlSetCursorImage(
|
||||||
NVHsChannelEvoRec *pHsChannel;
|
NVHsChannelEvoRec *pHsChannel;
|
||||||
NVSurfaceEvoRec *pSurfaceEvo = NULL;
|
NVSurfaceEvoRec *pSurfaceEvo = NULL;
|
||||||
|
|
||||||
if (apiHead > ARRAY_LEN(pDispEvo->pHsChannel)) {
|
if (apiHead >= ARRAY_LEN(pDispEvo->pHsChannel)) {
|
||||||
return FALSE;
|
return FALSE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||||
* SPDX-License-Identifier: MIT
|
* SPDX-License-Identifier: MIT
|
||||||
*
|
*
|
||||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
|
@ -40,4 +40,8 @@
|
||||||
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000
|
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_NONE 0x00000000
|
||||||
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001
|
#define NVGSP_PROXY_REG_CONF_COMPUTE_MULTI_GPU_MODE_PROTECTED_PCIE 0x00000001
|
||||||
|
|
||||||
|
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION 5:5
|
||||||
|
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_DISABLE 0x00000000
|
||||||
|
#define NVGSP_PROXY_REG_NVLINK_ENCRYPTION_ENABLE 0x00000001
|
||||||
|
|
||||||
#endif // NVGSP_PROXY_REG_H
|
#endif // NVGSP_PROXY_REG_H
|
||||||
|
|
|
@ -137,6 +137,7 @@ typedef struct CONF_COMPUTE_CAPS
|
||||||
NvBool bAcceptClientRequest;
|
NvBool bAcceptClientRequest;
|
||||||
NvBool bMultiGpuProtectedPcieModeEnabled;
|
NvBool bMultiGpuProtectedPcieModeEnabled;
|
||||||
NvBool bFatalFailure;
|
NvBool bFatalFailure;
|
||||||
|
NvBool bNvlEncryptionEnabled;
|
||||||
} CONF_COMPUTE_CAPS;
|
} CONF_COMPUTE_CAPS;
|
||||||
|
|
||||||
//
|
//
|
||||||
|
|
|
@ -311,6 +311,7 @@ struct KernelNvlink {
|
||||||
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
|
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
|
||||||
|
|
||||||
// Data members
|
// Data members
|
||||||
|
NvU32 gspProxyRegkeys;
|
||||||
struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3];
|
struct KernelIoctrl *PRIVATE_FIELD(pKernelIoctrl)[3];
|
||||||
NvU32 PRIVATE_FIELD(ioctrlMask);
|
NvU32 PRIVATE_FIELD(ioctrlMask);
|
||||||
NvU32 PRIVATE_FIELD(ipVerNvlink);
|
NvU32 PRIVATE_FIELD(ipVerNvlink);
|
||||||
|
@ -444,6 +445,7 @@ struct KernelNvlink_PRIVATE {
|
||||||
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
|
NvBool PDB_PROP_KNVLINK_ENCRYPTION_ENABLED;
|
||||||
|
|
||||||
// Data members
|
// Data members
|
||||||
|
NvU32 gspProxyRegkeys;
|
||||||
struct KernelIoctrl *pKernelIoctrl[3];
|
struct KernelIoctrl *pKernelIoctrl[3];
|
||||||
NvU32 ioctrlMask;
|
NvU32 ioctrlMask;
|
||||||
NvU32 ipVerNvlink;
|
NvU32 ipVerNvlink;
|
||||||
|
|
|
@ -41,6 +41,8 @@
|
||||||
#include "published/hopper/gh100/dev_riscv_pri.h"
|
#include "published/hopper/gh100/dev_riscv_pri.h"
|
||||||
#include "published/hopper/gh100/dev_vm.h"
|
#include "published/hopper/gh100/dev_vm.h"
|
||||||
|
|
||||||
|
#include "gpu/nvlink/kernel_nvlink.h"
|
||||||
|
|
||||||
#define RISCV_BR_ADDR_ALIGNMENT (8)
|
#define RISCV_BR_ADDR_ALIGNMENT (8)
|
||||||
|
|
||||||
const char*
|
const char*
|
||||||
|
@ -409,6 +411,12 @@ kgspSetupGspFmcArgs_GH100
|
||||||
pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys;
|
pGspFmcBootParams->initParams.regkeys = pCC->gspProxyRegkeys;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
|
||||||
|
if (pKernelNvlink != NULL)
|
||||||
|
{
|
||||||
|
pGspFmcBootParams->initParams.regkeys |= pKernelNvlink->gspProxyRegkeys;
|
||||||
|
}
|
||||||
|
|
||||||
pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0);
|
pGspFmcBootParams->bootGspRmParams.gspRmDescOffset = memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0);
|
||||||
pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta);
|
pGspFmcBootParams->bootGspRmParams.gspRmDescSize = sizeof(*pKernelGsp->pWprMeta);
|
||||||
pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor);
|
pGspFmcBootParams->bootGspRmParams.target = _kgspMemdescToDmaTarget(pKernelGsp->pWprMetaDescriptor);
|
||||||
|
|
|
@ -28,6 +28,9 @@
|
||||||
#include "nvrm_registry.h"
|
#include "nvrm_registry.h"
|
||||||
#include "os/os.h"
|
#include "os/os.h"
|
||||||
|
|
||||||
|
#include "gpu/conf_compute/conf_compute.h"
|
||||||
|
#include "gsp/gsp_proxy_reg.h"
|
||||||
|
|
||||||
/*!
|
/*!
|
||||||
* @brief Apply NVLink overrides from Registry
|
* @brief Apply NVLink overrides from Registry
|
||||||
*
|
*
|
||||||
|
@ -278,12 +281,34 @@ knvlinkApplyRegkeyOverrides_IMPL
|
||||||
if (NV_OK == osReadRegistryDword(pGpu,
|
if (NV_OK == osReadRegistryDword(pGpu,
|
||||||
NV_REG_STR_RM_NVLINK_ENCRYPTION, ®data))
|
NV_REG_STR_RM_NVLINK_ENCRYPTION, ®data))
|
||||||
{
|
{
|
||||||
|
//
|
||||||
|
// Nvlink Encryption PDB PROP is set when Nvlink Encryption regkey has been enabled AND
|
||||||
|
// either we are running in MODS or CC is enabled
|
||||||
|
//
|
||||||
if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_ENCRYPTION, _MODE, _ENABLE, regdata))
|
if (FLD_TEST_DRF(_REG_STR_RM, _NVLINK_ENCRYPTION, _MODE, _ENABLE, regdata))
|
||||||
{
|
{
|
||||||
pKernelNvlink->setProperty(pGpu, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
|
if (RMCFG_FEATURE_MODS_FEATURES)
|
||||||
NV_PRINTF(LEVEL_INFO,
|
{
|
||||||
"Nvlink Encryption is enabled\n");
|
pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
|
||||||
}
|
pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
|
||||||
|
NV_PRINTF(LEVEL_INFO,
|
||||||
|
"Nvlink Encryption is enabled via regkey\n");
|
||||||
|
return NV_OK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ConfidentialCompute *pCC = GPU_GET_CONF_COMPUTE(pGpu);
|
||||||
|
NvBool bCCFeatureEnabled = (pCC != NULL) && pCC->getProperty(pCC, PDB_PROP_CONFCOMPUTE_ENABLED);
|
||||||
|
if (bCCFeatureEnabled)
|
||||||
|
{
|
||||||
|
pKernelNvlink->setProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED, NV_TRUE);
|
||||||
|
pKernelNvlink->gspProxyRegkeys = DRF_DEF(GSP, _PROXY_REG, _NVLINK_ENCRYPTION, _ENABLE);
|
||||||
|
NV_PRINTF(LEVEL_INFO,
|
||||||
|
"Nvlink Encryption is enabled via regkey\n");
|
||||||
|
return NV_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return NV_OK;
|
return NV_OK;
|
||||||
|
|
|
@ -189,6 +189,36 @@ _gpumgrDetermineConfComputeCapabilities
|
||||||
return NV_OK;
|
return NV_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static NV_STATUS
|
||||||
|
_gpumgrDetermineNvlinkEncryptionCapabilities
|
||||||
|
(
|
||||||
|
OBJGPUMGR *pGpuMgr,
|
||||||
|
OBJGPU *pGpu
|
||||||
|
)
|
||||||
|
{
|
||||||
|
NvBool bNvlEncryptionEnabled = NV_FALSE;
|
||||||
|
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
|
||||||
|
bNvlEncryptionEnabled = (pKernelNvlink != NULL) &&
|
||||||
|
pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_ENCRYPTION_ENABLED);
|
||||||
|
|
||||||
|
// First GPU
|
||||||
|
if (ONEBITSET(pGpuMgr->gpuAttachMask))
|
||||||
|
{
|
||||||
|
pGpuMgr->ccCaps.bNvlEncryptionEnabled = bNvlEncryptionEnabled;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
//
|
||||||
|
// If one of the GPUs is not NVLE capable, the system as a whole
|
||||||
|
// is not NVLE capable
|
||||||
|
//
|
||||||
|
NV_ASSERT_OR_RETURN(pGpuMgr->ccCaps.bNvlEncryptionEnabled ==
|
||||||
|
bNvlEncryptionEnabled, NV_ERR_INVALID_STATE);
|
||||||
|
}
|
||||||
|
|
||||||
|
return NV_OK;
|
||||||
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
_gpumgrCacheClearMIGGpuIdInfo(NvU32 gpuId)
|
_gpumgrCacheClearMIGGpuIdInfo(NvU32 gpuId)
|
||||||
{
|
{
|
||||||
|
@ -1417,6 +1447,9 @@ gpumgrAttachGpu(NvU32 gpuInstance, GPUATTACHARG *pAttachArg)
|
||||||
// Determine conf compute params
|
// Determine conf compute params
|
||||||
NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu));
|
NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineConfComputeCapabilities(pGpuMgr, pGpu));
|
||||||
|
|
||||||
|
// Determine nvlink encryption params
|
||||||
|
NV_ASSERT_OK_OR_RETURN(_gpumgrDetermineNvlinkEncryptionCapabilities(pGpuMgr, pGpu));
|
||||||
|
|
||||||
if (!IS_GSP_CLIENT(pGpu))
|
if (!IS_GSP_CLIENT(pGpu))
|
||||||
pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance);
|
pGpuMgr->gpuMonolithicRmMask |= NVBIT(gpuInstance);
|
||||||
|
|
||||||
|
|
|
@ -178,6 +178,7 @@ void RmInitCpuInfo(void)
|
||||||
case AARCH64_VENDOR_PART(FUJITSU, A64FX):
|
case AARCH64_VENDOR_PART(FUJITSU, A64FX):
|
||||||
case AARCH64_VENDOR_PART(PHYTIUM, FT2000):
|
case AARCH64_VENDOR_PART(PHYTIUM, FT2000):
|
||||||
case AARCH64_VENDOR_PART(PHYTIUM, S2500):
|
case AARCH64_VENDOR_PART(PHYTIUM, S2500):
|
||||||
|
case AARCH64_VENDOR_PART(PHYTIUM, S5000):
|
||||||
case AARCH64_VENDOR_PART(AMPERE, ALTRA):
|
case AARCH64_VENDOR_PART(AMPERE, ALTRA):
|
||||||
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN96XX):
|
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN96XX):
|
||||||
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN98XX):
|
case AARCH64_VENDOR_PART(MARVELL, OCTEON_CN98XX):
|
||||||
|
|
|
@ -88,6 +88,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val);
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001
|
#define CP_MIDR_PRIMARY_PART_NUM_A64FX 0x001
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662
|
#define CP_MIDR_PRIMARY_PART_NUM_FT2000 0x662
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_S2500 0x663
|
#define CP_MIDR_PRIMARY_PART_NUM_S2500 0x663
|
||||||
|
#define CP_MIDR_PRIMARY_PART_NUM_S5000 0x862
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000
|
#define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
|
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2
|
||||||
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1
|
#define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1
|
||||||
|
|
|
@ -2541,6 +2541,7 @@ _controllerParseStaticTable_v22
|
||||||
|
|
||||||
switch (header.version)
|
switch (header.version)
|
||||||
{
|
{
|
||||||
|
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_24:
|
||||||
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23:
|
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_23:
|
||||||
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22:
|
case NVPCF_CONTROLLER_STATIC_TABLE_VERSION_22:
|
||||||
{
|
{
|
||||||
|
|
|
@ -1,4 +1,4 @@
|
||||||
NVIDIA_VERSION = 560.31.02
|
NVIDIA_VERSION = 560.35.03
|
||||||
|
|
||||||
# This file.
|
# This file.
|
||||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||||
|
|
Loading…
Reference in New Issue