From dac2350c7f6496ef0d7fb20fe6123a1270329bc8 Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Thu, 5 Jan 2023 10:40:27 -0800 Subject: [PATCH] 525.78.01 --- CHANGELOG.md | 2 + README.md | 21 +- kernel-open/Kbuild | 2 +- kernel-open/common/inc/nv.h | 1 - kernel-open/conftest.sh | 72 +- kernel-open/nvidia-drm/nvidia-drm-connector.c | 5 + kernel-open/nvidia-drm/nvidia-drm-drv.c | 4 - kernel-open/nvidia-drm/nvidia-drm.Kbuild | 1 + kernel-open/nvidia/i2c_nvswitch.c | 3 +- src/common/displayport/inc/dp_configcaps.h | 3 +- src/common/displayport/inc/dp_connectorimpl.h | 15 +- src/common/displayport/inc/dp_discovery.h | 2 +- src/common/displayport/inc/dp_linkconfig.h | 5 + .../displayport/inc/dp_regkeydatabase.h | 10 +- src/common/displayport/src/dp_configcaps.cpp | 38 +- .../displayport/src/dp_connectorimpl.cpp | 71 +- src/common/displayport/src/dp_deviceimpl.cpp | 36 +- src/common/displayport/src/dp_evoadapter.cpp | 4 +- src/common/displayport/src/dp_watermark.cpp | 13 +- src/common/inc/nvBldVer.h | 20 +- src/common/inc/nvPNPVendorIds.h | 2 + src/common/inc/nvUnixVersion.h | 2 +- .../published/ada/ad102/dev_gc6_island.h | 29 + .../ada/ad102/dev_gc6_island_addendum.h | 32 + src/common/modeset/timing/nvt_edidext_861.c | 10 +- .../modeset/timing/nvt_edidext_displayid20.c | 26 +- src/common/modeset/timing/nvtiming.h | 2 + src/common/nvlink/interface/nvlink.h | 16 + .../kernel/nvlink/core/nvlink_shutdown.c | 5 +- .../nvswitch/common/inc/soe/soeifcore.h | 19 +- .../nvswitch/interface/ctrl_dev_nvswitch.h | 74 +- .../kernel/flcn/flcn_call_hal_nvswitch.c | 10 +- .../nvswitch/kernel/inc/haldef_nvswitch.h | 7 +- .../kernel/inc/inforom/inforom_nvswitch.h | 11 +- .../nvswitch/kernel/inc/lr10/inforom_lr10.h | 6 + src/common/nvswitch/kernel/inc/lr10/lr10.h | 1 + .../nvswitch/kernel/inc/lr10/soe_lr10.h | 1 + .../nvswitch/kernel/inc/ls10/inforom_ls10.h | 6 + src/common/nvswitch/kernel/inc/ls10/ls10.h | 5 + .../nvswitch/kernel/inc/ls10/soe_ls10.h | 1 + .../kernel/inc/soe/bin/g_soeuc_lr10_dbg.h | 10 +- .../kernel/inc/soe/bin/g_soeuc_lr10_prd.h | 10 +- .../nvswitch/kernel/inforom/ifrro_nvswitch.c | 5 +- .../kernel/inforom/inforom_nvswitch.c | 44 +- .../nvswitch/kernel/lr10/inforom_lr10.c | 19 + src/common/nvswitch/kernel/lr10/link_lr10.c | 2 +- src/common/nvswitch/kernel/lr10/lr10.c | 84 +- src/common/nvswitch/kernel/lr10/soe_lr10.c | 11 + .../nvswitch/kernel/ls10/discovery_ls10.c | 49 +- src/common/nvswitch/kernel/ls10/flcn_ls10.c | 72 +- .../nvswitch/kernel/ls10/inforom_ls10.c | 24 +- src/common/nvswitch/kernel/ls10/intr_ls10.c | 25 +- src/common/nvswitch/kernel/ls10/link_ls10.c | 179 +- src/common/nvswitch/kernel/ls10/ls10.c | 183 +- src/common/nvswitch/kernel/ls10/soe_ls10.c | 65 + src/common/nvswitch/kernel/ls10/sugen_ls10.c | 27 +- src/common/nvswitch/kernel/nvswitch.c | 55 + src/common/sdk/nvidia/inc/class/cla084.h | 4 + .../nvidia/inc/class/cla084_notification.h | 3 +- .../nvidia/inc/ctrl/ctrl0000/ctrl0000system.h | 3 +- .../nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h | 16 + .../ctrl/ctrl2080/ctrl2080vgpumgrinternal.h | 4 + src/common/sdk/nvidia/inc/ctrl/ctrla080.h | 3 + src/common/sdk/nvidia/inc/finn_rm_api.h | 4 +- src/common/sdk/nvidia/inc/nvos.h | 2 +- .../uproc/os/common/include/liblogdecode.h | 11 +- .../uproc/os/libos-v3.1.0/lib/libdwarf.c | 7 + .../uproc/os/libos-v3.1.0/lib/liblogdecode.c | 15 +- src/nvidia-modeset/interface/nvkms-sync.h | 3 + src/nvidia-modeset/lib/nvkms-sync.c | 55 +- .../src/nvkms-headsurface-ioctl.c | 18 +- src/nvidia-modeset/src/nvkms-headsurface.c | 53 +- .../nvalloc/common/inc/dev_ctrl_defines.h | 2 + .../nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h | 9 +- .../nvalloc/common/inc/inforom/ifrstruct.h | 24 + .../arch/nvalloc/common/inc/inforom/omsdef.h | 32 + src/nvidia/arch/nvalloc/common/inc/nvcst.h | 2 + src/nvidia/arch/nvalloc/common/inc/nvdevid.h | 2 + .../arch/nvalloc/common/inc/oob/smbpbi.h | 26 +- src/nvidia/arch/nvalloc/common/inc/rmifrif.h | 1 - src/nvidia/arch/nvalloc/unix/include/nv.h | 1 - src/nvidia/arch/nvalloc/unix/src/os.c | 20 +- src/nvidia/arch/nvalloc/unix/src/osapi.c | 21 +- src/nvidia/arch/nvalloc/unix/src/unix_intr.c | 89 +- src/nvidia/exports_link_command.txt | 1 - src/nvidia/generated/g_bindata.c | 4 + ...bindata_kgspGetBinArchiveGspRmBoot_AD102.c | 7406 ++++++++--------- ...ksec2GetBinArchiveSecurescrubUcode_AD10X.c | 1281 +++ src/nvidia/generated/g_event_nvoc.h | 5 + src/nvidia/generated/g_gpu_nvoc.c | 12 +- src/nvidia/generated/g_gpu_nvoc.h | 17 +- src/nvidia/generated/g_kern_gmmu_nvoc.h | 8 +- src/nvidia/generated/g_kernel_ce_nvoc.h | 10 + src/nvidia/generated/g_kernel_channel_nvoc.c | 16 +- src/nvidia/generated/g_kernel_fifo_nvoc.h | 2 + src/nvidia/generated/g_kernel_gsp_nvoc.c | 62 +- src/nvidia/generated/g_kernel_gsp_nvoc.h | 83 +- .../g_kernel_hostvgpudeviceapi_nvoc.h | 2 +- src/nvidia/generated/g_kernel_nvlink_nvoc.c | 14 + src/nvidia/generated/g_kernel_nvlink_nvoc.h | 30 +- src/nvidia/generated/g_kernel_sec2_nvoc.c | 13 + src/nvidia/generated/g_kernel_sec2_nvoc.h | 13 + src/nvidia/generated/g_nv_name_released.h | 349 +- src/nvidia/generated/g_objgpumon_nvoc.h | 9 +- src/nvidia/generated/g_os_nvoc.h | 1 + src/nvidia/generated/g_resserv_nvoc.h | 6 + src/nvidia/generated/g_rpc-structures.h | 35 + src/nvidia/generated/g_rs_server_nvoc.h | 9 + src/nvidia/generated/g_sdk-structures.h | 2 +- src/nvidia/generated/g_subdevice_nvoc.c | 115 +- src/nvidia/generated/g_subdevice_nvoc.h | 24 +- src/nvidia/generated/rmconfig.h | 1 + src/nvidia/inc/kernel/core/prelude.h | 2 + .../gpu/mem_mgr/phys_mem_allocator/addrtree.h | 4 +- .../phys_mem_allocator/phys_mem_allocator.h | 5 +- .../gpu/mem_mgr/phys_mem_allocator/regmap.h | 4 +- src/nvidia/inc/libraries/nvport/atomic.h | 7 + .../libraries/nvport/inline/atomic_clang.h | 6 + .../inc/libraries/nvport/inline/atomic_gcc.h | 6 + .../libraries/nvport/inline/memory_tracking.h | 10 +- src/nvidia/inc/libraries/nvport/memory.h | 13 + src/nvidia/inc/libraries/resserv/resserv.h | 6 + src/nvidia/inc/libraries/resserv/rs_server.h | 9 + src/nvidia/interface/nv_sriov_defines.h | 50 +- src/nvidia/interface/nvrm_registry.h | 11 + src/nvidia/interface/rmapi/src/finn_rm_api.c | 108 +- src/nvidia/kernel/inc/objrpc.h | 1 + src/nvidia/kernel/inc/vgpu/rpc_global_enums.h | 1 + src/nvidia/kernel/vgpu/nv/rpc.c | 16 +- .../gpu/bif/arch/turing/kernel_bif_tu102.c | 97 +- .../gpu/bus/arch/maxwell/kern_bus_gm107.c | 10 +- .../gpu/bus/arch/pascal/kern_bus_gp100.c | 45 +- src/nvidia/src/kernel/gpu/bus/p2p.c | 5 +- src/nvidia/src/kernel/gpu/ce/kernel_ce.c | 52 +- .../src/kernel/gpu/ce/kernel_ce_shared.c | 59 + .../src/kernel/gpu/fifo/kernel_channel.c | 12 +- .../gpu/fifo/kernel_channel_group_api.c | 2 +- src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c | 57 +- .../kernel/gpu/fifo/kernel_idle_channels.c | 5 + src/nvidia/src/kernel/gpu/gpu.c | 47 +- src/nvidia/src/kernel/gpu/gpu_fabric_probe.c | 92 +- .../src/kernel/gpu/gr/kernel_graphics.c | 5 +- .../gpu/gsp/arch/ada/kernel_gsp_ad102.c | 111 + .../gpu/gsp/arch/ampere/kernel_gsp_ga102.c | 8 + .../gpu/gsp/arch/turing/kernel_gsp_tu102.c | 22 +- .../gsp/arch/turing/kernel_gsp_vbios_tu102.c | 2 +- src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c | 321 +- .../src/kernel/gpu/gsp/kernel_gsp_booter.c | 25 + .../kernel/gpu/intr/arch/ampere/intr_ga100.c | 23 +- .../gpu/mem_mgr/phys_mem_allocator/addrtree.c | 288 +- .../phys_mem_allocator/phys_mem_allocator.c | 13 +- .../phys_mem_allocator_util.c | 40 +- .../gpu/mem_mgr/phys_mem_allocator/regmap.c | 314 +- .../kernel/gpu/mig_mgr/kernel_mig_manager.c | 5 +- .../gpu/mmu/arch/turing/kern_gmmu_tu102.c | 5 +- .../gpu/mmu/arch/volta/kern_gmmu_gv100.c | 2 +- .../nvlink/arch/hopper/kernel_nvlink_gh100.c | 61 + .../src/kernel/gpu/nvlink/common_nvlinkapi.c | 5 +- .../src/kernel/gpu/nvlink/kernel_nvlink.c | 37 + .../gpu/nvlink/kernel_nvlinkcorelibtrain.c | 32 +- .../kernel/gpu/nvlink/kernel_nvlinkstate.c | 42 +- src/nvidia/src/kernel/gpu/pmu/kern_pmu.c | 2 +- .../gpu/subdevice/subdevice_ctrl_gpu_kernel.c | 13 + src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c | 19 +- src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c | 10 +- src/nvidia/src/kernel/mem_mgr/video_mem.c | 6 + src/nvidia/src/kernel/os/os_stubs.c | 5 + src/nvidia/src/kernel/platform/cpu.c | 3 + src/nvidia/src/kernel/platform/cpu_arm_def.h | 1 + src/nvidia/src/kernel/rmapi/alloc_free.c | 26 + .../src/kernel/rmapi/event_notification.c | 406 +- src/nvidia/src/kernel/rmapi/param_copy.c | 7 +- .../libraries/containers/eheap/eheap_old.c | 4 +- src/nvidia/src/libraries/nvport/core/core.c | 8 +- .../libraries/nvport/memory/memory_tracking.c | 196 +- .../libraries/prereq_tracker/prereq_tracker.c | 2 + .../src/libraries/resserv/src/rs_server.c | 31 +- src/nvidia/src/libraries/tls/tls.c | 56 +- src/nvidia/srcs.mk | 1 + version.mk | 2 +- 180 files changed, 9465 insertions(+), 4853 deletions(-) create mode 100644 src/common/inc/swref/published/ada/ad102/dev_gc6_island.h create mode 100644 src/common/inc/swref/published/ada/ad102/dev_gc6_island_addendum.h create mode 100644 src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c create mode 100644 src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c diff --git a/CHANGELOG.md b/CHANGELOG.md index 214616949..ba22c5b1c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,8 @@ ## Release 525 Entries +### [525.78.01] 2023-01-05 + ### [525.60.13] 2022-12-05 ### [525.60.11] 2022-11-28 diff --git a/README.md b/README.md index b7d068ef5..915d6ea5c 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 525.60.13. +version 525.78.01. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with GSP firmware and user-space NVIDIA GPU driver components from a corresponding -525.60.13 driver release. This can be achieved by installing +525.78.01 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -167,7 +167,7 @@ for the target kernel. ## Compatible GPUs The open-gpu-kernel-modules can be used on any Turing or later GPU -(see the table below). However, in the 525.60.13 release, +(see the table below). However, in the 525.78.01 release, GeForce and Workstation support is still considered alpha-quality. To enable use of the open kernel modules on GeForce and Workstation GPUs, @@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module parameter to 1. For more details, see the NVIDIA GPU driver end user README here: -https://us.download.nvidia.com/XFree86/Linux-x86_64/525.60.13/README/kernel_open.html +https://us.download.nvidia.com/XFree86/Linux-x86_64/525.78.01/README/kernel_open.html In the below table, if three IDs are listed, the first is the PCI Device ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI @@ -645,8 +645,8 @@ Subsystem Device ID. | NVIDIA A100-SXM4-80GB | 20B2 10DE 147F | | NVIDIA A100-SXM4-80GB | 20B2 10DE 1622 | | NVIDIA A100-SXM4-80GB | 20B2 10DE 1623 | -| NVIDIA PG506-242 | 20B3 10DE 14A7 | -| NVIDIA PG506-243 | 20B3 10DE 14A8 | +| NVIDIA A100-SXM-64GB | 20B3 10DE 14A7 | +| NVIDIA A100-SXM-64GB | 20B3 10DE 14A8 | | NVIDIA A100 80GB PCIe | 20B5 10DE 1533 | | NVIDIA A100 80GB PCIe | 20B5 10DE 1642 | | NVIDIA PG506-232 | 20B6 10DE 1492 | @@ -771,6 +771,7 @@ Subsystem Device ID. | NVIDIA RTX A2000 12GB | 2571 103C 1611 | | NVIDIA RTX A2000 12GB | 2571 10DE 1611 | | NVIDIA RTX A2000 12GB | 2571 17AA 1611 | +| NVIDIA GeForce RTX 3050 | 2582 | | NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A0 | | NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 8928 | | NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 89F9 | @@ -795,3 +796,11 @@ Subsystem Device ID. | NVIDIA RTX A1000 Embedded GPU | 25F9 | | NVIDIA RTX A2000 Embedded GPU | 25FA | | NVIDIA RTX A500 Embedded GPU | 25FB | +| NVIDIA GeForce RTX 4090 | 2684 | +| NVIDIA RTX 6000 Ada Generation | 26B1 1028 16A1 | +| NVIDIA RTX 6000 Ada Generation | 26B1 103C 16A1 | +| NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 | +| NVIDIA RTX 6000 Ada Generation | 26B1 17AA 16A1 | +| NVIDIA L40 | 26B5 10DE 169D | +| NVIDIA GeForce RTX 4080 | 2704 | +| NVIDIA GeForce RTX 4070 Ti | 2782 | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 2826327e3..f1df13be8 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.60.13\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.78.01\" EXTRA_CFLAGS += -Wno-unused-function diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 250e95cd2..8f884adbf 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -958,7 +958,6 @@ NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); -NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index c04dbe26d..1791f1b08 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -1059,6 +1059,23 @@ compile_test() { compile_check_conftest "$CODE" "NV_MDEV_DRIVER_HAS_SUPPORTED_TYPE_GROUPS" "" "types" ;; + vfio_device_ops_has_dma_unmap) + # + # Determine if 'vfio_device_ops' struct has 'dma_unmap' field. + # + # Added by commit ce4b4657ff18 ("vfio: Replace the DMA unmapping + # notifier with a callback") in v6.0 + # + CODE=" + #include + #include + int conftest_vfio_device_ops_has_dma_unmap(void) { + return offsetof(struct vfio_device_ops, dma_unmap); + }" + + compile_check_conftest "$CODE" "NV_VFIO_DEVICE_OPS_HAS_DMA_UNMAP" "" "types" + ;; + pci_irq_vector_helpers) # # Determine if pci_alloc_irq_vectors(), pci_free_irq_vectors() @@ -2611,7 +2628,7 @@ compile_test() { fi ;; - vfio_pin_pages) + vfio_pin_pages_has_vfio_device_arg) # # Determine if vfio_pin_pages() kABI accepts "struct vfio_device *" # argument instead of "struct device *" @@ -2642,6 +2659,37 @@ compile_test() { fi ;; + vfio_pin_pages_has_pages_arg) + # + # Determine if vfio_pin_pages() kABI accepts "struct pages **: + # argument instead of "unsigned long *phys_pfn" + # + # Replaced "unsigned long *phys_pfn" with "struct pages **pages" + # in commit 34a255e676159 ("vfio: Replace phys_pfn with pages for + # vfio_pin_pages()") in v6.0. + # + echo "$CONFTEST_PREAMBLE + #include + #include + int vfio_pin_pages(struct vfio_device *device, + dma_addr_t iova, + int npage, + int prot, + struct page **pages) { + return 0; + }" > conftest$$.c + + $CC $CFLAGS -c conftest$$.c > /dev/null 2>&1 + rm -f conftest$$.c + + if [ -f conftest$$.o ]; then + echo "#define NV_VFIO_PIN_PAGES_HAS_PAGES_ARG" | append_conftest "functions" + rm -f conftest$$.o + else + echo "#undef NV_VFIO_PIN_PAGES_HAS_PAGES_ARG" | append_conftest "functions" + fi + ;; + pci_driver_has_driver_managed_dma) # # Determine if "struct pci_driver" has .driver_managed_dma member. @@ -5404,6 +5452,28 @@ compile_test() { compile_check_conftest "$CODE" "NV_ACPI_VIDEO_BACKLIGHT_USE_NATIVE" "" "functions" ;; + drm_connector_has_override_edid) + # + # Determine if 'struct drm_connector' has an 'override_edid' member. + # + # Removed by commit 90b575f52c6ab ("drm/edid: detach debugfs EDID + # override from EDID property update") in linux-next, expected in + # v6.2-rc1. + # + CODE=" + #if defined(NV_DRM_DRM_CRTC_H_PRESENT) + #include + #endif + #if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT) + #include + #endif + int conftest_drm_connector_has_override_edid(void) { + return offsetof(struct drm_connector, override_edid); + }" + + compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HAS_OVERRIDE_EDID" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # diff --git a/kernel-open/nvidia-drm/nvidia-drm-connector.c b/kernel-open/nvidia-drm/nvidia-drm-connector.c index 77a6120e4..2b893c533 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-connector.c +++ b/kernel-open/nvidia-drm/nvidia-drm-connector.c @@ -42,6 +42,7 @@ #include #include +#include static void nv_drm_connector_destroy(struct drm_connector *connector) { @@ -98,7 +99,11 @@ __nv_drm_detect_encoder(struct NvKmsKapiDynamicDisplayParams *pDetectParams, break; } +#if defined(NV_DRM_CONNECTOR_HAS_OVERRIDE_EDID) if (connector->override_edid) { +#else + if (drm_edid_override_connector_update(connector) > 0) { +#endif const struct drm_property_blob *edid = connector->edid_blob_ptr; if (edid->length <= sizeof(pDetectParams->edid.buffer)) { diff --git a/kernel-open/nvidia-drm/nvidia-drm-drv.c b/kernel-open/nvidia-drm/nvidia-drm-drv.c index ac504ecea..cc6626a0c 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-drv.c +++ b/kernel-open/nvidia-drm/nvidia-drm-drv.c @@ -257,10 +257,6 @@ nv_drm_init_mode_config(struct nv_drm_device *nv_dev, dev->mode_config.preferred_depth = 24; dev->mode_config.prefer_shadow = 1; - /* Currently unused. Update when needed. */ - - dev->mode_config.fb_base = 0; - #if defined(NV_DRM_CRTC_STATE_HAS_ASYNC_FLIP) || \ defined(NV_DRM_CRTC_STATE_HAS_PAGEFLIP_FLAGS) dev->mode_config.async_page_flip = true; diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index 4d012bed3..6eef7f534 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -123,3 +123,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_has_hdr_output_metadata NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg +NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_has_override_edid diff --git a/kernel-open/nvidia/i2c_nvswitch.c b/kernel-open/nvidia/i2c_nvswitch.c index 592d5d846..de8318a70 100644 --- a/kernel-open/nvidia/i2c_nvswitch.c +++ b/kernel-open/nvidia/i2c_nvswitch.c @@ -288,8 +288,9 @@ nvswitch_i2c_add_adapter rc = nvswitch_os_snprintf(adapter->name, sizeof(adapter->name), - "NVIDIA NVSwitch i2c adapter %u at %x:%02x.%u", + "NVIDIA NVSwitch i2c adapter %u at %04x:%x:%02x.%u", port, + NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev), NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn)); diff --git a/src/common/displayport/inc/dp_configcaps.h b/src/common/displayport/inc/dp_configcaps.h index c85ae4fd8..a79a8ea65 100644 --- a/src/common/displayport/inc/dp_configcaps.h +++ b/src/common/displayport/inc/dp_configcaps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -245,6 +245,7 @@ namespace DisplayPort public: virtual bool getOuiSupported() = 0; virtual AuxRetry::status setOuiSource(unsigned ouiId, const char * model, size_t modelNameLength, NvU8 chipRevision) = 0; + virtual bool getOuiSource(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0; virtual bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) = 0; }; diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index 8cd1e877f..76b89bbd3 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -89,6 +89,11 @@ namespace DisplayPort Timer * timer; // OS provided timer services Connector::EventSink * sink; // Event Sink + // Cached Source OUI for restoring eDP OUI when powering up + unsigned cachedSourceOUI; + char cachedSourceModelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; + NvU8 cachedSourceChipRevision; + unsigned ouiId; // Sink ouiId char modelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; // Device Model-name bool bIgnoreSrcOuiHandshake; // Skip writing source OUI @@ -294,6 +299,8 @@ namespace DisplayPort bool bEnableFastLT; NvU32 maxLinkRateFromRegkey; + bool bEnableOuiRestoring; + // // Latency(ms) to apply between link-train and FEC enable for bug // 2561206. @@ -322,6 +329,12 @@ namespace DisplayPort // bool bDscCapBasedOnParent; + // + // MST device connnected to dock may issue IRQ for link lost. + // Send PowerDown path msg to suppress that. + // + bool bPowerDownPhyBeforeD3; + void sharedInit(); ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Connector::EventSink * sink); diff --git a/src/common/displayport/inc/dp_discovery.h b/src/common/displayport/inc/dp_discovery.h index b0aa1705f..d0a8fa7eb 100644 --- a/src/common/displayport/inc/dp_discovery.h +++ b/src/common/displayport/inc/dp_discovery.h @@ -57,7 +57,7 @@ namespace DisplayPort bool videoSink; // Should be true when a video sink is supported NvU64 maxTmdsClkRate; - Device():peerDevice(None),SDPStreams(0),SDPStreamSinks(0),dirty(false),videoSink(false) + Device():peerDevice(None),SDPStreams(0),SDPStreamSinks(0),dirty(false),videoSink(false),maxTmdsClkRate(0) { portMap.validMap = portMap.inputMap = portMap.internalMap = 0; } diff --git a/src/common/displayport/inc/dp_linkconfig.h b/src/common/displayport/inc/dp_linkconfig.h index 311b054a7..7a9994404 100644 --- a/src/common/displayport/inc/dp_linkconfig.h +++ b/src/common/displayport/inc/dp_linkconfig.h @@ -385,6 +385,11 @@ namespace DisplayPort void pbnRequired(const ModesetInfo & modesetInfo, unsigned & base_pbn, unsigned & slots, unsigned & slots_pbn) { base_pbn = pbnForMode(modesetInfo); + if (bEnableFEC) + { + // IF FEC is enabled, we need to consider 3% overhead as per DP1.4 spec. + base_pbn = (NvU32)(divide_ceil(base_pbn * 100, 97)); + } slots = slotsForPBN(base_pbn); slots_pbn = PBNForSlots(slots); } diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 6e49227d7..12afaf2ca 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -59,6 +59,12 @@ #define NV_DP_REGKEY_FORCE_EDP_ILR "DP_BYPASS_EDP_ILR_REV_CHECK" +// Regkey to enable OUI caching/restoring in release branch. +#define NV_DP_REGKEY_ENABLE_OUI_RESTORING "DP_ENABLE_OUI_RESTORING" + +// Message to power down video stream before power down link (set D3) +#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY" + // // DSC capability of downstream device should be decided based on device's own // and its parent's DSC capability. @@ -96,6 +102,8 @@ struct DP_REGKEY_DATABASE bool bOptLinkKeptAliveSst; bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; + bool bEnableOuiRestoring; + bool bPowerDownPhyBeforeD3; }; #endif //INCLUDED_DP_REGKEYDATABASE_H diff --git a/src/common/displayport/src/dp_configcaps.cpp b/src/common/displayport/src/dp_configcaps.cpp index 7cd4389ee..d4f46e05e 100644 --- a/src/common/displayport/src/dp_configcaps.cpp +++ b/src/common/displayport/src/dp_configcaps.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -863,6 +863,42 @@ struct DPCDHALImpl : DPCDHAL return bus.write(NV_DPCD_SOURCE_IEEE_OUI, &ouiBuffer[0], sizeof ouiBuffer); } + virtual bool getOuiSource(unsigned &ouiId, char * modelName, + size_t modelNameBufferSize, NvU8 & chipRevision) + { + NvU8 ouiBuffer[16]; + int address = NV_DPCD_SOURCE_IEEE_OUI; + + if (caps.revisionMajor <= 0) + DP_ASSERT(0 && "Something is wrong, revision major should be > 0"); + + // If buffer size is larger than dev_id size, the extras are not used. + // If buffer size is smaller, than we can only get certain bytes. + if (modelNameBufferSize > NV_DPCD_SOURCE_DEV_ID_STRING__SIZE) + { + modelNameBufferSize = NV_DPCD_SOURCE_DEV_ID_STRING__SIZE; + } + + if (AuxRetry::ack != bus.read(address, &ouiBuffer[0], sizeof ouiBuffer)) + { + *modelName = 0; + ouiId = 0; + chipRevision = 0; + return false; + } + // The first 3 bytes are IEEE_OUI. 2 hex digits per register. + ouiId = ouiBuffer[0] | (ouiBuffer[1] << 8) | (ouiBuffer[2] << 16); + + // Next 6 bytes are Device Identification String, copy as much as we can (limited buffer case). + unsigned int i; + for (i = 0; i < modelNameBufferSize; i++) + modelName[i] = ouiBuffer[3+i]; + + chipRevision = ouiBuffer[9]; + + return true; + } + virtual bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision) { NvU8 ouiBuffer[16]; diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index 451602945..fd641612a 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -188,6 +188,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab this->bDisableSSC = dpRegkeyDatabase.bSscDisabled; this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; + this->bEnableOuiRestoring = dpRegkeyDatabase.bEnableOuiRestoring; + this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3; } void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled) @@ -704,6 +706,13 @@ create: newDev->applyOUIOverrides(); + if (main->isEDP() && this->bEnableOuiRestoring) + { + // Save Source OUI information for eDP. + hal->getOuiSource(cachedSourceOUI, &cachedSourceModelName[0], + sizeof(cachedSourceModelName), cachedSourceChipRevision); + } + fireEvents(); } @@ -1178,7 +1187,7 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, this->isFECSupported() && // If GPU supports FEC pDscParams && // If client sent DSC info pDscParams->bCheckWithDsc && // If client wants to check with DSC - (dev && dev->isDSCPossible()) && // Either device or it's parent supports DSC + (dev && dev->devDoingDscDecompression) && // Either device or it's parent supports DSC bFecCapable && // If path up to dsc decoding device supports FEC (modesetParams.modesetInfo.bitsPerComponent != 6)) // DSC doesn't support bpc = 6 { @@ -1239,9 +1248,13 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, (modesetParams.colorFormat == dpColorFormat_YCbCr444 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCr444) || (modesetParams.colorFormat == dpColorFormat_YCbCr422 && !dev->parent->dscCaps.dscDecoderColorFormatCaps.bYCbCrSimple422)) { - if (pDscParams->forceDsc == DSC_FORCE_ENABLE) + if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || + (modesetParams.modesetInfo.mode == DSC_DUAL)) { - // If DSC is force enabled then return failure here + // + // If DSC is force enabled or DSC_DUAL mode is requested, + // then return failure here + // compoundQueryResult = false; pDscParams->bEnableDsc = false; return false; @@ -1270,9 +1283,24 @@ bool ConnectorImpl::compoundQueryAttach(Group * target, (NvU32*)(PPS), (NvU32*)(&bitsPerPixelX16))) != NVT_STATUS_SUCCESS) { - if (pDscParams->forceDsc == DSC_FORCE_ENABLE) + // + // If generating PPS failed + // AND + // (DSC is force enabled + // OR + // the requested DSC mode = DUAL) + //then + // return failure here + // Else + // we will check if non DSC path is possible. + // + // If dsc mode = DUAL failed to generate PPS and if we pursue + // non DSC path, DD will still follow 2Head1OR modeset path with + // DSC disabled, eventually leading to HW hang. Bug 3632901 + // + if ((pDscParams->forceDsc == DSC_FORCE_ENABLE) || + (modesetParams.modesetInfo.mode == DSC_DUAL)) { - // If DSC is force enabled then return failure here compoundQueryResult = false; pDscParams->bEnableDsc = false; return false; @@ -2667,6 +2695,21 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr this->bFECEnable |= bEnableFEC; highestAssessedLC.enableFEC(this->bFECEnable); + if (main->isEDP() && this->bEnableOuiRestoring) + { + // Power-up eDP and restore eDP OUI if it's powered off now. + bool bPanelPowerOn; + main->getEdpPowerData(&bPanelPowerOn, NULL); + if (!bPanelPowerOn) + { + main->configurePowerState(true); + hal->setOuiSource(cachedSourceOUI, + &cachedSourceModelName[0], + 6 /* string length of ieeeOuiDevId */, + cachedSourceChipRevision); + } + } + // if failed, we're guaranteed that assessed link rate didn't meet the mode requirements // isZombie() will catch this bLinkTrainingStatus = trainLinkOptimized(getMaxLinkConfig()); @@ -3248,6 +3291,22 @@ void ConnectorImpl::powerdownLink(bool bPowerdownPanel) powerOff.lanes = 0; // Inform Sink about Main Link Power Down. + if (linkUseMultistream() && bPowerDownPhyBeforeD3) + { + PowerDownPhyMessage powerDownPhyMsg; + NakData nack; + + for (Device * i = enumDevices(0); i; i=enumDevices(i)) + { + if (i->isPlugged() && i->isVideoSink()) + { + Address devAddress = ((DeviceImpl*)i)->address; + powerDownPhyMsg.set(devAddress.parent(), devAddress.tail(), NV_TRUE); + this->messageManager->send(&powerDownPhyMsg, nack); + } + } + } + // // 1> If it is eDP and the power is not on, we don't need to put it into D3 here // 2> If FEC is enabled then we have to put panel in D3 after powering down mainlink diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index f5d6cded5..b06c0c81a 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -920,23 +920,31 @@ void DeviceImpl::applyOUIOverrides() if ((buffer[3] == 0x53) && (buffer[4] == 0x59) && (buffer[5] == 0x4E) && (buffer[6] == 0x41)) { // For Synaptic VMM5331 and VMM5320, it only support MSA-Over-MST for DP after Firmware 5.4.5 - if (buffer[7] == 0x53 && - (buffer[8] == 0x31 || buffer[8] == 0x20)) + if (buffer[7] == 0x53) { - this->bSdpExtCapable = False; + // + // This flag will be checked only in DSC Pass through cases (MST). + // All Synaptics VMM53XX chips which support pass through can only support + // color formats that are listed in 0x69h even in pass through mode. + // this->bDscPassThroughColorFormatWar = true; - - // - // Check firmware version - // 0x50A: FW/SW Major Revision. - // 0x50B: FW/SW Minor Revision. - // 0x50C: Build Number. - // - if ((buffer[10] >= 0x06) || - ((buffer[10] == 0x05) && (buffer[11] >= 0x05)) || - ((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05))) + + if ((buffer[8] == 0x31) || (buffer[8] == 0x20)) { - this->bSdpExtCapable = True; + this->bSdpExtCapable = False; + + // + // Check firmware version + // 0x50A: FW/SW Major Revision. + // 0x50B: FW/SW Minor Revision. + // 0x50C: Build Number. + // + if ((buffer[10] >= 0x06) || + ((buffer[10] == 0x05) && (buffer[11] >= 0x05)) || + ((buffer[10] == 0x05) && (buffer[11] == 0x04) && (buffer[12] >= 0x05))) + { + this->bSdpExtCapable = True; + } } } } diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index b77a1ad49..7d55eefeb 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -93,7 +93,9 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, - {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL} + {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_ENABLE_OUI_RESTORING, &dpRegkeyDatabase.bEnableOuiRestoring, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : diff --git a/src/common/displayport/src/dp_watermark.cpp b/src/common/displayport/src/dp_watermark.cpp index 1dd43638d..daf89009b 100644 --- a/src/common/displayport/src/dp_watermark.cpp +++ b/src/common/displayport/src/dp_watermark.cpp @@ -852,21 +852,16 @@ bool DisplayPort::isModePossibleMSTWithFEC unsigned DisplayPort::pbnForMode(const ModesetInfo & modesetInfo) { + // When DSC is enabled consider depth will multiplied by 16 + unsigned dsc_factor = modesetInfo.bEnableDsc ? 16 : 1; + // // Calculate PBN in terms of 54/64 mbyte/sec // round up by .6% for spread de-rate. Note: if we're not spreading our link // this MUST still be counted. It's also to allow downstream links to be spread. // unsigned pbnForMode = (NvU32)(divide_ceil(modesetInfo.pixelClockHz * modesetInfo.depth * 1006 * 64 / 8, - (NvU64)54000000 *1000)); - - if(modesetInfo.bEnableDsc) - { - // - // When DSC is enabled consider depth will multiplied by 16 and also 3% FEC Overhead - // as per DP1.4 spec - pbnForMode = (NvU32)(divide_ceil(pbnForMode * 100, 97 * DSC_DEPTH_FACTOR)); - } + (NvU64)54000000 * 1000 * dsc_factor)); return pbnForMode; } diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index cd44144b2..7756bedb1 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,25 +36,25 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r526_91 + #define NV_BUILD_BRANCH r527_92 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r526_91 + #define NV_PUBLIC_BRANCH r527_92 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r526_91-183" -#define NV_BUILD_CHANGELIST_NUM (32139144) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r527_92-225" +#define NV_BUILD_CHANGELIST_NUM (32231446) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r525/r526_91-183" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32139144) +#define NV_BUILD_NAME "rel/gpu_drv/r525/r527_92-225" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32231446) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r526_91-9" -#define NV_BUILD_CHANGELIST_NUM (32103636) +#define NV_BUILD_BRANCH_VERSION "r527_92-2" +#define NV_BUILD_CHANGELIST_NUM (32226812) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "527.27" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32103636) +#define NV_BUILD_NAME "528.02" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32226812) #define NV_BUILD_BRANCH_BASE_VERSION R525 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvPNPVendorIds.h b/src/common/inc/nvPNPVendorIds.h index b1c423809..8c0ae38e4 100644 --- a/src/common/inc/nvPNPVendorIds.h +++ b/src/common/inc/nvPNPVendorIds.h @@ -120,6 +120,7 @@ static const PNPVendorId PNPVendorIds[] = { "BCD", _VENDOR_NAME_ENTRY("Dr. Seufert GmbH") }, { "BEO", _VENDOR_NAME_ENTRY("Bang & Olufsen") }, { "BGT", _VENDOR_NAME_ENTRY("Budzetron") }, + { "BIG", _VENDOR_NAME_ENTRY("Bigscreen, Inc.") }, { "BMM", _VENDOR_NAME_ENTRY("MAG Technology") }, { "BNQ", _VENDOR_NAME_ENTRY("BenQ") }, { "BOE", _VENDOR_NAME_ENTRY("BOE Technology Group Co., Ltd") }, @@ -276,6 +277,7 @@ static const PNPVendorId PNPVendorIds[] = { "IMA", _VENDOR_NAME_ENTRY("Imagraph") }, { "IMC", _VENDOR_NAME_ENTRY("IMC Networks") }, { "IMP", _VENDOR_NAME_ENTRY("Impression") }, + { "IMX", _VENDOR_NAME_ENTRY("Arpara Technology Co., Ltd.") }, { "INF", _VENDOR_NAME_ENTRY("Inframetrics") }, { "INL", _VENDOR_NAME_ENTRY("InnoLux Display Corporation") }, { "INP", _VENDOR_NAME_ENTRY("Interphase") }, diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 4e58462e3..afc4d8734 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "525.60.13" +#define NV_VERSION_STRING "525.78.01" #else diff --git a/src/common/inc/swref/published/ada/ad102/dev_gc6_island.h b/src/common/inc/swref/published/ada/ad102/dev_gc6_island.h new file mode 100644 index 000000000..634f8d57c --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_gc6_island.h @@ -0,0 +1,29 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ad102_dev_gc6_island_h__ +#define __ad102_dev_gc6_island_h__ + +#define NV_PGC6_BSI_SECURE_SCRATCH_15 0x001180fc /* RW-4R */ + +#endif // __ad102_dev_gc6_island_h__ diff --git a/src/common/inc/swref/published/ada/ad102/dev_gc6_island_addendum.h b/src/common/inc/swref/published/ada/ad102/dev_gc6_island_addendum.h new file mode 100644 index 000000000..780afbdf8 --- /dev/null +++ b/src/common/inc/swref/published/ada/ad102/dev_gc6_island_addendum.h @@ -0,0 +1,32 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __ad102_dev_gc6_island_addendum_h__ +#define __ad102_dev_gc6_island_addendum_h__ + +#define NV_PGC6_BSI_VPR_SECURE_SCRATCH_15 NV_PGC6_BSI_SECURE_SCRATCH_15 +#define NV_PGC6_BSI_VPR_SECURE_SCRATCH_15_SCRUBBER_HANDOFF 31:29 +#define NV_PGC6_BSI_VPR_SECURE_SCRATCH_15_SCRUBBER_HANDOFF_DONE 0x00000003 + +#endif // __ad102_dev_gc6_island_addendum_h__ + diff --git a/src/common/modeset/timing/nvt_edidext_861.c b/src/common/modeset/timing/nvt_edidext_861.c index 7fc19e443..102693c3e 100644 --- a/src/common/modeset/timing/nvt_edidext_861.c +++ b/src/common/modeset/timing/nvt_edidext_861.c @@ -32,6 +32,8 @@ #include "edid.h" + + PUSH_SEGMENTS #define EIA_TIMING(hv,hfp,hsw,ht,hsp,vv,vfp,vsw,vt,vsp,rrx1k,ip,aspect,rep,format) \ @@ -1111,10 +1113,12 @@ void parseCta861VsdbBlocks(NVT_EDID_CEA861_INFO *pExt861, case NVT_CEA861_NVDA_IEEE_ID: parseEdidNvidiaVSDBBlock((VSDB_DATA *)(&pExt861->vsdb[i]), pNvVsdb); + pExt861->valid.nvda_vsdb = 1; break; case NVT_CEA861_MSFT_IEEE_ID: parseEdidMsftVsdbBlock((VSDB_DATA *)(&pExt861->vsdb[i]), pMsftVsdb); + pExt861->valid.msft_vsdb = 1; break; } @@ -1233,12 +1237,6 @@ NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info) return NVT_STATUS_ERR; } - // DTD offset sanity check - if (p[2] >= 1 && p[2] <= 3) - { - return NVT_STATUS_ERR; - } - // don't do anything further if p861info is NULL if (p861info == NULL) { diff --git a/src/common/modeset/timing/nvt_edidext_displayid20.c b/src/common/modeset/timing/nvt_edidext_displayid20.c index 2a2ad1955..fb4f15fb2 100644 --- a/src/common/modeset/timing/nvt_edidext_displayid20.c +++ b/src/common/modeset/timing/nvt_edidext_displayid20.c @@ -245,13 +245,20 @@ parseDisplayId20EDIDExtDataBlocks( // copy all the vendor specific data block from DisplayId20 to pEdidInfo // NOTE: mixed CTA extension block and DID2.0 extension block are not handled - NVMISC_MEMCPY(&pEdidInfo->hdmiLlcInfo, &pDisplayId20Info->vendor_specific.hdmiLlc, sizeof(NVT_HDMI_LLC_INFO)); - NVMISC_MEMCPY(&pEdidInfo->hdmiForumInfo, &pDisplayId20Info->vendor_specific.hfvs, sizeof(NVT_HDMI_FORUM_INFO)); - NVMISC_MEMCPY(&pEdidInfo->nvdaVsdbInfo, &pDisplayId20Info->vendor_specific.nvVsdb, sizeof(NVDA_VSDB_PARSED_INFO)); - NVMISC_MEMCPY(&pEdidInfo->msftVsdbInfo, &pDisplayId20Info->vendor_specific.msftVsdb, sizeof(MSFT_VSDB_PARSED_INFO)); - NVMISC_MEMCPY(&pEdidInfo->hdr_static_metadata_info, &pDisplayId20Info->cta.hdrInfo, sizeof(NVT_HDR_STATIC_METADATA)); - NVMISC_MEMCPY(&pEdidInfo->dv_static_metadata_info, &pDisplayId20Info->cta.dvInfo, sizeof(NVT_DV_STATIC_METADATA)); - NVMISC_MEMCPY(&pEdidInfo->hdr10PlusInfo, &pDisplayId20Info->cta.hdr10PlusInfo, sizeof(NVT_HDR10PLUS_INFO)); + if (pEdidInfo->ext861.valid.H14B_VSDB == 0 && pEdidInfo->ext861_2.valid.H14B_VSDB == 0 && pDisplayId20Info->cta.cta861_info.valid.H14B_VSDB) + NVMISC_MEMCPY(&pEdidInfo->hdmiLlcInfo, &pDisplayId20Info->vendor_specific.hdmiLlc, sizeof(NVT_HDMI_LLC_INFO)); + if (pEdidInfo->ext861.valid.H20_HF_VSDB == 0 && pEdidInfo->ext861_2.valid.H20_HF_VSDB == 0 && pDisplayId20Info->cta.cta861_info.valid.H20_HF_VSDB) + NVMISC_MEMCPY(&pEdidInfo->hdmiForumInfo, &pDisplayId20Info->vendor_specific.hfvs, sizeof(NVT_HDMI_FORUM_INFO)); + if (pEdidInfo->ext861.valid.nvda_vsdb == 0 && pEdidInfo->ext861_2.valid.nvda_vsdb == 0 && pDisplayId20Info->cta.cta861_info.valid.nvda_vsdb) + NVMISC_MEMCPY(&pEdidInfo->nvdaVsdbInfo, &pDisplayId20Info->vendor_specific.nvVsdb, sizeof(NVDA_VSDB_PARSED_INFO)); + if (pEdidInfo->ext861.valid.msft_vsdb == 0 && pEdidInfo->ext861_2.valid.msft_vsdb == 0 && pDisplayId20Info->cta.cta861_info.valid.msft_vsdb) + NVMISC_MEMCPY(&pEdidInfo->msftVsdbInfo, &pDisplayId20Info->vendor_specific.msftVsdb, sizeof(MSFT_VSDB_PARSED_INFO)); + if (pEdidInfo->ext861.valid.hdr_static_metadata == 0 && pEdidInfo->ext861_2.valid.hdr_static_metadata == 0 && pDisplayId20Info->cta.cta861_info.valid.hdr_static_metadata) + NVMISC_MEMCPY(&pEdidInfo->hdr_static_metadata_info, &pDisplayId20Info->cta.hdrInfo, sizeof(NVT_HDR_STATIC_METADATA)); + if (pEdidInfo->ext861.valid.dv_static_metadata == 0 && pEdidInfo->ext861_2.valid.dv_static_metadata == 0 && pDisplayId20Info->cta.cta861_info.valid.dv_static_metadata) + NVMISC_MEMCPY(&pEdidInfo->dv_static_metadata_info, &pDisplayId20Info->cta.dvInfo, sizeof(NVT_DV_STATIC_METADATA)); + if (pEdidInfo->ext861.valid.hdr10Plus == 0 && pEdidInfo->ext861_2.valid.hdr10Plus == 0 && pDisplayId20Info->cta.cta861_info.valid.hdr10Plus) + NVMISC_MEMCPY(&pEdidInfo->hdr10PlusInfo, &pDisplayId20Info->cta.hdr10PlusInfo, sizeof(NVT_HDR10PLUS_INFO)); // If the CTA861 extension existed already, we need to synced the revision/basic_caps to CTA which is embedded in DID20 if (pEdidInfo->ext861.revision >= NVT_CEA861_REV_B) @@ -262,7 +269,10 @@ parseDisplayId20EDIDExtDataBlocks( } // this is the DisplayID20 Extension, so we need to copy from what is the CTA raw data in DID20 to Edid's CTA block - NVMISC_MEMCPY(&pEdidInfo->ext861, &pDisplayId20Info->cta.cta861_info, sizeof(NVT_EDID_CEA861_INFO)); + if (pEdidInfo->ext861.revision == 0) + NVMISC_MEMCPY(&pEdidInfo->ext861, &pDisplayId20Info->cta.cta861_info, sizeof(NVT_EDID_CEA861_INFO)); + else if (pEdidInfo->ext861_2.revision == 0) + NVMISC_MEMCPY(&pEdidInfo->ext861_2, &pDisplayId20Info->cta.cta861_info, sizeof(NVT_EDID_CEA861_INFO)); break; case DISPLAYID_2_0_BLOCK_TYPE_DISPLAY_PARAM: diff --git a/src/common/modeset/timing/nvtiming.h b/src/common/modeset/timing/nvtiming.h index e75f95971..c791b86bc 100644 --- a/src/common/modeset/timing/nvtiming.h +++ b/src/common/modeset/timing/nvtiming.h @@ -1123,6 +1123,8 @@ typedef struct tagNVT_VALID_EXTENDED_BLOCKS NvU32 hdr10Plus : 1; NvU32 SCDB : 1; NvU32 HF_EEODB : 1; + NvU32 nvda_vsdb : 1; + NvU32 msft_vsdb : 1; } NVT_VALID_EXTENDED_BLOCKS; diff --git a/src/common/nvlink/interface/nvlink.h b/src/common/nvlink/interface/nvlink.h index 46d74efbe..3415fe0c9 100644 --- a/src/common/nvlink/interface/nvlink.h +++ b/src/common/nvlink/interface/nvlink.h @@ -141,6 +141,20 @@ struct nvlink_link_change enum nvlink_link_change_type change_type; }; +// +// Structure representing Nvlink Error Threshold +// +struct nvlink_link_error_threshold +{ + NvU8 thresholdMan; + NvU8 thresholdExp; + NvU8 timescaleMan; + NvU8 timescaleExp; + NvBool bInterruptEn; + NvBool bUserConfig; + NvBool bInterruptTrigerred; // Error threshold interrupt generated +}; + // nvlink link state struct nvlink_link { @@ -233,6 +247,8 @@ struct nvlink_link //seed data for given nvlink NvU32 seedData[NVLINK_MAX_SEED_BUFFER_SIZE]; + + struct nvlink_link_error_threshold errorThreshold; }; // nvlink link handler ops diff --git a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c index 1931e5140..0bdc93e81 100644 --- a/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c +++ b/src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c @@ -1047,7 +1047,7 @@ nvlink_core_powerdown_floorswept_conns_to_off if (numConnsToShutdown != 0) { nvlink_core_powerdown_intranode_conns_from_active_to_off(connsToShutdown, numConnsToShutdown, 0); - nvlink_core_reset_intranode_conns(connsToShutdown, numConnsToShutdown, NVLINK_STATE_CHANGE_ASYNC); + nvlink_core_reset_intranode_conns(connsToShutdown, numConnsToShutdown, NVLINK_STATE_CHANGE_SYNC); for (j = 0; j < numConnsToShutdown; ++j) { @@ -1056,5 +1056,8 @@ nvlink_core_powerdown_floorswept_conns_to_off } } + nvlink_free(visitedConns); + nvlink_free(connsToShutdown); + return NVL_SUCCESS; } diff --git a/src/common/nvswitch/common/inc/soe/soeifcore.h b/src/common/nvswitch/common/inc/soe/soeifcore.h index 4af463fd9..09c5c7446 100644 --- a/src/common/nvswitch/common/inc/soe/soeifcore.h +++ b/src/common/nvswitch/common/inc/soe/soeifcore.h @@ -70,7 +70,18 @@ enum /*! * Set NPORT TPROD state */ - RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE + RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE, + + /*! + * Read VRs + * Needed to be in sync with chips_a defines + */ + RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES, + + /*! + * Init PLM2 protected registers + */ + RM_SOE_CORE_CMD_INIT_L2_STATE }; // Timeout for SOE reset callback function @@ -132,6 +143,11 @@ typedef struct NvU32 nport; } RM_SOE_CORE_CMD_NPORT_TPROD_STATE; +typedef struct +{ + NvU8 cmdType; +} RM_SOE_CORE_CMD_L2_STATE; + typedef union { NvU8 cmdType; @@ -141,5 +157,6 @@ typedef union RM_SOE_CORE_CMD_NPORT_RESET nportReset; RM_SOE_CORE_CMD_NPORT_STATE nportState; RM_SOE_CORE_CMD_NPORT_TPROD_STATE nportTprodState; + RM_SOE_CORE_CMD_L2_STATE l2State; } RM_SOE_CORE_CMD; #endif // _SOECORE_H_ diff --git a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h index ce9a47f28..04c187a37 100644 --- a/src/common/nvswitch/interface/ctrl_dev_nvswitch.h +++ b/src/common/nvswitch/interface/ctrl_dev_nvswitch.h @@ -99,7 +99,7 @@ typedef enum nvswitch_get_info_index NVSWITCH_GET_INFO_INDEX_PCI_DOMAIN = 0x300, NVSWITCH_GET_INFO_INDEX_PCI_BUS, NVSWITCH_GET_INFO_INDEX_PCI_DEVICE, - NVSWITCH_GET_INFO_INDEX_PCI_FUNCTION + NVSWITCH_GET_INFO_INDEX_PCI_FUNCTION, /* See enum modification guidelines at the top of this file */ } NVSWITCH_GET_INFO_INDEX; @@ -3285,6 +3285,23 @@ typedef struct nvswitch_inband_pending_data_stats_params NV_DECLARE_ALIGNED(NvU64 linkMask, 8); } NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS; +/* + * CTRL_NVSWITCH_GET_BOARD_PART_NUMBER + * + * Control for querying the board part number + * + * Parameters: + * [out] data[] + * Byte vector of the board part number. + */ + +#define NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES 20 + +typedef struct nvswitch_get_board_part_number_vector +{ + NvU8 data[NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES]; +} NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR; + #define NVSWITCH_GET_SW_INFO_COUNT_MAX 32 typedef enum nvswitch_get_sw_info_index @@ -3603,6 +3620,58 @@ typedef struct NvU32 val; // in: register value to write } NVSWITCH_REGISTER_WRITE; + +typedef struct +{ + NvU8 thresholdMan; + NvU8 thresholdExp; + NvU8 timescaleMan; + NvU8 timescaleExp; + NvBool bInterruptEn; + NvBool bInterruptTrigerred; + NvU32 flags; +} NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES; + +#define NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET 0x1 + +/* + * CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD + * + * Set the Nvlink Error Rate Threshold. + * + * Parameters: + * linkMask [IN] + * A valid link mask for which we need to set the Error Threshold + * + * errorThreshold [IN] + * Threshold values, interrupt enable/disable and flags + */ + +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 link_mask, 8); + NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS; + +/* + * CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD + * + * Control to query NVLIPT counter configuration. + * + * Parameters: + * linkMask [IN] + * A valid link mask for which we need to get the Error Threshold + * + * errorThreshold [OUT] + * Threshold values, interrupt enable/disable and flags + */ + +typedef struct +{ + NV_DECLARE_ALIGNED(NvU64 link_mask, 8); + NVSWITCH_NVLINK_ERROR_THRESHOLD_VALUES errorThreshold[NVSWITCH_NVLINK_MAX_LINKS]; +} NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS; + #define REGISTER_RW_ENGINE_RAW 0x00 #define REGISTER_RW_ENGINE_CLKS 0x10 @@ -3731,6 +3800,9 @@ typedef struct #define CTRL_NVSWITCH_GET_INFOROM_VERSION 0x4F #define CTRL_NVSWITCH_GET_ERR_INFO 0x50 #define CTRL_NVSWITCH_CLEAR_COUNTERS 0x51 +#define CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD 0x52 +#define CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD 0x53 +#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x54 #ifdef __cplusplus } diff --git a/src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c b/src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c index 513fedfa1..6d151fd30 100644 --- a/src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c +++ b/src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c @@ -23,6 +23,7 @@ #include "flcn/haldefs_flcn_nvswitch.h" #include "flcn/flcn_nvswitch.h" +#include "rmflcncmdif_nvswitch.h" #include "flcnifcmn.h" @@ -109,7 +110,10 @@ flcnQueueCmdPostBlocking if (status != NV_OK) { NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE, - "Fatal, Failed to post command to SOE\n"); + "Fatal, Failed to post command to SOE. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", + pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags, + pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd); + return status; } @@ -117,7 +121,9 @@ flcnQueueCmdPostBlocking if (status == NV_ERR_TIMEOUT) { NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_TIMEOUT, - "Fatal, Timed out while waiting for SOE command completion\n"); + "Fatal, Timed out while waiting for SOE command completion. Data {0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x}\n", + pCmd->cmdGen.hdr.unitId, pCmd->cmdGen.hdr.size, pCmd->cmdGen.hdr.ctrlFlags, + pCmd->cmdGen.hdr.seqNumId, pCmd->cmdGen.cmd, (NvU8)pCmd->cmdGen.cmd); flcnQueueCmdCancel(device, pFlcn, *pSeqDesc); } diff --git a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h index 02a6025ee..ddf79cd30 100644 --- a/src/common/nvswitch/kernel/inc/haldef_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/haldef_nvswitch.h @@ -119,6 +119,7 @@ _op(NvlStatus, nvswitch_deassert_link_reset, (nvswitch_device *device, nvlink_link *link), _arch) \ _op(NvBool, nvswitch_is_soe_supported, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_init_soe, (nvswitch_device *device), _arch) \ + _op(void, nvswitch_soe_init_l2_state, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_inforom_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_spi_supported, (nvswitch_device *device), _arch) \ _op(NvBool, nvswitch_is_smbpbi_supported, (nvswitch_device *device), _arch) \ @@ -147,6 +148,7 @@ _op(void, nvswitch_initialize_oms_state, (nvswitch_device *device, INFOROM_OMS_STATE *pOmsState), _arch) \ _op(NvlStatus, nvswitch_oms_inforom_flush, (nvswitch_device *device), _arch) \ _op(void, nvswitch_inforom_ecc_get_total_errors, (nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, NvU64 *corCount, NvU64 *uncCount), _arch) \ + _op(NvlStatus, nvswitch_inforom_load_obd, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_bbx_add_sxid, (nvswitch_device *device, NvU32 exceptionType, NvU32 data0, NvU32 data1, NvU32 data2), _arch) \ _op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \ _op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \ @@ -218,7 +220,10 @@ _op(NvlStatus, nvswitch_service_minion_link, (nvswitch_device *device, NvU32 link_id), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_sw_info, (nvswitch_device *device, NVSWITCH_GET_SW_INFO_PARAMS *p), _arch) \ _op(NvlStatus, nvswitch_ctrl_get_err_info, (nvswitch_device *device, NVSWITCH_NVLINK_GET_ERR_INFO_PARAMS *ret), _arch) \ - _op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) + _op(NvlStatus, nvswitch_ctrl_clear_counters, (nvswitch_device *device, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS *ret), _arch) \ + _op(NvlStatus, nvswitch_ctrl_set_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_nvlink_error_threshold, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams), _arch) \ + _op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) #define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \ _op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \ diff --git a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h index 9f800c608..ffad80a8d 100644 --- a/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h @@ -74,8 +74,15 @@ struct inforom struct { NvBool bValid; - NvU8 packedObject[INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE]; - INFOROM_OBD_OBJECT_V1_XX object; + union { + NvU8 v1[INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE]; + NvU8 v2[INFOROM_OBD_OBJECT_V2_XX_PACKED_SIZE]; + } packedObject; + union { + INFOROM_OBJECT_HEADER_V1_00 header; + INFOROM_OBD_OBJECT_V1_XX v1; + INFOROM_OBD_OBJECT_V2_XX v2; + } object; } OBD; struct diff --git a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h index b5d60ce43..1bea27489 100644 --- a/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h @@ -108,6 +108,12 @@ nvswitch_oms_inforom_flush_lr10 struct nvswitch_device *device ); +NvlStatus +nvswitch_inforom_load_obd_lr10 +( + nvswitch_device *device +); + NvlStatus nvswitch_bbx_add_sxid_lr10 ( diff --git a/src/common/nvswitch/kernel/inc/lr10/lr10.h b/src/common/nvswitch/kernel/inc/lr10/lr10.h index 93fd6a615..83043ab53 100644 --- a/src/common/nvswitch/kernel/inc/lr10/lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/lr10.h @@ -652,6 +652,7 @@ NvlStatus nvswitch_ctrl_get_sw_info_lr10(nvswitch_device *device, NVSWITCH_GET_S void nvswitch_setup_link_system_registers_lr10(nvswitch_device *device, nvlink_link *link); void nvswitch_load_link_disable_settings_lr10(nvswitch_device *device, nvlink_link *link); NvBool nvswitch_is_smbpbi_supported_lr10(nvswitch_device *device); +NvlStatus nvswitch_ctrl_get_board_part_number_lr10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); NvlStatus nvswitch_ctrl_set_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_SET_MC_RID_TABLE_PARAMS *p); NvlStatus nvswitch_ctrl_get_mc_rid_table_lr10(nvswitch_device *device, NVSWITCH_GET_MC_RID_TABLE_PARAMS *p); diff --git a/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h b/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h index 4e9ccab4a..b29954b42 100644 --- a/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h +++ b/src/common/nvswitch/kernel/inc/lr10/soe_lr10.h @@ -62,4 +62,5 @@ void nvswitch_soe_unregister_events_lr10(nvswitch_device *device); void nvswitch_therm_soe_callback_lr10(nvswitch_device *device, union RM_FLCN_MSG *pMsg, void *pParams, NvU32 seqDesc, NV_STATUS status); NvlStatus nvswitch_soe_register_event_callbacks_lr10(nvswitch_device *device); +void nvswitch_soe_init_l2_state_lr10(nvswitch_device *device); #endif //_SOE_LR10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h index 07f7e79fe..7848e9943 100644 --- a/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h @@ -79,6 +79,12 @@ nvswitch_inforom_ecc_get_total_errors_ls10 NvU64 *pUncorrectedTotal ); +NvlStatus +nvswitch_inforom_load_obd_ls10 +( + nvswitch_device *device +); + NvlStatus nvswitch_bbx_add_sxid_ls10 ( diff --git a/src/common/nvswitch/kernel/inc/ls10/ls10.h b/src/common/nvswitch/kernel/inc/ls10/ls10.h index 80cf219f7..bdd6da4ba 100644 --- a/src/common/nvswitch/kernel/inc/ls10/ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/ls10.h @@ -371,6 +371,7 @@ typedef struct _op(XAL, ) \ _op(XPL, ) \ _op(XTL, ) \ + _op(XTL_CONFIG, ) \ _op(SAW, ) \ _op(SOE, ) \ _op(SMR, ) \ @@ -962,12 +963,14 @@ NvBool nvswitch_i2c_is_device_access_allowed_ls10(nvswitch_device *device, Nv NvlStatus nvswitch_minion_get_ali_debug_registers_ls10(nvswitch_device *device, nvlink_link *link, NVSWITCH_MINION_ALI_DEBUG_REGISTERS *params); void nvswitch_setup_link_system_registers_ls10(nvswitch_device *device, nvlink_link *link); void nvswitch_load_link_disable_settings_ls10(nvswitch_device *device, nvlink_link *link); +void nvswitch_link_disable_interrupts_ls10(nvswitch_device *device, NvU32 link); void nvswitch_execute_unilateral_link_shutdown_ls10(nvlink_link *link); void nvswitch_init_dlpl_interrupts_ls10(nvlink_link *link); NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 link_mask); void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); +NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p); // // SU generated functions @@ -988,6 +991,8 @@ NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 lin void nvswitch_service_minion_all_links_ls10(nvswitch_device *device); NvBool nvswitch_is_inforom_supported_ls10(nvswitch_device *device); +void nvswitch_set_error_rate_threshold_ls10(nvlink_link *link, NvBool bIsDefault); +void nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink_link *link, NvBool bEnable); #endif //_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h index 53568b7f0..d01843642 100644 --- a/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h +++ b/src/common/nvswitch/kernel/inc/ls10/soe_ls10.h @@ -42,5 +42,6 @@ void nvswitch_soe_unregister_events_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_register_event_callbacks_ls10(nvswitch_device *device); NvlStatus nvswitch_soe_restore_nport_state_ls10(nvswitch_device *device, NvU32 nport); NvlStatus nvswitch_soe_issue_nport_reset_ls10(nvswitch_device *device, NvU32 nport); +void nvswitch_soe_init_l2_state_ls10(nvswitch_device *device); #endif //_SOE_LS10_H_ diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h index 80a2ddf72..50a4e56b8 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h @@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, - 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, - 0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, + 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, + 0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h index 41eac9e01..421771fb4 100644 --- a/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h +++ b/src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h @@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9, 0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd, 0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f, - 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0, - 0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, + 0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0, + 0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc, 0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d, 0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01, 0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206, @@ -569,7 +569,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x328908f4, 0xfbfa324f, 0xbf02f971, 0xbcb0b2b9, 0xb9a6b0c9, 0xe41708f4, 0xbcffffd9, 0xfba6f09b, 0x980b08f4, 0xf9a60109, 0xf8050df4, 0xb2dc7202, 0x28d77eed, 0xb201fb00, 0x05ab98b9, 0xdeb2cfb2, 0xfd729cb2, 0x0042a97e, 0xf0fc00f8, 0xf9fc30f4, 0xbf62f9f0, 0x08e1b0b9, 0xd4b2a5b2, 0xa630c9bc, - 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x010124bd, 0x763efc06, 0x02f80043, + 0x1d08f439, 0xa6f0d3bc, 0x1508f4f3, 0xa601b998, 0x0d0cf4f9, 0x24bd0101, 0x763efc06, 0x02f80043, 0x853e0101, 0x42bc0043, 0x0096b192, 0x060df401, 0x90010049, 0x96ff0399, 0x0b947e04, 0xb23bb200, 0xdd0c725a, 0x00001200, 0x7e3030bc, 0x320028d7, 0x00a433a1, 0x08b0b434, 0xb209c0b4, 0x1200da2d, 0x20bc0000, 0x01004e20, 0x0021367e, 0x0a00a033, 0x853e02f8, 0x00da0043, 0xbd000012, 0x01004cb4, @@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0xa1f0af45, 0xc2521354, 0x427cca67, 0x3b102336, - 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcdd28e1e, 0x6000ae0f, 0x492dfb26, 0x422cf074, + 0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x62f5c2c4, 0xc41c2f31, 0x9af0cbcc, 0xb7efe098, + 0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0x5f24a73a, 0x55cea6d1, 0x59205a69, 0x18a31f2d, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/src/common/nvswitch/kernel/inforom/ifrro_nvswitch.c b/src/common/nvswitch/kernel/inforom/ifrro_nvswitch.c index 636a364e3..ed67c705b 100644 --- a/src/common/nvswitch/kernel/inforom/ifrro_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/ifrro_nvswitch.c @@ -38,10 +38,7 @@ nvswitch_inforom_read_only_objects_load return -NVL_ERR_NOT_SUPPORTED; } - status = nvswitch_inforom_load_object(device, pInforom, "OBD", - INFOROM_OBD_OBJECT_V1_XX_FMT, - pInforom->OBD.packedObject, - &pInforom->OBD.object); + status = device->hal.nvswitch_inforom_load_obd(device); if (status != NVL_SUCCESS) { NVSWITCH_PRINT(device, ERROR, "Failed to load OBD object, rc:%d\n", diff --git a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c index 89b666efa..a144a7516 100644 --- a/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c +++ b/src/common/nvswitch/kernel/inforom/inforom_nvswitch.c @@ -493,7 +493,7 @@ _nvswitch_inforom_read_file nvswitch_os_memset(pDmaBuf, 0, transferSize); cmdSeqDesc = 0; - nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL, SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout); if (status != NV_OK) @@ -591,7 +591,8 @@ _nvswitch_inforom_write_file } cmdSeqDesc = 0; - nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + + nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout); status = flcnQueueCmdPostBlocking(device, pFlcn, (PRM_FLCN_CMD)&soeCmd, NULL, NULL, SOE_RM_CMDQ_LOG_ID, &cmdSeqDesc, &timeout); if (status != NV_OK) @@ -899,6 +900,7 @@ done: /*! * Fill in the static identification data structure for the use by the SOE * to be passed on to a BMC over the I2CS interface. + * For LR10 only so no HAL is needed. * * @param[in] device switch device pointer * @param[in] pInforom INFOROM object pointer @@ -916,13 +918,13 @@ nvswitch_inforom_read_static_data #define _INFOROM_TO_SOE_STRING_COPY(obj, irName, soeName) \ { \ NvU32 _i; \ - ct_assert(NV_ARRAY_ELEMENTS(pInforom->obj.object.irName) <= \ + ct_assert(NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName) <= \ NV_ARRAY_ELEMENTS(pData->obj.soeName)); \ - for (_i = 0; _i < NV_ARRAY_ELEMENTS(pInforom->obj.object.irName); ++_i) \ + for (_i = 0; _i < NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName); ++_i) \ { \ - pData->obj.soeName[_i] = (NvU8)(pInforom->obj.object.irName[_i] & 0xff); \ + pData->obj.soeName[_i] = (NvU8)(pInforom->obj.object.v1.irName[_i] & 0xff); \ } \ - if (NV_ARRAY_ELEMENTS(pInforom->obj.object.irName) < \ + if (NV_ARRAY_ELEMENTS(pInforom->obj.object.v1.irName) < \ NV_ARRAY_ELEMENTS(pData->obj.soeName)) \ { \ do \ @@ -935,21 +937,25 @@ nvswitch_inforom_read_static_data if (pInforom->OBD.bValid) { - pData->OBD.bValid = NV_TRUE; - pData->OBD.buildDate = (NvU32)pInforom->OBD.object.buildDate; - nvswitch_inforom_string_copy(pInforom->OBD.object.marketingName, - pData->OBD.marketingName, - NV_ARRAY_ELEMENTS(pData->OBD.marketingName)); + /* This should be called for LR10 (i.e., version 1.xx) only */ + if ((pInforom->OBD.object.header.version & 0xFF) == 1) + { + pData->OBD.bValid = NV_TRUE; + pData->OBD.buildDate = (NvU32)pInforom->OBD.object.v1.buildDate; + nvswitch_inforom_string_copy(pInforom->OBD.object.v1.marketingName, + pData->OBD.marketingName, + NV_ARRAY_ELEMENTS(pData->OBD.marketingName)); - nvswitch_inforom_string_copy(pInforom->OBD.object.serialNumber, - pData->OBD.serialNum, - NV_ARRAY_ELEMENTS(pData->OBD.serialNum)); + nvswitch_inforom_string_copy(pInforom->OBD.object.v1.serialNumber, + pData->OBD.serialNum, + NV_ARRAY_ELEMENTS(pData->OBD.serialNum)); - // - // boardPartNum requires special handling, as its size exceeds that - // of its InfoROM representation - // - _INFOROM_TO_SOE_STRING_COPY(OBD, productPartNumber, boardPartNum); + // + // boardPartNum requires special handling, as its size exceeds that + // of its InfoROM representation + // + _INFOROM_TO_SOE_STRING_COPY(OBD, productPartNumber, boardPartNum); + } } if (pInforom->OEM.bValid) diff --git a/src/common/nvswitch/kernel/lr10/inforom_lr10.c b/src/common/nvswitch/kernel/lr10/inforom_lr10.c index 8cbd25be7..d19c12e44 100644 --- a/src/common/nvswitch/kernel/lr10/inforom_lr10.c +++ b/src/common/nvswitch/kernel/lr10/inforom_lr10.c @@ -747,6 +747,25 @@ nvswitch_oms_set_device_disable_lr10 _oms_update_entry_checksum(pVerData->pNext); } +NvlStatus +nvswitch_inforom_load_obd_lr10 +( + nvswitch_device *device +) +{ + struct inforom *pInforom = device->pInforom; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return nvswitch_inforom_load_object(device, pInforom, "OBD", + INFOROM_OBD_OBJECT_V1_XX_FMT, + pInforom->OBD.packedObject.v1, + &pInforom->OBD.object.v1); +} + NvlStatus nvswitch_bbx_add_sxid_lr10 ( diff --git a/src/common/nvswitch/kernel/lr10/link_lr10.c b/src/common/nvswitch/kernel/lr10/link_lr10.c index f7c505a37..a9b0fb950 100644 --- a/src/common/nvswitch/kernel/lr10/link_lr10.c +++ b/src/common/nvswitch/kernel/lr10/link_lr10.c @@ -872,7 +872,7 @@ nvswitch_corelib_set_dl_link_mode_lr10 NVSWITCH_PRINT(device, ERROR, "%s: link #%d is still in reset, cannot change link state\n", __FUNCTION__, link->linkNumber); - return NVL_ERR_INVALID_STATE; + return -NVL_ERR_INVALID_STATE; } val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLDL, _NVLDL_TOP, _LINK_STATE); diff --git a/src/common/nvswitch/kernel/lr10/lr10.c b/src/common/nvswitch/kernel/lr10/lr10.c index 6d8ede7b5..0dc9ae9c9 100644 --- a/src/common/nvswitch/kernel/lr10/lr10.c +++ b/src/common/nvswitch/kernel/lr10/lr10.c @@ -6403,8 +6403,22 @@ nvswitch_ctrl_get_fom_values_lr10 { NvlStatus status; NvU32 statData; + nvlink_link *link; - NVSWITCH_ASSERT(p->linkId < nvswitch_get_num_links(device)); + link = nvswitch_get_link(device, p->linkId); + if (link == NULL) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d invalid\n", + __FUNCTION__, p->linkId); + return -NVL_BAD_ARGS; + } + + if (nvswitch_is_link_in_reset(device, link)) + { + NVSWITCH_PRINT(device, ERROR, "%s: link #%d is in reset\n", + __FUNCTION__, p->linkId); + return -NVL_ERR_INVALID_STATE; + } status = nvswitch_minion_get_dl_status(device, p->linkId, NV_NVLSTAT_TR16, 0, &statData); @@ -6791,6 +6805,8 @@ nvswitch_post_init_device_setup_lr10 NVSWITCH_PRINT(device, SETUP, "Skipping INFOROM init\n"); } + nvswitch_soe_init_l2_state(device); + return NVL_SUCCESS; } @@ -7373,6 +7389,52 @@ nvswitch_ctrl_inband_read_data_lr10 return -NVL_ERR_NOT_SUPPORTED; } +/* + * CTRL_NVSWITCH_GET_BOARD_PART_NUMBER + */ +NvlStatus +nvswitch_ctrl_get_board_part_number_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p +) +{ + struct inforom *pInforom = device->pInforom; + INFOROM_OBD_OBJECT_V1_XX *pOBDObj; + int byteIdx; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!pInforom->OBD.bValid) + { + NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n"); + return -NVL_ERR_GENERIC; + } + + pOBDObj = &pInforom->OBD.object.v1; + + if (sizeof(p->data) != sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008)) + { + NVSWITCH_PRINT(device, ERROR, + "board part number available size %lu is not same as the request size %lu\n", + sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008), sizeof(p->data)); + return -NVL_ERR_GENERIC; + } + + nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR)); + + /* Copy board type data */ + for (byteIdx = 0; byteIdx < NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES; byteIdx++) + { + p->data[byteIdx] =(NvU8)(pOBDObj->productPartNumber[byteIdx] & 0xFF); + } + + return NVL_SUCCESS; +} + /* * @brief: This function retrieves the NVLIPT public ID for a given global link idx * @params[in] device reference to current nvswitch device @@ -7765,6 +7827,26 @@ nvswitch_ctrl_clear_counters_lr10 return status; } +NvlStatus +nvswitch_ctrl_set_nvlink_error_threshold_lr10 +( + nvswitch_device *device, + NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *ret +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + +static NvlStatus +nvswitch_ctrl_get_nvlink_error_threshold_lr10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *ret +) +{ + return -NVL_ERR_NOT_SUPPORTED; +} + // // This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL // macro in haldef_nvswitch.h diff --git a/src/common/nvswitch/kernel/lr10/soe_lr10.c b/src/common/nvswitch/kernel/lr10/soe_lr10.c index 72b528ba2..70d21eeb7 100644 --- a/src/common/nvswitch/kernel/lr10/soe_lr10.c +++ b/src/common/nvswitch/kernel/lr10/soe_lr10.c @@ -872,6 +872,17 @@ nvswitch_init_soe_lr10 return status; } +void +nvswitch_soe_init_l2_state_lr10 +( + nvswitch_device *device +) +{ + NVSWITCH_PRINT(device, WARN, + "%s: Function not implemented on lr10\n", + __FUNCTION__); +} + /** * @brief SOE construct * diff --git a/src/common/nvswitch/kernel/ls10/discovery_ls10.c b/src/common/nvswitch/kernel/ls10/discovery_ls10.c index 82b9493c8..a84bb873b 100644 --- a/src/common/nvswitch/kernel/ls10/discovery_ls10.c +++ b/src/common/nvswitch/kernel/ls10/discovery_ls10.c @@ -1316,6 +1316,30 @@ nvswitch_process_discovery_ls10 NVSWITCH_ENG_VALID_LS10(device, NVLIPT, NVSWITCH_GET_LINK_ENG_INST(device, i, NVLIPT)); } + // + // Process common engine information + // + + // Mark all entries as invalid + for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++) + { + chip_device->io.common[i].eng_name = ""; + chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range + chip_device->io.common[i].eng_count = 0; + for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++) + { + chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; + } + chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID; + for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++) + { + chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; + } + chip_device->io.common[i].mc_addr_count = 0; + } + + NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON) + // // Disable engines requested by regkey "LinkEnableMask". // All the links are enabled by default. @@ -1330,6 +1354,7 @@ nvswitch_process_discovery_ls10 NVSWITCH_PRINT(device, SETUP, "%s: Disable link #%d\n", __FUNCTION__, i); + nvswitch_link_disable_interrupts_ls10(device, i); device->link[i].valid = NV_FALSE; chip_device->engNPORT[i].valid = NV_FALSE; chip_device->engNPORT_PERFMON[i].valid = NV_FALSE; @@ -1362,30 +1387,6 @@ nvswitch_process_discovery_ls10 } } - // - // Process common engine information - // - - // Mark all entries as invalid - for (i = 0; i < NVSWITCH_ENGINE_ID_SIZE; i++) - { - chip_device->io.common[i].eng_name = ""; - chip_device->io.common[i].eng_id = NVSWITCH_ENGINE_ID_SIZE; // Out of range - chip_device->io.common[i].eng_count = 0; - for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_UC_SIZE; j++) - { - chip_device->io.common[i].uc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; - } - chip_device->io.common[i].bc_addr = NVSWITCH_BASE_ADDR_INVALID; - for (j = 0; j < NVSWITCH_ENGINE_DESCRIPTOR_MC_SIZE; j++) - { - chip_device->io.common[i].mc_addr[j] = NVSWITCH_BASE_ADDR_INVALID; - } - chip_device->io.common[i].mc_addr_count = 0; - } - - NVSWITCH_LIST_LS10_ENGINES(NVSWITCH_PROCESS_COMMON) - return retval; } diff --git a/src/common/nvswitch/kernel/ls10/flcn_ls10.c b/src/common/nvswitch/kernel/ls10/flcn_ls10.c index c9e6269ff..5b18bacc3 100644 --- a/src/common/nvswitch/kernel/ls10/flcn_ls10.c +++ b/src/common/nvswitch/kernel/ls10/flcn_ls10.c @@ -277,8 +277,8 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10 PFLCN pFlcn ) { - NvU32 ctl, ridx, widx, count, bufferSize; - NvBool full; + NvU32 ctl, ridx, widx, bufferSize; + NvBool bWasFull; // Only supported on riscv if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn)) @@ -290,23 +290,22 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10 return; } - flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, - DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) | - DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) | - DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MMODE_ENABLE, _TRUE) | - DRF_DEF(_PRISCV_RISCV, _TRACECTL, _INTR_ENABLE, _FALSE) | - DRF_DEF(_PRISCV_RISCV, _TRACECTL, _HIGH_THSHD, _INIT)); - ctl = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL); + if (ctl == 0) + { + NVSWITCH_PRINT(device, ERROR, "Trace buffer is disabled.\n"); + return; + } - full = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl); - if (full) + bWasFull = FLD_TEST_DRF_NUM(_PRISCV_RISCV, _TRACECTL,_FULL, 1, ctl); + + if (bWasFull) { NVSWITCH_PRINT(device, INFO, "%s: Trace buffer full. Entries may have been lost.\n", __FUNCTION__); } - // Reset and disable buffer, we don't need it during dump + // Reset and disable buffer, we don't need it during dump (and if core is running) flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, 0); widx = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_WTIDX); @@ -316,35 +315,48 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10 bufferSize = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _MAXIDX, ridx); ridx = DRF_VAL(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx); - count = widx > ridx ? widx - ridx : bufferSize + widx - ridx; - - // - // Trace buffer is full when write idx == read idx and full is set, - // otherwise it is empty. - // - if (widx == ridx && !full) - count = 0; - - if (count) + if (bufferSize > 0) { NvU32 entry; - NVSWITCH_PRINT(device, INFO, "%s: Tracebuffer has %d entries. Starting with latest.\n", __FUNCTION__, count); + + switch (DRF_VAL(_PRISCV_RISCV, _TRACECTL, _MODE, ctl)) + { + case NV_PRISCV_RISCV_TRACECTL_MODE_FULL: + NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in full mode.\n"); + break; + case NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED: + NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in reduced mode.\n"); + break; + case NV_PRISCV_RISCV_TRACECTL_MODE_STACK: + NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in stack mode.\n"); + break; + default: + NVSWITCH_PRINT(device, ERROR, "Tracebuffer is in unknown mode.\n"); + } + + NVSWITCH_PRINT(device, ERROR, "Entries (most recent first):\n"); + ridx = widx; - for (entry = 0; entry < count; ++entry) + for (entry = 0; entry < bufferSize; entry++) { NvU64 pc; ridx = ridx > 0 ? ridx - 1 : bufferSize - 1; - flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx)); + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, + DRF_NUM(_PRISCV_RISCV, _TRACE_RDIDX, _RDIDX, ridx)); + pc = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_HI); pc = (pc << 32) | flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACEPC_LO); - NVSWITCH_PRINT(device, INFO, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc); + + // Non-mod2 values are invalid here, so stop (this likely indicates an init-marker val) + if (NvU64_LO32(pc) % 2U != 0U) + { + break; + } + + NVSWITCH_PRINT(device, ERROR, "%s: TRACE[%d] = 0x%16llx\n", __FUNCTION__, entry, pc); } } - else - { - NVSWITCH_PRINT(device, INFO, "%s: Trace buffer is empty.\n", __FUNCTION__); - } // reset trace buffer flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACE_RDIDX, 0); diff --git a/src/common/nvswitch/kernel/ls10/inforom_ls10.c b/src/common/nvswitch/kernel/ls10/inforom_ls10.c index 81a5d5120..b23bde0c3 100644 --- a/src/common/nvswitch/kernel/ls10/inforom_ls10.c +++ b/src/common/nvswitch/kernel/ls10/inforom_ls10.c @@ -108,6 +108,25 @@ nvswitch_inforom_ecc_get_total_errors_ls10 return; } +NvlStatus +nvswitch_inforom_load_obd_ls10 +( + nvswitch_device *device +) +{ + struct inforom *pInforom = device->pInforom; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + return nvswitch_inforom_load_object(device, pInforom, "OBD", + INFOROM_OBD_OBJECT_V2_XX_FMT, + pInforom->OBD.packedObject.v2, + &pInforom->OBD.object.v2); +} + NvlStatus nvswitch_bbx_add_sxid_ls10 ( @@ -178,7 +197,7 @@ nvswitch_bbx_unload_ls10 NVSWITCH_TIMEOUT timeout; pFlcn = device->pSoe->pFlcn; - nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout); nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; @@ -217,7 +236,7 @@ nvswitch_bbx_load_ls10 NVSWITCH_TIMEOUT timeout; pFlcn = device->pSoe->pFlcn; - nvswitch_timeout_create(NVSWITCH_INTERVAL_750MSEC_IN_NS, &timeout); + nvswitch_timeout_create(NVSWITCH_INTERVAL_4SEC_IN_NS, &timeout); nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd)); bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR; @@ -254,4 +273,3 @@ nvswitch_bbx_get_sxid_ls10 { return -NVL_ERR_NOT_SUPPORTED; } - diff --git a/src/common/nvswitch/kernel/ls10/intr_ls10.c b/src/common/nvswitch/kernel/ls10/intr_ls10.c index de76ed7d0..13c9c1c80 100644 --- a/src/common/nvswitch/kernel/ls10/intr_ls10.c +++ b/src/common/nvswitch/kernel/ls10/intr_ls10.c @@ -455,6 +455,8 @@ _nvswitch_initialize_nport_interrupts_ls10 nvswitch_device *device ) { +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NvU32 val; val = @@ -462,6 +464,7 @@ _nvswitch_initialize_nport_interrupts_ls10 DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _FATALENABLE, 1) | DRF_NUM(_NPORT, _ERR_CONTROL_COMMON_NPORT, _NONFATALENABLE, 1); NVSWITCH_NPORT_BCAST_WR32_LS10(device, _NPORT, _ERR_CONTROL_COMMON_NPORT, val); +#endif // 0 _nvswitch_initialize_route_interrupts(device); _nvswitch_initialize_ingress_interrupts(device); @@ -494,7 +497,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10 DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, 1) | DRF_NUM(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, 1); +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILE, _ERR_FATAL_INTR_EN, report_fatal); +#endif // 0 chip_device->intr_mask.tile.fatal = report_fatal; chip_device->intr_mask.tile.nonfatal = 0; @@ -509,7 +515,10 @@ _nvswitch_initialize_nxbar_interrupts_ls10 DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, 1) | DRF_NUM(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _EGRESS_CDT_PARITY_ERROR, 1); +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_BCAST_WR32_LS10(device, NXBAR, _NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, report_fatal); +#endif // 0 chip_device->intr_mask.tileout.fatal = report_fatal; chip_device->intr_mask.tileout.nonfatal = 0; @@ -5341,6 +5350,10 @@ _nvswitch_emit_link_errors_nvldl_nonfatal_link_ls10 bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_SHORT_ERROR_RATE, 1); if (nvswitch_test_flags(pending, bit)) { + // Disable further interrupts + nvlink_link *nvlink = nvswitch_get_link(device, link); + nvlink->errorThreshold.bInterruptTrigerred = NV_TRUE; + nvswitch_configure_error_rate_threshold_interrupt_ls10(nvlink, NV_FALSE); NVSWITCH_REPORT_NONFATAL(_HW_DLPL_RX_SHORT_ERROR_RATE, "RX Short Error Rate"); } } @@ -6295,18 +6308,24 @@ _nvswitch_service_nvlipt_link_nonfatal_ls10 NvU32 interruptingLinks = 0; NvU32 lnkStatusChangeLinks = 0; NvlStatus status; - + NvU64 link_enable_mask; + + link_enable_mask = ((NvU64)device->regkeys.link_enable_mask2 << 32 | + (NvU64)device->regkeys.link_enable_mask); for (i = 0; i < NVSWITCH_LINKS_PER_NVLIPT_LS10; ++i) { globalLink = (instance * NVSWITCH_LINKS_PER_NVLIPT_LS10) + i; - + if ((NVBIT64(globalLink) & link_enable_mask) == 0) + { + continue; + } intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0); if(intrLink) { interruptingLinks |= NVBIT(i); } - + intrLink = NVSWITCH_LINK_RD32(device, globalLink, NVLIPT_LNK, _NVLIPT_LNK, _INTR_STATUS); if(intrLink) diff --git a/src/common/nvswitch/kernel/ls10/link_ls10.c b/src/common/nvswitch/kernel/ls10/link_ls10.c index c9610b5d1..59f9c544d 100644 --- a/src/common/nvswitch/kernel/ls10/link_ls10.c +++ b/src/common/nvswitch/kernel/ls10/link_ls10.c @@ -1070,17 +1070,16 @@ nvswitch_store_topology_information_ls10 } void -nvswitch_init_dlpl_interrupts_ls10 +nvswitch_set_error_rate_threshold_ls10 ( - nvlink_link *link + nvlink_link *link, + NvBool bSetDefault ) { - nvswitch_device *device = link->dev->pDevInfo; - NvU32 linkNumber = link->linkNumber; - NvU32 intrRegVal; - NvU32 crcRegVal; - NvU32 shortRateMask; - NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short; + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + NvU32 crcShortRegkeyVal = device->regkeys.crc_bit_error_rate_short; + NvU32 crcRegVal; ct_assert(DRF_BASE(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) == DRF_BASE(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN)); @@ -1099,6 +1098,124 @@ nvswitch_init_dlpl_interrupts_ls10 ct_assert(DRF_EXTENT(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP) == DRF_EXTENT(NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP)); + crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL); + + // + // Case 1: When a Regkey is provided. We use it to calculate crcRegVal. + // + // Case 2: When the bSetDefault variable is set to NV_FALSE. This can happen + // when any client/application like NSCQ would provide specific values for + // the error threshold. In this case we use those values to calculate crcRegVal. + // + // Case 3: In all other cases, we want the default values to be used, which are + // provided in Bug 3365481. + // + if(crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT) + { + NvU32 shortRateMask; + shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) | + DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP); + + crcRegVal &= ~shortRateMask; + crcRegVal |= crcShortRegkeyVal; + + + link->errorThreshold.bUserConfig = NV_FALSE; + link->errorThreshold.bInterruptTrigerred = NV_FALSE; + } + else if (!bSetDefault) + { + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN, + link->errorThreshold.thresholdMan, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP, + link->errorThreshold.thresholdExp, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN, + link->errorThreshold.timescaleMan, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP, + link->errorThreshold.timescaleExp, + crcRegVal); + } + else + { + // + // Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT + // default values used below. + // + link->errorThreshold.thresholdMan = + NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN_DEFAULT; + link->errorThreshold.thresholdExp = + NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP_DEFAULT; + link->errorThreshold.timescaleMan = + NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN_DEFAULT; + link->errorThreshold.timescaleExp = + NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP_DEFAULT; + link->errorThreshold.bUserConfig = NV_FALSE; + link->errorThreshold.bInterruptTrigerred = NV_FALSE; + + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN, + link->errorThreshold.thresholdMan, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP, + link->errorThreshold.thresholdExp, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN, + link->errorThreshold.timescaleMan, + crcRegVal); + crcRegVal = FLD_SET_DRF_NUM(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP, + link->errorThreshold.timescaleExp, + crcRegVal); + } + + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, + _NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal); +} + +void +nvswitch_configure_error_rate_threshold_interrupt_ls10 +( + nvlink_link *link, + NvBool bEnable +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + NvU32 intrRegVal; + link->errorThreshold.bInterruptEn = bEnable; + + intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, + _NVLDL_TOP, _INTR_NONSTALL_EN); + + if (bEnable) + { + link->errorThreshold.bInterruptTrigerred = NV_FALSE; + intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1, + intrRegVal); + } + else + { + intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0, + intrRegVal); + } + + NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, + _NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal); +} + +void +nvswitch_init_dlpl_interrupts_ls10 +( + nvlink_link *link +) +{ + nvswitch_device *device = link->dev->pDevInfo; + NvU32 linkNumber = link->linkNumber; + // W1C any stale state. NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR, 0xffffffff); NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, _NVLDL_TOP, _INTR_SW2, 0xffffffff); @@ -1136,44 +1253,8 @@ nvswitch_init_dlpl_interrupts_ls10 DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _LTSSM_PROTOCOL, _DISABLE) | DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _MINION_REQUEST, _DISABLE)); - intrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, - _NVLDL_TOP, _INTR_NONSTALL_EN); - crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL, - _NVLDL_RX, _ERROR_RATE_CTRL); - - // - // Enable RX error rate short interrupt. - // Please refer to Bug 3365481 for details about the CRC_BIT_ERROR_RATE_SHORT - // values used below. - // - - // Enable RX error rate short interrupt if the regkey is set - if (crcShortRegkeyVal != NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_DEFAULT) - { - shortRateMask = DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | - DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | - DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) | - DRF_SHIFTMASK(NV_SWITCH_REGKEY_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP); - - intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); - crcRegVal &= ~shortRateMask; - crcRegVal |= crcShortRegkeyVal; - } - else - { - shortRateMask = DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_MAN) | - DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_THRESHOLD_EXP) | - DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_MAN) | - DRF_SHIFTMASK(NV_NVLDL_CRC_BIT_ERROR_RATE_SHORT_TIMESCALE_EXP); - - intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE); - crcRegVal &= ~shortRateMask; - } - - NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, - _NVLDL_TOP, _INTR_NONSTALL_EN, intrRegVal); - NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL, - _NVLDL_RX, _ERROR_RATE_CTRL, crcRegVal); + nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE); + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE); } static NvU32 @@ -1318,12 +1399,12 @@ nvswitch_execute_unilateral_link_shutdown_ls10 ) { nvswitch_device *device = link->dev->pDevInfo; - NvlStatus status = NVL_SUCCESS; + NvlStatus status = NVL_SUCCESS; NvU32 retry_count = 3; NvU32 link_state_request; NvU32 link_state; - NvU32 stat_data; - NvU32 link_intr_subcode; + NvU32 stat_data = 0; + NvU32 link_intr_subcode = 0; if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber)) { diff --git a/src/common/nvswitch/kernel/ls10/ls10.c b/src/common/nvswitch/kernel/ls10/ls10.c index 9815a1665..8a33730eb 100644 --- a/src/common/nvswitch/kernel/ls10/ls10.c +++ b/src/common/nvswitch/kernel/ls10/ls10.c @@ -65,7 +65,7 @@ #include "ls10/minion_nvlink_defines_public_ls10.h" #define NVSWITCH_IFR_MIN_BIOS_VER_LS10 0x9610170000ull -#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610170000ull +#define NVSWITCH_SMBPBI_MIN_BIOS_VER_LS10 0x9610220000ull void * nvswitch_alloc_chipdevice_ls10 @@ -1091,8 +1091,8 @@ _nvswitch_portstat_reset_latency_counters_ls10 /* * Disable interrupts comming from NPG & NVLW blocks. */ -static void -_nvswitch_link_disable_interrupts_ls10 +void +nvswitch_link_disable_interrupts_ls10 ( nvswitch_device *device, NvU32 link @@ -1434,7 +1434,7 @@ nvswitch_reset_and_drain_links_ls10 // // Step 2.0 : Disable NPG & NVLW interrupts // - _nvswitch_link_disable_interrupts_ls10(device, link); + nvswitch_link_disable_interrupts_ls10(device, link); // // Step 3.0 : @@ -1575,6 +1575,7 @@ nvswitch_set_nport_port_config_ls10 ) { NvU32 val; + NvlStatus status = NVL_SUCCESS; if (p->requesterLinkID >= NVBIT( DRF_SIZE(NV_NPORT_REQLINKID_REQROUTINGID) + @@ -1624,7 +1625,7 @@ nvswitch_set_nport_port_config_ls10 if (p->type == CONNECT_TRUNK_SWITCH) { - if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device)) + if (!nvswitch_is_soe_supported(device)) { // Set trunk specific settings (TPROD) on PRE-SILION @@ -1773,7 +1774,13 @@ nvswitch_set_nport_port_config_ls10 else { // Set trunk specific settings (TPROD) in SOE - // nvswitch_set_nport_tprod_state_ls10(device, p->portNum); + status = nvswitch_set_nport_tprod_state_ls10(device, p->portNum); + if (status != NVL_SUCCESS) + { + NVSWITCH_PRINT(device, ERROR, + "%s: Failed to set NPORT TPROD state\n", + __FUNCTION__); + } } } else @@ -1784,7 +1791,7 @@ nvswitch_set_nport_port_config_ls10 NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE0, NvU64_LO32(p->trunkSrcMask)); NVSWITCH_LINK_WR32(device, p->portNum, NPORT, _NPORT, _SRC_PORT_TYPE1, NvU64_HI32(p->trunkSrcMask)); - return NVL_SUCCESS; + return status; } /* @@ -4216,6 +4223,8 @@ _nvswitch_init_nport_ecc_control_ls10 nvswitch_device *device ) { +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 // Set ingress ECC error limits NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, DRF_NUM(_INGRESS, _ERR_NCISOC_HDR_ECC_ERROR_COUNTER, _ERROR_COUNT, 0x0)); @@ -4274,6 +4283,7 @@ _nvswitch_init_nport_ecc_control_ls10 NVSWITCH_ENG_WR32(device, NPORT, _BCAST, 0, _SOURCETRACK, _ERR_ECC_CTRL, DRF_DEF(_SOURCETRACK, _ERR_ECC_CTRL, _CREQ_TCEN0_CRUMBSTORE_ECC_ENABLE, __PROD)); +#endif // 0 } NvlStatus @@ -4306,6 +4316,8 @@ nvswitch_init_nport_ls10 _nvswitch_init_nport_ecc_control_ls10(device); +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 if (DRF_VAL(_SWITCH_REGKEY, _ATO_CONTROL, _DISABLE, device->regkeys.ato_control) == NV_SWITCH_REGKEY_ATO_CONTROL_DISABLE_TRUE) { @@ -4329,7 +4341,7 @@ nvswitch_init_nport_ls10 DRF_NUM(_TSTATE, _ATO_TIMER_LIMIT, _LIMIT, timeout)); } } - +#endif // 0 if (DRF_VAL(_SWITCH_REGKEY, _STO_CONTROL, _DISABLE, device->regkeys.sto_control) == NV_SWITCH_REGKEY_STO_CONTROL_DISABLE_TRUE) { @@ -4366,17 +4378,7 @@ nvswitch_init_nxbar_ls10 nvswitch_device *device ) { - NvlStatus status = NVL_SUCCESS; - - status = nvswitch_apply_prod_nxbar_ls10(device); - if (status != NVL_SUCCESS) - { - NVSWITCH_PRINT(device, ERROR, - "%s: NXBAR PRODs failed\n", - __FUNCTION__); - return status; - } - + NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__); return NVL_SUCCESS; } @@ -5314,6 +5316,52 @@ nvswitch_ctrl_inband_read_data_ls10 return nvswitch_inband_read_data(device, p->buffer, p->linkId, &p->dataSize); } +/* + * CTRL_NVSWITCH_GET_BOARD_PART_NUMBER + */ +NvlStatus +nvswitch_ctrl_get_board_part_number_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p +) +{ + struct inforom *pInforom = device->pInforom; + INFOROM_OBD_OBJECT_V2_XX *pOBDObj; + int byteIdx; + + if (pInforom == NULL) + { + return -NVL_ERR_NOT_SUPPORTED; + } + + if (!pInforom->OBD.bValid) + { + NVSWITCH_PRINT(device, ERROR, "OBD data is not available\n"); + return -NVL_ERR_GENERIC; + } + + pOBDObj = &pInforom->OBD.object.v2; + + if (sizeof(p->data) != sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008)) + { + NVSWITCH_PRINT(device, ERROR, + "board part number available size %lu is not same as the request size %lu\n", + sizeof(pOBDObj->productPartNumber)/sizeof(inforom_U008), sizeof(p->data)); + return -NVL_ERR_GENERIC; + } + + nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR)); + + /* Copy board type data */ + for (byteIdx = 0; byteIdx < NVSWITCH_BOARD_PART_NUMBER_SIZE_IN_BYTES; byteIdx++) + { + p->data[byteIdx] =(NvU8)(pOBDObj->productPartNumber[byteIdx] & 0xFF); + } + + return NVL_SUCCESS; +} + NvlStatus nvswitch_ctrl_get_nvlink_lp_counters_ls10 ( @@ -5466,6 +5514,103 @@ nvswitch_ctrl_clear_counters_ls10 return status; } +NvlStatus +nvswitch_ctrl_set_nvlink_error_threshold_ls10 +( + nvswitch_device *device, + NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams +) +{ + nvlink_link *link; + NvU8 i; + + FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + continue; + } + + if (pParams->errorThreshold[link->linkNumber].flags & NVSWITCH_NVLINK_ERROR_THRESHOLD_RESET) + { + link->errorThreshold.bUserConfig = NV_FALSE; + + // Disable the interrupt + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE); + + // Set to default value + nvswitch_set_error_rate_threshold_ls10(link, NV_TRUE); + + // Enable the interrupt + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_TRUE); + } + else + { + link->errorThreshold.thresholdMan = + pParams->errorThreshold[link->linkNumber].thresholdMan; + link->errorThreshold.thresholdExp = + pParams->errorThreshold[link->linkNumber].thresholdExp; + link->errorThreshold.timescaleMan = + pParams->errorThreshold[link->linkNumber].timescaleMan; + link->errorThreshold.timescaleExp = + pParams->errorThreshold[link->linkNumber].timescaleExp; + link->errorThreshold.bInterruptEn = + pParams->errorThreshold[link->linkNumber].bInterruptEn; + link->errorThreshold.bUserConfig = NV_TRUE; + + // Disable the interrupt + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, NV_FALSE); + + // Set the Error threshold + nvswitch_set_error_rate_threshold_ls10(link, NV_FALSE); + + // Configure the interrupt + nvswitch_configure_error_rate_threshold_interrupt_ls10(link, + link->errorThreshold.bInterruptEn); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + +NvlStatus +nvswitch_ctrl_get_nvlink_error_threshold_ls10 +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams +) +{ + nvlink_link *link; + NvU8 i; + + FOR_EACH_INDEX_IN_MASK(64, i, pParams->link_mask) + { + link = nvswitch_get_link(device, i); + if (link == NULL) + { + continue; + } + + pParams->errorThreshold[link->linkNumber].thresholdMan = + link->errorThreshold.thresholdMan; + pParams->errorThreshold[link->linkNumber].thresholdExp = + link->errorThreshold.thresholdExp; + pParams->errorThreshold[link->linkNumber].timescaleMan = + link->errorThreshold.timescaleMan; + pParams->errorThreshold[link->linkNumber].timescaleExp = + link->errorThreshold.timescaleExp; + pParams->errorThreshold[link->linkNumber].bInterruptEn = + link->errorThreshold.bInterruptEn; + pParams->errorThreshold[link->linkNumber].bInterruptTrigerred = + link->errorThreshold.bInterruptTrigerred; + } + FOR_EACH_INDEX_IN_MASK_END; + + return NVL_SUCCESS; +} + NvlStatus nvswitch_read_vbios_link_entries_ls10 ( diff --git a/src/common/nvswitch/kernel/ls10/soe_ls10.c b/src/common/nvswitch/kernel/ls10/soe_ls10.c index 44a45f1be..8ab6b5f3e 100644 --- a/src/common/nvswitch/kernel/ls10/soe_ls10.c +++ b/src/common/nvswitch/kernel/ls10/soe_ls10.c @@ -337,6 +337,13 @@ nvswitch_set_nport_tprod_state_ls10 NVSWITCH_TIMEOUT timeout; RM_SOE_CORE_CMD_NPORT_TPROD_STATE *nportTprodState; + if (!NVSWITCH_ENG_IS_VALID(device, NPORT, nport)) + { + NVSWITCH_PRINT(device, ERROR, "%s: NPORT #%d invalid\n", + __FUNCTION__, nport); + return -NVL_BAD_ARGS; + } + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); cmd.hdr.unitId = RM_SOE_UNIT_CORE; @@ -364,6 +371,56 @@ nvswitch_set_nport_tprod_state_ls10 return NVL_SUCCESS; } +/* + * @Brief : INIT L2 register state in SOE + * + * @param[in] device + * @param[in] nport + */ +void +nvswitch_soe_init_l2_state_ls10 +( + nvswitch_device *device +) +{ + FLCN *pFlcn; + NvU32 cmdSeqDesc = 0; + NV_STATUS status; + RM_FLCN_CMD_SOE cmd; + NVSWITCH_TIMEOUT timeout; + RM_SOE_CORE_CMD_L2_STATE *pL2State; + + if (!nvswitch_is_soe_supported(device)) + { + NVSWITCH_PRINT(device, INFO, "%s: SOE is not supported. skipping!\n", + __FUNCTION__); + return; + } + + pFlcn = device->pSoe->pFlcn; + + nvswitch_os_memset(&cmd, 0, sizeof(cmd)); + cmd.hdr.unitId = RM_SOE_UNIT_CORE; + cmd.hdr.size = sizeof(cmd); + + pL2State = &cmd.cmd.core.l2State; + pL2State->cmdType = RM_SOE_CORE_CMD_INIT_L2_STATE; + + nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout); + status = flcnQueueCmdPostBlocking(device, pFlcn, + (PRM_FLCN_CMD)&cmd, + NULL, // pMsg + NULL, // pPayload + SOE_RM_CMDQ_LOG_ID, + &cmdSeqDesc, + &timeout); + if (status != NV_OK) + { + NVSWITCH_PRINT(device, ERROR, "%s: Failed to send INIT_L2_STATE command to SOE, status 0x%x\n", + __FUNCTION__, status); + } +} + /* * @Brief : Init sequence for SOE FSP RISCV image * @@ -424,6 +481,14 @@ nvswitch_init_soe_ls10 return status; } + // + // Set TRACEPC to stack mode for better ucode trace + // In Vulcan CR firmware, this is set to reduced mode in the SOE's manifest + // + data = flcnRiscvRegRead_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL); + data = FLD_SET_DRF(_PRISCV, _RISCV_TRACECTL, _MODE, _STACK, data); + flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, data); + // Sanity the command and message queues as a final check if (_nvswitch_soe_send_test_cmd(device) != NV_OK) { diff --git a/src/common/nvswitch/kernel/ls10/sugen_ls10.c b/src/common/nvswitch/kernel/ls10/sugen_ls10.c index ff8781ac5..ddb46354d 100644 --- a/src/common/nvswitch/kernel/ls10/sugen_ls10.c +++ b/src/common/nvswitch/kernel/ls10/sugen_ls10.c @@ -706,8 +706,8 @@ nvswitch_apply_prod_nxbar_ls10 nvswitch_device *device ) { - - +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 // .NXBAR PROD value application NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _CTRL0, @@ -724,6 +724,7 @@ nvswitch_apply_prod_nxbar_ls10 DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_BURST_GT_9_DATA_VC, __PROD) | DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_BURSTY_PKT, __PROD) | DRF_DEF(_NXBAR_TILEOUT, _ERR_FATAL_INTR_EN, _INGRESS_NON_STICKY_PKT, __PROD)); +#endif // 0 NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG, _DI_DT_SKEW_VAL, __PROD) | @@ -742,7 +743,9 @@ nvswitch_apply_prod_nxbar_ls10 NVSWITCH_ENG_WR32(device, TILEOUT, _BCAST, 0, _NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, DRF_DEF(_NXBAR_TILEOUT, _PRI_NXBAR_TILEOUT_CG1, _MONITOR_CG_EN, __PROD)); - + +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _CTRL0, DRF_DEF(_NXBAR_TILE, _CTRL0, _MULTI_VALID_XFN_CTRL, _ENABLE) | DRF_DEF(_NXBAR_TILE, _CTRL0, _PARTIAL_RAM_WR_CTRL, _ENABLE) | @@ -760,7 +763,7 @@ nvswitch_apply_prod_nxbar_ls10 DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_PKT_PARITY_ERROR, __PROD) | DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_REDUCTION_PKT_ERROR, __PROD) | DRF_DEF(_NXBAR_TILE, _ERR_FATAL_INTR_EN, _INGRESS_SIDEBAND_PARITY_ERROR, __PROD)); - +#endif // 0 NVSWITCH_ENG_WR32(device, TILE, _BCAST, 0, _NXBAR_TILE, _PRI_NXBAR_TILE_CG, DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _DI_DT_SKEW_VAL, __PROD) | DRF_DEF(_NXBAR_TILE, _PRI_NXBAR_TILE_CG, _HALT_CG_EN, __PROD) | @@ -801,7 +804,8 @@ nvswitch_nvs_top_prod_ls10 NvU32 i; // .NVS_TOP PROD application - + // Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_ENG_WR32(device, CLKS_P0, , 0, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); @@ -813,7 +817,7 @@ nvswitch_nvs_top_prod_ls10 NVSWITCH_ENG_WR32(device, CLKS_P0, , 3, _CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, DRF_DEF(_CLOCK_NVSW_PRT, _NVLINK_UPHY0_PLL0_SLCG, _CFGSM, __PROD)); - +#endif // 0 NVSWITCH_ENG_WR32(device, GIN, , 0, _CTRL, _PRI_CTRL_CG1, DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_CTRLPRI, __PROD) | DRF_DEF(_CTRL, _PRI_CTRL_CG1, _SLCG_MSIX, __PROD)); @@ -855,16 +859,21 @@ nvswitch_nvs_top_prod_ls10 NVSWITCH_ENG_WR32(device, PTIMER, , 0, _PTIMER, _PRI_TMR_CG1, DRF_DEF(_PTIMER, _PRI_TMR_CG1, _MONITOR_CG_EN, __PROD) | DRF_DEF(_PTIMER, _PRI_TMR_CG1, _SLCG, __PROD)); - + +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _CTRL_CLOCK_GATING, DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_PCIE, __PROD) | DRF_DEF(_NVLSAW, _CTRL_CLOCK_GATING, _CG1_SLCG_SAW, __PROD)); - +#endif // 0 NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _GLBLLATENCYTIMERCTRL, DRF_DEF(_NVLSAW, _GLBLLATENCYTIMERCTRL, _ENABLE, __PROD)); - +// Moving this L2 register access to SOE. Refer bug #3747687 +#if 0 NVSWITCH_ENG_WR32(device, SAW, , 0, _NVLSAW, _PCIE_PRI_CLOCK_GATING, DRF_DEF(_NVLSAW, _PCIE_PRI_CLOCK_GATING, _CG1_SLCG, __PROD)); +#endif // 0 + NVSWITCH_REG_WR32(device, _PSE, _CG1, DRF_DEF(_PSE, _CG1, _SLCG, __PROD)); diff --git a/src/common/nvswitch/kernel/nvswitch.c b/src/common/nvswitch/kernel/nvswitch.c index d3420ebeb..d9d07a389 100644 --- a/src/common/nvswitch/kernel/nvswitch.c +++ b/src/common/nvswitch/kernel/nvswitch.c @@ -743,6 +743,15 @@ nvswitch_init_soe return device->hal.nvswitch_init_soe(device); } +void +nvswitch_soe_init_l2_state +( + nvswitch_device *device +) +{ + device->hal.nvswitch_soe_init_l2_state(device); +} + static NvlStatus _nvswitch_construct_soe ( @@ -3217,6 +3226,22 @@ _nvswitch_ctrl_inband_pending_data_stats return NVL_SUCCESS; } +static NvlStatus +_nvswitch_ctrl_get_board_part_number +( + nvswitch_device *device, + NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p +) +{ + if (!nvswitch_is_inforom_supported(device)) + { + NVSWITCH_PRINT(device, ERROR, "InfoROM is not supported\n"); + return -NVL_ERR_NOT_SUPPORTED; + } + + return device->hal.nvswitch_ctrl_get_board_part_number(device, p); +} + static NvlStatus _nvswitch_ctrl_i2c_smbus_command ( @@ -4647,6 +4672,26 @@ nvswitch_load_link_disable_settings device->hal.nvswitch_load_link_disable_settings(device, link); } +static NvlStatus +_nvswitch_ctrl_set_nvlink_error_threshold +( + nvswitch_device *device, + NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams +) +{ + return device->hal.nvswitch_ctrl_set_nvlink_error_threshold(device, pParams); +} + +static NvlStatus +_nvswitch_ctrl_get_nvlink_error_threshold +( + nvswitch_device *device, + NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS *pParams +) +{ + return device->hal.nvswitch_ctrl_get_nvlink_error_threshold(device, pParams); +} + NvlStatus nvswitch_lib_ctrl ( @@ -4952,6 +4997,9 @@ nvswitch_lib_ctrl _nvswitch_ctrl_inband_pending_data_stats, NVSWITCH_INBAND_PENDING_DATA_STATS_PARAMS, osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_BOARD_PART_NUMBER, + _nvswitch_ctrl_get_board_part_number, + NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR); NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED( CTRL_NVSWITCH_GET_SW_INFO, _nvswitch_ctrl_get_sw_info, @@ -4973,6 +5021,13 @@ nvswitch_lib_ctrl _nvswitch_ctrl_clear_counters, NVSWITCH_NVLINK_CLEAR_COUNTERS_PARAMS, osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(CTRL_NVSWITCH_SET_NVLINK_ERROR_THRESHOLD, + _nvswitch_ctrl_set_nvlink_error_threshold, + NVSWITCH_SET_NVLINK_ERROR_THRESHOLD_PARAMS, + osPrivate, flags); + NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_NVLINK_ERROR_THRESHOLD, + _nvswitch_ctrl_get_nvlink_error_threshold, + NVSWITCH_GET_NVLINK_ERROR_THRESHOLD_PARAMS); default: nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd); diff --git a/src/common/sdk/nvidia/inc/class/cla084.h b/src/common/sdk/nvidia/inc/class/cla084.h index a224c6df1..15752d725 100644 --- a/src/common/sdk/nvidia/inc/class/cla084.h +++ b/src/common/sdk/nvidia/inc/class/cla084.h @@ -73,5 +73,9 @@ typedef struct NVA084_ALLOC_PARAMETERS { NvHandle guestFbHandleList[NVA084_MAX_VMMU_SEGMENTS]; NvHandle hPluginHeapMemory; NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); NvBool bDeviceProfilingEnabled; } NVA084_ALLOC_PARAMETERS; diff --git a/src/common/sdk/nvidia/inc/class/cla084_notification.h b/src/common/sdk/nvidia/inc/class/cla084_notification.h index da2ec5b5f..8f1f0a03a 100644 --- a/src/common/sdk/nvidia/inc/class/cla084_notification.h +++ b/src/common/sdk/nvidia/inc/class/cla084_notification.h @@ -39,7 +39,8 @@ extern "C" { #define NVA084_NOTIFIERS_EVENT_VGPU_PLUGIN_TASK_CRASHED (2) #define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_LOADED (3) #define NVA084_NOTIFIERS_EVENT_GUEST_DRIVER_UNLOADED (4) -#define NVA084_NOTIFIERS_MAXCOUNT (5) +#define NVA084_NOTIFIERS_EVENT_PRINT_ERROR_MESSAGE (5) +#define NVA084_NOTIFIERS_MAXCOUNT (6) #define NVA084_NOTIFICATION_STATUS_IN_PROGRESS (0x8000) #define NVA084_NOTIFICATION_STATUS_BAD_ARGUMENT (0x4000) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h index 74b65c799..7aa23f49b 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h @@ -296,8 +296,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS { /* Generic types */ #define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC (0xA00FF000U) - - +#define NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC (0xA00FF001U) /* processor capabilities */ #define NV0000_CTRL_SYSTEM_CPU_CAP_MMX (0x00000001U) diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h index 090f81365..5ee1de07f 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h @@ -2945,6 +2945,22 @@ typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS { #define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */ +/* + * NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP + * + * This command is to trigger the next sequence after the 10 sec delay + * + * [out] linkId + * Link number which the sequence should be triggered + */ +#define NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID (0x42U) + +typedef struct NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS { + NvU32 linkId; +} NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS; + +#define NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP (0x20803042U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS_MESSAGE_ID" */ + /* _ctrl2080nvlink_h_ */ diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h index 2da2c8025..12f41e099 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h @@ -79,6 +79,10 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryPhysAddr, 8); NV_DECLARE_ALIGNED(NvU64 pluginHeapMemoryLength, 8); NV_DECLARE_ALIGNED(NvU64 ctrlBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8); + NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8); NvBool bDeviceProfilingEnabled; } NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS; diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h index b956ab91b..f16717758 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrla080.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrla080.h @@ -625,6 +625,9 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS { #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED 20:20 #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_FALSE (0x00000000) #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_TIMESLICE_OVERRIDE_ENABLED_TRUE (0x00000001) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS 21:21 +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_FALSE (0x00000000) +#define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_VGPU_DEV_CAPS_USE_NON_STALL_LINUX_EVENTS_TRUE (0x00000001) /* UVM supported features */ #define NVA080_CTRL_CMD_VGPU_GET_CONFIG_PARAMS_UVM_FEATURES_REPLAYABLE_FAULTS_ENABLED 0:0 diff --git a/src/common/sdk/nvidia/inc/finn_rm_api.h b/src/common/sdk/nvidia/inc/finn_rm_api.h index 0722dd9a0..eac891a2f 100644 --- a/src/common/sdk/nvidia/inc/finn_rm_api.h +++ b/src/common/sdk/nvidia/inc/finn_rm_api.h @@ -40,7 +40,7 @@ * FINN compiler version */ #define FINN_VERSION_MAJOR 1 -#define FINN_VERSION_MINOR 14 +#define FINN_VERSION_MINOR 15 #define FINN_VERSION_PATCH 0 typedef struct FINN_RM_API @@ -130,7 +130,7 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src */ /**@{*/ NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); -NV_STATUS FinnRmApiDeserializeUp(NvU8 * const *src, NvLength src_size, void *dst, NvLength dst_size); +NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size); /**@}*/ /*! diff --git a/src/common/sdk/nvidia/inc/nvos.h b/src/common/sdk/nvidia/inc/nvos.h index 4fb187071..27fe427de 100644 --- a/src/common/sdk/nvidia/inc/nvos.h +++ b/src/common/sdk/nvidia/inc/nvos.h @@ -1446,7 +1446,7 @@ typedef struct #define NVOS32_ALLOC_FLAGS_BANK_GROW_UP 0x00000000 #define NVOS32_ALLOC_FLAGS_BANK_GROW_DOWN 0x00000200 #define NVOS32_ALLOC_FLAGS_LAZY 0x00000400 -// unused 0x00000800 +#define NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC 0x00000800 #define NVOS32_ALLOC_FLAGS_NO_SCANOUT 0x00001000 #define NVOS32_ALLOC_FLAGS_PITCH_FORCE 0x00002000 #define NVOS32_ALLOC_FLAGS_MEMORY_HANDLE_PROVIDED 0x00004000 diff --git a/src/common/uproc/os/common/include/liblogdecode.h b/src/common/uproc/os/common/include/liblogdecode.h index 7346c6c3e..eefb3e94a 100644 --- a/src/common/uproc/os/common/include/liblogdecode.h +++ b/src/common/uproc/os/common/include/liblogdecode.h @@ -141,6 +141,11 @@ typedef struct char lineBuffer[LIBOS_LOG_LINE_BUFFER_SIZE]; NvBool bSynchronousBuffer; NvBool bPtrSymbolResolve; + + // Attempt to decode %s format arguments + // This requires all %s libos log arguments to be present in the logging elf, otherwise + // garbage output may be produced. + NvBool bDecodeStrFmt; #endif // LIBOS_LOG_DECODE_ENABLE #if defined(NVSYM_STANDALONE) && !defined(PROTODMP_BUILD) @@ -168,11 +173,13 @@ void libosLogAddLog(LIBOS_LOG_DECODE *logDecode, void *buffer, NvU64 bufferSize, #if LIBOS_LOG_DECODE_ENABLE void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfSize); void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize); + LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, + NvBool bPtrSymbolResolve, NvBool bDecodeStrFmt, NvU64 elfSize); #else void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf, NvU64 elfSize); void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, void *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize); + LIBOS_LOG_DECODE *logDecode, void *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, + NvBool bDecodeStrFmt, NvU64 elfSize); #endif // LIBOS_LOG_DECODE_ENABLE void libosLogSymbolicateAddress(LIBOS_LOG_DECODE *logDecode, char *decodedLine, NvLength decodedLineSize, NvUPtr addr); diff --git a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c index 4845ff1f9..e7fe926bf 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/libdwarf.c @@ -195,6 +195,10 @@ NvBool LibosDebugResolveSymbolToName( { LibosElf64Symbol *i = (LibosElf64Symbol *)pThis->symtabStart; NvU64 count = (pThis->symtabEnd - pThis->symtabStart) / sizeof(LibosElf64Symbol); + + if (i == NULL) + return NV_FALSE; + while (count--) { if (i->name && (symbolAddress == i->value || (symbolAddress >= i->value && symbolAddress < i->value + i->size))) @@ -732,6 +736,9 @@ static void libosDwarfBuildTables(LibosDebugResolver *pThis) pThis->arangeTable = NULL; pThis->nARangeEntries = 0; + if (pThis->debugARangesStart == NULL || pThis->debugLineStart == NULL) + return; + // Run through the .debug_aranges elf section to get a count of consolidated ranges. dwarfBuildARangeTable(pThis); diff --git a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c index e4213392b..cf0fb6885 100644 --- a/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c +++ b/src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c @@ -725,7 +725,7 @@ static int libos_printf_a( } goto print_string; case 's': - a = (char *)LibosElfMapVirtualString(&pRec->log->elfImage, (NvUPtr)arg.p, NV_FALSE); + a = (char *)LibosElfMapVirtualString(&pRec->log->elfImage, (NvUPtr)arg.p, logDecode->bDecodeStrFmt); if (!a) a = (char *)"(bad-pointer)"; print_string: @@ -1467,8 +1467,8 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfS // This will allow us to calculate for max possible number of log entries, // i.e. if none of them have args and are thus the smallest size possible. // - NvU64 minLogBufferEntryLength = 0; - minLogBufferEntryLength++; // account for metadata pointer + NvU64 minLogBufferEntryLength = 1;// account for metadata pointer + if (!logDecode->bSynchronousBuffer) { minLogBufferEntryLength++; // account for timestamp @@ -1530,11 +1530,13 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvU64 elfS } void libosLogInitEx( - LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize) + LIBOS_LOG_DECODE *logDecode, LibosElf64Header *elf, NvBool bSynchronousBuffer, + NvBool bPtrSymbolResolve, NvBool bDecodeStrFmt, NvU64 elfSize) { // Set extended config logDecode->bSynchronousBuffer = bSynchronousBuffer; logDecode->bPtrSymbolResolve = bPtrSymbolResolve; + logDecode->bDecodeStrFmt = bDecodeStrFmt; // Complete init libosLogInit(logDecode, elf, elfSize); @@ -1546,7 +1548,7 @@ void libosLogInit(LIBOS_LOG_DECODE *logDecode, void *elf, NvU64 elfSize) {} void libosLogInitEx( LIBOS_LOG_DECODE *logDecode, void *elf, - NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvU64 elfSize) + NvBool bSynchronousBuffer, NvBool bPtrSymbolResolve, NvBool bDecodeStrFmt, NvU64 elfSize) { // No extended config to set when decode is disabled } @@ -1589,6 +1591,9 @@ void libosLogDestroy(LIBOS_LOG_DECODE *logDecode) logDecode->scratchBuffer = NULL; } #endif // LIBOS_LOG_DECODE_ENABLE + + logDecode->numLogBuffers = 0; + logDecode->bIsDecodable = NV_FALSE; } void libosExtractLogs(LIBOS_LOG_DECODE *logDecode, NvBool bSyncNvLog) diff --git a/src/nvidia-modeset/interface/nvkms-sync.h b/src/nvidia-modeset/interface/nvkms-sync.h index 4f4e1ddf2..e399ad40e 100644 --- a/src/nvidia-modeset/interface/nvkms-sync.h +++ b/src/nvidia-modeset/interface/nvkms-sync.h @@ -58,6 +58,9 @@ static inline NvU32 nvKmsSizeOfNotifier(enum NvKmsNIsoFormat format, } } +void nvKmsSetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, + NvU32 index, void *base, NvU64 timeStamp); + void nvKmsResetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, NvU32 index, void *base); diff --git a/src/nvidia-modeset/lib/nvkms-sync.c b/src/nvidia-modeset/lib/nvkms-sync.c index 928fde875..996bcf699 100644 --- a/src/nvidia-modeset/lib/nvkms-sync.c +++ b/src/nvidia-modeset/lib/nvkms-sync.c @@ -75,46 +75,59 @@ static void GetNotifierTimeStamp(volatile const NvU32 *notif, } while (1); } -static void ResetNotifierLegacy(NvBool overlay, volatile void *in) +static void SetNotifierLegacy(NvBool overlay, volatile void *in, NvBool begun, + NvU64 timeStamp) { volatile NvU32 *notif = in; if (overlay) { - notif[NV_DISP_NOTIFICATION_2_INFO16_3] = + notif[NV_DISP_NOTIFICATION_2_INFO16_3] = begun ? + DRF_DEF(_DISP, _NOTIFICATION_2__3, _STATUS, _BEGUN) : DRF_DEF(_DISP, _NOTIFICATION_2__3, _STATUS, _NOT_BEGUN); - notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_0] = + notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_0] = begun ? NvU64_LO32(timeStamp) : NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_LO_INVALID; + notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_1] = begun ? NvU64_HI32(timeStamp) : + NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_HI_INVALID; } else { - notif[NV_DISP_BASE_NOTIFIER_1__0] = + notif[NV_DISP_BASE_NOTIFIER_1__0] = begun ? + DRF_DEF(_DISP, _BASE_NOTIFIER_1__0, _STATUS, _BEGUN) : DRF_DEF(_DISP, _BASE_NOTIFIER_1__0, _STATUS, _NOT_BEGUN); } } -static void ResetNotifierFourWord(volatile void *in) +static void SetNotifierFourWord(volatile void *in, NvBool begun, + NvU64 timeStamp) { volatile NvU32 *notif = in; - notif[NV_DISP_NOTIFICATION_2_INFO16_3] = + notif[NV_DISP_NOTIFICATION_2_INFO16_3] = begun ? + DRF_DEF(_DISP, _NOTIFICATION_2__3, _STATUS, _BEGUN) : DRF_DEF(_DISP, _NOTIFICATION_2__3, _STATUS, _NOT_BEGUN); - notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_0] = + notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_0] = begun ? NvU64_LO32(timeStamp) : NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_LO_INVALID; + notif[NV_DISP_NOTIFICATION_2_TIME_STAMP_1] = begun ? NvU64_HI32(timeStamp) : + NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_HI_INVALID; } -static void ResetNotifierFourWordNVDisplay(volatile void *in) +static void SetNotifierFourWordNVDisplay(volatile void *in, NvBool begun, + NvU64 timeStamp) { volatile NvU32 *notif = in; - notif[NV_DISP_NOTIFIER__0] = + notif[NV_DISP_NOTIFIER__0] = begun ? + DRF_DEF(_DISP, _NOTIFIER__0, _STATUS, _BEGUN) : DRF_DEF(_DISP, _NOTIFIER__0, _STATUS, _NOT_BEGUN); - notif[NV_DISP_NOTIFIER__2] = + notif[NV_DISP_NOTIFIER__2] = begun ? NvU64_LO32(timeStamp) : NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_LO_INVALID; + notif[NV_DISP_NOTIFIER__3] = begun ? NvU64_HI32(timeStamp) : + NVKMS_LIB_SYNC_NOTIFIER_TIMESTAMP_HI_INVALID; } -void nvKmsResetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, - NvU32 index, void *base) +static void SetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, + NvU32 index, void *base, NvBool begun, NvU64 timeStamp) { const NvU32 sizeInBytes = nvKmsSizeOfNotifier(format, overlay); void *notif = @@ -122,17 +135,29 @@ void nvKmsResetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, switch (format) { case NVKMS_NISO_FORMAT_LEGACY: - ResetNotifierLegacy(overlay, notif); + SetNotifierLegacy(overlay, notif, begun, timeStamp); break; case NVKMS_NISO_FORMAT_FOUR_WORD: - ResetNotifierFourWord(notif); + SetNotifierFourWord(notif, begun, timeStamp); break; case NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY: - ResetNotifierFourWordNVDisplay(notif); + SetNotifierFourWordNVDisplay(notif, begun, timeStamp); break; } } +void nvKmsSetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, + NvU32 index, void *base, NvU64 timeStamp) +{ + SetNotifier(format, overlay, index, base, NV_TRUE, timeStamp); +} + +void nvKmsResetNotifier(enum NvKmsNIsoFormat format, NvBool overlay, + NvU32 index, void *base) +{ + SetNotifier(format, overlay, index, base, NV_FALSE, 0); +} + static void ParseNotifierLegacy(NvBool overlay, volatile const void *in, struct nvKmsParsedNotifier *out) { diff --git a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c index b6a65243b..f75c9fb17 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c +++ b/src/nvidia-modeset/src/nvkms-headsurface-ioctl.c @@ -325,13 +325,6 @@ static NvBool HsIoctlFlipValidateOneHwState( const NVFlipChannelEvoHwState *pHwState, const NvU32 sd) { - /* HeadSurface does not support completion notifiers, yet. */ - - if ((pHwState->completionNotifier.surface.pSurfaceEvo != NULL) || - (pHwState->completionNotifier.awaken)) { - return FALSE; - } - /* The semaphore surface must have a CPU mapping. */ if (!pHwState->syncObject.usingSyncpt) { @@ -406,6 +399,17 @@ static NvBool HsIoctlFlipAssignHwStateOneHead( continue; } + /* + * HeadSurface only supports client notifiers when running in + * swapgroup mode where each flip IOCTL will result in a real + * flip in HW. + */ + if (((pFlipState->layer[layer].completionNotifier.surface.pSurfaceEvo != NULL) || + pFlipState->layer[layer].completionNotifier.awaken) && + !pHsChannel->config.neededForSwapGroup) { + return FALSE; + } + if (!HsIoctlFlipValidateOneHwState(&pFlipState->layer[layer], sd)) { return FALSE; } diff --git a/src/nvidia-modeset/src/nvkms-headsurface.c b/src/nvidia-modeset/src/nvkms-headsurface.c index c64209f8b..42777c097 100644 --- a/src/nvidia-modeset/src/nvkms-headsurface.c +++ b/src/nvidia-modeset/src/nvkms-headsurface.c @@ -1960,6 +1960,53 @@ static NvBool IsPreviousFrameDone(NVHsChannelEvoPtr pHsChannel) } } +/*! + * If the client provided a notifier surface with a real flip + * request while swap groups were enabled, write to that + * notifier with the BEGUN status and the most recent + * headsurface notifier timestamp to emulate what the client + * would observe if their notifier was used in hardware. + */ +static void HsUpdateClientNotifier(NVHsChannelEvoPtr pHsChannel) +{ + const NVDispEvoRec *pDispEvo = pHsChannel->pDispEvo; + const NvU32 apiHead = pHsChannel->apiHead; + const NvU32 sd = pDispEvo->displayOwner; + const NVHsDeviceEvoRec *pHsDevice = pDispEvo->pDevEvo->pHsDevice; + const NVHsNotifiersRec *pHsNotifiers = &pHsDevice->notifiers; + const NVHsNotifiersOneSdRec *pHsNotifiersOneSd = pHsNotifiers->sd[sd].ptr; + const NvU8 nextSlot = pHsNotifiers->sd[sd].apiHead[apiHead].nextSlot; + struct nvKmsParsedNotifier parsed = { }; + NVFlipNIsoSurfaceEvoHwState *pClientNotifier = + &pHsChannel->flipQueue[NVKMS_MAIN_LAYER].current.completionNotifier.surface; + + if (pClientNotifier->pSurfaceEvo == NULL) { + return; + } + + const NvU8 prevSlot = + A_minus_b_with_wrap_U8(nextSlot, 1, + NVKMS_HEAD_SURFACE_MAX_NOTIFIERS_PER_HEAD); + + nvKmsParseNotifier(pHsNotifiers->nIsoFormat, FALSE /* overlay */, + prevSlot, pHsNotifiersOneSd->notifier[apiHead], &parsed); + + nvAssert(parsed.status == NVKMS_NOTIFIER_STATUS_BEGUN); + + /* + * XXX NVKMS HEADSURFACE TODO: Get valid timestamp through other means to + * support this on platforms with legacy HW semaphores without valid + * HW notifier timestamps in the main channel. + */ + nvAssert(parsed.timeStampValid); + + nvKmsSetNotifier(pClientNotifier->format, + FALSE /* overlay */, + pClientNotifier->offsetInWords / 4, + pClientNotifier->pSurfaceEvo->cpuAddress[sd], + parsed.timeStamp); +} + /*! * Check if all flips completed for this SwapGroup. If so, release the * SwapGroup. @@ -2004,8 +2051,9 @@ static void HsCheckSwapGroupFlipDone( } /* - * The SwapGroup is ready: increment nextIndex for all active heads, so that - * subsequent frames of headSurface render to the next buffer. + * The SwapGroup is ready: update client notifiers if necessary and + * increment nextIndex for all active heads, so that subsequent frames of + * headSurface render to the next buffer. */ FOR_ALL_EVO_DISPLAYS(pDispEvo, dispIndex, pDevEvo) { NvU32 apiHead; @@ -2022,6 +2070,7 @@ static void HsCheckSwapGroupFlipDone( nvAssert(pHsChannel->config.neededForSwapGroup); nvAssert(IsPreviousFlipDone(pHsChannel)); + HsUpdateClientNotifier(pHsChannel); HsIncrementNextIndex(pHsDevice, pHsChannel); } } diff --git a/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h b/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h index 1644e3d72..351aebe8f 100644 --- a/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h +++ b/src/nvidia/arch/nvalloc/common/inc/dev_ctrl_defines.h @@ -53,6 +53,8 @@ #define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(i) ((i)*2) #define NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(i) (((i)*2) + 1) +#define NV_CTRL_INTR_LEAF_IDX_TO_SUBTREE(i) ((i)/2) + // // Given a LEAF register index, the below macros give us the range of GPU // interrupt vectors that correspond to those leafs. diff --git a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h index c056000d6..ac88094fb 100644 --- a/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h +++ b/src/nvidia/arch/nvalloc/common/inc/gsp/gsp_fw_wpr_meta.h @@ -139,17 +139,22 @@ typedef struct NvU32 elfCodeSize; NvU32 elfDataSize; + // Bit 0 is used to check if [VGPU-GSP] mode is active in init partition + NvU8 driverModel; + // Pad structure to exactly 256 bytes. Can replace padding with additional // fields without incrementing revision. Padding initialized to 0. - NvU32 padding[3]; + NvU8 padding[11]; // BL to use for verification (i.e. Booter says OK to boot) NvU64 verified; // 0x0 -> unverified, 0xa0a0a0a0a0a0a0a0 -> verified - } GspFwWprMeta; #define GSP_FW_WPR_META_VERIFIED 0xa0a0a0a0a0a0a0a0ULL #define GSP_FW_WPR_META_REVISION 1 #define GSP_FW_WPR_META_MAGIC 0xdc3aae21371a60b3ULL +// Bit 0 is used to check if [VGPU-GSP] mode is active in init partition +#define DRIVERMODEL_VGPU 0 + #endif // GSP_FW_WPR_META_H_ diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h index 0ea7235f9..ea174e989 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h @@ -28,6 +28,7 @@ #include "inforom/ifrecc.h" #include "inforom/ifrdem.h" +#include "inforom/omsdef.h" #define INFOROM_OBD_OBJECT_V1_XX_PACKED_SIZE 128 @@ -49,6 +50,29 @@ struct INFOROM_OBD_OBJECT_V1_XX #define INFOROM_OBD_OBJECT_V1_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d116b" typedef struct INFOROM_OBD_OBJECT_V1_XX INFOROM_OBD_OBJECT_V1_XX; +#define INFOROM_OBD_OBJECT_V2_XX_PACKED_SIZE 224 + +struct INFOROM_OBD_OBJECT_V2_XX +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 buildDate; + inforom_U008 marketingName[24]; + inforom_U008 serialNumber[16]; + inforom_U008 memoryManufacturer; + inforom_U008 memoryPartID[20]; + inforom_U008 memoryDateCode[6]; + inforom_U008 productPartNumber[20]; + inforom_U008 boardRevision[3]; + inforom_U008 boardType; + inforom_U008 board699PartNumber[20]; + inforom_U032 productLength; + inforom_U032 productWidth; + inforom_U032 productHeight; + inforom_U008 reserved[89]; +}; +#define INFOROM_OBD_OBJECT_V2_XX_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "d111b3d89b" +typedef struct INFOROM_OBD_OBJECT_V2_XX INFOROM_OBD_OBJECT_V2_XX; + // // OEM 1.0 // diff --git a/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h b/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h index 921482e1f..9509a7bd7 100644 --- a/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h +++ b/src/nvidia/arch/nvalloc/common/inc/inforom/omsdef.h @@ -35,6 +35,29 @@ #define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_NO 0 #define INFOROM_OMS_OBJECT_V1_SETTINGS_ENTRY_DATA_FORCE_DEVICE_DISABLE_YES 1 +#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_RESERVED 23:2 +#define INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 31:24 + +typedef struct INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY +{ + inforom_U032 data; + inforom_U032 clockLimitMin; + inforom_U032 clockLimitMax; +} INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY; + +#define INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES 8 + +typedef struct INFOROM_OMS_OBJECT_V1G +{ + INFOROM_OBJECT_HEADER_V1_00 header; + inforom_U032 lifetimeRefreshCount; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY settings[ + INFOROM_OMS_OBJECT_V1G_NUM_SETTINGS_ENTRIES]; + inforom_U032 reserved; +} INFOROM_OMS_OBJECT_V1G; + +#define INFOROM_OMS_OBJECT_V1G_FMT INFOROM_OBJECT_HEADER_V1_00_FMT "26d" + #define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_RESERVED 7:2 #define INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY_DATA_ENTRY_CHECKSUM 15:8 @@ -62,15 +85,24 @@ typedef struct INFOROM_OMS_V1S_DATA INFOROM_OMS_OBJECT_V1S_SETTINGS_ENTRY *pNext; } INFOROM_OMS_V1S_DATA; +typedef struct INFOROM_OMS_V1G_DATA +{ + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pIter; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY prev; + INFOROM_OMS_OBJECT_V1G_SETTINGS_ENTRY *pNext; +} INFOROM_OMS_V1G_DATA; + typedef union { INFOROM_OBJECT_HEADER_V1_00 header; INFOROM_OMS_OBJECT_V1S v1s; + INFOROM_OMS_OBJECT_V1G v1g; } INFOROM_OMS_OBJECT; typedef union { INFOROM_OMS_V1S_DATA v1s; + INFOROM_OMS_V1G_DATA v1g; } INFOROM_OMS_DATA; typedef struct diff --git a/src/nvidia/arch/nvalloc/common/inc/nvcst.h b/src/nvidia/arch/nvalloc/common/inc/nvcst.h index 9a86d5e42..92419de99 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvcst.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvcst.h @@ -290,6 +290,7 @@ VENDORNAME vendorName[] = {PCI_VENDOR_ID_FUJITSU, "Fujitsu"}, {PCI_VENDOR_ID_CADENCE, "Cadence"}, {PCI_VENDOR_ID_ARM, "ARM"}, + {PCI_VENDOR_ID_ALIBABA, "Alibaba"}, {0, "Unknown"} // Indicates end of the table }; @@ -345,6 +346,7 @@ ARMCSALLOWLISTINFO armChipsetAllowListInfo[] = {PCI_VENDOR_ID_ARM, 0x0100, CS_ARM_NEOVERSEN1}, // Arm Neoverse N1 {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN96XX}, // Marvell OCTEON CN96xx {PCI_VENDOR_ID_MARVELL, 0xA02D, CS_MARVELL_OCTEON_CN98XX}, // Marvell OCTEON CN98xx + {PCI_VENDOR_ID_ALIBABA, 0x8000, CS_ALIBABA_YITIAN}, // Alibaba Yitian // last element must have chipset CS_UNKNOWN (zero) {0, 0, CS_UNKNOWN} diff --git a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h index 559bcb743..a1cf28646 100644 --- a/src/nvidia/arch/nvalloc/common/inc/nvdevid.h +++ b/src/nvidia/arch/nvalloc/common/inc/nvdevid.h @@ -145,6 +145,7 @@ #define PCI_VENDOR_ID_CADENCE 0x17CD #define PCI_VENDOR_ID_ARM 0x13B5 #define PCI_VENDOR_ID_HYGON 0x1D94 +#define PCI_VENDOR_ID_ALIBABA 0x1DED #define NV_PCI_DEVID_DEVICE 31:16 /* RW--F */ #define NV_PCI_SUBID_DEVICE 31:16 /* RW--F */ @@ -642,6 +643,7 @@ enum { , CS_HYGON_C86 , CS_PHYTIUM_S2500 , CS_MELLANOX_BLUEFIELD2 +, CS_ALIBABA_YITIAN , CS_INTEL_1B81 , CS_INTEL_18DC , CS_INTEL_7A04 diff --git a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h index e5b17a0ed..f1946ede0 100644 --- a/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h +++ b/src/nvidia/arch/nvalloc/common/inc/oob/smbpbi.h @@ -111,6 +111,7 @@ #define NV_MSGBOX_CMD_ARG1_TEMP_NUM_SENSORS 8 #define NV_MSGBOX_CMD_ARG1_POWER_TOTAL 0x00000000 #define NV_MSGBOX_CMD_ARG1_SMBPBI_POWER 0x00000001 +#define NV_MSGBOX_CMD_ARG1_POWER_FB 0x00000002 /* SysId info type encodings for opcode NV_MSGBOX_CMD_OPCODE_GET_SYS_ID_DATA (0x05) */ #define NV_MSGBOX_CMD_ARG1_BOARD_PART_NUM_V1 0x00000000 #define NV_MSGBOX_CMD_ARG1_OEM_INFO_V1 0x00000001 @@ -171,6 +172,8 @@ #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MIN 0x00000001 #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_MAX 0x00000002 #define NV_MSGBOX_CMD_ARG1_GET_CLOCK_FREQ_INFO_PAGE_3 0x00000003 +#define NV_MSGBOX_CMD_ARG1_GET_SUPPORTED_CLOCK_THROTTLE_REASONS 0x00000004 +#define NV_MSGBOX_CMD_ARG1_GET_CURRENT_CLOCK_THROTTLE_REASONS 0x00000005 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_RAW_COUNTS 0x00000000 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_STATE_FLAGS 0x00000001 #define NV_MSGBOX_CMD_ARG1_REMAP_ROWS_HISTOGRAM 0x00000002 @@ -639,6 +642,9 @@ #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS 29:29 #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_0_GET_FABRIC_STATE_FLAGS_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB 30:30 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_0_POWER_FB_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_1 1 #define NV_MSGBOX_DATA_CAP_1_BOARD_PART_NUM_V1 0:0 @@ -731,6 +737,9 @@ #define NV_MSGBOX_DATA_CAP_1_ECC_V6 30:30 #define NV_MSGBOX_DATA_CAP_1_ECC_V6_NOT_AVAILABLE 0x00000000 #define NV_MSGBOX_DATA_CAP_1_ECC_V6_AVAILABLE 0x00000001 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON 31:31 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_NOT_AVAILABLE 0x00000000 +#define NV_MSGBOX_DATA_CAP_1_CLOCK_THROTTLE_REASON_AVAILABLE 0x00000001 #define NV_MSGBOX_DATA_CAP_2 2 #define NV_MSGBOX_DATA_CAP_2_GPU_DRIVER 0:0 @@ -1057,6 +1066,21 @@ #define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE 3:0 #define NV_MSGBOX_DATA_GET_CLOCK_FREQ_INFO_PAGE_3_CURRENT_PSTATE_INVALID 0x0000000F +/** + * Response to + * NV_MSGBOX_CMD_ARG1_GET_CLOCK_THROTTLE_REASON + */ +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON 31:0 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_NONE 0x00000000 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_POWER_CAP 0x00000001 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_SLOWDOWN 0x00000002 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SYNC_BOOST 0x00000004 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TLIMIT 0x00000008 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TAVG 0x00000010 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_SW_THERMAL_SLOWDOWN_TMEM 0x00000020 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_THERMAL_SLOWDOWN 0x00000040 +#define NV_MSGBOX_DATA_CLOCK_THROTTLE_REASON_HW_POWER_BREAK_SLOWDOWN 0x00000080 + /* * Number of Nvlink data outputs (dataOut, extData) for * NV_MSGBOX_CMD_ARG1_GET_NVLINK_INFO_LINK queries @@ -2525,7 +2549,7 @@ typedef union { NV_MSGBOX_CMD(_GPU_PERFORMANCE_MONITORING, 0, 0) | \ DRF_DEF(_MSGBOX, _CMD, _ARG1_GPM_ACTION, type) | \ DRF_NUM(_MSGBOX, _CMD, _ARG1_GPM_METRIC, metric) | \ - DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION, partition) \ + DRF_NUM(_MSGBOX, _CMD, _ARG2_GPM_PARTITION_INDEX, partition) \ ) #define NV_MSGBOX_CMD_GPM_SET_MULTIPLIER(multiplier) \ diff --git a/src/nvidia/arch/nvalloc/common/inc/rmifrif.h b/src/nvidia/arch/nvalloc/common/inc/rmifrif.h index 048fcf8bd..b774d02bb 100644 --- a/src/nvidia/arch/nvalloc/common/inc/rmifrif.h +++ b/src/nvidia/arch/nvalloc/common/inc/rmifrif.h @@ -112,7 +112,6 @@ typedef struct * scanning of the whole of memory (e.g. when something goes wrong). */ #define RM_IFR_GC6_CTX_END_OFFSET_MAX 0x1000000 // 16MB -#define RM_IFR_GC6_CTX_END_OFFSET_MAX_WITH_GSP 0x10000000 // 256MB /*! * Maximum size of the context data in bytes. diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 5cb4d1b13..c43faee0c 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -958,7 +958,6 @@ NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *); void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd); NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id); NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); -NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked(nvidia_stack_t *, nv_state_t *, NvU32 *); NV_STATUS NV_API_CALL rm_gpu_handle_mmu_faults(nvidia_stack_t *, nv_state_t *, NvU32 *); NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *); NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *); diff --git a/src/nvidia/arch/nvalloc/unix/src/os.c b/src/nvidia/arch/nvalloc/unix/src/os.c index 5f65ba4a8..aa1de4cf5 100644 --- a/src/nvidia/arch/nvalloc/unix/src/os.c +++ b/src/nvidia/arch/nvalloc/unix/src/os.c @@ -1221,12 +1221,11 @@ static void postEvent( NvBool dataValid ) { - nv_state_t *nv = nv_get_ctl_state(); - portSyncSpinlockAcquire(nv->event_spinlock); - if (event->active) - nv_post_event(event, hEvent, notifyIndex, - info32, info16, dataValid); - portSyncSpinlockRelease(nv->event_spinlock); + if (osReferenceObjectCount(event) != NV_OK) + return; + nv_post_event(event, hEvent, notifyIndex, + info32, info16, dataValid); + osDereferenceObjectCount(event); } NvU32 osSetEvent @@ -1445,6 +1444,12 @@ NV_STATUS osReferenceObjectCount(void *pEvent) nv_event_t *event = pEvent; portSyncSpinlockAcquire(nv->event_spinlock); + // If event->active is false, don't allow any more reference + if (!event->active) + { + portSyncSpinlockRelease(nv->event_spinlock); + return NV_ERR_INVALID_EVENT; + } ++event->refcount; portSyncSpinlockRelease(nv->event_spinlock); return NV_OK; @@ -1457,11 +1462,10 @@ NV_STATUS osDereferenceObjectCount(void *pOSEvent) portSyncSpinlockAcquire(nv->event_spinlock); NV_ASSERT(event->refcount > 0); - --event->refcount; // If event->refcount == 0 but event->active is true, the client // has not yet freed the OS event. free_os_event will free its // memory when they do, or else when the client itself is freed. - if (event->refcount == 0 && !event->active) + if (--event->refcount == 0 && !event->active) portMemFree(event); portSyncSpinlockRelease(nv->event_spinlock); diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index dcd860498..6d4054184 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -354,9 +354,7 @@ static void free_os_event_under_lock(nv_event_t *event) // If refcount > 0, event will be freed by osDereferenceObjectCount // when the last associated RM event is freed. if (event->refcount == 0) - { portMemFree(event); - } } static void free_os_events( @@ -2910,23 +2908,21 @@ static NV_STATUS RmRunNanoTimerCallback( void *pTmrEvent ) { - OBJSYS *pSys = SYS_GET_INSTANCE(); POBJTMR pTmr = GPU_GET_TIMER(pGpu); THREAD_STATE_NODE threadState; NV_STATUS status = NV_OK; // LOCK: try to acquire GPUs lock if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK) { - PTMR_EVENT_PVT pEvent = (PTMR_EVENT_PVT) pTmrEvent; - // We failed to acquire the lock; schedule a timer to try again. - return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->super.pOSTmrCBdata, 1000); - } + TMR_EVENT *pEvent = (TMR_EVENT *)pTmrEvent; - if ((status = osCondAcquireRmSema(pSys->pSema)) != NV_OK) - { - // UNLOCK: release GPUs lock - rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL); - return status; + // + // We failed to acquire the lock - depending on what's holding it, + // the lock could be held for a while, so try again soon, but not too + // soon to prevent the owner from making forward progress indefinitely. + // + return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->pOSTmrCBdata, + osGetTickResolution()); } threadStateInitISRAndDeferredIntHandler(&threadState, pGpu, @@ -2939,7 +2935,6 @@ static NV_STATUS RmRunNanoTimerCallback( threadStateFreeISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER); - osReleaseRmSema(pSys->pSema, NULL); // UNLOCK: release GPUs lock rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, pGpu); diff --git a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c index d60a30d73..6d562c7a1 100644 --- a/src/nvidia/arch/nvalloc/unix/src/unix_intr.c +++ b/src/nvidia/arch/nvalloc/unix/src/unix_intr.c @@ -608,36 +608,19 @@ done: // Use this call when MMU faults needs to be copied // outisde of RM lock. // -NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults_unlocked( - nvidia_stack_t *sp, - nv_state_t *nv, - NvU32 *faultsCopied +static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked( + OBJGPU *pGpu, + NvU32 *pFaultsCopied, + THREAD_STATE_NODE *pThreadState ) { - OBJGPU *pGpu; - void *fp; - NV_STATUS status = NV_OK; - - NV_ENTER_RM_RUNTIME(sp,fp); - - pGpu = NV_GET_NV_PRIV_PGPU(nv); - if (pGpu == NULL || faultsCopied == NULL) - { - status = NV_ERR_OBJECT_NOT_FOUND; - goto done; - } - // Non-replayable faults are copied to the client shadow buffer by GSP-RM. if (IS_GSP_CLIENT(pGpu)) { - status = NV_ERR_NOT_SUPPORTED; - goto done; + return NV_ERR_NOT_SUPPORTED; } -done: - NV_EXIT_RM_RUNTIME(sp,fp); - - return status; + return NV_OK; } // @@ -650,10 +633,12 @@ NV_STATUS rm_gpu_handle_mmu_faults( ) { NvU32 status = NV_OK; + OBJGPU *pGpu; + void *fp; + + NV_ENTER_RM_RUNTIME(sp,fp); *faultsCopied = 0; - - OBJGPU *pGpu; pGpu = NV_GET_NV_PRIV_PGPU(nv); if (pGpu == NULL) @@ -661,40 +646,50 @@ NV_STATUS rm_gpu_handle_mmu_faults( return NV_ERR_OBJECT_NOT_FOUND; } - if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)) { + KernelGmmu *pKernelGmmu; + PORT_MEM_ALLOCATOR *pIsrAllocator; THREAD_STATE_NODE threadState; + NvU8 stackAllocator[TLS_ISR_ALLOCATOR_SIZE]; // ISR allocations come from this buffer - KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - Intr *pIntr = GPU_GET_INTR(pGpu); - - NvU32 hw_put = 0; - NvU32 hw_get = 0; - + pIsrAllocator = portMemAllocatorCreateOnExistingBlock(stackAllocator, sizeof(stackAllocator)); + tlsIsrInit(pIsrAllocator); threadStateInitISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); - kgmmuReadFaultBufferPutPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, - &hw_put, &threadState); + pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu); - kgmmuReadFaultBufferGetPtr_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, - &hw_get, &threadState); - - if(hw_get != hw_put) + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && !IS_VIRTUAL(pGpu)) { - // We have to clear the top level interrupt bit here since otherwise - // the bottom half will attempt to service the interrupt on the CPU - // side before GSP recieves the notification and services it - kgmmuClearNonReplayableFaultIntr(pGpu, pKernelGmmu, &threadState); - status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); + Intr *pIntr = GPU_GET_INTR(pGpu); + if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState)) + { + // We have to clear the top level interrupt bit here since otherwise + // the bottom half will attempt to service the interrupt on the CPU + // side before GSP recieves the notification and services it + kgmmuClearNonReplayableFaultIntr_HAL(pGpu, pKernelGmmu, &threadState); + status = intrTriggerPrivDoorbell_HAL(pGpu, pIntr, NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE); + + } + } + else if (IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, &threadState)) + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); + } + } + else + { + status = _rm_gpu_copy_mmu_faults_unlocked(pGpu, faultsCopied, &threadState); } threadStateFreeISRLockless(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR_LOCKLESS); + tlsIsrDestroy(pIsrAllocator); + portMemAllocatorRelease(pIsrAllocator); } - else - { - status = rm_gpu_copy_mmu_faults_unlocked(sp, nv, faultsCopied); - } + + NV_EXIT_RM_RUNTIME(sp,fp); return status; } diff --git a/src/nvidia/exports_link_command.txt b/src/nvidia/exports_link_command.txt index cf0e1d8d7..86fa80556 100644 --- a/src/nvidia/exports_link_command.txt +++ b/src/nvidia/exports_link_command.txt @@ -154,7 +154,6 @@ --undefined=nvswitch_lib_i2c_transfer --undefined=rm_gpu_copy_mmu_faults --undefined=rm_gpu_handle_mmu_faults ---undefined=rm_gpu_copy_mmu_faults_unlocked --undefined=rm_gpu_need_4k_page_isolation --undefined=rm_is_chipset_io_coherent --undefined=rm_get_device_remove_flag diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index fcd1660a8..0bbb5217f 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -69,6 +69,7 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" +#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c" #undef BINDATA_INCLUDE_STORAGE_PVT_DECL #undef BINDATA_NO_SEGMENTS @@ -97,6 +98,7 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" +#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c" #undef BINDATA_INCLUDE_DATA @@ -123,6 +125,7 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt = #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" +#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c" #undef BINDATA_INCLUDE_STORAGE_PVT_DEFN #undef BINDATA_NO_SEGMENTS @@ -152,6 +155,7 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_AD102.c" #include "g_bindata_ksec2GetBinArchiveBlUcode_TU102.c" +#include "g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c" #undef BINDATA_INCLUDE_FUNCTION #undef BINDATA_INCLUDE_ARCHIVE diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c index 4b54971d3..a6d9a3b9f 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_AD102.c @@ -35,1861 +35,1861 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 32768 -// COMPRESSED SIZE (bytes): 29603 +// COMPRESSED SIZE (bytes): 29605 // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data[] = { - 0xed, 0xb7, 0x53, 0xb8, 0x6e, 0xcb, 0xb2, 0x2d, 0x38, 0xec, 0x39, 0x6c, 0xdb, 0xb6, 0x6d, 0x9b, - 0x73, 0xd8, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0xe7, 0xb0, 0x6d, 0xb3, 0xd6, 0xde, 0x6b, - 0x9d, 0x73, 0x6e, 0xdd, 0x5b, 0x0f, 0xf5, 0x56, 0x0f, 0xb5, 0xe3, 0xfb, 0xfe, 0xde, 0x22, 0x7a, - 0x46, 0x44, 0xcb, 0xcc, 0xc8, 0xe8, 0xbd, 0xff, 0x5e, 0xf1, 0x03, 0x18, 0xe5, 0xf3, 0x3a, 0xb1, - 0xa2, 0x11, 0xb5, 0x04, 0xed, 0x5a, 0xf5, 0x15, 0x21, 0xa9, 0xec, 0x0d, 0x97, 0x40, 0x74, 0x0c, - 0xb3, 0x07, 0xb7, 0xb4, 0x2f, 0x13, 0xb3, 0x4b, 0xa9, 0x6c, 0x9d, 0x37, 0xa3, 0xcd, 0xa1, 0x8b, - 0x75, 0xae, 0x37, 0x65, 0x46, 0x00, 0x56, 0xdf, 0x0f, 0xa1, 0x85, 0x3e, 0xcd, 0x44, 0xe0, 0x98, - 0xda, 0x77, 0xcc, 0x9a, 0xc0, 0x2a, 0x96, 0x42, 0x93, 0x39, 0xd2, 0x38, 0xd8, 0x29, 0x36, 0x1b, - 0x7b, 0xcb, 0x9e, 0x50, 0x25, 0x4b, 0xf3, 0xca, 0x31, 0x85, 0xa0, 0x9a, 0x60, 0x81, 0x3a, 0x99, - 0x3c, 0x0c, 0x03, 0xe9, 0x4b, 0x45, 0x14, 0xbf, 0xeb, 0x48, 0x95, 0x3f, 0x99, 0xdd, 0x53, 0x75, - 0xd3, 0x1c, 0x79, 0x4b, 0x90, 0x4a, 0xe6, 0xd1, 0x06, 0xa3, 0xa5, 0xf9, 0xf1, 0x08, 0x1c, 0x49, - 0xf0, 0x47, 0xaa, 0x7b, 0x2c, 0x41, 0x73, 0x85, 0x63, 0x2f, 0x59, 0xf8, 0x5f, 0x74, 0xd7, 0xf1, - 0xd5, 0x7d, 0x5d, 0x22, 0x6b, 0xe8, 0xc6, 0xce, 0xb7, 0x0c, 0x1c, 0x51, 0x77, 0x8a, 0xae, 0xcc, - 0x4c, 0x20, 0x3f, 0xda, 0x60, 0xbc, 0x92, 0x82, 0x7c, 0x23, 0xdd, 0x20, 0x94, 0x93, 0x92, 0x35, - 0xe7, 0x17, 0x7c, 0x37, 0x06, 0x72, 0xf9, 0x6f, 0xee, 0x60, 0x45, 0x8e, 0x95, 0x43, 0x4a, 0x94, - 0x01, 0x08, 0x95, 0x71, 0x3d, 0x7f, 0x21, 0x13, 0xed, 0x8c, 0xd5, 0x06, 0xd5, 0x69, 0x04, 0x43, - 0xb7, 0x4e, 0xcf, 0x13, 0xd0, 0x9f, 0xbc, 0xc3, 0xb0, 0x4b, 0xbc, 0x61, 0x29, 0x43, 0xcc, 0x15, - 0x96, 0xd5, 0xc1, 0xea, 0xfd, 0xa2, 0xab, 0x92, 0xdf, 0x1f, 0xf9, 0x3d, 0x37, 0x9a, 0xc4, 0x34, - 0x04, 0xef, 0x78, 0x5f, 0xf4, 0xc2, 0x07, 0x02, 0x15, 0x5d, 0x4f, 0x6f, 0xc6, 0x8a, 0x67, 0x40, - 0xad, 0x58, 0xa5, 0x7d, 0x3d, 0x53, 0xa9, 0xcc, 0x43, 0x97, 0x11, 0x45, 0xa1, 0x1b, 0x65, 0x6d, - 0xc9, 0xe2, 0x90, 0xb9, 0x4f, 0xc7, 0x90, 0xf8, 0x8b, 0xe0, 0xb8, 0x02, 0xa6, 0x18, 0x8d, 0x0d, - 0x39, 0xe1, 0xcc, 0xa0, 0xb8, 0x91, 0x75, 0x0c, 0x2f, 0x10, 0xb8, 0x9c, 0xb0, 0x14, 0x15, 0x1c, - 0x4c, 0x40, 0xf2, 0x14, 0xb4, 0x09, 0x4e, 0xb7, 0xfc, 0xb3, 0x92, 0xdf, 0x67, 0x49, 0x82, 0xf9, - 0x6d, 0x68, 0x80, 0xcf, 0xf8, 0x92, 0x92, 0x5c, 0xbe, 0xb3, 0x05, 0xb2, 0x6a, 0x92, 0x8f, 0x32, - 0x08, 0x1e, 0x81, 0xef, 0x70, 0xbf, 0x34, 0xd4, 0xcb, 0xcc, 0xaf, 0x37, 0x07, 0x06, 0x22, 0x14, - 0xd5, 0x0b, 0x48, 0xc5, 0x95, 0x5b, 0x9f, 0x64, 0xf9, 0xd3, 0x14, 0xa6, 0xd6, 0xad, 0xf6, 0x8c, - 0x41, 0x34, 0x4a, 0xe2, 0x6c, 0x46, 0xf5, 0xe1, 0x23, 0x40, 0x41, 0xe9, 0xad, 0x2a, 0xb4, 0x46, - 0x7c, 0x31, 0xa5, 0x4f, 0x33, 0xa1, 0xfa, 0xaa, 0x02, 0x44, 0xcf, 0x95, 0x20, 0xdb, 0xca, 0xe1, - 0xd2, 0x63, 0x73, 0xe6, 0xaa, 0x84, 0xc3, 0x04, 0x35, 0xf2, 0x94, 0x60, 0x73, 0x69, 0x92, 0x77, - 0xda, 0x8f, 0xcf, 0x9b, 0xd1, 0x0e, 0xc3, 0x93, 0xbc, 0x55, 0x1d, 0xd2, 0x8e, 0xc9, 0x10, 0xd0, - 0xae, 0x91, 0x9b, 0x59, 0x65, 0x7f, 0xd9, 0x7f, 0xa7, 0xf0, 0x4f, 0x6f, 0x88, 0x77, 0x44, 0x3f, - 0x85, 0xac, 0xca, 0x62, 0x04, 0xe6, 0x0f, 0xd6, 0x9f, 0x44, 0xe4, 0x46, 0xe0, 0xe0, 0x0d, 0x12, - 0xa3, 0x79, 0x09, 0xc0, 0x22, 0xc0, 0x99, 0xdc, 0xc2, 0xae, 0xa9, 0xe9, 0xcd, 0x41, 0x3a, 0xf6, - 0x45, 0x1d, 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defined(BINDATA_INCLUDE_DATA) @@ -1900,7 +1900,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 32768, // uncompressed data size (bytes) - 29603, // compressed data size (bytes) + 29605, // compressed data size (bytes) kgspBinArchiveGspRmBoot_AD102_ucode_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1957,1856 +1957,1856 @@ BINDATA_STORAGE_PVT kgspBinArchiveGspRmBoot_AD102_ucode_desc_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveGspRmBoot_AD102_ucode_image_prod_data[] = { - 0xed, 0xbb, 0x53, 0xb8, 0x6e, 0xcb, 0xb2, 0x2d, 0x38, 0x6c, 0xdb, 0xb6, 0x6d, 0x7b, 0x0e, 0x1b, - 0x73, 0xd8, 0xb6, 0xe7, 0xb0, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xbb, 0xd6, 0xde, 0x6b, - 0x9d, 0x73, 0x6e, 0xdd, 0x5b, 0x0f, 0xf5, 0x56, 0x0f, 0xb5, 0xe3, 0xfb, 0xfe, 0xde, 0x22, 0x7a, - 0x66, 0x46, 0xcb, 0x8c, 0xc8, 0xe8, 0xd9, 0xfb, 0xc3, 0x5f, 0x1f, 0x1e, 0xc8, 0xae, 0x78, 0x56, - 0x5f, 0x8d, 0x38, 0x16, 0xf1, 0xa8, 0x7a, 0x90, 0x95, 0x94, 0x6c, 0x27, 0xc2, 0x15, 0x71, 0x46, - 0xa6, 0x63, 0x66, 0xf1, 0xf2, 0x3c, 0x9d, 0xed, 0xed, 0x9a, 0x5b, 0xa1, 0xa8, 0x19, 0x57, 0xb1, - 0x10, 0x1a, 0x54, 0x97, 0x7f, 0xce, 0x82, 0xa2, 0x30, 0xe3, 0x6b, 0x8f, 0x2a, 0x62, 0x16, 0xc1, - 0xf5, 0xeb, 0x5c, 0xe9, 0x89, 0x49, 0xf6, 0xf9, 0xb3, 0xb2, 0xdc, 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0xff, 0x73, 0xff, 0x77, 0xdf, 0xa8, 0xff, 0x2b, 0x13, 0xff, + 0xae, 0x43, 0xfe, 0x87, 0x2d, 0x54, 0x85, 0xe6, 0xbf, 0xe7, 0x8a, 0xfc, 0xd7, 0x9d, 0x59, 0x21, + 0x7e, 0x10, 0xfd, 0x9f, 0x8e, 0x44, 0x06, 0x0b, 0x45, 0x44, 0x30, 0xc2, 0x18, 0x40, 0x06, 0x07, + 0x80, 0xf9, 0x5f, 0x9e, 0xcd, 0x11, 0xff, 0xdf, 0x57, 0x9f, 0xc2, 0x65, 0x1b, 0x13, 0xe7, 0x83, + 0x03, 0x84, 0x1b, 0x11, 0xb9, 0xff, 0x7b, 0xde, 0x10, 0xfe, 0xcd, 0xaa, 0x03, 0xe1, 0xff, 0x39, + 0x8f, 0xff, 0xd7, 0xfe, 0x82, 0xfb, 0xef, 0xac, 0xfe, 0xa7, 0x9e, 0x8d, 0x10, 0x20, 0x88, 0xff, + 0xf5, 0x5a, 0x25, 0x60, 0x01, 0x09, 0xfa, 0x6f, 0x34, 0x40, 0xfb, 0x8f, 0xfd, 0x16, 0xf0, 0x1f, + 0x24, 0x29, 0xc7, 0xff, 0x6f, 0xa4, 0xf8, 0x17, 0xf3, 0xff, 0x95, 0x26, 0x03, 0x2c, 0x76, 0xc2, + 0x5a, 0xae, 0x2d, 0x18, 0xc0, 0x7f, 0xe7, 0x81, 0xfd, 0x07, 0x41, 0xfe, 0x45, 0x88, 0x7f, 0x11, + 0xe1, 0xdf, 0x71, 0x8a, 0x7f, 0x11, 0xe3, 0x5f, 0x44, 0xf9, 0x17, 0x71, 0xfe, 0xc5, 0x3d, 0xa0, + 0xff, 0x20, 0x00, 0xe8, 0xbf, 0x7e, 0xfe, 0x45, 0x9a, 0xff, 0x65, 0xff, 0xbb, 0x4f, 0x07, 0xd4, + 0xff, 0xa0, 0xcb, 0xbf, 0xe8, 0xf1, 0x2f, 0xfe, 0xef, 0x0f, 0x84, 0x08, 0xc6, 0x7f, 0xc3, 0x1f, + 0x00, 0x84, 0xff, 0xc6, 0xdf, 0x7f, 0xe5, 0x7f, 0x8f, 0x07, 0xfc, 0x7b, 0xfd, 0x23, 0xf5, 0x90, + 0xff, 0x5f, 0x7d, 0x72, 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x47, + 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x47, 0xfe, 0x7f, 0x28, 0xff, 0x2f, 0xa8, 0x10, 0xc5, 0x2c, 0x00, 0x80, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c new file mode 100644 index 000000000..a4b89a8c2 --- /dev/null +++ b/src/nvidia/generated/g_bindata_ksec2GetBinArchiveSecurescrubUcode_AD10X.c @@ -0,0 +1,1281 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ + + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("image_dbg") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_dbg.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_ucode_data_ad10x_boot_from_hs +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 7424 +// COMPRESSED SIZE (bytes): 6242 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_data[] = +{ + 0xed, 0x99, 0x45, 0x50, 0x1c, 0x80, 0xd2, 0xad, 0x71, 0x77, 0x77, 0x0b, 0xee, 0xee, 0x4e, 0xf0, + 0xe0, 0x3a, 0x83, 0x3b, 0x04, 0x77, 0x1b, 0x2c, 0xb8, 0x24, 0x24, 0xc8, 0xe0, 0xee, 0x6e, 0x01, + 0x02, 0x0c, 0xc1, 0x5d, 0x06, 0x77, 0x0b, 0xee, 0xee, 0xfa, 0xee, 0xfa, 0x6e, 0xde, 0xf2, 0x7f, + 0x55, 0xef, 0xff, 0x76, 0x67, 0xd1, 0xab, 0xee, 0x3a, 0xe7, 0x54, 0x35, 0x0c, 0xcc, 0xff, 0xdf, + 0x88, 0xd1, 0xe6, 0x8c, 0xd4, 0x06, 0x79, 0x26, 0x44, 0xba, 0xc4, 0xe8, 0xfe, 0x50, 0xb9, 0x6c, + 0x0b, 0x2d, 0xba, 0x75, 0xa3, 0xea, 0x08, 0x66, 0x3b, 0xb5, 0xec, 0x55, 0x7c, 0xcc, 0x7a, 0xea, + 0xd8, 0xef, 0x48, 0x1d, 0xfa, 0xce, 0x16, 0xd9, 0x86, 0x5a, 0x0d, 0x02, 0x3b, 0x9d, 0x31, 0xaf, + 0xb4, 0xae, 0xc8, 0x39, 0x90, 0x27, 0xf3, 0x87, 0xa1, 0xd6, 0x47, 0x49, 0x36, 0xd4, 0x90, 0x07, + 0x2c, 0x97, 0x15, 0x6a, 0x1d, 0xf7, 0x57, 0xef, 0xef, 0x9c, 0x1a, 0xcb, 0x89, 0x25, 0x11, 0x9b, + 0x39, 0x0e, 0x74, 0xec, 0xa3, 0x02, 0x2e, 0x65, 0x90, 0x44, 0xbe, 0xf4, 0xc6, 0x41, 0x67, 0x83, + 0xd5, 0xb7, 0xe9, 0xb1, 0xe5, 0x7d, 0xd0, 0x98, 0x31, 0x2c, 0x26, 0x85, 0x01, 0x24, 0xf5, 0x21, + 0x4d, 0xc6, 0xcb, 0xfa, 0x1e, 0xb4, 0x5e, 0x64, 0x70, 0x5a, 0x28, 0xa9, 0xa4, 0xed, 0x18, 0x92, + 0xdb, 0xcd, 0xa5, 0xd7, 0xb7, 0x78, 0xc5, 0xf6, 0x23, 0x1a, 0x53, 0xd7, 0x48, 0x66, 0xc5, 0x1d, + 0x27, 0x61, 0xe0, 0x0f, 0x6b, 0x54, 0xcc, 0x2c, 0xcf, 0xf2, 0x9d, 0x5b, 0x50, 0x49, 0xc8, 0xd5, + 0xaf, 0x9e, 0x1a, 0xee, 0xd0, 0xe9, 0xc1, 0x25, 0x78, 0x63, 0xa7, 0x82, 0x43, 0x1f, 0x92, 0xd8, + 0x29, 0xca, 0x2c, 0x50, 0x96, 0x9d, 0x0f, 0xba, 0x63, 0x73, 0x59, 0x6c, 0x9b, 0x74, 0x70, 0x54, + 0xeb, 0x86, 0x80, 0x76, 0xa1, 0x28, 0x23, 0x10, 0x3f, 0x07, 0x2e, 0xbc, 0xd0, 0x80, 0xa6, 0x9e, + 0x25, 0xeb, 0x09, 0xab, 0xf8, 0xad, 0xa9, 0x7a, 0x34, 0x25, 0xcf, 0x98, 0xf5, 0x2b, 0x0f, 0x0d, + 0x2d, 0x67, 0xfd, 0x9c, 0x4f, 0xaa, 0x0f, 0x15, 0xeb, 0xa6, 0x3d, 0x65, 0x25, 0x7f, 0x8b, 0xd5, + 0x09, 0x58, 0xf2, 0x7c, 0xba, 0xc4, 0x6b, 0xb6, 0x1f, 0xf1, 0x3c, 0xc4, 0x99, 0xe3, 0x9c, 0xb5, + 0xf3, 0xa4, 0x41, 0xd5, 0x44, 0x55, 0xe5, 0x71, 0x66, 0x6a, 0x19, 0x7e, 0x0a, 0x9e, 0x1e, 0xfd, + 0x07, 0x5e, 0x13, 0xcf, 0xd9, 0x5f, 0xa2, 0xe1, 0x78, 0xcc, 0xd2, 0x3f, 0xf4, 0x61, 0x8c, 0x95, + 0x09, 0xc2, 0x2c, 0x96, 0xaf, 0x70, 0x67, 0xee, 0x5f, 0x49, 0xae, 0x8f, 0x59, 0x2c, 0x49, 0xf0, + 0xb7, 0xa3, 0x94, 0x01, 0xb9, 0x95, 0x8b, 0xfe, 0x38, 0xc2, 0x1a, 0x2d, 0xf7, 0x15, 0x48, 0x9d, + 0xd2, 0xd5, 0x03, 0x5a, 0x8b, 0xaf, 0x84, 0x5b, 0xe5, 0x81, 0x67, 0x91, 0x95, 0x5c, 0x8a, 0x29, + 0x7e, 0x1c, 0x75, 0x41, 0xd4, 0xf5, 0xba, 0x77, 0x2c, 0x9e, 0x54, 0x79, 0x0d, 0xf0, 0x1d, 0x15, + 0x92, 0x91, 0x4c, 0xff, 0x02, 0xd3, 0x9e, 0x15, 0xa3, 0xb4, 0xdd, 0x09, 0xaa, 0x00, 0xbd, 0xb9, + 0x2d, 0xc6, 0x50, 0x47, 0x81, 0x0e, 0x00, 0x63, 0x5f, 0x7a, 0xba, 0xc3, 0xcf, 0x70, 0x53, 0xa6, + 0x35, 0x12, 0xac, 0xfb, 0x34, 0xf7, 0x75, 0xad, 0x1d, 0x0e, 0x89, 0xaa, 0x10, 0x58, 0xf7, 0x90, + 0xb9, 0x57, 0xe8, 0x63, 0xe0, 0xc0, 0x50, 0x51, 0x26, 0xe2, 0x2a, 0x35, 0xae, 0x94, 0xcd, 0x74, + 0x40, 0xa8, 0x2e, 0xfc, 0xbd, 0x71, 0xcc, 0xf8, 0x32, 0x6b, 0xed, 0xd4, 0x17, 0x28, 0x3e, 0x40, + 0x98, 0x5e, 0xa6, 0x8d, 0x44, 0x05, 0x2b, 0xf1, 0x59, 0x24, 0x10, 0xfe, 0x85, 0x9f, 0xc3, 0xa8, + 0x2c, 0x73, 0x69, 0xfa, 0x2f, 0x5f, 0xb7, 0xea, 0x37, 0x2c, 0x2a, 0xd7, 0x93, 0xe4, 0x34, 0xb5, + 0x95, 0x6f, 0xe7, 0xbe, 0x46, 0x03, 0xef, 0x7f, 0xfe, 0x5a, 0x7a, 0xc8, 0x9c, 0x25, 0xac, 0x1f, + 0xed, 0xd5, 0x9a, 0xf2, 0x73, 0x77, 0x9c, 0x13, 0x5f, 0xfb, 0xf7, 0xef, 0x14, 0xd8, 0xa8, 0x1c, + 0xec, 0x42, 0x49, 0xfc, 0x39, 0xea, 0x1e, 0xb1, 0x4c, 0x66, 0xe6, 0xb8, 0x53, 0x50, 0x58, 0xc3, + 0x66, 0x4e, 0xdd, 0x23, 0xfb, 0x96, 0x7f, 0x12, 0x1f, 0xba, 0x87, 0x80, 0xa6, 0x1a, 0xaa, 0x73, + 0xd1, 0xcf, 0x09, 0x9b, 0x1a, 0x97, 0x70, 0x07, 0x3b, 0x1d, 0x7a, 0x28, 0x46, 0xcb, 0x06, 0x78, + 0x23, 0xf2, 0x58, 0x04, 0x76, 0xba, 0xf1, 0xdf, 0x29, 0x8d, 0x20, 0xa6, 0x13, 0x1a, 0x3f, 0x42, + 0xa2, 0x58, 0xb8, 0x66, 0x08, 0xd8, 0x91, 0x4b, 0x4e, 0x14, 0xd4, 0xde, 0x75, 0x8b, 0xeb, 0xa6, + 0x2f, 0xb3, 0x88, 0x31, 0xbb, 0xb0, 0x97, 0x3f, 0x39, 0x4f, 0xeb, 0xc6, 0x7f, 0x94, 0x8e, 0x6d, + 0x24, 0x21, 0xef, 0x10, 0x70, 0x3a, 0x3c, 0x69, 0xe5, 0x0a, 0x33, 0x5c, 0x94, 0xdd, 0x9b, 0xd1, + 0x03, 0x54, 0xc8, 0x6a, 0xf2, 0x61, 0xc8, 0xdc, 0x23, 0xc3, 0xee, 0x3f, 0x31, 0xc5, 0x4f, 0x98, + 0xab, 0xe9, 0x6c, 0xde, 0x6f, 0x92, 0x86, 0xb8, 0x8e, 0xb6, 0x20, 0x78, 0x05, 0x14, 0x8b, 0x34, + 0xd3, 0x0a, 0xc7, 0xda, 0x36, 0x7f, 0xba, 0x25, 0xdb, 0x93, 0xa4, 0xbd, 0xac, 0x60, 0xa5, 0xd9, + 0x2d, 0x38, 0xd8, 0xf3, 0x36, 0x26, 0x3b, 0x2d, 0xd9, 0xf0, 0xc1, 0x46, 0x65, 0x3a, 0x5f, 0xa1, + 0x1d, 0xe9, 0xd9, 0x7b, 0xbb, 0xb7, 0x44, 0x10, 0x80, 0xbb, 0x7e, 0x82, 0xcb, 0x9c, 0x46, 0xe0, + 0x39, 0x34, 0xa8, 0x89, 0xc8, 0x57, 0x8d, 0xde, 0x2e, 0x83, 0x8e, 0xbf, 0x0b, 0xf8, 0x08, 0x1f, + 0x4a, 0xe7, 0xc3, 0xd2, 0xf5, 0x4d, 0xdf, 0xf0, 0xb7, 0x6b, 0x07, 0xaf, 0xec, 0xb1, 0x33, 0xb9, + 0xa1, 0x25, 0xe1, 0x45, 0xb3, 0x30, 0xa0, 0x88, 0x2b, 0x4e, 0x55, 0x61, 0x11, 0x14, 0xd3, 0xe7, + 0x0b, 0xd0, 0x9e, 0xe7, 0x2c, 0xdd, 0x03, 0xf6, 0xe9, 0x21, 0xeb, 0x3c, 0x9f, 0xfb, 0x3f, 0xe1, + 0x11, 0xf8, 0x0b, 0x3e, 0xee, 0xb6, 0xcf, 0x84, 0x72, 0xab, 0xf9, 0x90, 0xff, 0x8a, 0xf8, 0x12, + 0xf6, 0x24, 0xe3, 0xa0, 0xe7, 0x4b, 0x68, 0x3f, 0x40, 0xdf, 0xf0, 0x15, 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0xda, 0xaf, 0xbe, 0x54, 0x09, 0xb7, 0x03, 0xae, 0x33, 0x79, 0xe6, 0xe8, 0xd6, + 0x82, 0x45, 0x16, 0x43, 0x03, 0xfd, 0x73, 0x49, 0xa1, 0xf5, 0x52, 0xbf, 0xe0, 0xf7, 0x36, 0x17, + 0xe2, 0x36, 0x41, 0xac, 0xa1, 0x0c, 0xca, 0xc5, 0x17, 0x50, 0x05, 0xae, 0xd0, 0xc5, 0x3d, 0xc1, + 0x88, 0x2d, 0xff, 0xad, 0x0e, 0xbe, 0x01, 0xfb, 0x06, 0x43, 0x71, 0x34, 0xad, 0xee, 0x18, 0x0f, + 0xa2, 0xcc, 0x7f, 0xb0, 0xf7, 0x2c, 0x15, 0x1d, 0x59, 0x44, 0x73, 0xd7, 0xab, 0x26, 0xda, 0x1d, + 0xae, 0xcc, 0x6c, 0x49, 0x9b, 0x74, 0x35, 0x0c, 0xc8, 0xc8, 0x11, 0xbf, 0x47, 0xf9, 0xec, 0xe1, + 0x4a, 0xb4, 0x09, 0xe6, 0xa0, 0x0b, 0x33, 0x1a, 0x89, 0x7a, 0xa1, 0xde, 0x8b, 0xdc, 0xa3, 0xde, + 0x64, 0xa1, 0xe1, 0x03, 0xc4, 0x3d, 0xe2, 0xc6, 0x03, 0xee, 0x4f, 0xd2, 0xc6, 0x90, 0x23, 0xc9, + 0x57, 0xc8, 0xb8, 0xdb, 0x7d, 0x96, 0x0c, 0xd3, 0x85, 0x55, 0x80, 0xf9, 0x88, 0x9d, 0x01, 0xe1, + 0xf5, 0xdb, 0x39, 0x58, 0xe8, 0xf1, 0x58, 0x54, 0x17, 0x58, 0x1c, 0x50, 0xb2, 0xa4, 0xe3, 0x9f, + 0x13, 0xb8, 0x65, 0xca, 0x02, 0x82, 0x1b, 0xc8, 0x70, 0xd4, 0xea, 0x6b, 0x71, 0x2d, 0x27, 0xa5, + 0x2a, 0x51, 0x16, 0xc5, 0x28, 0xaa, 0x26, 0x1a, 0x04, 0xb7, 0xc1, 0x6a, 0xcc, 0x8c, 0x13, 0x78, + 0x22, 0x7a, 0xbf, 0xb7, 0xcb, 0x28, 0x47, 0x99, 0x6d, 0xdd, 0x48, 0x2a, 0xf4, 0x53, 0x93, 0x39, + 0x08, 0x03, 0x3d, 0x19, 0x51, 0x0e, 0x9e, 0x95, 0xe3, 0xe8, 0xa9, 0x36, 0x35, 0x44, 0x17, 0x49, + 0x93, 0xaa, 0x72, 0xc2, 0x28, 0xad, 0x88, 0x8f, 0x6b, 0x69, 0xa9, 0xd7, 0x24, 0xeb, 0x0f, 0xb4, + 0x19, 0x94, 0xab, 0x48, 0x80, 0x6c, 0xff, 0x9d, 0x67, 0x04, 0x64, 0x47, 0xb9, 0x0d, 0x45, 0x48, + 0xe0, 0x0a, 0xea, 0x39, 0xce, 0xa0, 0x14, 0xe9, 0x1d, 0x8e, 0x95, 0x48, 0xfb, 0x99, 0xc1, 0x09, + 0x82, 0x92, 0x06, 0x56, 0x98, 0xa9, 0x1b, 0x48, 0xa5, 0x7a, 0x09, 0x58, 0xc7, 0x77, 0xe8, 0xdf, + 0x3e, 0x64, 0x3e, 0x18, 0x1f, 0x39, 0x1d, 0x29, 0xd5, 0x76, 0xf2, 0xe9, 0x30, 0x52, 0x9b, 0xda, + 0x52, 0xf1, 0xd2, 0x3a, 0x51, 0x28, 0x06, 0x71, 0x4d, 0xbb, 0x66, 0x0a, 0x38, 0x14, 0xed, 0xac, + 0x2f, 0xa1, 0x13, 0x84, 0xb9, 0x49, 0xfb, 0x55, 0x69, 0xbe, 0xf2, 0xd1, 0x3f, 0x68, 0x72, 0xbc, + 0xab, 0xc0, 0xbd, 0x19, 0x59, 0xf5, 0xdc, 0xf9, 0x5d, 0x13, 0xc9, 0xd6, 0xd7, 0x29, 0x98, 0xed, + 0x21, 0x70, 0x55, 0x29, 0xc2, 0xf9, 0x29, 0xf4, 0xb3, 0x66, 0xb6, 0x3a, 0xfe, 0xca, 0x0c, 0xe3, + 0xca, 0x2d, 0x32, 0x80, 0xa1, 0x64, 0x29, 0x99, 0xa6, 0xb6, 0xa3, 0x81, 0xa0, 0x35, 0xb9, 0x81, + 0xc4, 0x58, 0xcb, 0x30, 0x6c, 0xcb, 0x86, 0x11, 0xe1, 0x8c, 0x6b, 0x1c, 0x3a, 0x5c, 0x24, 0x3c, + 0xf2, 0x07, 0x5d, 0x00, 0xab, 0xbc, 0xdf, 0x85, 0x99, 0xf0, 0xdd, 0xdd, 0x98, 0x53, 0xaa, 0x0f, + 0x04, 0xfb, 0x56, 0x67, 0xb3, 0x49, 0xc7, 0xea, 0xb3, 0xe2, 0x67, 0xc1, 0x60, 0xd0, 0xdb, 0x58, + 0xc8, 0xc9, 0xfd, 0xf6, 0xa0, 0x6e, 0x08, 0x1b, 0x43, 0xd7, 0x32, 0x9c, 0x6b, 0x1e, 0x3a, 0x11, + 0x10, 0x1b, 0x9b, 0xbb, 0x32, 0x57, 0x0a, 0xd3, 0x14, 0xd1, 0x47, 0xbb, 0x90, 0x33, 0xa8, 0x99, + 0x9b, 0xcd, 0xa5, 0x47, 0xa0, 0x24, 0xc5, 0x3d, 0xf3, 0x7f, 0xdb, 0xc7, 0x49, 0xfa, 0x96, 0x42, + 0xe7, 0xa9, 0xfd, 0x9d, 0x82, 0x18, 0x0a, 0x09, 0x3f, 0x7e, 0xc0, 0xc3, 0x90, 0x12, 0x75, 0xf8, + 0x0f, 0x0c, 0x25, 0x80, 0xac, 0x5f, 0x5e, 0xfa, 0x42, 0x44, 0xf2, 0x6a, 0x48, 0xc7, 0x5e, 0x53, + 0x80, 0x9d, 0x0d, 0x0a, 0xee, 0xec, 0xba, 0x16, 0x07, 0xe7, 0xb3, 0x5d, 0x22, 0xd1, 0xdf, 0x5c, + 0x7d, 0xde, 0x1b, 0x41, 0x43, 0x32, 0x9b, 0x45, 0xda, 0x50, 0xb4, 0x98, 0xfc, 0x84, 0xfb, 0xe0, + 0x27, 0x25, 0x1b, 0x5c, 0x3a, 0xd4, 0x59, 0x09, 0xca, 0x47, 0xb3, 0x6f, 0x7b, 0x79, 0xe8, 0x6b, + 0x19, 0x25, 0x12, 0xa0, 0x49, 0xd3, 0x08, 0x4d, 0x12, 0x5a, 0x2f, 0x9c, 0xdc, 0xf2, 0xf2, 0x06, + 0xff, 0x71, 0xe1, 0x83, 0xee, 0xed, 0xca, 0xb8, 0xac, 0x53, 0x1e, 0x0b, 0x11, 0x5e, 0xa4, 0x8c, + 0xef, 0xca, 0x90, 0x36, 0x3d, 0xc7, 0x7d, 0xe0, 0x12, 0xbb, 0x43, 0xb3, 0xf3, 0x7f, 0x7c, 0x9c, + 0x94, 0xa5, 0xde, 0x0d, 0xf2, 0x9c, 0xf3, 0x41, 0x3e, 0x51, 0x83, 0x16, 0x80, 0xb8, 0x3a, 0xd3, + 0x9a, 0xd0, 0xcf, 0x46, 0x21, 0xbc, 0x0f, 0xed, 0x74, 0x15, 0xe1, 0x70, 0x0f, 0x22, 0x48, 0x39, + 0x1e, 0xe5, 0x09, 0xb9, 0x42, 0x22, 0xd5, 0x36, 0x6c, 0x0a, 0xf7, 0xfd, 0x7f, 0x5d, 0xff, 0x4f, + 0xff, 0x5f, 0xfe, 0x97, 0xff, 0xe5, 0x7f, 0x92, 0xff, 0x03, 0xe0, 0x9f, 0x53, 0xc0, 0x00, 0x1d, + 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 7424, // uncompressed data size (bytes) + 6242, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("header_dbg") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_dbg.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_ucode_header_ad10x_boot_from_hs +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_header_dbg_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x66, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x30, 0x39, 0x0a, 0xfc, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_header_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_header_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("image_prod") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_prod.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_ucode_data_ad10x_boot_from_hs +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 7424 +// COMPRESSED SIZE (bytes): 6246 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_data[] = +{ + 0xed, 0x99, 0x45, 0x50, 0x1c, 0x00, 0x97, 0xad, 0xf1, 0xe0, 0x04, 0x0d, 0x16, 0x34, 0x58, 0x90, + 0xe0, 0xee, 0xc1, 0x02, 0x8d, 0x36, 0xee, 0x04, 0x1a, 0x0d, 0x0e, 0xc1, 0xdd, 0xb5, 0x71, 0x77, + 0x97, 0x34, 0x8d, 0x04, 0x82, 0xbb, 0xa4, 0x71, 0x77, 0x09, 0x16, 0xdc, 0x1b, 0x0b, 0x34, 0xcc, + 0x5b, 0xff, 0x9b, 0xb7, 0x9c, 0xa9, 0x9a, 0xf9, 0x76, 0x77, 0x71, 0x57, 0xe7, 0xd4, 0x3d, 0xa7, + 0xea, 0x22, 0x21, 0xfd, 0xef, 0xc6, 0xc4, 0x86, 0xb1, 0x55, 0x43, 0x82, 0xeb, 0xcd, 0xcb, 0x8b, + 0x9c, 0x88, 0x29, 0x23, 0xe0, 0xcb, 0xd9, 0x4f, 0xc7, 0xda, 0xc9, 0xfb, 0xc1, 0xc1, 0x14, 0x8d, + 0xc4, 0x03, 0xe3, 0x0d, 0x60, 0xb0, 0x26, 0x23, 0x27, 0xfa, 0x98, 0x9a, 0x96, 0x96, 0xc5, 0x02, + 0x28, 0xef, 0xc9, 0x14, 0x36, 0xb7, 0x1d, 0x51, 0xdc, 0xfc, 0x05, 0x6b, 0xc5, 0x04, 0xec, 0x3d, + 0x76, 0xdf, 0x33, 0x60, 0xd9, 0x10, 0xef, 0x1d, 0xbb, 0x99, 0x79, 0xe9, 0x06, 0xa2, 0x87, 0xeb, + 0xbe, 0x66, 0xac, 0x63, 0xe0, 0x21, 0xde, 0xec, 0x11, 0x85, 0x97, 0xbf, 0xbb, 0xce, 0x10, 0xa2, + 0x59, 0xb5, 0x2c, 0x72, 0xf9, 0x50, 0xc8, 0x54, 0xe1, 0x29, 0xde, 0x26, 0x5e, 0x20, 0x50, 0x2c, + 0x6a, 0xaf, 0xbb, 0x7d, 0xe5, 0x61, 0xdd, 0xfa, 0x46, 0xaa, 0x91, 0x1b, 0x27, 0x85, 0xed, 0x17, + 0xbf, 0x9a, 0x1c, 0x58, 0xb2, 0x66, 0x6c, 0x20, 0xe4, 0xe4, 0x87, 0x91, 0xee, 0x9f, 0xa4, 0xfe, + 0x58, 0x73, 0x9f, 0x6d, 0x36, 0x9d, 0xe4, 0x2d, 0xda, 0xd7, 0x24, 0xf4, 0xca, 0x19, 0x89, 0xea, + 0x33, 0x17, 0x27, 0x26, 0x58, 0x4a, 0x55, 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+BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 7424, // uncompressed data size (bytes) + 6246, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("header_prod") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_prod.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_ucode_header_ad10x_boot_from_hs +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 36 +// COMPRESSED SIZE (bytes): 27 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_data[] = +{ + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x66, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x30, 0x39, 0x0a, 0xfc, 0x24, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 36, // uncompressed data size (bytes) + 27, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("sig_dbg") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_sig_dbg_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0xd0, 0x17, 0xc0, 0x36, 0x32, 0xbc, 0x2a, 0xbc, 0x68, 0x11, 0xa0, + 0x27, 0x05, 0x9d, 0x73, 0xff, 0x55, 0xe0, 0x63, 0x92, 0x06, 0x82, 0xbd, 0xfd, 0xc3, 0xf5, 0xcf, + 0x46, 0xa8, 0xbc, 0x9f, 0xec, 0x0c, 0x78, 0x57, 0x79, 0xbf, 0x79, 0x07, 0xa3, 0x8b, 0x27, 0x33, + 0x8c, 0x71, 0x98, 0x44, 0x42, 0x9b, 0x1b, 0xae, 0x39, 0xf4, 0x18, 0xbd, 0x9b, 0xc3, 0xb0, 0xca, + 0x44, 0x22, 0xb8, 0x5a, 0x50, 0x18, 0x27, 0x0d, 0x09, 0x44, 0xc1, 0x6d, 0xfd, 0x35, 0x11, 0xfe, + 0x9f, 0xe8, 0x98, 0x37, 0xb5, 0xb6, 0xca, 0x4c, 0xf5, 0x64, 0x05, 0x24, 0x3f, 0x7c, 0xaf, 0x4a, + 0x25, 0x11, 0x3d, 0x03, 0xda, 0x0b, 0x74, 0xef, 0x37, 0xe9, 0xf9, 0x73, 0xaa, 0xe4, 0x1f, 0xa9, + 0xf5, 0x19, 0x8b, 0x29, 0xb9, 0x38, 0x15, 0x7a, 0xac, 0xe5, 0xe1, 0x58, 0x46, 0x19, 0xfb, 0x9b, + 0xaf, 0xfc, 0x4a, 0x0b, 0x7e, 0x31, 0xf2, 0xc6, 0x19, 0x38, 0x7f, 0xfa, 0x54, 0x7e, 0xc0, 0x79, + 0x8f, 0xcb, 0x72, 0x22, 0x7c, 0x99, 0x49, 0xcc, 0x43, 0xb4, 0x4f, 0x74, 0x77, 0x2a, 0x4e, 0x9c, + 0x3d, 0x4b, 0x88, 0x38, 0xb5, 0x3f, 0x8a, 0xba, 0xf7, 0x53, 0xdf, 0x77, 0x8e, 0xbc, 0xb3, 0x34, + 0x53, 0x24, 0xb1, 0x53, 0x73, 0xf7, 0xb1, 0xd9, 0x8d, 0x52, 0x75, 0xcc, 0xd6, 0xf6, 0xf8, 0x34, + 0x87, 0xaa, 0xf5, 0x0c, 0x29, 0x39, 0xea, 0x95, 0x18, 0x31, 0x4d, 0xcc, 0x7e, 0x12, 0x24, 0xed, + 0x05, 0x3f, 0x98, 0x62, 0x08, 0x03, 0xa8, 0xd3, 0x85, 0x70, 0xbe, 0x8f, 0xcb, 0x0a, 0xa4, 0x28, + 0xed, 0x71, 0x37, 0xb3, 0xf1, 0xe3, 0x18, 0x73, 0xaf, 0x71, 0xb5, 0xbb, 0x4b, 0x35, 0xb4, 0x19, + 0xdb, 0x1b, 0x72, 0x0a, 0x7e, 0xeb, 0x3b, 0x09, 0xc9, 0x08, 0x2b, 0xef, 0x30, 0x6c, 0xda, 0x08, + 0x24, 0xfa, 0x9c, 0x42, 0x09, 0xbd, 0xf7, 0xc5, 0xfc, 0x89, 0x86, 0xdd, 0x18, 0xa5, 0x43, 0x88, + 0xa6, 0xba, 0x43, 0x07, 0xd4, 0xb7, 0xdb, 0x69, 0xb6, 0xf6, 0xaa, 0x4c, 0x54, 0x17, 0x44, 0xa6, + 0x48, 0xa2, 0x69, 0xbc, 0x8f, 0x6d, 0x3c, 0x43, 0x1c, 0xc3, 0x8c, 0xc0, 0xcb, 0xa4, 0x5e, 0xd5, + 0xd4, 0x6f, 0xd9, 0xdc, 0x77, 0xe7, 0xa2, 0x74, 0xd0, 0xfd, 0x78, 0x1c, 0xff, 0x80, 0x1d, 0x6d, + 0x68, 0x5f, 0x21, 0xb7, 0x0a, 0xaa, 0x77, 0xe2, 0xd8, 0xdf, 0x0d, 0xd6, 0xf3, 0x76, 0x13, 0x9b, + 0x8a, 0xa9, 0x67, 0x18, 0x2d, 0x4e, 0xac, 0xcc, 0x5d, 0xab, 0x6e, 0xa0, 0xdd, 0x95, 0xce, 0xf3, + 0x07, 0x90, 0xc9, 0x21, 0x5b, 0x1c, 0x2d, 0xc2, 0x3c, 0xe6, 0x22, 0x18, 0x24, 0x65, 0xcb, 0x36, + 0xf7, 0xab, 0x2f, 0x84, 0x30, 0x02, 0x61, 0x4b, 0xd5, 0xfb, 0x14, 0x3f, 0xbc, 0x1a, 0xd7, 0x7b, + 0x49, 0x62, 0x26, 0xb4, 0x53, 0x3a, 0x8f, 0xa9, 0xc8, 0xd9, 0xde, 0xe2, 0x00, 0x25, 0x91, 0x4f, + 0x66, 0x68, 0x92, 0x0b, 0x63, 0x39, 0xb4, 0x72, 0xbf, 0x0b, 0xca, 0x70, 0x16, 0x1d, 0xa5, 0x3e, + 0x6d, 0x7c, 0xd4, 0xc4, 0x65, 0x87, 0x09, 0x1e, 0x3d, 0xb1, 0x62, 0x5e, 0x23, 0xa5, 0xb0, 0x94, + 0xb0, 0x89, 0x60, 0x0a, 0xa3, 0xea, 0xfb, 0x83, 0x64, 0xb3, 0x77, 0x23, 0x29, 0x41, 0xe1, 0xdf, + 0x72, 0x34, 0x26, 0x3c, 0x9c, 0x41, 0xb2, 0x50, 0x3a, 0x5e, 0x23, 0xe9, 0x1e, 0x37, 0xe9, 0x72, + 0xa7, 0x09, 0x69, 0xd4, 0x37, 0x17, 0x88, 0xab, 0x32, 0xef, 0x55, 0x66, 0x77, 0x3a, 0xbe, 0x2a, + 0x47, 0xdf, 0xee, 0x72, 0x27, 0x91, 0xe5, 0xc9, 0xe3, 0xf7, 0x11, 0x9a, 0xd4, 0x9e, 0x8c, 0x3c, + 0x60, 0x42, 0xf4, 0x4e, 0x97, 0x49, 0xd6, 0xbf, 0x20, 0x5d, 0xea, 0x2f, 0xcb, 0x2f, 0xfe, 0xa7, + 0x89, 0xce, 0xe4, 0x72, 0x7c, 0xbd, 0x57, 0xf1, 0xbc, 0x38, 0xe6, 0x96, 0xa8, 0x85, 0xb9, 0x35, + 0x4b, 0xbd, 0x30, 0xa1, 0x3d, 0xdb, 0x86, 0xb0, 0xee, 0x7c, 0xf4, 0x3f, 0xbf, 0xf2, 0x4b, 0x1c, + 0xa1, 0x96, 0xd5, 0xf7, 0x52, 0x8f, 0xe5, 0x07, 0xb9, 0xdb, 0xde, 0x13, 0x51, 0x61, 0x60, 0x3c, + 0x5b, 0x7b, 0x27, 0xa0, 0x7c, 0x7a, 0x9d, 0xc4, 0xc2, 0xd0, 0xfb, 0x3c, 0x3b, 0x45, 0x1c, 0x6f, + 0xb7, 0x9a, 0x5a, 0x54, 0xb3, 0x47, 0x38, 0x14, 0xaa, 0x30, 0x67, 0x10, 0x75, 0x96, 0xf9, 0x22, + 0x0a, 0x09, 0x7b, 0x25, 0x48, 0x68, 0x75, 0x8b, 0xfe, 0x35, 0x6b, 0xee, 0x57, 0x68, 0x08, 0x4f, + 0x86, 0xeb, 0x39, 0x03, 0xde, 0x6e, 0x3f, 0x1b, 0xe3, 0x3c, 0x9a, 0x13, 0x84, 0xe5, 0x6b, 0x0c, + 0x3d, 0xd6, 0xd3, 0xaa, 0x03, 0xce, 0xcb, 0xb9, 0x83, 0xf9, 0x6b, 0xfb, 0x87, 0x30, 0xb4, 0xff, + 0xec, 0x60, 0xb2, 0xf6, 0xaf, 0x9e, 0xc1, 0x39, 0x85, 0xad, 0x2d, 0xdc, 0x67, 0x00, 0x2c, 0x27, + 0xe7, 0x33, 0xd3, 0x31, 0xd5, 0x98, 0xec, 0xb0, 0x7e, 0xb9, 0x0d, 0xb6, 0x78, 0x02, 0xf2, 0x7a, + 0xe7, 0x6a, 0x6e, 0x78, 0x38, 0x47, 0x85, 0xca, 0x95, 0x6a, 0xa4, 0x2b, 0xdb, 0xee, 0xe3, 0x69, + 0x5f, 0x49, 0x07, 0x1b, 0x05, 0xfa, 0x95, 0xaa, 0xb8, 0xd3, 0xa3, 0x58, 0x0b, 0x29, 0x3c, 0x2c, + 0x86, 0xc7, 0x3a, 0xbb, 0xe6, 0xbf, 0x1b, 0x9a, 0xed, 0x32, 0x6d, 0x5c, 0x94, 0xe3, 0x3f, 0x70, + 0x28, 0x0f, 0x99, 0xb8, 0x78, 0x9a, 0x53, 0xab, 0x0f, 0x2e, 0x96, 0x3f, 0x38, 0x7c, 0xca, 0xfb, + 0x18, 0x53, 0xf0, 0xa2, 0xcf, 0x6e, 0x60, 0xbf, 0xda, 0x23, 0xe5, 0xa8, 0xf2, 0xc4, 0x73, 0x20, + 0xe7, 0x84, 0x5c, 0x66, 0x0c, 0xe2, 0x05, 0x5f, 0x94, 0x74, 0xa4, 0x8a, 0xc4, 0xeb, 0x4e, 0x4d, + 0x93, 0xd2, 0xea, 0xa3, 0x4c, 0x88, 0x2e, 0x97, 0x16, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("sig_prod") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_sig_prod_ad10x +// COMPRESSION: YES +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 768 +// COMPRESSED SIZE (bytes): 781 +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_data[] = +{ + 0x01, 0x00, 0x03, 0xff, 0xfc, 0x4e, 0x2a, 0xb9, 0x75, 0xf3, 0x2d, 0x67, 0x09, 0x14, 0x97, 0xe7, + 0x51, 0x0a, 0x28, 0x03, 0xa1, 0x59, 0xd7, 0xe7, 0xd5, 0xeb, 0x40, 0xce, 0xf0, 0x63, 0x89, 0x7f, + 0x19, 0xdf, 0xc9, 0x0e, 0x57, 0x3d, 0x11, 0xf6, 0x97, 0xd5, 0x0e, 0xf3, 0x57, 0x3b, 0xdc, 0xd9, + 0x37, 0xb6, 0x7b, 0xba, 0x3b, 0x25, 0x4f, 0x69, 0x80, 0x07, 0xf9, 0x96, 0xe6, 0x41, 0x4d, 0x63, + 0xd8, 0xbd, 0x9e, 0x6a, 0xe5, 0xab, 0x71, 0xf3, 0x86, 0xbb, 0xae, 0xea, 0x26, 0xae, 0x47, 0x70, + 0x57, 0x7a, 0xe1, 0x47, 0x00, 0x6c, 0x24, 0x6c, 0x9a, 0x8d, 0x27, 0x9c, 0xb4, 0xeb, 0x18, 0x01, + 0x72, 0x96, 0xe2, 0xc2, 0x3e, 0xdc, 0x01, 0xad, 0xfd, 0xcc, 0x64, 0x77, 0xe7, 0xcd, 0x95, 0x02, + 0xe8, 0x26, 0xaa, 0xd1, 0x3b, 0x03, 0x64, 0x9f, 0xed, 0x04, 0x38, 0xb1, 0x49, 0xce, 0xec, 0xc6, + 0x3f, 0xd0, 0x5f, 0x49, 0xff, 0xda, 0xfe, 0xdf, 0x12, 0x6b, 0x67, 0x65, 0x8f, 0x14, 0x6e, 0x6f, + 0x83, 0xbd, 0x7b, 0xc6, 0xcd, 0x6a, 0x1c, 0x87, 0xad, 0x3d, 0xa6, 0xb8, 0x42, 0x02, 0x99, 0x58, + 0x4b, 0x5a, 0xc1, 0xcf, 0xab, 0xf9, 0xe3, 0x84, 0xae, 0xda, 0x75, 0xd5, 0x71, 0x06, 0x5b, 0xe0, + 0x97, 0x54, 0x95, 0xae, 0x3c, 0x82, 0xad, 0x56, 0x5f, 0x25, 0x82, 0x5d, 0x66, 0x51, 0x38, 0x24, + 0x1b, 0xa9, 0x73, 0x9c, 0xb4, 0x4d, 0xc4, 0x2e, 0x85, 0x4d, 0x68, 0x05, 0x1a, 0x19, 0x86, 0xba, + 0x24, 0xe3, 0x42, 0xd7, 0x64, 0xbd, 0x28, 0xc7, 0x04, 0x42, 0x29, 0x15, 0x18, 0xa2, 0x1f, 0x36, + 0x6c, 0x37, 0x9c, 0xbf, 0x92, 0x62, 0xd6, 0xd6, 0x95, 0x4d, 0xb2, 0xb4, 0x6d, 0x01, 0xc3, 0x07, + 0xc0, 0x90, 0x8e, 0xf1, 0x42, 0x71, 0x77, 0x93, 0x5a, 0x8a, 0x8f, 0x1d, 0xa0, 0x34, 0xc2, 0xc7, + 0xcb, 0x94, 0xb0, 0xe8, 0x4e, 0x0d, 0xed, 0x72, 0xc9, 0xbc, 0xf2, 0xd3, 0xde, 0x66, 0x2a, 0x3b, + 0xc4, 0xfd, 0x03, 0x50, 0xe4, 0x6d, 0xa5, 0x53, 0x0b, 0x6e, 0x1f, 0xfc, 0xbd, 0x20, 0xf1, 0x0e, + 0x44, 0x8c, 0x73, 0x2b, 0x11, 0xed, 0x28, 0x21, 0xc0, 0x17, 0xf4, 0xef, 0xbb, 0x38, 0x01, 0xdf, + 0x2f, 0xf1, 0xb4, 0x17, 0x92, 0x95, 0x81, 0xc0, 0xad, 0x23, 0xb2, 0x3c, 0xd1, 0xc9, 0xd9, 0xde, + 0x40, 0x0f, 0xf9, 0x79, 0x43, 0xd7, 0xa9, 0x4d, 0xe9, 0x2a, 0x40, 0x8b, 0x35, 0xc9, 0xe6, 0x8c, + 0x53, 0x93, 0x9d, 0x95, 0x6a, 0xf6, 0x43, 0xf6, 0x38, 0xa0, 0x96, 0x1e, 0x66, 0xbe, 0x30, 0xeb, + 0xc0, 0xe9, 0xb4, 0x25, 0x07, 0xb7, 0x08, 0x01, 0x49, 0xbe, 0xcf, 0x5a, 0x5f, 0xb1, 0x7e, 0x51, + 0xc2, 0x74, 0x8e, 0xbf, 0x67, 0xc1, 0x82, 0x4f, 0xdf, 0x36, 0x0e, 0xe1, 0x1f, 0xb0, 0x79, 0x82, + 0x5b, 0x83, 0xf1, 0x2d, 0x30, 0x1f, 0x29, 0xe3, 0x7b, 0x90, 0x77, 0xe8, 0x92, 0x50, 0x69, 0xc8, + 0xba, 0xf4, 0x66, 0xc6, 0x9a, 0x76, 0x6b, 0x29, 0xf1, 0x4c, 0x1e, 0x6e, 0x16, 0x1c, 0xb1, 0xd8, + 0x5b, 0xd7, 0x13, 0x5b, 0x85, 0xd9, 0x20, 0xb9, 0xf1, 0xec, 0x14, 0xa8, 0x9a, 0x01, 0x28, 0xee, + 0x5f, 0x09, 0x13, 0xc4, 0x2d, 0xe7, 0x2e, 0xd1, 0x77, 0x5c, 0x9d, 0x30, 0x73, 0xff, 0xd3, 0xdf, + 0xb0, 0x5d, 0x2a, 0x53, 0x94, 0x42, 0x89, 0xa2, 0x88, 0xe9, 0x5e, 0xd8, 0x75, 0x4a, 0x9c, 0xb4, + 0x85, 0xfc, 0xb7, 0x28, 0xdf, 0x1b, 0x88, 0x96, 0x5f, 0xb7, 0xd0, 0xf1, 0x08, 0x77, 0x75, 0xd0, + 0x3c, 0x38, 0x59, 0x94, 0x9a, 0x10, 0xad, 0x84, 0xaf, 0x1e, 0x92, 0x5d, 0x43, 0x0a, 0x84, 0x0f, + 0xaa, 0xa7, 0x1f, 0x91, 0x9e, 0xe5, 0x9c, 0xfe, 0x48, 0x75, 0x8f, 0x28, 0xba, 0xc4, 0x7b, 0x0d, + 0x70, 0x77, 0x7e, 0x9a, 0x78, 0x4a, 0x04, 0x3c, 0x66, 0xd7, 0x1d, 0x76, 0x11, 0xa3, 0x54, 0x02, + 0x2c, 0x76, 0xb5, 0xbb, 0x50, 0x2b, 0x8b, 0xc8, 0x79, 0x84, 0xd3, 0x2b, 0x87, 0x64, 0x49, 0x7e, + 0xc6, 0x6a, 0x34, 0x59, 0x90, 0x1c, 0xbd, 0xe3, 0xdc, 0x9c, 0x2e, 0x43, 0xc8, 0x02, 0x8a, 0xf3, + 0x42, 0xbe, 0xfc, 0x6f, 0xa4, 0x60, 0xce, 0x23, 0x52, 0xda, 0xf2, 0x51, 0x51, 0xe2, 0xcf, 0x9b, + 0xca, 0x25, 0x97, 0xc4, 0xf9, 0x97, 0x64, 0x39, 0xcf, 0x62, 0xb3, 0xca, 0x5d, 0xf0, 0x6b, 0xa2, + 0x79, 0x83, 0x7a, 0xa5, 0xb5, 0xf0, 0xf2, 0x0d, 0x45, 0x02, 0x42, 0x51, 0xeb, 0xbd, 0x59, 0xa7, + 0x8d, 0xf3, 0xc6, 0x32, 0x05, 0x25, 0x7f, 0x2a, 0x10, 0x04, 0x83, 0x6c, 0x3c, 0xfd, 0x48, 0x63, + 0x65, 0x05, 0x45, 0x63, 0xd0, 0x76, 0x0a, 0x6b, 0x0e, 0xa7, 0x4d, 0xa3, 0x6e, 0x86, 0xb2, 0x08, + 0x67, 0xc1, 0x90, 0x58, 0xc2, 0x30, 0x9a, 0x92, 0xb9, 0x0a, 0x75, 0x76, 0xce, 0xba, 0x1a, 0xc4, + 0xfb, 0xde, 0xe4, 0x38, 0x25, 0x5c, 0x02, 0x0a, 0x47, 0x38, 0x9f, 0x82, 0x87, 0x46, 0xf6, 0x75, + 0x7a, 0x2a, 0xd3, 0x4c, 0x3e, 0xcc, 0x08, 0xfd, 0xe5, 0x11, 0x5e, 0x91, 0x0d, 0x3a, 0xa7, 0xf0, + 0xdd, 0x48, 0x82, 0x34, 0x1d, 0xe7, 0xd1, 0x9f, 0x96, 0x26, 0xec, 0xee, 0x32, 0x8b, 0x04, 0x2c, + 0x85, 0x9c, 0x93, 0x1f, 0x12, 0x6e, 0x1d, 0x0c, 0xd3, 0xa0, 0x28, 0xc9, 0x7c, 0xa6, 0xe4, 0x46, + 0x33, 0xf4, 0x9b, 0x2e, 0xd3, 0x23, 0xb0, 0x85, 0x78, 0x0f, 0xf1, 0xb0, 0x8e, 0x42, 0x5e, 0x0c, + 0xf7, 0x5a, 0x3f, 0xd2, 0x62, 0x78, 0xfa, 0xc3, 0x1d, 0x69, 0x57, 0xfc, 0x75, 0xfb, 0xfc, 0x83, + 0x22, 0x86, 0xfe, 0x48, 0x8d, 0x27, 0x0b, 0xa9, 0x01, 0x0e, 0x2d, 0x5a, 0x76, 0x7f, 0xc7, 0x08, + 0x22, 0x61, 0x8f, 0xf5, 0x71, 0xc3, 0x0b, 0x28, 0xe8, 0x00, 0x03, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 768, // uncompressed data size (bytes) + 781, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_data, // compressed data pointer + NV_TRUE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("patch_loc") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_sig_ad10x_patch_location +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_patch_loc_data[] = +{ + 0x00, 0x1a, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_patch_loc_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_patch_loc_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("patch_sig") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_sig_ad10x_patch_signature +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_patch_sig_data[] = +{ + 0x00, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_patch_sig_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_patch_sig_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("patch_meta") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: securescrub_sig_ad10x_patch_meta_data +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 12 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_patch_meta_data[] = +{ + 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_patch_meta_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 12, // uncompressed data size (bytes) + 12, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_patch_meta_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_DATA) +// +// FUNCTION: ksec2GetBinArchiveSecurescrubUcode_AD10X("num_sigs") +// FILE NAME: kernel/inc/securescrub/bin/ad10x/g_securescrubuc_sec2_ad10x_boot_from_hs_ad10x_rsa3k_0_sig.h +// FILE TYPE: TEXT +// VAR NAME: num_sigs_per_ucode +// COMPRESSION: NO +// COMPLEX_STRUCT: NO +// DATA SIZE (bytes): 4 +// COMPRESSED SIZE (bytes): N/A +// +static BINDATA_CONST NvU8 ksec2BinArchiveSecurescrubUcode_AD10X_num_sigs_data[] = +{ + 0x02, 0x00, 0x00, 0x00, +}; +#endif // defined(BINDATA_INCLUDE_DATA) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) +BINDATA_STORAGE_PVT ksec2BinArchiveSecurescrubUcode_AD10X_num_sigs_storage_pvt; +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) + +#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) +{ + 4, // uncompressed data size (bytes) + 4, // compressed data size (bytes) + ksec2BinArchiveSecurescrubUcode_AD10X_num_sigs_data, // compressed data pointer + NV_FALSE, // is pData compressed? + NV_TRUE, // contain information for file overriding? + NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) +}, +#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) + + +#if defined(BINDATA_INCLUDE_ARCHIVE) +// +// Bindata Archive structure +// +static const BINDATA_ARCHIVE __ksec2GetBinArchiveSecurescrubUcode_AD10X = +{ + 10, // entryNum + { + // entries[] : { "name", pBinStorage } + { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_image_dbg_storage_pvt }, + { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_header_dbg_storage_pvt }, + { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_image_prod_storage_pvt }, + { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_header_prod_storage_pvt }, + { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_sig_dbg_storage_pvt }, + { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_sig_prod_storage_pvt }, + { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_patch_loc_storage_pvt }, + { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_patch_sig_storage_pvt }, + { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_patch_meta_storage_pvt }, + { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.ksec2BinArchiveSecurescrubUcode_AD10X_num_sigs_storage_pvt }, + } +}; + +#endif // defined(BINDATA_INCLUDE_ARCHIVE) + + + +#if defined(BINDATA_INCLUDE_FUNCTION) +const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_AD10X(struct KernelSec2 *pKernelSec2) +{ + return &__ksec2GetBinArchiveSecurescrubUcode_AD10X; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION) + + +#if defined(BINDATA_INCLUDE_FUNCTION_STUB) +const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_AD10X(struct KernelSec2 *pKernelSec2) +{ + return NULL; +} +#endif // defined(BINDATA_INCLUDE_FUNCTION_STUB) + + + + + diff --git a/src/nvidia/generated/g_event_nvoc.h b/src/nvidia/generated/g_event_nvoc.h index 38935b93e..2b05ff42b 100644 --- a/src/nvidia/generated/g_event_nvoc.h +++ b/src/nvidia/generated/g_event_nvoc.h @@ -538,6 +538,11 @@ NV_STATUS engineNonStallIntrNotify(OBJGPU *, RM_ENGINE_TYPE); NV_STATUS notifyEvents(OBJGPU*, EVENTNOTIFICATION*, NvU32, NvU32, NvU32, NV_STATUS, NvU32); NV_STATUS engineNonStallIntrNotifyEvent(OBJGPU *, RM_ENGINE_TYPE, NvHandle); +typedef struct GpuEngineEventNotificationList GpuEngineEventNotificationList; + +NV_STATUS gpuEngineEventNotificationListCreate(OBJGPU *, GpuEngineEventNotificationList **); +void gpuEngineEventNotificationListDestroy(OBJGPU *, GpuEngineEventNotificationList *); + #endif // _EVENT_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 313f5d913..3e5afcef9 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -126,7 +126,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ { pThis->setProperty(pThis, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, ((NvBool)(0 == 0))); } @@ -199,7 +199,15 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) { } // NVOC Property Hal field -- PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE - pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 == 0))); + } + // default + else + { + pThis->setProperty(pThis, PDB_PROP_GPU_VGPU_OFFLOAD_CAPABLE, ((NvBool)(0 != 0))); + } // NVOC Property Hal field -- PDB_PROP_GPU_SKIP_CE_MAPPINGS_NO_NVLINK if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index 17fae547d..1b4e83d8b 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -609,21 +609,6 @@ typedef struct // GPU specific data for core logic object, stored in GPU object #define GPU_STATE_DEFAULT 0 // Default flags for destructive state loads // and unloads -typedef struct engine_event_node -{ - PEVENTNOTIFICATION pEventNotify; - struct Memory *pMemory; - struct engine_event_node *pNext; -} ENGINE_EVENT_NODE; - -// Linked list of per engine non-stall event nodes -typedef struct -{ - ENGINE_EVENT_NODE *pEventNode; - // lock to protect above list - PORT_SPINLOCK *pSpinlock; -} ENGINE_EVENT_LIST; - struct OBJHWBC; typedef struct hwbc_list { @@ -936,7 +921,7 @@ struct OBJGPU { OS_RM_CAPS *pOsRmCaps; NvU32 halImpl; void *hPci; - ENGINE_EVENT_LIST engineNonstallIntr[62]; + GpuEngineEventNotificationList *engineNonstallIntrEventNotifications[62]; NvBool bIsSOC; NvU32 gpuInstance; NvU32 gpuDisabled; diff --git a/src/nvidia/generated/g_kern_gmmu_nvoc.h b/src/nvidia/generated/g_kern_gmmu_nvoc.h index 1576f22ab..170f744d5 100644 --- a/src/nvidia/generated/g_kern_gmmu_nvoc.h +++ b/src/nvidia/generated/g_kern_gmmu_nvoc.h @@ -874,19 +874,19 @@ static inline void kgmmuWriteMmuFaultStatus(OBJGPU *pGpu, struct KernelGmmu *pKe #define kgmmuWriteMmuFaultStatus_HAL(pGpu, pKernelGmmu, arg0) kgmmuWriteMmuFaultStatus(pGpu, pKernelGmmu, arg0) -NvBool kgmmuIsNonReplayableFaultPending_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); +NvBool kgmmuIsNonReplayableFaultPending_TU102(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0); #ifdef __nvoc_kern_gmmu_h_disabled -static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu) { +static inline NvBool kgmmuIsNonReplayableFaultPending(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu, struct THREAD_STATE_NODE *arg0) { NV_ASSERT_FAILED_PRECOMP("KernelGmmu was disabled!"); return NV_FALSE; } #else //__nvoc_kern_gmmu_h_disabled -#define kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu) kgmmuIsNonReplayableFaultPending_TU102(pGpu, pKernelGmmu) +#define kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending_TU102(pGpu, pKernelGmmu, arg0) #endif //__nvoc_kern_gmmu_h_disabled -#define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu) +#define kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, arg0) kgmmuIsNonReplayableFaultPending(pGpu, pKernelGmmu, arg0) NV_STATUS kgmmuClientShadowFaultBufferAlloc_GV100(OBJGPU *pGpu, struct KernelGmmu *pKernelGmmu); diff --git a/src/nvidia/generated/g_kernel_ce_nvoc.h b/src/nvidia/generated/g_kernel_ce_nvoc.h index 33eabd0c7..678133316 100644 --- a/src/nvidia/generated/g_kernel_ce_nvoc.h +++ b/src/nvidia/generated/g_kernel_ce_nvoc.h @@ -673,6 +673,16 @@ NV_STATUS kceGetFaultMethodBufferSize_IMPL(OBJGPU *pGpu, NvU32 *size); NV_STATUS kceGetAvailableHubPceMask_IMPL(OBJGPU *pGpu, NVLINK_TOPOLOGY_PARAMS *pTopoParams); #define kceGetAvailableHubPceMask(pGpu, pTopoParams) kceGetAvailableHubPceMask_IMPL(pGpu, pTopoParams) +void kceGetNvlinkCaps_IMPL(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps); + +#ifdef __nvoc_kernel_ce_h_disabled +static inline void kceGetNvlinkCaps(OBJGPU *pGpu, struct KernelCE *pKCe, NvU8 *pKCeCaps) { + NV_ASSERT_FAILED_PRECOMP("KernelCE was disabled!"); +} +#else //__nvoc_kernel_ce_h_disabled +#define kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps) kceGetNvlinkCaps_IMPL(pGpu, pKCe, pKCeCaps) +#endif //__nvoc_kernel_ce_h_disabled + NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *gpu, struct KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, NvU8 *ceCaps); #ifdef __nvoc_kernel_ce_h_disabled diff --git a/src/nvidia/generated/g_kernel_channel_nvoc.c b/src/nvidia/generated/g_kernel_channel_nvoc.c index ec06a9c27..5b8e0acc4 100644 --- a/src/nvidia/generated/g_kernel_channel_nvoc.c +++ b/src/nvidia/generated/g_kernel_channel_nvoc.c @@ -740,12 +740,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [34] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdSetChannelHwState_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) - /*flags=*/ 0x102204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) + /*flags=*/ 0x142204u, /*accessRight=*/0x0u, /*methodId=*/ 0xb06f0110u, /*paramSize=*/ sizeof(NVB06F_CTRL_SET_CHANNEL_HW_STATE_PARAMS), @@ -770,12 +770,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_KernelCh #endif }, { /* [36] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) kchannelCtrlCmdRestoreEngineCtxData_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) - /*flags=*/ 0x102204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) + /*flags=*/ 0x142204u, /*accessRight=*/0x0u, /*methodId=*/ 0xb06f0112u, /*paramSize=*/ sizeof(NVB06F_CTRL_RESTORE_ENGINE_CTX_DATA_PARAMS), @@ -1166,7 +1166,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdGetChannelHwState__ = &kchannelCtrlCmdGetChannelHwState_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) pThis->__kchannelCtrlCmdSetChannelHwState__ = &kchannelCtrlCmdSetChannelHwState_IMPL; #endif @@ -1174,7 +1174,7 @@ static void __nvoc_init_funcTable_KernelChannel_1(KernelChannel *pThis, RmHalspe pThis->__kchannelCtrlCmdSaveEngineCtxData__ = &kchannelCtrlCmdSaveEngineCtxData_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x142204u) pThis->__kchannelCtrlCmdRestoreEngineCtxData__ = &kchannelCtrlCmdRestoreEngineCtxData_IMPL; #endif diff --git a/src/nvidia/generated/g_kernel_fifo_nvoc.h b/src/nvidia/generated/g_kernel_fifo_nvoc.h index 3b27b0a8a..3d0d999b0 100644 --- a/src/nvidia/generated/g_kernel_fifo_nvoc.h +++ b/src/nvidia/generated/g_kernel_fifo_nvoc.h @@ -268,6 +268,7 @@ struct channel_iterator NvU32 numRunlists; NvU32 physicalChannelID; NvU32 runlistId; + EMEMBLOCK *pFifoDataBlock; CHANNEL_NODE channelNode; }; @@ -455,6 +456,7 @@ struct KernelFifo { FifoSchedulingHandlerEntryList preSchedulingDisableHandlerList; NvBool bUseChidHeap; NvBool bUsePerRunlistChram; + NvBool bDisableChidIsolation; NvBool bIsPerRunlistChramSupportedInHw; NvBool bHostEngineExpansion; NvBool bHostHasLbOverflow; diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index 1906741ee..de45262c0 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -497,6 +497,19 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * } } + // Hal function -- kgspGetPrescrubbedTopFbSize + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fbe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_e1e623; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000400UL) )) /* ChipHal: GA100 | GH100 */ + { + pThis->__kgspGetPrescrubbedTopFbSize__ = &kgspGetPrescrubbedTopFbSize_dd2c0b; + } + } + // Hal function -- kgspExtractVbiosFromRom if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -536,6 +549,19 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * } } + // Hal function -- kgspExecuteScrubberIfNeeded + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_AD102; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + { + pThis->__kgspExecuteScrubberIfNeeded__ = &kgspExecuteScrubberIfNeeded_5baef9; + } + } + // Hal function -- kgspExecuteBooterLoad if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { @@ -653,13 +679,43 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * // Hal function -- kgspGetWprHeapSize if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x100007e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GH100 */ { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_e77d51; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_5661b8; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_15390a; } else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ { - pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_38f3bc; + pThis->__kgspGetWprHeapSize__ = &kgspGetWprHeapSize_AD102; + } + } + + // Hal function -- kgspInitVgpuPartitionLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_395e98; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgspInitVgpuPartitionLogging__ = &kgspInitVgpuPartitionLogging_IMPL; + } + } + + // Hal function -- kgspFreeVgpuPartitionLogging + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_395e98; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__kgspFreeVgpuPartitionLogging__ = &kgspFreeVgpuPartitionLogging_IMPL; } } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 510011df6..ead674727 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -49,6 +49,7 @@ extern "C" { #include "gpu/gsp/gsp_static_config.h" #include "gpu/gsp/gsp_init_args.h" #include "nv-firmware.h" +#include "nv_sriov_defines.h" #include "rmRiscvUcode.h" #include "libos_init_args.h" @@ -213,7 +214,7 @@ typedef struct GSP_FIRMWARE enum { LOGIDX_INIT, - LOGIDX_VGPU, + LOGIDX_INTR, LOGIDX_RM, LOGIDX_SIZE }; @@ -267,9 +268,11 @@ struct KernelGsp { NV_STATUS (*__kgspResetHw__)(struct OBJGPU *, struct KernelGsp *); NvBool (*__kgspIsEngineInReset__)(struct OBJGPU *, struct KernelGsp *); NvU32 (*__kgspGetFrtsSize__)(struct OBJGPU *, struct KernelGsp *); + NvU64 (*__kgspGetPrescrubbedTopFbSize__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExtractVbiosFromRom__)(struct OBJGPU *, struct KernelGsp *, KernelGspVbiosImg **); NV_STATUS (*__kgspExecuteFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64); NV_STATUS (*__kgspExecuteFwsecSb__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *); + NV_STATUS (*__kgspExecuteScrubberIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteBooterLoad__)(struct OBJGPU *, struct KernelGsp *, const NvU64); NV_STATUS (*__kgspExecuteBooterUnloadIfNeeded__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); @@ -277,6 +280,8 @@ struct KernelGsp { const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); NvU64 (*__kgspGetWprHeapSize__)(struct OBJGPU *, struct KernelGsp *); + NV_STATUS (*__kgspInitVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32, NvU64, NvU64, NvU64, NvU64); + NV_STATUS (*__kgspFreeVgpuPartitionLogging__)(struct OBJGPU *, struct KernelGsp *, NvU32); const char *(*__kgspGetSignatureSectionNamePrefix__)(struct OBJGPU *, struct KernelGsp *); NV_STATUS (*__kgspSetupGspFmcArgs__)(struct OBJGPU *, struct KernelGsp *, GSP_FIRMWARE *); void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); @@ -302,6 +307,7 @@ struct KernelGsp { NV_STATUS (*__kgspSetTunableState__)(POBJGPU, struct KernelGsp *, void *); struct OBJRPC *pRpc; KernelGspFlcnUcode *pFwsecUcode; + KernelGspFlcnUcode *pScrubberUcode; KernelGspFlcnUcode *pBooterLoadUcode; KernelGspFlcnUcode *pBooterUnloadUcode; MEMORY_DESCRIPTOR *pWprMetaDescriptor; @@ -324,8 +330,12 @@ struct KernelGsp { MEMORY_DESCRIPTOR *pGspUCodeRadix3Descriptor; MEMORY_DESCRIPTOR *pSignatureMemdesc; LIBOS_LOG_DECODE logDecode; + LIBOS_LOG_DECODE logDecodeVgpuPartition[32]; RM_LIBOS_LOG_MEM rmLibosLogMem[3]; + RM_LIBOS_LOG_MEM gspPluginInitTaskLogMem[32]; + RM_LIBOS_LOG_MEM gspPluginVgpuTaskLogMem[32]; void *pLogElf; + NvU64 logElfDataSize; NvBool bLibosLogsPollingEnabled; NvBool bInInit; NvBool bPollingForRpcResponse; @@ -402,12 +412,16 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspIsEngineInReset_HAL(pGpu, pKernelGsp) kgspIsEngineInReset_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetFrtsSize_HAL(pGpu, pKernelGsp) kgspGetFrtsSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp) +#define kgspGetPrescrubbedTopFbSize_HAL(pGpu, pKernelGsp) kgspGetPrescrubbedTopFbSize_DISPATCH(pGpu, pKernelGsp) #define kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) #define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom_DISPATCH(pGpu, pKernelGsp, ppVbiosImg) #define kgspExecuteFwsecFrts(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) #define kgspExecuteFwsecFrts_HAL(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) kgspExecuteFwsecFrts_DISPATCH(pGpu, pKernelGsp, pFwsecUcode, frtsOffset) #define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) #define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_DISPATCH(pGpu, pKernelGsp, pFwsecUcode) +#define kgspExecuteScrubberIfNeeded(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) +#define kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp) kgspExecuteScrubberIfNeeded_DISPATCH(pGpu, pKernelGsp) #define kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) #define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad_DISPATCH(pGpu, pKernelGsp, gspFwWprMetaOffset) #define kgspExecuteBooterUnloadIfNeeded(pGpu, pKernelGsp) kgspExecuteBooterUnloadIfNeeded_DISPATCH(pGpu, pKernelGsp) @@ -422,6 +436,10 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetWprHeapSize(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) #define kgspGetWprHeapSize_HAL(pGpu, pKernelGsp) kgspGetWprHeapSize_DISPATCH(pGpu, pKernelGsp) +#define kgspInitVgpuPartitionLogging(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) +#define kgspInitVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) kgspInitVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize) +#define kgspFreeVgpuPartitionLogging(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid) +#define kgspFreeVgpuPartitionLogging_HAL(pGpu, pKernelGsp, gfid) kgspFreeVgpuPartitionLogging_DISPATCH(pGpu, pKernelGsp, gfid) #define kgspGetSignatureSectionNamePrefix(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspGetSignatureSectionNamePrefix_HAL(pGpu, pKernelGsp) kgspGetSignatureSectionNamePrefix_DISPATCH(pGpu, pKernelGsp) #define kgspSetupGspFmcArgs(pGpu, pKernelGsp, pGspFw) kgspSetupGspFmcArgs_DISPATCH(pGpu, pKernelGsp, pGspFw) @@ -681,6 +699,18 @@ static inline NvU32 kgspGetFrtsSize_DISPATCH(struct OBJGPU *pGpu, struct KernelG return pKernelGsp->__kgspGetFrtsSize__(pGpu, pKernelGsp); } +static inline NvU64 kgspGetPrescrubbedTopFbSize_e1e623(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 256 * 1024 * 1024; +} + +static inline NvU64 kgspGetPrescrubbedTopFbSize_dd2c0b(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return (NvU64)(-1); +} + +static inline NvU64 kgspGetPrescrubbedTopFbSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspGetPrescrubbedTopFbSize__(pGpu, pKernelGsp); +} + NV_STATUS kgspExtractVbiosFromRom_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg); static inline NV_STATUS kgspExtractVbiosFromRom_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspVbiosImg **ppVbiosImg) { @@ -711,6 +741,16 @@ static inline NV_STATUS kgspExecuteFwsecSb_DISPATCH(struct OBJGPU *pGpu, struct return pKernelGsp->__kgspExecuteFwsecSb__(pGpu, pKernelGsp, pFwsecUcode); } +NV_STATUS kgspExecuteScrubberIfNeeded_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +static inline NV_STATUS kgspExecuteScrubberIfNeeded_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED); +} + +static inline NV_STATUS kgspExecuteScrubberIfNeeded_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return pKernelGsp->__kgspExecuteScrubberIfNeeded__(pGpu, pKernelGsp); +} + NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); static inline NV_STATUS kgspExecuteBooterLoad_5baef9(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset) { @@ -787,18 +827,40 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_DISPATCH return pKernelGsp->__kgspGetBinArchiveBooterUnloadUcode__(pKernelGsp); } -static inline NvU64 kgspGetWprHeapSize_e77d51(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return (64 * 1024 * 1024); +static inline NvU64 kgspGetWprHeapSize_5661b8(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 64 * 1024 * 1024; } -static inline NvU64 kgspGetWprHeapSize_38f3bc(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - return (80 * 1024 * 1024); +static inline NvU64 kgspGetWprHeapSize_15390a(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + return 80 * 1024 * 1024; } +NvU64 kgspGetWprHeapSize_AD102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + static inline NvU64 kgspGetWprHeapSize_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { return pKernelGsp->__kgspGetWprHeapSize__(pGpu, pKernelGsp); } +static inline NV_STATUS kgspInitVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgspInitVgpuPartitionLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize); + +static inline NV_STATUS kgspInitVgpuPartitionLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid, NvU64 initTaskLogBUffOffset, NvU64 initTaskLogBUffSize, NvU64 vgpuTaskLogBUffOffset, NvU64 vgpuTaskLogBuffSize) { + return pKernelGsp->__kgspInitVgpuPartitionLogging__(pGpu, pKernelGsp, gfid, initTaskLogBUffOffset, initTaskLogBUffSize, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize); +} + +static inline NV_STATUS kgspFreeVgpuPartitionLogging_395e98(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid) { + return NV_ERR_NOT_SUPPORTED; +} + +NV_STATUS kgspFreeVgpuPartitionLogging_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid); + +static inline NV_STATUS kgspFreeVgpuPartitionLogging_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvU32 gfid) { + return pKernelGsp->__kgspFreeVgpuPartitionLogging__(pGpu, pKernelGsp, gfid); +} + const char *kgspGetSignatureSectionNamePrefix_GH100(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); static inline const char *kgspGetSignatureSectionNamePrefix_789efb(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { @@ -1034,6 +1096,17 @@ static inline NV_STATUS kgspParseFwsecUcodeFromVbiosImg(struct OBJGPU *pGpu, str #define kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode) kgspParseFwsecUcodeFromVbiosImg_IMPL(pGpu, pKernelGsp, pVbiosImg, ppFwsecUcode) #endif //__nvoc_kernel_gsp_h_disabled +NV_STATUS kgspAllocateScrubberUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppScrubberUcode); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspAllocateScrubberUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppScrubberUcode) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspAllocateScrubberUcodeImage(pGpu, pKernelGsp, ppScrubberUcode) kgspAllocateScrubberUcodeImage_IMPL(pGpu, pKernelGsp, ppScrubberUcode) +#endif //__nvoc_kernel_gsp_h_disabled + NV_STATUS kgspAllocateBooterLoadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterLoadUcode); #ifdef __nvoc_kernel_gsp_h_disabled diff --git a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h index a47492319..788adf527 100644 --- a/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h +++ b/src/nvidia/generated/g_kernel_hostvgpudeviceapi_nvoc.h @@ -149,7 +149,7 @@ struct KernelHostVgpuDeviceApi { NV_STATUS (*__kernelhostvgpudeviceapiMap__)(struct KernelHostVgpuDeviceApi *, CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, RsCpuMapping *); NvBool (*__kernelhostvgpudeviceapiAccessCallback__)(struct KernelHostVgpuDeviceApi *, struct RsClient *, void *, RsAccessRight); struct KernelHostVgpuDeviceShr *pShared; - NvU32 notifyActions[5]; + NvU32 notifyActions[6]; }; #ifndef __NVOC_CLASS_KernelHostVgpuDeviceApi_TYPEDEF__ diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.c b/src/nvidia/generated/g_kernel_nvlink_nvoc.c index cf057ccff..c5a357d4b 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.c +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.c @@ -341,6 +341,20 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO } } + // Hal function -- knvlinkHandleFaultUpInterrupt + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */ + { + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_GH100; + } + // default + else + { + pThis->__knvlinkHandleFaultUpInterrupt__ = &knvlinkHandleFaultUpInterrupt_46f6a7; + } + } + // Hal function -- knvlinkValidateFabricBaseAddress if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { diff --git a/src/nvidia/generated/g_kernel_nvlink_nvoc.h b/src/nvidia/generated/g_kernel_nvlink_nvoc.h index e8af2d6da..7d35edb3d 100644 --- a/src/nvidia/generated/g_kernel_nvlink_nvoc.h +++ b/src/nvidia/generated/g_kernel_nvlink_nvoc.h @@ -38,6 +38,7 @@ extern "C" { #include "core/locks.h" #include "gpu/eng_state.h" #include "lib/ref_count.h" +#include "objtmr.h" #include "nvCpuUuid.h" #include "gpu/bus/kern_bus.h" @@ -98,6 +99,9 @@ typedef struct _def_knvlink_conn_info #define NVLINK_INITOPTIMIZE_POLL_TIMEOUT_EMU 20000000 #define NVLINK_INITOPTIMIZE_POLL_COUNT_DELAY_MS 1000 +// Link Retrain after reset time = 10s +#define NVLINK_RETRAIN_TIME 10000000000 + /**********************************************************/ // NvGpu identifier in nvlink core library @@ -179,6 +183,8 @@ typedef struct _def_knvlink_link // RXDET per-lane status NvU32 laneRxdetStatusMask; + TMR_EVENT *pTmrEvent; + } KNVLINK_RM_LINK, *PKNVLINK_RM_LINK; typedef struct NVLINK_INBAND_CALLBACK @@ -189,6 +195,12 @@ typedef struct NVLINK_INBAND_CALLBACK NvU32 wqItemFlags; } NVLINK_INBAND_MSG_CALLBACK; +typedef struct +{ + NvU8 linkId; +} NVLINK_ID, *PNVLINK_ID; + +MAKE_LIST(FaultUpList, NVLINK_ID); /*! * KernelNvlink is a logical abstraction of the GPU Nvlink Engine. The @@ -215,6 +227,7 @@ struct KernelNvlink { NV_STATUS (*__knvlinkStatePostUnload__)(OBJGPU *, struct KernelNvlink *, NvU32); NvBool (*__knvlinkIsPresent__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); + NV_STATUS (*__knvlinkHandleFaultUpInterrupt__)(OBJGPU *, struct KernelNvlink *, NvU32); NV_STATUS (*__knvlinkValidateFabricBaseAddress__)(OBJGPU *, struct KernelNvlink *, NvU64); NvU32 (*__knvlinkGetConnectedLinksMask__)(OBJGPU *, struct KernelNvlink *); NV_STATUS (*__knvlinkEnableLinksPostTopology__)(OBJGPU *, struct KernelNvlink *, NvU32); @@ -283,6 +296,7 @@ struct KernelNvlink { NvU32 bridgeSensableLinks; NvU32 bridgedLinks; NvU32 enabledLinks; + FaultUpList faultUpLinks; NvU32 initializedLinks; KNVLINK_RM_LINK nvlinkLinks[18]; NvBool bIsGpuDegraded; @@ -381,6 +395,8 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32); #define knvlinkIsPresent(arg0, arg1) knvlinkIsPresent_DISPATCH(arg0, arg1) #define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) +#define knvlinkHandleFaultUpInterrupt(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) +#define knvlinkHandleFaultUpInterrupt_HAL(pGpu, pKernelNvlink, arg0) knvlinkHandleFaultUpInterrupt_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkValidateFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg0) knvlinkValidateFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg0) #define knvlinkGetConnectedLinksMask(pGpu, pKernelNvlink) knvlinkGetConnectedLinksMask_DISPATCH(pGpu, pKernelNvlink) @@ -1351,6 +1367,16 @@ static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(OBJGPU *pGpu, return pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__(pGpu, pKernelNvlink, arg0); } +NV_STATUS knvlinkHandleFaultUpInterrupt_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0); + +static inline NV_STATUS knvlinkHandleFaultUpInterrupt_46f6a7(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { + return NV_ERR_NOT_SUPPORTED; +} + +static inline NV_STATUS knvlinkHandleFaultUpInterrupt_DISPATCH(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU32 arg0) { + return pKernelNvlink->__knvlinkHandleFaultUpInterrupt__(pGpu, pKernelNvlink, arg0); +} + NV_STATUS knvlinkValidateFabricBaseAddress_GA100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); NV_STATUS knvlinkValidateFabricBaseAddress_GH100(OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg0); @@ -1640,7 +1666,7 @@ NV_STATUS knvlinkRetrainLinkFromSafe(OBJGPU *pGpu, struct KernelNvlink *pKernelN // NVLINK Callback functions from core library // #if defined(INCLUDE_NVLINK_LIB) - + // Device callback functions NvlStatus knvlinkCoreAddDeviceCallback (nvlink_device *dev); @@ -1674,6 +1700,8 @@ NvlStatus knvlinkCoreAliTrainingCallback (nvlink_link *link); // NVLINK Utility Functions void knvlinkUtoa(NvU8 *, NvU64, NvU64); +NV_STATUS ioctrlFaultUpTmrHandler(OBJGPU *, struct OBJTMR *,TMR_EVENT *); + #endif // _KERNEL_NVLINK_H_ #ifdef __cplusplus diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.c b/src/nvidia/generated/g_kernel_sec2_nvoc.c index fbd17dbba..8e75e56cc 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.c +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.c @@ -314,6 +314,19 @@ static void __nvoc_init_funcTable_KernelSec2_1(KernelSec2 *pThis, RmHalspecOwner } } + // Hal function -- ksec2GetBinArchiveSecurescrubUcode + if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */ + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_AD10X; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x1000ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | GH100 */ + { + pThis->__ksec2GetBinArchiveSecurescrubUcode__ = &ksec2GetBinArchiveSecurescrubUcode_80f438; + } + } + pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelSec2_engstateConstructEngine; pThis->__nvoc_base_KernelFalcon.__kflcnResetHw__ = &__nvoc_thunk_KernelSec2_kflcnResetHw; diff --git a/src/nvidia/generated/g_kernel_sec2_nvoc.h b/src/nvidia/generated/g_kernel_sec2_nvoc.h index bfd97083d..4a371ff5f 100644 --- a/src/nvidia/generated/g_kernel_sec2_nvoc.h +++ b/src/nvidia/generated/g_kernel_sec2_nvoc.h @@ -64,6 +64,7 @@ struct KernelSec2 { NvU32 (*__ksec2ReadUcodeFuseVersion__)(struct OBJGPU *, struct KernelSec2 *, NvU32); const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveBlUcode__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2GetGenericBlUcode__)(struct OBJGPU *, struct KernelSec2 *, const RM_FLCN_BL_DESC **, const NvU8 **); + const BINDATA_ARCHIVE *(*__ksec2GetBinArchiveSecurescrubUcode__)(struct OBJGPU *, struct KernelSec2 *); NV_STATUS (*__ksec2ReconcileTunableState__)(POBJGPU, struct KernelSec2 *, void *); NV_STATUS (*__ksec2StateLoad__)(POBJGPU, struct KernelSec2 *, NvU32); NV_STATUS (*__ksec2StateUnload__)(POBJGPU, struct KernelSec2 *, NvU32); @@ -131,6 +132,8 @@ NV_STATUS __nvoc_objCreate_KernelSec2(KernelSec2**, Dynamic*, NvU32); #define ksec2GetBinArchiveBlUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveBlUcode_DISPATCH(pGpu, pKernelSec2) #define ksec2GetGenericBlUcode(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) #define ksec2GetGenericBlUcode_HAL(pGpu, pKernelSec2, ppDesc, ppImg) ksec2GetGenericBlUcode_DISPATCH(pGpu, pKernelSec2, ppDesc, ppImg) +#define ksec2GetBinArchiveSecurescrubUcode(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) +#define ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2) ksec2GetBinArchiveSecurescrubUcode_DISPATCH(pGpu, pKernelSec2) #define ksec2ReconcileTunableState(pGpu, pEngstate, pTunableState) ksec2ReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define ksec2StateLoad(pGpu, pEngstate, arg0) ksec2StateLoad_DISPATCH(pGpu, pEngstate, arg0) #define ksec2StateUnload(pGpu, pEngstate, arg0) ksec2StateUnload_DISPATCH(pGpu, pEngstate, arg0) @@ -220,6 +223,16 @@ static inline NV_STATUS ksec2GetGenericBlUcode_DISPATCH(struct OBJGPU *pGpu, str return pKernelSec2->__ksec2GetGenericBlUcode__(pGpu, pKernelSec2, ppDesc, ppImg); } +const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_AD10X(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2); + +static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_80f438(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); +} + +static inline const BINDATA_ARCHIVE *ksec2GetBinArchiveSecurescrubUcode_DISPATCH(struct OBJGPU *pGpu, struct KernelSec2 *pKernelSec2) { + return pKernelSec2->__ksec2GetBinArchiveSecurescrubUcode__(pGpu, pKernelSec2); +} + static inline NV_STATUS ksec2ReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelSec2 *pEngstate, void *pTunableState) { return pEngstate->__ksec2ReconcileTunableState__(pGpu, pEngstate, pTunableState); } diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index e77bfa394..9ffc76efe 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -808,8 +808,8 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" }, { 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" }, { 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" }, - { 0x20B3, 0x14a7, 0x10de, "NVIDIA PG506-242" }, - { 0x20B3, 0x14a8, 0x10de, "NVIDIA PG506-243" }, + { 0x20B3, 0x14a7, 0x10de, "NVIDIA A100-SXM-64GB" }, + { 0x20B3, 0x14a8, 0x10de, "NVIDIA A100-SXM-64GB" }, { 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" }, { 0x20B5, 0x1642, 0x10de, "NVIDIA A100 80GB PCIe" }, { 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" }, @@ -935,6 +935,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2571, 0x1611, 0x103c, "NVIDIA RTX A2000 12GB" }, { 0x2571, 0x1611, 0x10de, "NVIDIA RTX A2000 12GB" }, { 0x2571, 0x1611, 0x17aa, "NVIDIA RTX A2000 12GB" }, + { 0x2582, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050" }, { 0x25A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 3050 Ti Laptop GPU" }, { 0x25A0, 0x8928, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" }, { 0x25A0, 0x89f9, 0x103c, "NVIDIA GeForce RTX 3050Ti Laptop GPU" }, @@ -960,9 +961,13 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25FA, 0x0000, 0x0000, "NVIDIA RTX A2000 Embedded GPU" }, { 0x25FB, 0x0000, 0x0000, "NVIDIA RTX A500 Embedded GPU" }, { 0x2684, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090" }, + { 0x26B1, 0x16a1, 0x1028, "NVIDIA RTX 6000 Ada Generation" }, + { 0x26B1, 0x16a1, 0x103c, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" }, + { 0x26B1, 0x16a1, 0x17aa, "NVIDIA RTX 6000 Ada Generation" }, { 0x26B5, 0x169d, 0x10de, "NVIDIA L40" }, { 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" }, + { 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" }, { 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" }, { 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" }, { 0x13BD, 0x11ce, 0x10DE, "GRID M10-0Q" }, @@ -970,6 +975,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13BD, 0x11d0, 0x10DE, "GRID M10-2Q" }, { 0x13BD, 0x11d1, 0x10DE, "GRID M10-4Q" }, { 0x13BD, 0x11d2, 0x10DE, "GRID M10-8Q" }, + { 0x13BD, 0x11d3, 0x10DE, "GRID M10-1A" }, + { 0x13BD, 0x11d4, 0x10DE, "GRID M10-2A" }, + { 0x13BD, 0x11d5, 0x10DE, "GRID M10-4A" }, + { 0x13BD, 0x11d6, 0x10DE, "GRID M10-8A" }, { 0x13BD, 0x1286, 0x10DE, "GRID M10-2B" }, { 0x13BD, 0x12ee, 0x10DE, "GRID M10-2B4" }, { 0x13BD, 0x1339, 0x10DE, "GRID M10-1B4" }, @@ -981,6 +990,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F2, 0x1176, 0x10DE, "GRID M60-0B" }, { 0x13F2, 0x1177, 0x10DE, "GRID M60-1B" }, { 0x13F2, 0x117d, 0x10DE, "GRID M60-2B" }, + { 0x13F2, 0x11ae, 0x10DE, "GRID M60-1A" }, + { 0x13F2, 0x11af, 0x10DE, "GRID M60-2A" }, + { 0x13F2, 0x11b0, 0x10DE, "GRID M60-4A" }, + { 0x13F2, 0x11b1, 0x10DE, "GRID M60-8A" }, { 0x13F2, 0x12ec, 0x10DE, "GRID M60-2B4" }, { 0x13F2, 0x1337, 0x10DE, "GRID M60-1B4" }, { 0x13F3, 0x117c, 0x10DE, "GRID M6-2B" }, @@ -991,6 +1004,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x13F3, 0x1182, 0x10DE, "GRID M6-2Q" }, { 0x13F3, 0x1183, 0x10DE, "GRID M6-4Q" }, { 0x13F3, 0x1184, 0x10DE, "GRID M6-8Q" }, + { 0x13F3, 0x11aa, 0x10DE, "GRID M6-1A" }, + { 0x13F3, 0x11ab, 0x10DE, "GRID M6-2A" }, + { 0x13F3, 0x11ac, 0x10DE, "GRID M6-4A" }, + { 0x13F3, 0x11ad, 0x10DE, "GRID M6-8A" }, { 0x13F3, 0x12ed, 0x10DE, "GRID M6-2B4" }, { 0x13F3, 0x1338, 0x10DE, "GRID M6-1B4" }, { 0x15F7, 0x1265, 0x10DE, "GRID P100C-1B" }, @@ -999,6 +1016,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F7, 0x1268, 0x10DE, "GRID P100C-4Q" }, { 0x15F7, 0x1269, 0x10DE, "GRID P100C-6Q" }, { 0x15F7, 0x126a, 0x10DE, "GRID P100C-12Q" }, + { 0x15F7, 0x126b, 0x10DE, "GRID P100C-1A" }, + { 0x15F7, 0x126c, 0x10DE, "GRID P100C-2A" }, + { 0x15F7, 0x126d, 0x10DE, "GRID P100C-4A" }, + { 0x15F7, 0x126e, 0x10DE, "GRID P100C-6A" }, + { 0x15F7, 0x126f, 0x10DE, "GRID P100C-12A" }, { 0x15F7, 0x128d, 0x10DE, "GRID P100C-2B" }, { 0x15F7, 0x12f4, 0x10DE, "GRID P100C-2B4" }, { 0x15F7, 0x133f, 0x10DE, "GRID P100C-1B4" }, @@ -1011,6 +1033,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F8, 0x1224, 0x10DE, "GRID P100-4Q" }, { 0x15F8, 0x1225, 0x10DE, "GRID P100-8Q" }, { 0x15F8, 0x1226, 0x10DE, "GRID P100-16Q" }, + { 0x15F8, 0x1227, 0x10DE, "GRID P100-1A" }, + { 0x15F8, 0x1228, 0x10DE, "GRID P100-2A" }, + { 0x15F8, 0x1229, 0x10DE, "GRID P100-4A" }, + { 0x15F8, 0x122a, 0x10DE, "GRID P100-8A" }, + { 0x15F8, 0x122b, 0x10DE, "GRID P100-16A" }, { 0x15F8, 0x128c, 0x10DE, "GRID P100-2B" }, { 0x15F8, 0x12f2, 0x10DE, "GRID P100-2B4" }, { 0x15F8, 0x133d, 0x10DE, "GRID P100-1B4" }, @@ -1023,6 +1050,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x15F9, 0x122f, 0x10DE, "GRID P100X-4Q" }, { 0x15F9, 0x1230, 0x10DE, "GRID P100X-8Q" }, { 0x15F9, 0x1231, 0x10DE, "GRID P100X-16Q" }, + { 0x15F9, 0x1232, 0x10DE, "GRID P100X-1A" }, + { 0x15F9, 0x1233, 0x10DE, "GRID P100X-2A" }, + { 0x15F9, 0x1234, 0x10DE, "GRID P100X-4A" }, + { 0x15F9, 0x1235, 0x10DE, "GRID P100X-8A" }, + { 0x15F9, 0x1236, 0x10DE, "GRID P100X-16A" }, { 0x15F9, 0x128b, 0x10DE, "GRID P100X-2B" }, { 0x15F9, 0x12f3, 0x10DE, "GRID P100X-2B4" }, { 0x15F9, 0x133e, 0x10DE, "GRID P100X-1B4" }, @@ -1038,6 +1070,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1B38, 0x11ed, 0x10DE, "GRID P40-8Q" }, { 0x1B38, 0x11ee, 0x10DE, "GRID P40-12Q" }, { 0x1B38, 0x11ef, 0x10DE, "GRID P40-24Q" }, + { 0x1B38, 0x11f0, 0x10DE, "GRID P40-1A" }, + { 0x1B38, 0x11f1, 0x10DE, "GRID P40-2A" }, + { 0x1B38, 0x11f2, 0x10DE, "GRID P40-3A" }, + { 0x1B38, 0x11f3, 0x10DE, "GRID P40-4A" }, + { 0x1B38, 0x11f4, 0x10DE, "GRID P40-6A" }, + { 0x1B38, 0x11f5, 0x10DE, "GRID P40-8A" }, + { 0x1B38, 0x11f6, 0x10DE, "GRID P40-12A" }, + { 0x1B38, 0x11f7, 0x10DE, "GRID P40-24A" }, { 0x1B38, 0x1287, 0x10DE, "GRID P40-2B" }, { 0x1B38, 0x12b1, 0x10DE, "GeForce GTX P40-24" }, { 0x1B38, 0x12b2, 0x10DE, "GeForce GTX P40-12" }, @@ -1058,6 +1098,10 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB3, 0x1205, 0x10DE, "GRID P4-2Q" }, { 0x1BB3, 0x1206, 0x10DE, "GRID P4-4Q" }, { 0x1BB3, 0x1207, 0x10DE, "GRID P4-8Q" }, + { 0x1BB3, 0x1208, 0x10DE, "GRID P4-1A" }, + { 0x1BB3, 0x1209, 0x10DE, "GRID P4-2A" }, + { 0x1BB3, 0x120a, 0x10DE, "GRID P4-4A" }, + { 0x1BB3, 0x120b, 0x10DE, "GRID P4-8A" }, { 0x1BB3, 0x1288, 0x10DE, "GRID P4-2B" }, { 0x1BB3, 0x12f1, 0x10DE, "GRID P4-2B4" }, { 0x1BB3, 0x133c, 0x10DE, "GRID P4-1B4" }, @@ -1072,6 +1116,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1BB4, 0x11fb, 0x10DE, "GRID P6-4Q" }, { 0x1BB4, 0x11fc, 0x10DE, "GRID P6-8Q" }, { 0x1BB4, 0x11fd, 0x10DE, "GRID P6-16Q" }, + { 0x1BB4, 0x11fe, 0x10DE, "GRID P6-1A" }, + { 0x1BB4, 0x11ff, 0x10DE, "GRID P6-2A" }, + { 0x1BB4, 0x1200, 0x10DE, "GRID P6-4A" }, + { 0x1BB4, 0x1201, 0x10DE, "GRID P6-8A" }, + { 0x1BB4, 0x1202, 0x10DE, "GRID P6-16A" }, { 0x1BB4, 0x1289, 0x10DE, "GRID P6-2B" }, { 0x1BB4, 0x12f0, 0x10DE, "GRID P6-2B4" }, { 0x1BB4, 0x133b, 0x10DE, "GRID P6-1B4" }, @@ -1084,6 +1133,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB1, 0x125c, 0x10DE, "GRID V100X-4Q" }, { 0x1DB1, 0x125d, 0x10DE, "GRID V100X-8Q" }, { 0x1DB1, 0x125e, 0x10DE, "GRID V100X-16Q" }, + { 0x1DB1, 0x125f, 0x10DE, "GRID V100X-1A" }, + { 0x1DB1, 0x1260, 0x10DE, "GRID V100X-2A" }, + { 0x1DB1, 0x1261, 0x10DE, "GRID V100X-4A" }, + { 0x1DB1, 0x1262, 0x10DE, "GRID V100X-8A" }, + { 0x1DB1, 0x1263, 0x10DE, "GRID V100X-16A" }, { 0x1DB1, 0x128e, 0x10DE, "GRID V100X-2B" }, { 0x1DB1, 0x12f6, 0x10DE, "GRID V100X-2B4" }, { 0x1DB1, 0x1341, 0x10DE, "GRID V100X-1B4" }, @@ -1097,6 +1151,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB3, 0x1294, 0x10DE, "GRID V100L-4Q" }, { 0x1DB3, 0x1295, 0x10DE, "GRID V100L-8Q" }, { 0x1DB3, 0x1296, 0x10DE, "GRID V100L-16Q" }, + { 0x1DB3, 0x1297, 0x10DE, "GRID V100L-1A" }, + { 0x1DB3, 0x1298, 0x10DE, "GRID V100L-2A" }, + { 0x1DB3, 0x1299, 0x10DE, "GRID V100L-4A" }, + { 0x1DB3, 0x129a, 0x10DE, "GRID V100L-8A" }, + { 0x1DB3, 0x129b, 0x10DE, "GRID V100L-16A" }, { 0x1DB3, 0x12f9, 0x10DE, "GRID V100L-2B4" }, { 0x1DB3, 0x1344, 0x10DE, "GRID V100L-1B4" }, { 0x1DB3, 0x137a, 0x10DE, "GRID V100L-16C" }, @@ -1108,6 +1167,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB4, 0x1251, 0x10DE, "GRID V100-4Q" }, { 0x1DB4, 0x1252, 0x10DE, "GRID V100-8Q" }, { 0x1DB4, 0x1253, 0x10DE, "GRID V100-16Q" }, + { 0x1DB4, 0x1254, 0x10DE, "GRID V100-1A" }, + { 0x1DB4, 0x1255, 0x10DE, "GRID V100-2A" }, + { 0x1DB4, 0x1256, 0x10DE, "GRID V100-4A" }, + { 0x1DB4, 0x1257, 0x10DE, "GRID V100-8A" }, + { 0x1DB4, 0x1258, 0x10DE, "GRID V100-16A" }, { 0x1DB4, 0x128f, 0x10DE, "GRID V100-2B" }, { 0x1DB4, 0x12f5, 0x10DE, "GRID V100-2B4" }, { 0x1DB4, 0x1340, 0x10DE, "GRID V100-1B4" }, @@ -1122,6 +1186,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB5, 0x12d0, 0x10DE, "GRID V100DX-8Q" }, { 0x1DB5, 0x12d1, 0x10DE, "GRID V100DX-16Q" }, { 0x1DB5, 0x12d2, 0x10DE, "GRID V100DX-32Q" }, + { 0x1DB5, 0x12d3, 0x10DE, "GRID V100DX-1A" }, + { 0x1DB5, 0x12d4, 0x10DE, "GRID V100DX-2A" }, + { 0x1DB5, 0x12d5, 0x10DE, "GRID V100DX-4A" }, + { 0x1DB5, 0x12d6, 0x10DE, "GRID V100DX-8A" }, + { 0x1DB5, 0x12d7, 0x10DE, "GRID V100DX-16A" }, + { 0x1DB5, 0x12d8, 0x10DE, "GRID V100DX-32A" }, { 0x1DB5, 0x12f8, 0x10DE, "GRID V100DX-2B4" }, { 0x1DB5, 0x1343, 0x10DE, "GRID V100DX-1B4" }, { 0x1DB5, 0x1376, 0x10DE, "GRID V100DX-32C" }, @@ -1136,6 +1206,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DB6, 0x12c2, 0x10DE, "GRID V100D-8Q" }, { 0x1DB6, 0x12c3, 0x10DE, "GRID V100D-16Q" }, { 0x1DB6, 0x12c4, 0x10DE, "GRID V100D-32Q" }, + { 0x1DB6, 0x12c5, 0x10DE, "GRID V100D-1A" }, + { 0x1DB6, 0x12c6, 0x10DE, "GRID V100D-2A" }, + { 0x1DB6, 0x12c7, 0x10DE, "GRID V100D-4A" }, + { 0x1DB6, 0x12c8, 0x10DE, "GRID V100D-8A" }, + { 0x1DB6, 0x12c9, 0x10DE, "GRID V100D-16A" }, + { 0x1DB6, 0x12ca, 0x10DE, "GRID V100D-32A" }, { 0x1DB6, 0x12f7, 0x10DE, "GRID V100D-2B4" }, { 0x1DB6, 0x1342, 0x10DE, "GRID V100D-1B4" }, { 0x1DB6, 0x1377, 0x10DE, "GRID V100D-32C" }, @@ -1153,6 +1229,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1DF6, 0x13e8, 0x10DE, "GRID V100S-8Q" }, { 0x1DF6, 0x13e9, 0x10DE, "GRID V100S-16Q" }, { 0x1DF6, 0x13ea, 0x10DE, "GRID V100S-32Q" }, + { 0x1DF6, 0x13eb, 0x10DE, "GRID V100S-1A" }, + { 0x1DF6, 0x13ec, 0x10DE, "GRID V100S-2A" }, + { 0x1DF6, 0x13ed, 0x10DE, "GRID V100S-4A" }, + { 0x1DF6, 0x13ee, 0x10DE, "GRID V100S-8A" }, + { 0x1DF6, 0x13ef, 0x10DE, "GRID V100S-16A" }, + { 0x1DF6, 0x13f0, 0x10DE, "GRID V100S-32A" }, { 0x1DF6, 0x13f1, 0x10DE, "GRID V100S-4C" }, { 0x1DF6, 0x13f2, 0x10DE, "GRID V100S-8C" }, { 0x1DF6, 0x13f3, 0x10DE, "GRID V100S-16C" }, @@ -1197,8 +1279,26 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E30, 0x13cc, 0x10DE, "GRID RTX8000-16" }, { 0x1E30, 0x1437, 0x10DE, "GRID RTX6000-1B" }, { 0x1E30, 0x1438, 0x10DE, "GRID RTX6000-2B" }, + { 0x1E30, 0x1439, 0x10DE, "GRID RTX6000-1A" }, + { 0x1E30, 0x143a, 0x10DE, "GRID RTX6000-2A" }, + { 0x1E30, 0x143b, 0x10DE, "GRID RTX6000-3A" }, + { 0x1E30, 0x143c, 0x10DE, "GRID RTX6000-4A" }, + { 0x1E30, 0x143d, 0x10DE, "GRID RTX6000-6A" }, + { 0x1E30, 0x143e, 0x10DE, "GRID RTX6000-8A" }, + { 0x1E30, 0x143f, 0x10DE, "GRID RTX6000-12A" }, + { 0x1E30, 0x1440, 0x10DE, "GRID RTX6000-24A" }, { 0x1E30, 0x1441, 0x10DE, "GRID RTX8000-1B" }, { 0x1E30, 0x1442, 0x10DE, "GRID RTX8000-2B" }, + { 0x1E30, 0x1443, 0x10DE, "GRID RTX8000-1A" }, + { 0x1E30, 0x1444, 0x10DE, "GRID RTX8000-2A" }, + { 0x1E30, 0x1445, 0x10DE, "GRID RTX8000-3A" }, + { 0x1E30, 0x1446, 0x10DE, "GRID RTX8000-4A" }, + { 0x1E30, 0x1447, 0x10DE, "GRID RTX8000-6A" }, + { 0x1E30, 0x1448, 0x10DE, "GRID RTX8000-8A" }, + { 0x1E30, 0x1449, 0x10DE, "GRID RTX8000-12A" }, + { 0x1E30, 0x144a, 0x10DE, "GRID RTX8000-16A" }, + { 0x1E30, 0x144b, 0x10DE, "GRID RTX8000-24A" }, + { 0x1E30, 0x144c, 0x10DE, "GRID RTX8000-48A" }, { 0x1E37, 0x1347, 0x10DE, "GeForce RTX T10x-8" }, { 0x1E37, 0x1348, 0x10DE, "GeForce RTX T10x-4" }, { 0x1E37, 0x1349, 0x10DE, "GeForce RTX T10x-2" }, @@ -1224,6 +1324,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x13fe, 0x10DE, "GRID RTX6000P-8Q" }, { 0x1E78, 0x13ff, 0x10DE, "GRID RTX6000P-12Q" }, { 0x1E78, 0x1400, 0x10DE, "GRID RTX6000P-24Q" }, + { 0x1E78, 0x1401, 0x10DE, "GRID RTX6000P-1A" }, + { 0x1E78, 0x1402, 0x10DE, "GRID RTX6000P-2A" }, + { 0x1E78, 0x1403, 0x10DE, "GRID RTX6000P-3A" }, + { 0x1E78, 0x1404, 0x10DE, "GRID RTX6000P-4A" }, + { 0x1E78, 0x1405, 0x10DE, "GRID RTX6000P-6A" }, + { 0x1E78, 0x1406, 0x10DE, "GRID RTX6000P-8A" }, + { 0x1E78, 0x1407, 0x10DE, "GRID RTX6000P-12A" }, + { 0x1E78, 0x1408, 0x10DE, "GRID RTX6000P-24A" }, { 0x1E78, 0x1409, 0x10DE, "GRID RTX6000P-6" }, { 0x1E78, 0x140a, 0x10DE, "GRID RTX6000P-8" }, { 0x1E78, 0x140b, 0x10DE, "GRID RTX6000P-12" }, @@ -1245,6 +1353,15 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x141b, 0x10DE, "GRID RTX8000P-16Q" }, { 0x1E78, 0x141c, 0x10DE, "GRID RTX8000P-24Q" }, { 0x1E78, 0x141d, 0x10DE, "GRID RTX8000P-48Q" }, + { 0x1E78, 0x141e, 0x10DE, "GRID RTX8000P-1A" }, + { 0x1E78, 0x141f, 0x10DE, "GRID RTX8000P-2A" }, + { 0x1E78, 0x1420, 0x10DE, "GRID RTX8000P-3A" }, + { 0x1E78, 0x1421, 0x10DE, "GRID RTX8000P-4A" }, + { 0x1E78, 0x1422, 0x10DE, "GRID RTX8000P-6A" }, + { 0x1E78, 0x1423, 0x10DE, "GRID RTX8000P-8A" }, + { 0x1E78, 0x1424, 0x10DE, "GRID RTX8000P-12A" }, + { 0x1E78, 0x1425, 0x10DE, "GRID RTX8000P-24A" }, + { 0x1E78, 0x1426, 0x10DE, "GRID RTX8000P-48A" }, { 0x1E78, 0x1427, 0x10DE, "GRID RTX8000P-12" }, { 0x1E78, 0x1428, 0x10DE, "GRID RTX8000P-16" }, { 0x1E78, 0x1429, 0x10DE, "GRID RTX8000P-24" }, @@ -1256,6 +1373,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1E78, 0x142f, 0x10DE, "GRID RTX8000P-16C" }, { 0x1E78, 0x1430, 0x10DE, "GRID RTX8000P-24C" }, { 0x1E78, 0x1431, 0x10DE, "GRID RTX8000P-48C" }, + { 0x1E78, 0x1436, 0x10DE, "GRID RTX8000P-16A" }, { 0x1EB8, 0x1309, 0x10DE, "GRID T4-1B" }, { 0x1EB8, 0x130a, 0x10DE, "GRID T4-2B" }, { 0x1EB8, 0x130b, 0x10DE, "GRID T4-2B4" }, @@ -1264,6 +1382,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x1EB8, 0x130e, 0x10DE, "GRID T4-4Q" }, { 0x1EB8, 0x130f, 0x10DE, "GRID T4-8Q" }, { 0x1EB8, 0x1310, 0x10DE, "GRID T4-16Q" }, + { 0x1EB8, 0x1311, 0x10DE, "GRID T4-1A" }, + { 0x1EB8, 0x1312, 0x10DE, "GRID T4-2A" }, + { 0x1EB8, 0x1313, 0x10DE, "GRID T4-4A" }, + { 0x1EB8, 0x1314, 0x10DE, "GRID T4-8A" }, + { 0x1EB8, 0x1315, 0x10DE, "GRID T4-16A" }, { 0x1EB8, 0x1345, 0x10DE, "GRID T4-1B4" }, { 0x1EB8, 0x1367, 0x10DE, "GRID RTX T4-4" }, { 0x1EB8, 0x1368, 0x10DE, "GRID RTX T4-8" }, @@ -1382,6 +1505,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2230, 0x1503, 0x10DE, "NVIDIA RTXA6000-16Q" }, { 0x2230, 0x1504, 0x10DE, "NVIDIA RTXA6000-24Q" }, { 0x2230, 0x1505, 0x10DE, "NVIDIA RTXA6000-48Q" }, + { 0x2230, 0x1506, 0x10DE, "NVIDIA RTXA6000-1A" }, + { 0x2230, 0x1507, 0x10DE, "NVIDIA RTXA6000-2A" }, + { 0x2230, 0x1508, 0x10DE, "NVIDIA RTXA6000-3A" }, + { 0x2230, 0x1509, 0x10DE, "NVIDIA RTXA6000-4A" }, + { 0x2230, 0x150a, 0x10DE, "NVIDIA RTXA6000-6A" }, + { 0x2230, 0x150b, 0x10DE, "NVIDIA RTXA6000-8A" }, + { 0x2230, 0x150c, 0x10DE, "NVIDIA RTXA6000-12A" }, + { 0x2230, 0x150d, 0x10DE, "NVIDIA RTXA6000-16A" }, + { 0x2230, 0x150e, 0x10DE, "NVIDIA RTXA6000-24A" }, + { 0x2230, 0x150f, 0x10DE, "NVIDIA RTXA6000-48A" }, { 0x2230, 0x1510, 0x10DE, "NVIDIA RTXA6000-12" }, { 0x2230, 0x1511, 0x10DE, "NVIDIA RTXA6000-16" }, { 0x2230, 0x1512, 0x10DE, "NVIDIA RTXA6000-24" }, @@ -1403,6 +1536,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2231, 0x1569, 0x10DE, "NVIDIA RTXA5000-8Q" }, { 0x2231, 0x156a, 0x10DE, "NVIDIA RTXA5000-12Q" }, { 0x2231, 0x156b, 0x10DE, "NVIDIA RTXA5000-24Q" }, + { 0x2231, 0x156c, 0x10DE, "NVIDIA RTXA5000-1A" }, + { 0x2231, 0x156d, 0x10DE, "NVIDIA RTXA5000-2A" }, + { 0x2231, 0x156e, 0x10DE, "NVIDIA RTXA5000-3A" }, + { 0x2231, 0x156f, 0x10DE, "NVIDIA RTXA5000-4A" }, + { 0x2231, 0x1570, 0x10DE, "NVIDIA RTXA5000-6A" }, + { 0x2231, 0x1571, 0x10DE, "NVIDIA RTXA5000-8A" }, + { 0x2231, 0x1572, 0x10DE, "NVIDIA RTXA5000-12A" }, + { 0x2231, 0x1573, 0x10DE, "NVIDIA RTXA5000-24A" }, { 0x2231, 0x1574, 0x10DE, "NVIDIA RTXA5000-6" }, { 0x2231, 0x1575, 0x10DE, "NVIDIA RTXA5000-8" }, { 0x2231, 0x1576, 0x10DE, "NVIDIA RTXA5000-12" }, @@ -1422,6 +1563,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2233, 0x1663, 0x10DE, "NVIDIA RTXA5500-8Q" }, { 0x2233, 0x1664, 0x10DE, "NVIDIA RTXA5500-12Q" }, { 0x2233, 0x1665, 0x10DE, "NVIDIA RTXA5500-24Q" }, + { 0x2233, 0x1666, 0x10DE, "NVIDIA RTXA5500-1A" }, + { 0x2233, 0x1667, 0x10DE, "NVIDIA RTXA5500-2A" }, + { 0x2233, 0x1668, 0x10DE, "NVIDIA RTXA5500-3A" }, + { 0x2233, 0x1669, 0x10DE, "NVIDIA RTXA5500-4A" }, + { 0x2233, 0x166a, 0x10DE, "NVIDIA RTXA5500-6A" }, + { 0x2233, 0x166b, 0x10DE, "NVIDIA RTXA5500-8A" }, + { 0x2233, 0x166c, 0x10DE, "NVIDIA RTXA5500-12A" }, + { 0x2233, 0x166d, 0x10DE, "NVIDIA RTXA5500-24A" }, { 0x2233, 0x166e, 0x10DE, "NVIDIA RTXA5500-6" }, { 0x2233, 0x166f, 0x10DE, "NVIDIA RTXA5500-8" }, { 0x2233, 0x1670, 0x10DE, "NVIDIA RTXA5500-12" }, @@ -1443,6 +1592,16 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2235, 0x14de, 0x10DE, "NVIDIA A40-16Q" }, { 0x2235, 0x14df, 0x10DE, "NVIDIA A40-24Q" }, { 0x2235, 0x14e0, 0x10DE, "NVIDIA A40-48Q" }, + { 0x2235, 0x14e1, 0x10DE, "NVIDIA A40-1A" }, + { 0x2235, 0x14e2, 0x10DE, "NVIDIA A40-2A" }, + { 0x2235, 0x14e3, 0x10DE, "NVIDIA A40-3A" }, + { 0x2235, 0x14e4, 0x10DE, "NVIDIA A40-4A" }, + { 0x2235, 0x14e5, 0x10DE, "NVIDIA A40-6A" }, + { 0x2235, 0x14e6, 0x10DE, "NVIDIA A40-8A" }, + { 0x2235, 0x14e7, 0x10DE, "NVIDIA A40-12A" }, + { 0x2235, 0x14e8, 0x10DE, "NVIDIA A40-16A" }, + { 0x2235, 0x14e9, 0x10DE, "NVIDIA A40-24A" }, + { 0x2235, 0x14ea, 0x10DE, "NVIDIA A40-48A" }, { 0x2235, 0x14eb, 0x10DE, "NVIDIA A40-12" }, { 0x2235, 0x14ec, 0x10DE, "NVIDIA A40-16" }, { 0x2235, 0x14ed, 0x10DE, "NVIDIA A40-24" }, @@ -1470,6 +1629,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2236, 0x14bd, 0x10DE, "NVIDIA A10-8Q" }, { 0x2236, 0x14be, 0x10DE, "NVIDIA A10-12Q" }, { 0x2236, 0x14bf, 0x10DE, "NVIDIA A10-24Q" }, + { 0x2236, 0x14c0, 0x10DE, "NVIDIA A10-1A" }, + { 0x2236, 0x14c1, 0x10DE, "NVIDIA A10-2A" }, + { 0x2236, 0x14c2, 0x10DE, "NVIDIA A10-3A" }, + { 0x2236, 0x14c3, 0x10DE, "NVIDIA A10-4A" }, + { 0x2236, 0x14c4, 0x10DE, "NVIDIA A10-6A" }, + { 0x2236, 0x14c5, 0x10DE, "NVIDIA A10-8A" }, + { 0x2236, 0x14c6, 0x10DE, "NVIDIA A10-12A" }, + { 0x2236, 0x14c7, 0x10DE, "NVIDIA A10-24A" }, { 0x2236, 0x14c8, 0x10DE, "NVIDIA A10-6" }, { 0x2236, 0x14c9, 0x10DE, "NVIDIA A10-8" }, { 0x2236, 0x14ca, 0x10DE, "NVIDIA A10-12" }, @@ -1501,6 +1668,14 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" }, { 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" }, { 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" }, + { 0x2237, 0x1634, 0x10DE, "NVIDIA A10G-1A" }, + { 0x2237, 0x1635, 0x10DE, "NVIDIA A10G-2A" }, + { 0x2237, 0x1636, 0x10DE, "NVIDIA A10G-3A" }, + { 0x2237, 0x1637, 0x10DE, "NVIDIA A10G-4A" }, + { 0x2237, 0x1638, 0x10DE, "NVIDIA A10G-6A" }, + { 0x2237, 0x1639, 0x10DE, "NVIDIA A10G-8A" }, + { 0x2237, 0x163a, 0x10DE, "NVIDIA A10G-12A" }, + { 0x2237, 0x163b, 0x10DE, "NVIDIA A10G-24A" }, { 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" }, { 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" }, { 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" }, @@ -1509,6 +1684,12 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16a8, 0x10DE, "NVIDIA A10M-5Q" }, { 0x2238, 0x16a9, 0x10DE, "NVIDIA A10M-10Q" }, { 0x2238, 0x16aa, 0x10DE, "NVIDIA A10M-20Q" }, + { 0x2238, 0x16ab, 0x10DE, "NVIDIA A10M-1A" }, + { 0x2238, 0x16ac, 0x10DE, "NVIDIA A10M-2A" }, + { 0x2238, 0x16ad, 0x10DE, "NVIDIA A10M-4A" }, + { 0x2238, 0x16ae, 0x10DE, "NVIDIA A10M-5A" }, + { 0x2238, 0x16af, 0x10DE, "NVIDIA A10M-10A" }, + { 0x2238, 0x16b0, 0x10DE, "NVIDIA A10M-20A" }, { 0x2238, 0x16b1, 0x10DE, "NVIDIA A10M-2" }, { 0x2238, 0x16b2, 0x10DE, "NVIDIA A10M-4" }, { 0x2238, 0x16b3, 0x10DE, "NVIDIA A10M-5" }, @@ -1519,6 +1700,20 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" }, { 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" }, { 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" }, + { 0x2322, 0x17e2, 0x10DE, "NVIDIA H800-1-10CME" }, + { 0x2322, 0x17e3, 0x10DE, "NVIDIA H800-1-10C" }, + { 0x2322, 0x17e4, 0x10DE, "NVIDIA H800-2-20C" }, + { 0x2322, 0x17e5, 0x10DE, "NVIDIA H800-3-40C" }, + { 0x2322, 0x17e6, 0x10DE, "NVIDIA H800-4-40C" }, + { 0x2322, 0x17e7, 0x10DE, "NVIDIA H800-7-80C" }, + { 0x2322, 0x17e8, 0x10DE, "NVIDIA H800-4C" }, + { 0x2322, 0x17e9, 0x10DE, "NVIDIA H800-5C" }, + { 0x2322, 0x17ea, 0x10DE, "NVIDIA H800-8C" }, + { 0x2322, 0x17eb, 0x10DE, "NVIDIA H800-10C" }, + { 0x2322, 0x17ec, 0x10DE, "NVIDIA H800-16C" }, + { 0x2322, 0x17ed, 0x10DE, "NVIDIA H800-20C" }, + { 0x2322, 0x17ee, 0x10DE, "NVIDIA H800-40C" }, + { 0x2322, 0x17ef, 0x10DE, "NVIDIA H800-80C" }, { 0x2331, 0x16d3, 0x10DE, "NVIDIA H100-1-10C" }, { 0x2331, 0x16d4, 0x10DE, "NVIDIA H100-2-20C" }, { 0x2331, 0x16d5, 0x10DE, "NVIDIA H100-3-40C" }, @@ -1540,6 +1735,11 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x1601, 0x10DE, "NVIDIA A16-4Q" }, { 0x25B6, 0x1602, 0x10DE, "NVIDIA A16-8Q" }, { 0x25B6, 0x1603, 0x10DE, "NVIDIA A16-16Q" }, + { 0x25B6, 0x1604, 0x10DE, "NVIDIA A16-1A" }, + { 0x25B6, 0x1605, 0x10DE, "NVIDIA A16-2A" }, + { 0x25B6, 0x1606, 0x10DE, "NVIDIA A16-4A" }, + { 0x25B6, 0x1607, 0x10DE, "NVIDIA A16-8A" }, + { 0x25B6, 0x1608, 0x10DE, "NVIDIA A16-16A" }, { 0x25B6, 0x1609, 0x10DE, "NVIDIA A16-4C" }, { 0x25B6, 0x160a, 0x10DE, "NVIDIA A16-8C" }, { 0x25B6, 0x160b, 0x10DE, "NVIDIA A16-16C" }, @@ -1550,12 +1750,157 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x25B6, 0x164a, 0x10DE, "NVIDIA A2-4Q" }, { 0x25B6, 0x164b, 0x10DE, "NVIDIA A2-8Q" }, { 0x25B6, 0x164c, 0x10DE, "NVIDIA A2-16Q" }, + { 0x25B6, 0x164d, 0x10DE, "NVIDIA A2-1A" }, + { 0x25B6, 0x164e, 0x10DE, "NVIDIA A2-2A" }, + { 0x25B6, 0x164f, 0x10DE, "NVIDIA A2-4A" }, + { 0x25B6, 0x1650, 0x10DE, "NVIDIA A2-8A" }, + { 0x25B6, 0x1651, 0x10DE, "NVIDIA A2-16A" }, { 0x25B6, 0x1652, 0x10DE, "NVIDIA A2-4" }, { 0x25B6, 0x1653, 0x10DE, "NVIDIA A2-8" }, { 0x25B6, 0x1654, 0x10DE, "NVIDIA A2-16" }, { 0x25B6, 0x1655, 0x10DE, "NVIDIA A2-4C" }, { 0x25B6, 0x1656, 0x10DE, "NVIDIA A2-8C" }, { 0x25B6, 0x1657, 0x10DE, "NVIDIA A2-16C" }, + { 0x26B1, 0x1708, 0x10DE, "NVIDIA RTX 6000 Ada-1B" }, + { 0x26B1, 0x1709, 0x10DE, "NVIDIA RTX 6000 Ada-2B" }, + { 0x26B1, 0x170a, 0x10DE, "NVIDIA RTX 6000 Ada-1Q" }, + { 0x26B1, 0x170b, 0x10DE, "NVIDIA RTX 6000 Ada-2Q" }, + { 0x26B1, 0x170c, 0x10DE, "NVIDIA RTX 6000 Ada-3Q" }, + { 0x26B1, 0x170d, 0x10DE, "NVIDIA RTX 6000 Ada-4Q" }, + { 0x26B1, 0x170e, 0x10DE, "NVIDIA RTX 6000 Ada-6Q" }, + { 0x26B1, 0x170f, 0x10DE, "NVIDIA RTX 6000 Ada-8Q" }, + { 0x26B1, 0x1710, 0x10DE, "NVIDIA RTX 6000 Ada-12Q" }, + { 0x26B1, 0x1711, 0x10DE, "NVIDIA RTX 6000 Ada-16Q" }, + { 0x26B1, 0x1712, 0x10DE, "NVIDIA RTX 6000 Ada-24Q" }, + { 0x26B1, 0x1713, 0x10DE, "NVIDIA RTX 6000 Ada-48Q" }, + { 0x26B1, 0x1714, 0x10DE, "NVIDIA RTX 6000 Ada-1A" }, + { 0x26B1, 0x1715, 0x10DE, "NVIDIA RTX 6000 Ada-2A" }, + { 0x26B1, 0x1716, 0x10DE, "NVIDIA RTX 6000 Ada-3A" }, + { 0x26B1, 0x1717, 0x10DE, "NVIDIA RTX 6000 Ada-4A" }, + { 0x26B1, 0x1718, 0x10DE, "NVIDIA RTX 6000 Ada-6A" }, + { 0x26B1, 0x1719, 0x10DE, "NVIDIA RTX 6000 Ada-8A" }, + { 0x26B1, 0x171a, 0x10DE, "NVIDIA RTX 6000 Ada-12A" }, + { 0x26B1, 0x171b, 0x10DE, "NVIDIA RTX 6000 Ada-16A" }, + { 0x26B1, 0x171c, 0x10DE, "NVIDIA RTX 6000 Ada-24A" }, + { 0x26B1, 0x171d, 0x10DE, "NVIDIA RTX 6000 Ada-48A" }, + { 0x26B1, 0x171e, 0x10DE, "NVIDIA RTX 6000 Ada-1" }, + { 0x26B1, 0x171f, 0x10DE, "NVIDIA RTX 6000 Ada-2" }, + { 0x26B1, 0x1720, 0x10DE, "NVIDIA RTX 6000 Ada-3" }, + { 0x26B1, 0x1721, 0x10DE, "NVIDIA RTX 6000 Ada-4" }, + { 0x26B1, 0x1722, 0x10DE, "NVIDIA RTX 6000 Ada-6" }, + { 0x26B1, 0x1723, 0x10DE, "NVIDIA RTX 6000 Ada-8" }, + { 0x26B1, 0x1724, 0x10DE, "NVIDIA RTX 6000 Ada-12" }, + { 0x26B1, 0x1725, 0x10DE, "NVIDIA RTX 6000 Ada-16" }, + { 0x26B1, 0x1726, 0x10DE, "NVIDIA RTX 6000 Ada-24" }, + { 0x26B1, 0x1727, 0x10DE, "NVIDIA RTX 6000 Ada-48" }, + { 0x26B1, 0x1728, 0x10DE, "NVIDIA RTX 6000 Ada-4C" }, + { 0x26B1, 0x1729, 0x10DE, "NVIDIA RTX 6000 Ada-6C" }, + { 0x26B1, 0x172a, 0x10DE, "NVIDIA RTX 6000 Ada-8C" }, + { 0x26B1, 0x172b, 0x10DE, "NVIDIA RTX 6000 Ada-12C" }, + { 0x26B1, 0x172c, 0x10DE, "NVIDIA RTX 6000 Ada-16C" }, + { 0x26B1, 0x172d, 0x10DE, "NVIDIA RTX 6000 Ada-24C" }, + { 0x26B1, 0x172e, 0x10DE, "NVIDIA RTX 6000 Ada-48C" }, + { 0x26B5, 0x176d, 0x10DE, "NVIDIA L40-1B" }, + { 0x26B5, 0x176e, 0x10DE, "NVIDIA L40-2B" }, + { 0x26B5, 0x176f, 0x10DE, "NVIDIA L40-1Q" }, + { 0x26B5, 0x1770, 0x10DE, "NVIDIA L40-2Q" }, + { 0x26B5, 0x1771, 0x10DE, "NVIDIA L40-3Q" }, + { 0x26B5, 0x1772, 0x10DE, "NVIDIA L40-4Q" }, + { 0x26B5, 0x1773, 0x10DE, "NVIDIA L40-6Q" }, + { 0x26B5, 0x1774, 0x10DE, "NVIDIA L40-8Q" }, + { 0x26B5, 0x1775, 0x10DE, "NVIDIA L40-12Q" }, + { 0x26B5, 0x1776, 0x10DE, "NVIDIA L40-16Q" }, + { 0x26B5, 0x1777, 0x10DE, "NVIDIA L40-24Q" }, + { 0x26B5, 0x1778, 0x10DE, "NVIDIA L40-48Q" }, + { 0x26B5, 0x1779, 0x10DE, "NVIDIA L40-1A" }, + { 0x26B5, 0x177a, 0x10DE, "NVIDIA L40-2A" }, + { 0x26B5, 0x177b, 0x10DE, "NVIDIA L40-3A" }, + { 0x26B5, 0x177c, 0x10DE, "NVIDIA L40-4A" }, + { 0x26B5, 0x177d, 0x10DE, "NVIDIA L40-6A" }, + { 0x26B5, 0x177e, 0x10DE, "NVIDIA L40-8A" }, + { 0x26B5, 0x177f, 0x10DE, "NVIDIA L40-12A" }, + { 0x26B5, 0x1780, 0x10DE, "NVIDIA L40-16A" }, + { 0x26B5, 0x1781, 0x10DE, "NVIDIA L40-24A" }, + { 0x26B5, 0x1782, 0x10DE, "NVIDIA L40-48A" }, + { 0x26B5, 0x1783, 0x10DE, "NVIDIA L40-1" }, + { 0x26B5, 0x1784, 0x10DE, "NVIDIA L40-2" }, + { 0x26B5, 0x1785, 0x10DE, "NVIDIA L40-3" }, + { 0x26B5, 0x1786, 0x10DE, "NVIDIA L40-4" }, + { 0x26B5, 0x1787, 0x10DE, "NVIDIA L40-6" }, + { 0x26B5, 0x1788, 0x10DE, "NVIDIA L40-8" }, + { 0x26B5, 0x1789, 0x10DE, "NVIDIA L40-12" }, + { 0x26B5, 0x178a, 0x10DE, "NVIDIA L40-16" }, + { 0x26B5, 0x178b, 0x10DE, "NVIDIA L40-24" }, + { 0x26B5, 0x178c, 0x10DE, "NVIDIA L40-48" }, + { 0x26B5, 0x178d, 0x10DE, "NVIDIA L40-4C" }, + { 0x26B5, 0x178e, 0x10DE, "NVIDIA L40-6C" }, + { 0x26B5, 0x178f, 0x10DE, "NVIDIA L40-8C" }, + { 0x26B5, 0x1790, 0x10DE, "NVIDIA L40-12C" }, + { 0x26B5, 0x1791, 0x10DE, "NVIDIA L40-16C" }, + { 0x26B5, 0x1792, 0x10DE, "NVIDIA L40-24C" }, + { 0x26B5, 0x1793, 0x10DE, "NVIDIA L40-48C" }, + { 0x26B8, 0x174e, 0x10DE, "NVIDIA L40G-1B" }, + { 0x26B8, 0x174f, 0x10DE, "NVIDIA L40G-2B" }, + { 0x26B8, 0x1750, 0x10DE, "NVIDIA L40G-1Q" }, + { 0x26B8, 0x1751, 0x10DE, "NVIDIA L40G-2Q" }, + { 0x26B8, 0x1752, 0x10DE, "NVIDIA L40G-3Q" }, + { 0x26B8, 0x1753, 0x10DE, "NVIDIA L40G-4Q" }, + { 0x26B8, 0x1754, 0x10DE, "NVIDIA L40G-6Q" }, + { 0x26B8, 0x1755, 0x10DE, "NVIDIA L40G-8Q" }, + { 0x26B8, 0x1756, 0x10DE, "NVIDIA L40G-12Q" }, + { 0x26B8, 0x1757, 0x10DE, "NVIDIA L40G-24Q" }, + { 0x26B8, 0x1758, 0x10DE, "NVIDIA L40G-1A" }, + { 0x26B8, 0x1759, 0x10DE, "NVIDIA L40G-2A" }, + { 0x26B8, 0x175a, 0x10DE, "NVIDIA L40G-3A" }, + { 0x26B8, 0x175b, 0x10DE, "NVIDIA L40G-4A" }, + { 0x26B8, 0x175c, 0x10DE, "NVIDIA L40G-6A" }, + { 0x26B8, 0x175d, 0x10DE, "NVIDIA L40G-8A" }, + { 0x26B8, 0x175e, 0x10DE, "NVIDIA L40G-12A" }, + { 0x26B8, 0x175f, 0x10DE, "NVIDIA L40G-24A" }, + { 0x26B8, 0x1760, 0x10DE, "NVIDIA L40G-1" }, + { 0x26B8, 0x1761, 0x10DE, "NVIDIA L40G-2" }, + { 0x26B8, 0x1762, 0x10DE, "NVIDIA L40G-3" }, + { 0x26B8, 0x1763, 0x10DE, "NVIDIA L40G-4" }, + { 0x26B8, 0x1764, 0x10DE, "NVIDIA L40G-6" }, + { 0x26B8, 0x1765, 0x10DE, "NVIDIA L40G-8" }, + { 0x26B8, 0x1766, 0x10DE, "NVIDIA L40G-12" }, + { 0x26B8, 0x1767, 0x10DE, "NVIDIA L40G-24" }, + { 0x26B8, 0x1768, 0x10DE, "NVIDIA L40G-4C" }, + { 0x26B8, 0x1769, 0x10DE, "NVIDIA L40G-6C" }, + { 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" }, + { 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" }, + { 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" }, + { 0x27B8, 0x172f, 0x10DE, "NVIDIA GPU 27B8-172F" }, + { 0x27B8, 0x1730, 0x10DE, "NVIDIA GPU 27B8-1730" }, + { 0x27B8, 0x1731, 0x10DE, "NVIDIA GPU 27B8-1731" }, + { 0x27B8, 0x1732, 0x10DE, "NVIDIA GPU 27B8-1732" }, + { 0x27B8, 0x1733, 0x10DE, "NVIDIA GPU 27B8-1733" }, + { 0x27B8, 0x1734, 0x10DE, "NVIDIA GPU 27B8-1734" }, + { 0x27B8, 0x1735, 0x10DE, "NVIDIA GPU 27B8-1735" }, + { 0x27B8, 0x1736, 0x10DE, "NVIDIA GPU 27B8-1736" }, + { 0x27B8, 0x1737, 0x10DE, "NVIDIA GPU 27B8-1737" }, + { 0x27B8, 0x1738, 0x10DE, "NVIDIA GPU 27B8-1738" }, + { 0x27B8, 0x1739, 0x10DE, "NVIDIA GPU 27B8-1739" }, + { 0x27B8, 0x173a, 0x10DE, "NVIDIA GPU 27B8-173A" }, + { 0x27B8, 0x173b, 0x10DE, "NVIDIA GPU 27B8-173B" }, + { 0x27B8, 0x173c, 0x10DE, "NVIDIA GPU 27B8-173C" }, + { 0x27B8, 0x173d, 0x10DE, "NVIDIA GPU 27B8-173D" }, + { 0x27B8, 0x173e, 0x10DE, "NVIDIA GPU 27B8-173E" }, + { 0x27B8, 0x173f, 0x10DE, "NVIDIA GPU 27B8-173F" }, + { 0x27B8, 0x1740, 0x10DE, "NVIDIA GPU 27B8-1740" }, + { 0x27B8, 0x1741, 0x10DE, "NVIDIA GPU 27B8-1741" }, + { 0x27B8, 0x1742, 0x10DE, "NVIDIA GPU 27B8-1742" }, + { 0x27B8, 0x1743, 0x10DE, "NVIDIA GPU 27B8-1743" }, + { 0x27B8, 0x1744, 0x10DE, "NVIDIA GPU 27B8-1744" }, + { 0x27B8, 0x1745, 0x10DE, "NVIDIA GPU 27B8-1745" }, + { 0x27B8, 0x1746, 0x10DE, "NVIDIA GPU 27B8-1746" }, + { 0x27B8, 0x1747, 0x10DE, "NVIDIA GPU 27B8-1747" }, + { 0x27B8, 0x1748, 0x10DE, "NVIDIA GPU 27B8-1748" }, + { 0x27B8, 0x1749, 0x10DE, "NVIDIA GPU 27B8-1749" }, + { 0x27B8, 0x174a, 0x10DE, "NVIDIA GPU 27B8-174A" }, + { 0x27B8, 0x174b, 0x10DE, "NVIDIA GPU 27B8-174B" }, + { 0x27B8, 0x174c, 0x10DE, "NVIDIA GPU 27B8-174C" }, + { 0x27B8, 0x174d, 0x10DE, "NVIDIA GPU 27B8-174D" }, }; #endif // G_NV_NAME_RELEASED_H diff --git a/src/nvidia/generated/g_objgpumon_nvoc.h b/src/nvidia/generated/g_objgpumon_nvoc.h index 65f6f9b9f..5cde8e28e 100644 --- a/src/nvidia/generated/g_objgpumon_nvoc.h +++ b/src/nvidia/generated/g_objgpumon_nvoc.h @@ -42,6 +42,7 @@ extern "C" { #include "gpu/gpu.h" #include "gpu/eng_state.h" +#include "kernel/gpu/fifo/kernel_fifo.h" #include "ctrl/ctrl2080/ctrl2080perf.h" @@ -130,18 +131,18 @@ NV_STATUS __nvoc_objCreate_OBJGPUMON(OBJGPUMON**, Dynamic*, NvU32); #define gpumonSetTunableState(pGpu, pEngstate, pTunableState) gpumonSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define gpumonConstructEngine(pGpu, pEngstate, arg0) gpumonConstructEngine_DISPATCH(pGpu, pEngstate, arg0) #define gpumonIsPresent(pGpu, pEngstate) gpumonIsPresent_DISPATCH(pGpu, pEngstate) -void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3); +void gpumonGetContextProcessInfo_GM107(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName); #ifdef __nvoc_objgpumon_h_disabled -static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, NvU32 arg0, NvU32 *arg1, NvU32 *arg2, const char **arg3) { +static inline void gpumonGetContextProcessInfo(struct OBJGPU *pGpu, struct OBJGPUMON *pGpumon, RM_ENGINE_TYPE rmEngineTypeBegin, RM_ENGINE_TYPE rmEngineTypeEnd, NvU32 context, NvU32 *pProcID, NvU32 *pSubProcessID, const char **pSubProcessName) { NV_ASSERT_FAILED_PRECOMP("OBJGPUMON was disabled!"); } #else //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, arg0, arg1, arg2, arg3) +#define gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo_GM107(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) #endif //__nvoc_objgpumon_h_disabled -#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, arg0, arg1, arg2, arg3) gpumonGetContextProcessInfo(pGpu, pGpumon, arg0, arg1, arg2, arg3) +#define gpumonGetContextProcessInfo_HAL(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) gpumonGetContextProcessInfo(pGpu, pGpumon, rmEngineTypeBegin, rmEngineTypeEnd, context, pProcID, pSubProcessID, pSubProcessName) static inline NV_STATUS gpumonReconcileTunableState_DISPATCH(POBJGPU pGpu, struct OBJGPUMON *pEngstate, void *pTunableState) { return pEngstate->__gpumonReconcileTunableState__(pGpu, pEngstate, pTunableState); diff --git a/src/nvidia/generated/g_os_nvoc.h b/src/nvidia/generated/g_os_nvoc.h index 882aa210b..13c5ae4ba 100644 --- a/src/nvidia/generated/g_os_nvoc.h +++ b/src/nvidia/generated/g_os_nvoc.h @@ -749,6 +749,7 @@ NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo, NvU32 averageBandwidthKBPS, NvU32 floorBandwidthKBPS); +NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid); NvBool osIsAdministrator(void); NvBool osAllowPriorityOverride(void); NV_STATUS osGetCurrentTime(NvU32 *pSec,NvU32 *puSec); diff --git a/src/nvidia/generated/g_resserv_nvoc.h b/src/nvidia/generated/g_resserv_nvoc.h index b42276697..b413afe71 100644 --- a/src/nvidia/generated/g_resserv_nvoc.h +++ b/src/nvidia/generated/g_resserv_nvoc.h @@ -180,6 +180,12 @@ typedef void *PUID_TOKEN; /// Internal Client handles start at this base value #define RS_CLIENT_INTERNAL_HANDLE_BASE 0xC1E00000 +/// VF Client handles start at this base value +#define RS_CLIENT_VF_HANDLE_BASE 0xE0000000 + +/// Get the VF client handle range for gfid +#define RS_CLIENT_GET_VF_HANDLE_BASE(gfid) (RS_CLIENT_VF_HANDLE_BASE + ((gfid) - 1) * RS_CLIENT_HANDLE_MAX) + // // Print a warning if any client's resource count exceeds this // threshold. Unless this was intentional, this is likely a client bug. diff --git a/src/nvidia/generated/g_rpc-structures.h b/src/nvidia/generated/g_rpc-structures.h index e99f5c70d..f9ce6556a 100644 --- a/src/nvidia/generated/g_rpc-structures.h +++ b/src/nvidia/generated/g_rpc-structures.h @@ -431,6 +431,13 @@ typedef struct rpc_perf_bridgeless_info_update_v17_00 typedef rpc_perf_bridgeless_info_update_v17_00 rpc_perf_bridgeless_info_update_v; +typedef struct rpc_nvlink_fault_up_v17_00 +{ + NvU32 linkId; +} rpc_nvlink_fault_up_v17_00; + +typedef rpc_nvlink_fault_up_v17_00 rpc_nvlink_fault_up_v; + typedef struct rpc_nvlink_inband_received_data_256_v17_00 { NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_256_PARAMS_v17_00 params; @@ -1911,6 +1918,25 @@ static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_perf_bridgeless_info_update_v17_00 = { }; #endif +#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 +static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00[] = { + { + .vtype = vtype_NvU32, + .offset = NV_OFFSETOF(rpc_nvlink_fault_up_v17_00, linkId), + .name = "linkId" + }, + { + .vtype = vt_end + } +}; + +static vmiopd_mdesc_t vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00 = { + .name = "rpc_nvlink_fault_up", + .header_length = NV_SIZEOF32(rpc_nvlink_fault_up_v17_00), + .fdesc = vmiopd_fdesc_t_rpc_nvlink_fault_up_v17_00 +}; +#endif + #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_nvlink_inband_received_data_256_v17_00[] = { { @@ -2450,6 +2476,13 @@ vmiopd_mdesc_t *rpcdebugPerfBridgelessInfoUpdate_v17_00(void) } #endif +#ifndef SKIP_PRINT_rpc_nvlink_fault_up_v17_00 +vmiopd_mdesc_t *rpcdebugNvlinkFaultUp_v17_00(void) +{ + return &vmiopd_mdesc_t_rpc_nvlink_fault_up_v17_00; +} +#endif + #ifndef SKIP_PRINT_rpc_nvlink_inband_received_data_256_v17_00 vmiopd_mdesc_t *rpcdebugNvlinkInbandReceivedData256_v17_00(void) { @@ -2603,6 +2636,8 @@ typedef union rpc_generic_union { rpc_perf_gpu_boost_sync_limits_callback_v perf_gpu_boost_sync_limits_callback_v; rpc_perf_bridgeless_info_update_v17_00 perf_bridgeless_info_update_v17_00; rpc_perf_bridgeless_info_update_v perf_bridgeless_info_update_v; + rpc_nvlink_fault_up_v17_00 nvlink_fault_up_v17_00; + rpc_nvlink_fault_up_v nvlink_fault_up_v; rpc_nvlink_inband_received_data_256_v17_00 nvlink_inband_received_data_256_v17_00; rpc_nvlink_inband_received_data_256_v nvlink_inband_received_data_256_v; rpc_nvlink_inband_received_data_512_v17_00 nvlink_inband_received_data_512_v17_00; diff --git a/src/nvidia/generated/g_rs_server_nvoc.h b/src/nvidia/generated/g_rs_server_nvoc.h index 28eb2ab11..71c01dcb6 100644 --- a/src/nvidia/generated/g_rs_server_nvoc.h +++ b/src/nvidia/generated/g_rs_server_nvoc.h @@ -491,6 +491,15 @@ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +/** + * Return an available client handle for new client allocation + * + * @param[in] pServer This server instance + * @param[in] bInternalHandle Client is an RM internal client + * @param[in] pSecInfo Security context of this client allocation + */ +extern NvU32 serverAllocClientHandleBase(RsServer *pServer, NvBool bInternalHandle, API_SECURITY_INFO *pSecInfo); + /** * Allocate a resource. Assumes top-level lock has been taken. * diff --git a/src/nvidia/generated/g_sdk-structures.h b/src/nvidia/generated/g_sdk-structures.h index 483c09b3c..8ec3dea1f 100644 --- a/src/nvidia/generated/g_sdk-structures.h +++ b/src/nvidia/generated/g_sdk-structures.h @@ -409,7 +409,7 @@ typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 { NvU8 chipletType; NvU8 chipletIndex; - NvU8 numCredits; + NvU16 numCredits; } NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08; typedef NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v21_08 NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_INFO_v; diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 1423bbead..94d2f42c2 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -6545,6 +6545,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [421] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPostFaultUp_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + /*flags=*/ 0x200u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20803042u, + /*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdNvlinkPostFaultUp" +#endif + }, + { /* [422] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6559,7 +6574,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [422] */ + { /* [423] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6574,7 +6589,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [423] */ + { /* [424] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6589,7 +6604,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [424] */ + { /* [425] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6604,7 +6619,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [425] */ + { /* [426] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6619,7 +6634,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [426] */ + { /* [427] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6634,7 +6649,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [427] */ + { /* [428] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6649,7 +6664,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [428] */ + { /* [429] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6664,7 +6679,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [429] */ + { /* [430] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6679,13 +6694,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [430] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) + { /* [431] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlaSetupInstanceMemBlock_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) - /*flags=*/ 0x2204u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) + /*flags=*/ 0x102204u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803502u, /*paramSize=*/ sizeof(NV2080_CTRL_FLA_SETUP_INSTANCE_MEM_BLOCK_PARAMS), @@ -6694,13 +6709,13 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [431] */ -#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) + { /* [432] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) /*pFunc=*/ (void (*)(void)) NULL, #else /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdFlaGetRange_IMPL, -#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) - /*flags=*/ 0x4u, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) + /*flags=*/ 0x100004u, /*accessRight=*/0x0u, /*methodId=*/ 0x20803503u, /*paramSize=*/ sizeof(NV2080_CTRL_FLA_GET_RANGE_PARAMS), @@ -6709,7 +6724,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [432] */ + { /* [433] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6724,7 +6739,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [433] */ + { /* [434] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6739,7 +6754,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [434] */ + { /* [435] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6754,7 +6769,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [435] */ + { /* [436] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6769,7 +6784,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [436] */ + { /* [437] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6784,7 +6799,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [437] */ + { /* [438] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6799,7 +6814,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [438] */ + { /* [439] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6814,7 +6829,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [439] */ + { /* [440] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6829,7 +6844,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [440] */ + { /* [441] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6844,7 +6859,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask" #endif }, - { /* [441] */ + { /* [442] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6859,7 +6874,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask" #endif }, - { /* [442] */ + { /* [443] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6874,7 +6889,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType" #endif }, - { /* [443] */ + { /* [444] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6889,7 +6904,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu" #endif }, - { /* [444] */ + { /* [445] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6904,7 +6919,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo" #endif }, - { /* [445] */ + { /* [446] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6919,7 +6934,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage" #endif }, - { /* [446] */ + { /* [447] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6934,7 +6949,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity" #endif }, - { /* [447] */ + { /* [448] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6949,7 +6964,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources" #endif }, - { /* [448] */ + { /* [449] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6964,7 +6979,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding" #endif }, - { /* [449] */ + { /* [450] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6979,7 +6994,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport" #endif }, - { /* [450] */ + { /* [451] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6994,7 +7009,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig" #endif }, - { /* [451] */ + { /* [452] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7009,7 +7024,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [452] */ + { /* [453] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -7029,7 +7044,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 453, + /*numEntries=*/ 454, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7465,6 +7480,10 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdNvlinkInbandSendData__ = &subdeviceCtrlCmdNvlinkInbandSendData_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) + pThis->__subdeviceCtrlCmdNvlinkPostFaultUp__ = &subdeviceCtrlCmdNvlinkPostFaultUp_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) pThis->__subdeviceCtrlCmdNvlinkEomControl__ = &subdeviceCtrlCmdNvlinkEomControl_IMPL; #endif @@ -8136,10 +8155,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner * #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__subdeviceCtrlCmdGpuQueryComputeModeRules__ = &subdeviceCtrlCmdGpuQueryComputeModeRules_IMPL; #endif - -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) - pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL; -#endif } static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) { @@ -8150,6 +8165,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * PORT_UNREFERENCED_VARIABLE(rmVariantHal); PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx); +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) + pThis->__subdeviceCtrlCmdGpuAcquireComputeModeReservation__ = &subdeviceCtrlCmdGpuAcquireComputeModeReservation_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) pThis->__subdeviceCtrlCmdGpuReleaseComputeModeReservation__ = &subdeviceCtrlCmdGpuReleaseComputeModeReservation_IMPL; #endif @@ -8402,10 +8421,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeGetCaps__ = &subdeviceCtrlCmdCeGetCaps_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) - pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL; -#endif - #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) pThis->__subdeviceCtrlCmdCeGetCePceMask__ = &subdeviceCtrlCmdCeGetCePceMask_IMPL; #endif @@ -8418,6 +8433,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdCeGetCapsV2__ = &subdeviceCtrlCmdCeGetCapsV2_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2850u) + pThis->__subdeviceCtrlCmdCeGetAllCaps__ = &subdeviceCtrlCmdCeGetAllCaps_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) pThis->__subdeviceCtrlCmdFlcnGetDmemUsage__ = &subdeviceCtrlCmdFlcnGetDmemUsage_IMPL; #endif @@ -8466,11 +8485,11 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdFlaRange__ = &subdeviceCtrlCmdFlaRange_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x102204u) pThis->__subdeviceCtrlCmdFlaSetupInstanceMemBlock__ = &subdeviceCtrlCmdFlaSetupInstanceMemBlock_IMPL; #endif -#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100004u) pThis->__subdeviceCtrlCmdFlaGetRange__ = &subdeviceCtrlCmdFlaGetRange_IMPL; #endif diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 4a905f745..4614a34fd 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -213,6 +213,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdNvlinkEnableLinks__)(struct Subdevice *); NV_STATUS (*__subdeviceCtrlCmdNvlinkProcessInitDisabledLinks__)(struct Subdevice *, NV2080_CTRL_NVLINK_PROCESS_INIT_DISABLED_LINKS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkInbandSendData__)(struct Subdevice *, NV2080_CTRL_NVLINK_INBAND_SEND_DATA_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdNvlinkPostFaultUp__)(struct Subdevice *, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkEomControl__)(struct Subdevice *, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkL1Threshold__)(struct Subdevice *, NV2080_CTRL_NVLINK_L1_THRESHOLD_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdNvlinkDirectConnectCheck__)(struct Subdevice *, NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS *); @@ -443,10 +444,10 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdLpwrDifrPrefetchResponse__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_PREFETCH_RESPONSE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdLpwrDifrCtrl__)(struct Subdevice *, NV2080_CTRL_CMD_LPWR_DIFR_CTRL_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_PARAMS *); - NV_STATUS (*__subdeviceCtrlCmdCeGetAllCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCePceMask__)(struct Subdevice *, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeUpdatePceLceMappings__)(struct Subdevice *, NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdCeGetCapsV2__)(struct Subdevice *, NV2080_CTRL_CE_GET_CAPS_V2_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdCeGetAllCaps__)(struct Subdevice *, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetDmemUsage__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnGetEngineArch__)(struct Subdevice *, NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdFlcnUstreamerQueueInfo__)(struct Subdevice *, NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS *); @@ -752,6 +753,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdNvlinkEnableLinks(pSubdevice) subdeviceCtrlCmdNvlinkEnableLinks_DISPATCH(pSubdevice) #define subdeviceCtrlCmdNvlinkProcessInitDisabledLinks(pSubdevice, pParams) subdeviceCtrlCmdNvlinkProcessInitDisabledLinks_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkInbandSendData(pSubdevice, pParams) subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdNvlinkPostFaultUp(pSubdevice, pParams) subdeviceCtrlCmdNvlinkPostFaultUp_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkEomControl(pSubdevice, pParams) subdeviceCtrlCmdNvlinkEomControl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkL1Threshold(pSubdevice, pParams) subdeviceCtrlCmdNvlinkL1Threshold_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdNvlinkDirectConnectCheck(pSubdevice, pParams) subdeviceCtrlCmdNvlinkDirectConnectCheck_DISPATCH(pSubdevice, pParams) @@ -986,10 +988,10 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdLpwrDifrPrefetchResponse(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrPrefetchResponse_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdLpwrDifrCtrl(pSubdevice, pParams) subdeviceCtrlCmdLpwrDifrCtrl_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdCeGetCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCaps_DISPATCH(pSubdevice, pCeCapsParams) -#define subdeviceCtrlCmdCeGetAllCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdCeGetCePceMask(pSubdevice, pCePceMaskParams) subdeviceCtrlCmdCeGetCePceMask_DISPATCH(pSubdevice, pCePceMaskParams) #define subdeviceCtrlCmdCeUpdatePceLceMappings(pSubdevice, pCeUpdatePceLceMappingsParams) subdeviceCtrlCmdCeUpdatePceLceMappings_DISPATCH(pSubdevice, pCeUpdatePceLceMappingsParams) #define subdeviceCtrlCmdCeGetCapsV2(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetCapsV2_DISPATCH(pSubdevice, pCeCapsParams) +#define subdeviceCtrlCmdCeGetAllCaps(pSubdevice, pCeCapsParams) subdeviceCtrlCmdCeGetAllCaps_DISPATCH(pSubdevice, pCeCapsParams) #define subdeviceCtrlCmdFlcnGetDmemUsage(pSubdevice, pFlcnDmemUsageParams) subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(pSubdevice, pFlcnDmemUsageParams) #define subdeviceCtrlCmdFlcnGetEngineArch(pSubdevice, pParams) subdeviceCtrlCmdFlcnGetEngineArch_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdFlcnUstreamerQueueInfo(pSubdevice, pParams) subdeviceCtrlCmdFlcnUstreamerQueueInfo_DISPATCH(pSubdevice, pParams) @@ -1722,6 +1724,12 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkInbandSendData_DISPATCH(struct Sub return pSubdevice->__subdeviceCtrlCmdNvlinkInbandSendData__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdNvlinkPostFaultUp_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdNvlinkPostFaultUp_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdNvlinkPostFaultUp__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdNvlinkEomControl_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdNvlinkEomControl_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_NVLINK_EOM_CONTROL_PARAMS *pParams) { @@ -3104,12 +3112,6 @@ static inline NV_STATUS subdeviceCtrlCmdCeGetCaps_DISPATCH(struct Subdevice *pSu return pSubdevice->__subdeviceCtrlCmdCeGetCaps__(pSubdevice, pCeCapsParams); } -NV_STATUS subdeviceCtrlCmdCeGetAllCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams); - -static inline NV_STATUS subdeviceCtrlCmdCeGetAllCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams) { - return pSubdevice->__subdeviceCtrlCmdCeGetAllCaps__(pSubdevice, pCeCapsParams); -} - NV_STATUS subdeviceCtrlCmdCeGetCePceMask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pCePceMaskParams); static inline NV_STATUS subdeviceCtrlCmdCeGetCePceMask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS *pCePceMaskParams) { @@ -3128,6 +3130,12 @@ static inline NV_STATUS subdeviceCtrlCmdCeGetCapsV2_DISPATCH(struct Subdevice *p return pSubdevice->__subdeviceCtrlCmdCeGetCapsV2__(pSubdevice, pCeCapsParams); } +NV_STATUS subdeviceCtrlCmdCeGetAllCaps_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams); + +static inline NV_STATUS subdeviceCtrlCmdCeGetAllCaps_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams) { + return pSubdevice->__subdeviceCtrlCmdCeGetAllCaps__(pSubdevice, pCeCapsParams); +} + NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams); static inline NV_STATUS subdeviceCtrlCmdFlcnGetDmemUsage_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_FLCN_GET_DMEM_USAGE_PARAMS *pFlcnDmemUsageParams) { diff --git a/src/nvidia/generated/rmconfig.h b/src/nvidia/generated/rmconfig.h index 8ac500f0c..ccede6203 100644 --- a/src/nvidia/generated/rmconfig.h +++ b/src/nvidia/generated/rmconfig.h @@ -242,6 +242,7 @@ #define RMCFG_FEATURE_RMCORE_BASE 1 // RMCORE Base #define RMCFG_FEATURE_KERNEL_RM 1 // Kernel layer of RM #define RMCFG_FEATURE_ORIN_PHYSICAL_RM 1 // Physical layer of RM, disabled only on Orin +#define RMCFG_FEATURE_VGPU_GSP_PLUGIN_OFFLOAD 1 // vGPU GSP plugin offload #define RMCFG_FEATURE_LIBOS_3_X 1 // Enable Libos-3.x feature #define RMCFG_FEATURE_NOTEBOOK 1 // Notebook support #define RMCFG_FEATURE_EXTDEV 1 // Daughter boards connected to Quadro GPUs diff --git a/src/nvidia/inc/kernel/core/prelude.h b/src/nvidia/inc/kernel/core/prelude.h index 38b30a236..7ae35a75c 100644 --- a/src/nvidia/inc/kernel/core/prelude.h +++ b/src/nvidia/inc/kernel/core/prelude.h @@ -81,7 +81,9 @@ typedef struct THREAD_STATE_NODE THREAD_STATE_NODE; // FW declare thread state #define NV_ROUNDUP(a,b) ((NV_CEIL(a,b))*(b)) #define NV_ROUND_TO_QUANTA(a, quanta) (((quanta) == 0) ? (a): ((((a) + ((quanta) >> 1)) / (quanta)) * (quanta))) #define NV_FLOOR_TO_QUANTA(a, quanta) (((a) / (quanta)) * (quanta)) +#ifndef NV_SIZEOF32 #define NV_SIZEOF32(x) (sizeof(x)) +#endif #define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0]))) #define NV_ARRAY_ELEMENTS32(x) ((NV_SIZEOF32(x)/NV_SIZEOF32((x)[0]))) #define NV_BYTESWAP16(a) ((((a) & 0xff00)>>8) | \ diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h index a7fef86c2..9ed743385 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.h @@ -128,12 +128,12 @@ void pmaAddrtreeSetEvictingFrames(void *pMap, NvU64 frameEvictionsInProcess); NV_STATUS pmaAddrtreeScanContiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); NV_STATUS pmaAddrtreeScanDiscontiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); void pmaAddrtreePrintTree(void *pMap, const char* str); diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h index 9bddaf607..36f489016 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h @@ -98,6 +98,7 @@ typedef struct SCRUB_NODE SCRUB_NODE; #define PMA_ALLOCATE_NO_ZERO NVBIT(10) #define PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11) #define PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12) +#define PMA_ALLOCATE_REVERSE_ALLOC NVBIT(13) // Output flags #define PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0) @@ -183,10 +184,10 @@ typedef void (*pmaMapChangePageStateAttrib_t)(void *pMap, NvU64 startFrame, NvU typedef PMA_PAGESTATUS (*pmaMapRead_t)(void *pMap, NvU64 frameNum, NvBool readAttrib); typedef NV_STATUS (*pmaMapScanContiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef NV_STATUS (*pmaMapScanDiscontiguous_t)(void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); typedef void (*pmaMapGetSize_t)(void *pMap, NvU64 *pBytesTotal); typedef void (*pmaMapGetLargestFree_t)(void *pMap, NvU64 *pLargestFree); typedef NV_STATUS (*pmaMapScanContiguousNumaEviction_t)(void *pMap, NvU64 addrBase, NvLength actualSize, diff --git a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h index f5d90b742..1bb49ea35 100644 --- a/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h +++ b/src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.h @@ -189,7 +189,7 @@ PMA_PAGESTATUS pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib); NV_STATUS pmaRegmapScanContiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! * @brief Scan the list for any space @@ -216,7 +216,7 @@ NV_STATUS pmaRegmapScanContiguous( NV_STATUS pmaRegmapScanDiscontiguous( void *pMap, NvU64 addrBase, NvU64 rangeStart, NvU64 rangeEnd, NvU64 numPages, NvU64 *freelist, NvU32 pageSize, NvU64 alignment, - NvU64 *pagesAllocated, NvBool bSkipEvict); + NvU64 *pagesAllocated, NvBool bSkipEvict, NvBool bReverseAlloc); /*! * @brief Gets the total size of specified PMA managed region. diff --git a/src/nvidia/inc/libraries/nvport/atomic.h b/src/nvidia/inc/libraries/nvport/atomic.h index 8922b730c..42a02c51a 100644 --- a/src/nvidia/inc/libraries/nvport/atomic.h +++ b/src/nvidia/inc/libraries/nvport/atomic.h @@ -70,6 +70,13 @@ * @{ */ +/** + * @brief Initialization function for port atomics + * + * This function is only needed for Libos + */ +PORT_ATOMIC_INLINE void portAtomicInit(void); + /** * @brief Atomic addition on a signed 32b integer * diff --git a/src/nvidia/inc/libraries/nvport/inline/atomic_clang.h b/src/nvidia/inc/libraries/nvport/inline/atomic_clang.h index 8d73e2f35..40dd6c263 100644 --- a/src/nvidia/inc/libraries/nvport/inline/atomic_clang.h +++ b/src/nvidia/inc/libraries/nvport/inline/atomic_clang.h @@ -68,6 +68,12 @@ portAtomicTimerBarrier(void) #if PORT_COMPILER_HAS_INTRINSIC_ATOMICS && !defined(NV_MODS) && !NVOS_IS_LIBOS +PORT_ATOMIC_INLINE void +portAtomicInit(void) +{ + +} + PORT_ATOMIC_INLINE NvS32 portAtomicAddS32 ( diff --git a/src/nvidia/inc/libraries/nvport/inline/atomic_gcc.h b/src/nvidia/inc/libraries/nvport/inline/atomic_gcc.h index 0b00799b6..3e71d945b 100644 --- a/src/nvidia/inc/libraries/nvport/inline/atomic_gcc.h +++ b/src/nvidia/inc/libraries/nvport/inline/atomic_gcc.h @@ -93,6 +93,12 @@ portAtomicTimerBarrier(void) #if PORT_COMPILER_HAS_INTRINSIC_ATOMICS && !defined(NV_MODS) && !NVOS_IS_LIBOS +PORT_ATOMIC_INLINE void +portAtomicInit(void) +{ + +} + PORT_ATOMIC_INLINE NvS32 portAtomicAddS32 ( diff --git a/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h b/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h index 5ebdae10e..1b52fc716 100644 --- a/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h +++ b/src/nvidia/inc/libraries/nvport/inline/memory_tracking.h @@ -43,6 +43,10 @@ void *_portMemAllocatorAlloc(PORT_MEM_ALLOCATOR *pAlloc, NvLength length); /** @brief Wrapper around pAlloc->_portFree() that tracks the allocation */ void _portMemAllocatorFree(PORT_MEM_ALLOCATOR *pAlloc, void *pMem); +#if PORT_MEM_TRACK_USE_LIMIT +/** @brief Initialize per VF tracking limit **/ +void portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 heapSize, NvBool bLimitEnabled); +#endif typedef struct PORT_MEM_COUNTER { @@ -146,7 +150,7 @@ PORT_MEM_ALLOCATOR *portMemExAllocatorCreateLockedOnExistingBlock_CallerInfo(voi #endif // CALLERINFO -#if PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_ALLOCLIST || PORT_MEM_TRACK_USE_CALLERINFO +#if PORT_MEM_TRACK_USE_FENCEPOSTS || PORT_MEM_TRACK_USE_ALLOCLIST || PORT_MEM_TRACK_USE_CALLERINFO || PORT_MEM_TRACK_USE_LIMIT typedef struct PORT_MEM_HEADER { #if PORT_MEM_TRACK_USE_CALLERINFO @@ -158,6 +162,10 @@ typedef struct PORT_MEM_HEADER #if PORT_MEM_TRACK_USE_FENCEPOSTS PORT_MEM_FENCE_HEAD fence; #endif +#if PORT_MEM_TRACK_USE_LIMIT + NvU64 blockSize; + NvU32 pid; +#endif } PORT_MEM_HEADER; typedef struct PORT_MEM_FOOTER diff --git a/src/nvidia/inc/libraries/nvport/memory.h b/src/nvidia/inc/libraries/nvport/memory.h index dd5646e52..a27f6ef4d 100644 --- a/src/nvidia/inc/libraries/nvport/memory.h +++ b/src/nvidia/inc/libraries/nvport/memory.h @@ -904,6 +904,19 @@ void portMemExUnmapIOSpace(void *addr, NvU64 byteSize); */ #define PORT_MEM_TRACK_USE_LOGGING 0 #endif +#if !defined(PORT_MEM_TRACK_USE_LIMIT) +/** + * @brief Track and enforce a heap memory usage limit on processes + * running in GSP-RM. + * + * Default is on in GSP-RM only. + */ +#ifndef GSP_PLUGIN_BUILD +#define PORT_MEM_TRACK_USE_LIMIT (NVOS_IS_LIBOS) +#else +#define PORT_MEM_TRACK_USE_LIMIT 0 +#endif +#endif // !defined(PORT_MEM_TRACK_USE_LIMIT) /** @brief Nothing is printed unless @ref portMemPrintTrackingInfo is called */ #define PORT_MEM_TRACK_PRINT_LEVEL_SILENT 0 diff --git a/src/nvidia/inc/libraries/resserv/resserv.h b/src/nvidia/inc/libraries/resserv/resserv.h index 7085bf8a5..39b30f2c2 100644 --- a/src/nvidia/inc/libraries/resserv/resserv.h +++ b/src/nvidia/inc/libraries/resserv/resserv.h @@ -139,6 +139,12 @@ typedef void *PUID_TOKEN; /// Internal Client handles start at this base value #define RS_CLIENT_INTERNAL_HANDLE_BASE 0xC1E00000 +/// VF Client handles start at this base value +#define RS_CLIENT_VF_HANDLE_BASE 0xE0000000 + +/// Get the VF client handle range for gfid +#define RS_CLIENT_GET_VF_HANDLE_BASE(gfid) (RS_CLIENT_VF_HANDLE_BASE + ((gfid) - 1) * RS_CLIENT_HANDLE_MAX) + // // Print a warning if any client's resource count exceeds this // threshold. Unless this was intentional, this is likely a client bug. diff --git a/src/nvidia/inc/libraries/resserv/rs_server.h b/src/nvidia/inc/libraries/resserv/rs_server.h index 55297898f..3ef6515a0 100644 --- a/src/nvidia/inc/libraries/resserv/rs_server.h +++ b/src/nvidia/inc/libraries/resserv/rs_server.h @@ -354,6 +354,15 @@ NvBool serverShareIterNext(RS_SHARE_ITERATOR*); NV_STATUS serverSetClientHandleBase(RsServer *pServer, NvU32 clientHandleBase); +/** + * Return an available client handle for new client allocation + * + * @param[in] pServer This server instance + * @param[in] bInternalHandle Client is an RM internal client + * @param[in] pSecInfo Security context of this client allocation + */ +extern NvU32 serverAllocClientHandleBase(RsServer *pServer, NvBool bInternalHandle, API_SECURITY_INFO *pSecInfo); + /** * Allocate a resource. Assumes top-level lock has been taken. * diff --git a/src/nvidia/interface/nv_sriov_defines.h b/src/nvidia/interface/nv_sriov_defines.h index 3a60a1ecc..32bd4fcc6 100644 --- a/src/nvidia/interface/nv_sriov_defines.h +++ b/src/nvidia/interface/nv_sriov_defines.h @@ -32,35 +32,39 @@ * - Doorbell interrupt handles for Host CPU-Plugin to GSP-Plugin communication */ -// -// Ring Doorbell register to setup GSP Notification interrupt -// We have total 4096 bits for notifications (128 notify leaf registers). -// Setup to use leaf register index 0 for all communications from Guest VM to GSP-Plugin -// bit index 0x0 to 0xF used for CPU-Plugin <----> GSP-Plugin communication -// bit index 0x10 to 0x1F used for Guest VM <----> GSP-Plugin communication -// bit index 0x10 in the gsp notify register is used for RPC setup request -// bit index 0x11 in the gsp notify register is used for sending RPC send request -// +// Guest interrupts -// These defines are applicable per VM i.e. replicated per VM. -#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST 1:1 -#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_EN (0x1) -#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_DIS (0x0) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 2:2 -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_EN (0x1) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_DIS (0x0) -#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST 16:16 +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST 0:0 #define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST_EN (0x1) #define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST_DIS (0x0) -#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST 17:17 +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST) + +#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST 1:1 #define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST_EN (0x1) #define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST_DIS (0x0) - -#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST) -#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST) -#define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_REQUEST) #define NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_REQUEST) +#define NV_DOORBELL_NOTIFY_LEAF_VF_MASK (NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_SETUP_HANDLE) | \ + NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_RPC_MESSAGE_HANDLE)) + +// Host PF interrupts + +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST 16:16 +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_REQUEST) + +#define NV_DOORBELL_NOTIFY_LEAF_HOST_PF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_SERVICE_NON_REPLAYABLE_FAULT_HANDLE) + +// Host VF interrupts + +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST 17:17 +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_EN (0x1) +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST_DIS (0x0) +#define NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_HANDLE (0 ? NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_REQUEST) + +#define NV_DOORBELL_NOTIFY_LEAF_HOST_VF_MASK NVBIT(NV_DOORBELL_NOTIFY_LEAF_VF_CPU_PLUGIN_HANDLE) + // current write offset of the FECS trace buffer #define NV_VF_SCRATCH_REGISTER_FECS_TRACE_WR_RD_OFFSET 0x0 // current read offset of the FECS trace buffer @@ -70,3 +74,5 @@ #define NV_VF_SCRATCH_REGISTER_GUEST_RPC_LO 0x2 // used in VGPU-GSP RPC setup #define NV_VF_SCRATCH_REGISTER_GUEST_RPC_HI 0x3 + +#define MAX_PARTITIONS_WITH_GFID (32) \ No newline at end of file diff --git a/src/nvidia/interface/nvrm_registry.h b/src/nvidia/interface/nvrm_registry.h index f18cbd54d..2e6c3273f 100644 --- a/src/nvidia/interface/nvrm_registry.h +++ b/src/nvidia/interface/nvrm_registry.h @@ -1725,4 +1725,15 @@ // 1 - Multicast FLA Enabled on supported GPU // 0 - Multicast FLA Disabled on specific GPU // +// +// TYPE Dword +// Determines whether or not to emulate VF MMU TLB Invalidation register range +// Encoding : 1 - Emulate register range (Default) +// : 0 - Do not emulate register range. +// +#define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE "RMBug3007008EmulateVfMmuTlbInvalidate" +#define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE 0x00000001 +#define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE 0x00000000 +#define NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_ENABLE + #endif // NVRM_REGISTRY_H diff --git a/src/nvidia/interface/rmapi/src/finn_rm_api.c b/src/nvidia/interface/rmapi/src/finn_rm_api.c index 27510fe68..762519a91 100644 --- a/src/nvidia/interface/rmapi/src/finn_rm_api.c +++ b/src/nvidia/interface/rmapi/src/finn_rm_api.c @@ -13,16 +13,22 @@ #include "ctrl/ctrl2080/ctrl2080nvd.h" #include "ctrl/ctrl2080/ctrl2080perf.h" #include "ctrl/ctrl2080/ctrl2080rc.h" +#include "ctrl/ctrl2080/ctrl2080ucodefuzzer.h" #include "ctrl/ctrl208f/ctrl208fgpu.h" #include "ctrl/ctrl402c.h" #include "ctrl/ctrl83de/ctrl83dedebug.h" #include "ctrl/ctrlb06f.h" +#if defined(NVRM) /* Kernel Mode */ #include #include -#if defined(NVRM) /* Kernel Mode */ +#include "nvport/nvport.h" +#elif defined(NV_LIBOS) /* LIBOS */ +#include #include "nvport/nvport.h" #else /* User Mode */ +#include +#include #include #include #endif @@ -42,6 +48,9 @@ #elif defined(NVRM) /* Kernel Mode */ #define FINN_MALLOC(size) portMemAllocNonPaged(size) +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MALLOC(size) portMemAllocNonPaged(size) + #else /* User Mode */ #define FINN_MALLOC(size) malloc(size) #endif @@ -51,6 +60,9 @@ #elif defined(NVRM) /* Kernel Mode */ #define FINN_FREE(buf) portMemFree(buf) +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_FREE(buf) portMemFree(buf) + #else /* User Mode */ #define FINN_FREE(buf) free(buf) #endif @@ -60,6 +72,9 @@ #elif defined(NVRM) /* Kernel Mode */ #define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMZERO(buf, size) portMemSet(buf, 0, size) + #else /* User Mode */ #define FINN_MEMZERO(buf, size) memset(buf, 0, size) #endif @@ -69,6 +84,9 @@ #elif defined(NVRM) /* Kernel Mode */ #define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_MEMCPY(dst, src, size) portMemCopy(dst, size, src, size) + #else /* User Mode */ #define FINN_MEMCPY(dst, src, size) memcpy(dst, src, size) #endif @@ -78,6 +96,9 @@ #elif defined(NVRM) /* Kernel Mode */ #define FINN_ERROR(err) /* No-op */ +#elif defined(NV_LIBOS) /* LIBOS */ +#define FINN_ERROR(err) /* No-op */ + #else /* User Mode */ #define FINN_ERROR(err) /* No-op */ #endif @@ -252,7 +273,7 @@ struct finn_bit_pump_for_write // Both `sod` and `eob` are null. // When closed, `bp->buffer_position` contains the byte count. // -static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, uint64_t *eob) +static inline void finn_open_buffer_for_write(finn_bit_pump_for_write *bp, uint64_t *sod, const uint64_t *eob) { bp->accumulator = 0U; bp->buffer_position = sod; @@ -369,7 +390,7 @@ static inline void finn_close_buffer_for_write(finn_bit_pump_for_write *bp) static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, const char *src, char **dst, size_t dst_size, NvBool seri_up); static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); -static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); +static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up); static NV_STATUS FinnRmApiDeserializeInterface(NvU64 interface, NvU64 message, finn_bit_pump_for_read *bp, char *dst, NvLength dst_size, NvBool deser_up); static NV_STATUS FinnNv01RootNvdSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS FinnNv01RootNvdDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV01_ROOT_NVD *dst, NvLength dst_size, NvBool deser_up); @@ -413,6 +434,7 @@ static NvU64 FinnNv20Subdevice0PerfGetUnserializedSize(NvU64 message); static NV_STATUS FinnNv20Subdevice0RcSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS FinnNv20Subdevice0RcDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_0_RC *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20Subdevice0RcGetUnserializedSize(NvU64 message); + static NV_STATUS FinnNv20SubdeviceDiagGpuSerializeMessage(NvU64 message, const char *src, finn_bit_pump_for_write *bp, NvBool seri_up); static NV_STATUS FinnNv20SubdeviceDiagGpuDeserializeMessage(NvU64 message, finn_bit_pump_for_read *bp, FINN_NV20_SUBDEVICE_DIAG_GPU *dst, NvLength dst_size, NvBool deser_up); static NvU64 FinnNv20SubdeviceDiagGpuGetUnserializedSize(NvU64 message); @@ -519,12 +541,12 @@ NV_STATUS FinnRmApiSerializeDown(NvU64 interface, NvU64 message, const void *src NV_STATUS FinnRmApiDeserializeDown(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) { - return FinnRmApiDeserializeInternal((char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_FALSE); + return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_FALSE); } -NV_STATUS FinnRmApiDeserializeUp(NvU8 * const *src, NvLength src_size, void *dst, NvLength dst_size) +NV_STATUS FinnRmApiDeserializeUp(NvU8 **src, NvLength src_size, void *dst, NvLength dst_size) { - return FinnRmApiDeserializeInternal((char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_TRUE); + return FinnRmApiDeserializeInternal((const char **) src, src_size / sizeof(NvU8), (char *) dst, dst_size, NV_TRUE); } @@ -568,7 +590,7 @@ static NV_STATUS FinnRmApiSerializeInternal(NvU64 interface, NvU64 message, cons (*dst) += sizeof(FINN_RM_API); // Open the bit pump. - finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (uint64_t *) dst_end); + finn_open_buffer_for_write(&bp, (uint64_t *) *dst, (const uint64_t *) dst_end); // Call the serializer. error_code = FinnRmApiSerializeInterface(interface, message, src, &bp, seri_up); @@ -641,10 +663,10 @@ static NV_STATUS FinnRmApiSerializeInterface(NvU64 interface, NvU64 message, con } -static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) +static NV_STATUS FinnRmApiDeserializeInternal(const char **src, NvLength src_size, char *dst, NvLength dst_size, NvBool deser_up) { // Header - FINN_RM_API *header; + const FINN_RM_API *header; // End of data const char *src_max; @@ -665,7 +687,7 @@ static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, cha } // Header data comes first. - header = (FINN_RM_API *) *src; + header = (const FINN_RM_API *) *src; // Check the version. if (header->version != FINN_SERIALIZATION_VERSION) @@ -680,11 +702,9 @@ static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, cha // Check that source buffer is large enough. if (sizeof(FINN_RM_API) > src_size || header->payloadSize > src_size || - header->payloadSize < sizeof(FINN_RM_API) || - *src + header->payloadSize > src_max || - *src + header->payloadSize < *src) + header->payloadSize < sizeof(FINN_RM_API)) { - *src = (char *) &header->payloadSize; + *src = (const char *) &header->payloadSize; FINN_ERROR(NV_ERR_BUFFER_TOO_SMALL); return NV_ERR_BUFFER_TOO_SMALL; } @@ -696,7 +716,7 @@ static NV_STATUS FinnRmApiDeserializeInternal(char **src, NvLength src_size, cha status = FinnRmApiDeserializeInterface(header->interface, header->message, &bp, dst, dst_size, deser_up); // Update the buffer position, error or not. - *(src) = (char *) bp.buffer_position; + *(src) = (const char *) bp.buffer_position; // Nothing more to do if there was an error. if (status != NV_OK) @@ -774,12 +794,12 @@ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src { // Bit pump with writing disabled. finn_bit_pump_for_write bp; - finn_open_buffer_for_write(&bp, (uint64_t *) 0, (uint64_t *) 0); + finn_open_buffer_for_write(&bp, (uint64_t *) 0, (const uint64_t *) 0); // Call the serializer with write-suppressed bit pump. // The size is the same in bith directions (up/down). // Eeturn zero on error to indicate that this API is not serialized by FINN. - if (FinnRmApiSerializeInterface(interface, message, (const char *) src, &bp, 0) != NV_OK) + if (FinnRmApiSerializeInterface(interface, message, (const char *) NvP64_VALUE(src), &bp, 0) != NV_OK) return 0; // Close the bit pump. @@ -787,7 +807,7 @@ NvU64 FinnRmApiGetSerializedSize(NvU64 interface, NvU64 message, const NvP64 src // Add the header size in bytes to the amount of data serialzied. // `buffer_position` is the payload size (not really the buffer position). - return (NvU64) bp.buffer_position + sizeof(FINN_RM_API); + return (NvU64) NV_PTR_TO_NvP64(bp.buffer_position) + sizeof(FINN_RM_API); } @@ -1777,7 +1797,7 @@ static NV_STATUS Nv0000CtrlNvdGetDumpParamsSerialize(const NV0000_CTRL_NVD_GET_D // Free memory that was allocated during downward deserialization. if (seri_up && src->pBuffer) - FINN_FREE(src->pBuffer); + FINN_FREE(NvP64_VALUE(src->pBuffer)); } goto exit; // Suppress potential not-used warning @@ -2057,7 +2077,7 @@ static NV_STATUS Nv0080CtrlDmaUpdatePde2ParamsSerialize(const NV0080_CTRL_DMA_UP // Free memory that was allocated during downward deserialization. if (seri_up && src->pPdeBuffer) - FINN_FREE(src->pPdeBuffer); + FINN_FREE(NvP64_VALUE(src->pPdeBuffer)); } goto exit; // Suppress potential not-used warning @@ -2221,7 +2241,7 @@ static NV_STATUS Nv0080CtrlFbGetCapsParamsSerialize(const NV0080_CTRL_FB_GET_CAP // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -2368,7 +2388,7 @@ static NV_STATUS Nv0080CtrlFifoGetCapsParamsSerialize(const NV0080_CTRL_FIFO_GET // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -2743,7 +2763,7 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Free memory that was allocated during downward deserialization. if (seri_up && src->pChannelHandleList) - FINN_FREE(src->pChannelHandleList); + FINN_FREE(NvP64_VALUE(src->pChannelHandleList)); } // Set data-presence indicator. @@ -2771,7 +2791,7 @@ static NV_STATUS Nv0080CtrlFifoGetChannellistParamsSerialize(const NV0080_CTRL_F // Free memory that was allocated during downward deserialization. if (seri_up && src->pChannelList) - FINN_FREE(src->pChannelList); + FINN_FREE(NvP64_VALUE(src->pChannelList)); } goto exit; // Suppress potential not-used warning @@ -2945,7 +2965,7 @@ static NV_STATUS Nv0080CtrlGpuGetClasslistParamsSerialize(const NV0080_CTRL_GPU_ // Free memory that was allocated during downward deserialization. if (seri_up && src->classList) - FINN_FREE(src->classList); + FINN_FREE(NvP64_VALUE(src->classList)); } goto exit; // Suppress potential not-used warning @@ -3080,7 +3100,7 @@ static NV_STATUS Nv0080CtrlGrGetCapsParamsSerialize(const NV0080_CTRL_GR_GET_CAP // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -3221,7 +3241,7 @@ static NV_STATUS Nv0080CtrlHostGetCapsParamsSerialize(const NV0080_CTRL_HOST_GET // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -3368,7 +3388,7 @@ static NV_STATUS Nv0080CtrlMsencGetCapsParamsSerialize(const NV0080_CTRL_MSENC_G // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -3525,7 +3545,7 @@ static NV_STATUS Nv2080CtrlCeGetCapsParamsSerialize(const NV2080_CTRL_CE_GET_CAP // Free memory that was allocated during downward deserialization. if (seri_up && src->capsTbl) - FINN_FREE(src->capsTbl); + FINN_FREE(NvP64_VALUE(src->capsTbl)); } goto exit; // Suppress potential not-used warning @@ -3671,7 +3691,7 @@ static NV_STATUS Nv2080CtrlGpuGetEnginesParamsSerialize(const NV2080_CTRL_GPU_GE // Free memory that was allocated during downward deserialization. if (seri_up && src->engineList) - FINN_FREE(src->engineList); + FINN_FREE(NvP64_VALUE(src->engineList)); } goto exit; // Suppress potential not-used warning @@ -3816,7 +3836,7 @@ static NV_STATUS Nv2080CtrlGpuGetEngineClasslistParamsSerialize(const NV2080_CTR // Free memory that was allocated during downward deserialization. if (seri_up && src->classList) - FINN_FREE(src->classList); + FINN_FREE(NvP64_VALUE(src->classList)); } goto exit; // Suppress potential not-used warning @@ -3986,7 +4006,7 @@ static NV_STATUS Nv2080CtrlGpumonSamplesSerialize(const NV2080_CTRL_GPUMON_SAMPL // Free memory that was allocated during downward deserialization. if (seri_up && src->pSamples) - FINN_FREE(src->pSamples); + FINN_FREE(NvP64_VALUE(src->pSamples)); } goto exit; // Suppress potential not-used warning @@ -4212,7 +4232,7 @@ static NV_STATUS Nv2080CtrlI2cAccessParamsSerialize(const NV2080_CTRL_I2C_ACCESS // Free memory that was allocated during downward deserialization. if (seri_up && src->data) - FINN_FREE(src->data); + FINN_FREE(NvP64_VALUE(src->data)); } goto exit; // Suppress potential not-used warning @@ -4398,7 +4418,7 @@ static NV_STATUS Nv2080CtrlNvdGetDumpParamsSerialize(const NV2080_CTRL_NVD_GET_D // Free memory that was allocated during downward deserialization. if (seri_up && src->pBuffer) - FINN_FREE(src->pBuffer); + FINN_FREE(NvP64_VALUE(src->pBuffer)); } goto exit; // Suppress potential not-used warning @@ -4558,7 +4578,7 @@ static NV_STATUS Nv2080CtrlRcReadVirtualMemParamsSerialize(const NV2080_CTRL_RC_ // Free memory that was allocated during downward deserialization. if (seri_up && src->bufferPtr) - FINN_FREE(src->bufferPtr); + FINN_FREE(NvP64_VALUE(src->bufferPtr)); } goto exit; // Suppress potential not-used warning @@ -4772,7 +4792,7 @@ static NV_STATUS Nv402cCtrlI2cIndexedParamsSerialize(const NV402C_CTRL_I2C_INDEX // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -5139,7 +5159,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBlockRwSerialize(const NV402C_CT // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -5501,7 +5521,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataI2cBufferRwSerialize(const NV402C_C // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -5671,7 +5691,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusBlockRwSerialize(const NV402C_ // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -6123,7 +6143,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataSmbusMultibyteRegisterBlockRwSerial // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -6307,7 +6327,7 @@ static NV_STATUS Nv402cCtrlI2cTransactionDataReadEdidDdcSerialize(const NV402C_C // Free memory that was allocated during downward deserialization. if (seri_up && src->pMessage) - FINN_FREE(src->pMessage); + FINN_FREE(NvP64_VALUE(src->pMessage)); } goto exit; // Suppress potential not-used warning @@ -6848,7 +6868,7 @@ static NV_STATUS Nv83deCtrlDebugReadMemoryParamsSerialize(const NV83DE_CTRL_DEBU // Free memory that was allocated during downward deserialization. if (seri_up && src->buffer) - FINN_FREE(src->buffer); + FINN_FREE(NvP64_VALUE(src->buffer)); } goto exit; // Suppress potential not-used warning @@ -7013,7 +7033,7 @@ static NV_STATUS Nv83deCtrlDebugWriteMemoryParamsSerialize(const NV83DE_CTRL_DEB // Free memory that was allocated during downward deserialization. if (seri_up && src->buffer) - FINN_FREE(src->buffer); + FINN_FREE(NvP64_VALUE(src->buffer)); } goto exit; // Suppress potential not-used warning @@ -7168,7 +7188,7 @@ static NV_STATUS Nvb06fCtrlGetEngineCtxDataParamsSerialize(const NVB06F_CTRL_GET // Free memory that was allocated during downward deserialization. if (seri_up && src->pEngineCtxBuff) - FINN_FREE(src->pEngineCtxBuff); + FINN_FREE(NvP64_VALUE(src->pEngineCtxBuff)); } goto exit; // Suppress potential not-used warning diff --git a/src/nvidia/kernel/inc/objrpc.h b/src/nvidia/kernel/inc/objrpc.h index d3bc6a654..1fb06bd0c 100644 --- a/src/nvidia/kernel/inc/objrpc.h +++ b/src/nvidia/kernel/inc/objrpc.h @@ -111,6 +111,7 @@ NV_STATUS _allocRpcMemDesc(OBJGPU *pGpu, NvU64 size, NvBool bContig, NV_ADDRESS_ void _freeRpcMemDesc(OBJGPU *pGpu, MEMORY_DESCRIPTOR **ppMemDesc, void **ppMemBuffer, void **ppMemBufferPriv); NV_STATUS vgpuGspSetupBuffers(OBJGPU *pGpu); void vgpuGspTeardownBuffers(OBJGPU *pGpu); +NV_STATUS vgpuReinitializeRpcInfraOnStateLoad(POBJGPU pGpu); // // OBJGPU RPC member accessors. diff --git a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h index 014aaa78d..b4a2d981d 100644 --- a/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h +++ b/src/nvidia/kernel/inc/vgpu/rpc_global_enums.h @@ -246,6 +246,7 @@ enum { E(TIMED_SEMAPHORE_RELEASE) // 0x1018 E(NVLINK_IS_GPU_DEGRADED) // 0x1019 E(PFM_REQ_HNDLR_STATE_SYNC_CALLBACK) // 0x101a + E(NVLINK_FAULT_UP) // 0x101c E(NUM_EVENTS) // END #ifdef DEFINING_E_IN_RPC_GLOBAL_ENUMS_H }; diff --git a/src/nvidia/kernel/vgpu/nv/rpc.c b/src/nvidia/kernel/vgpu/nv/rpc.c index 7086c8f51..30e9e5bf4 100644 --- a/src/nvidia/kernel/vgpu/nv/rpc.c +++ b/src/nvidia/kernel/vgpu/nv/rpc.c @@ -100,6 +100,7 @@ typedef struct rpc_vgx_version } RPC_VGX_VERSION; static RPC_VGX_VERSION rpcVgxVersion; +static NvBool bSkipRpcVersionHandshake = NV_FALSE; void rpcSetIpVersion(OBJGPU *pGpu, OBJRPC *pRpc, NvU32 ipVersion) { @@ -671,10 +672,17 @@ NV_STATUS RmRpcSetGuestSystemInfo(OBJGPU *pGpu, OBJRPC *pRpc) { if (rpcVgxVersion.majorNum != 0) { - NV_PRINTF(LEVEL_INFO, - "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", - gpuGetInstance(pGpu)); - goto skip_ver_handshake; + if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) && !bSkipRpcVersionHandshake) + { + bSkipRpcVersionHandshake = NV_TRUE; + } + else + { + NV_PRINTF(LEVEL_INFO, + "NVRM_RPC: Skipping RPC version handshake for instance 0x%x\n", + gpuGetInstance(pGpu)); + goto skip_ver_handshake; + } } else { diff --git a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c index 0d2e9d2ef..909cfbcde 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/turing/kernel_bif_tu102.c @@ -144,6 +144,9 @@ kbifGetVFSparseMmapRegions_TU102 NvU64 *sizes) { NvBool bEmulateVfTlbInvalidation = pGpu->getProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE); + NvU64 offsetStart = 0; + NvU64 offsetEnd = 0; + int idx = 0; if (offsets && sizes && pKernelHostVgpuDevice != NULL) { @@ -154,75 +157,71 @@ kbifGetVFSparseMmapRegions_TU102 if (status != NV_OK) return NV_ERR_INVALID_ARGUMENT; + // For SRIOV heavy, trap BOOT_0 page if (gpuIsWarBug200577889SriovHeavyEnabled(pGpu)) { - // For SRIOV heavy trap BOOT_* and BAR setup registers in plugin - offsets[0] = 0 + os_page_size; // 0x1000 ==> 0x2FFF - if (maxInstance > 1 && bEmulateVfTlbInvalidation) - { - sizes[0] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) - offsets[0]; - } - else - { - sizes[0] = DRF_BASE(NV_VGPU_EMU) - offsets[0]; - } - } - else - { - offsets[0] = 0; // 0x0000 => 0x2FFF - if (maxInstance > 1 && bEmulateVfTlbInvalidation) - { - sizes[0] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); - } - else - { - sizes[0] = DRF_BASE(NV_VGPU_EMU); - } + offsetStart = os_page_size; } - if (hypervisorIsType(OS_HYPERVISOR_HYPERV)) + // For VF TLB emulation, trap MMU FAULT BUFFER page + if ((maxInstance > 1) && bEmulateVfTlbInvalidation) { - // For Hyperv, we need to mitigate RPC page - if (maxInstance > 1 && bEmulateVfTlbInvalidation) - { - offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; // 0x4000 ==> 0xEFFF - sizes[1] = DRF_BASE(NV_VGPU_EMU) - offsets[1]; + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0); + offsets[idx] = offsetStart; + sizes[idx] = offsetEnd - offsetStart; + idx++; - offsets[2] = DRF_BASE(NV_VGPU_EMU) + os_page_size; // 0x10000 ==> 0x40000 - sizes[2] = pGpu->sriovState.vfBarSize[0] - offsets[2]; - } - else - { - offsets[1] = DRF_BASE(NV_VGPU_EMU) + os_page_size; // 0x10000 ==> 0x40000 - sizes[1] = pGpu->sriovState.vfBarSize[0] - offsets[1]; - } + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; } - else + + // For non-GSP, trap VGPU_EMU page + if (!IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) { - if (maxInstance > 1 && bEmulateVfTlbInvalidation) - { - offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(0) + os_page_size; // 0x4000 ==> 0xEFFF - sizes[1] = DRF_BASE(NV_VGPU_EMU) - offsets[1]; + offsetEnd = DRF_BASE(NV_VGPU_EMU); + offsets[idx] = offsetStart; + sizes[idx] = offsetEnd - offsetStart; + idx++; - offsets[2] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; // 0x11000 ==> 0x40000 - sizes[2] = pGpu->sriovState.vfBarSize[0] - offsets[2]; - } - else - { - offsets[1] = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; // 0x11000 ==> 0x40000 - sizes[1] = pGpu->sriovState.vfBarSize[0] - offsets[1]; - } + offsetStart = DRF_BASE(NV_VGPU_EMU) + os_page_size; + } + // For non-HyperV, trap MSI-X table page + if (!hypervisorIsType(OS_HYPERVISOR_HYPERV)) + { // Assert whenever the MSI-X table page is not immediately after // the NV_VGPU_EMU page, as it will break the current assumption. NV_ASSERT((DRF_BASE(NV_VGPU_EMU) + DRF_SIZE(NV_VGPU_EMU)) == NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0)); + + offsetEnd = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0); + + // Since MSI-X page is immediately after VGPU_EMU, if both are + // trapped, skip creating a 0 size region in between + if (offsetEnd > offsetStart) + { + offsets[idx] = offsetStart; + sizes[idx] = offsetEnd - offsetStart; + idx++; + } + + offsetStart = NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(0) + os_page_size; } + + offsetEnd = pGpu->sriovState.vfBarSize[0]; + offsets[idx] = offsetStart; + sizes[idx] = offsetEnd - offsetStart; + idx++; } else { return NV_ERR_INVALID_ARGUMENT; } + for (int i = 0; i < idx; i++) + { + NV_PRINTF(LEVEL_INFO, "VF Sparse Mmap Region[%u] range 0x%llx - 0x%llx, size 0x%llx\n", + i, offsets[i], offsets[i] + sizes[i], sizes[i]); + } + return NV_OK; } diff --git a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c index 26ac0d909..58b1d7a13 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c @@ -291,17 +291,17 @@ kbusStateInitLockedKernel_GM107 // NV_ASSERT_OK_OR_RETURN(kbusInitBar2_HAL(pGpu, pKernelBus, GPU_GFID_PF)); + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) + { + vgpuGspSetupBuffers(pGpu); + } + if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING)) { // Verify that BAR2 and the MMU actually works NV_ASSERT_OK_OR_RETURN(kbusVerifyBar2_HAL(pGpu, pKernelBus, NULL, NULL, 0, 0)); } - if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_VIRTUAL_WITH_SRIOV(pGpu)) - { - vgpuGspSetupBuffers(pGpu); - } - // // For "unsupported" mmu invalidate skipping mode, we align virtual BAR2 // to avoid false TLB fills and disallow address reuse. diff --git a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c index 7c88800ad..1d73b55db 100644 --- a/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c +++ b/src/nvidia/src/kernel/gpu/bus/arch/pascal/kern_bus_gp100.c @@ -203,35 +203,12 @@ kbusCreateP2PMappingForNvlink_GP100 NvU32 gpu1Instance = gpuGetInstance(pGpu1); NvBool bLoopback = (pGpu0 == pGpu1); NV_STATUS status = NV_OK; - NvU32 nvlinkPeer0 = BUS_INVALID_PEER; - NvU32 nvlinkPeer1 = BUS_INVALID_PEER; if (peer0 == NULL || peer1 == NULL) { return NV_ERR_INVALID_ARGUMENT; } - // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1 - if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, - pGpu1, pKernelBus1, - &nvlinkPeer0)) != NV_OK) - { - return status; - } - - // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 - if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu1, pKernelBus1, - pGpu0, pKernelBus0, - &nvlinkPeer1)) != NV_OK) - { - return status; - } - - if (nvlinkPeer0 == BUS_INVALID_PEER || nvlinkPeer1 == BUS_INVALID_PEER) - { - return NV_ERR_INVALID_REQUEST; - } - // Set the default RM mapping if peer id's are not explicitly provided if (*peer0 == BUS_INVALID_PEER || *peer1 == BUS_INVALID_PEER) { @@ -249,8 +226,26 @@ kbusCreateP2PMappingForNvlink_GP100 } else { - *peer0 = nvlinkPeer0; - *peer1 = nvlinkPeer1; + // Get the peer ID pGpu0 should use for P2P over NVLINK to pGpu1 + if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu0, pKernelBus0, + pGpu1, pKernelBus1, + peer0)) != NV_OK) + { + return status; + } + + // Get the peer ID pGpu1 should use for P2P over NVLINK to pGpu0 + if ((status = kbusGetNvlinkP2PPeerId_HAL(pGpu1, pKernelBus1, + pGpu0, pKernelBus0, + peer1)) != NV_OK) + { + return status; + } + + if (*peer0 == BUS_INVALID_PEER || *peer1 == BUS_INVALID_PEER) + { + return NV_ERR_INVALID_REQUEST; + } } NV_PRINTF(LEVEL_INFO, "- P2P: Using Default RM mapping for P2P.\n"); diff --git a/src/nvidia/src/kernel/gpu/bus/p2p.c b/src/nvidia/src/kernel/gpu/bus/p2p.c index c896ad3d2..20eff5e63 100644 --- a/src/nvidia/src/kernel/gpu/bus/p2p.c +++ b/src/nvidia/src/kernel/gpu/bus/p2p.c @@ -272,9 +272,7 @@ out: if (tmpStatus != NV_OK) { - _freeMappingExtentInfo(*ppExtentInfo); - - return tmpStatus; + goto cleanup; } } @@ -292,6 +290,7 @@ out: NV_ASSERT(tmpStatus == NV_OK); } +cleanup: _freeMappingExtentInfo(*ppExtentInfo); } return status; diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c index dd47d7306..df5f0cf89 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce.c @@ -106,7 +106,7 @@ static void printCaps(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmEngineType, } -static void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) +void kceGetNvlinkCaps(OBJGPU *pGpu, KernelCE *pKCe, NvU8 *pKCeCaps) { if (kceIsCeSysmemRead_HAL(pGpu, pKCe)) RMCTRL_SET_CAP(pKCeCaps, NV2080_CTRL_CE_CAPS, _CE_SYSMEM_READ); @@ -167,56 +167,6 @@ NV_STATUS kceGetDeviceCaps_IMPL(OBJGPU *pGpu, KernelCE *pKCe, RM_ENGINE_TYPE rmE return NV_OK; } -NV_STATUS -subdeviceCtrlCmdCeGetAllCaps_IMPL -( - Subdevice *pSubdevice, - NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams -) -{ - OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); - NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); - KernelCE *pKCe; - - ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); - - KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - - // - // Since some CE capabilities depend on the nvlink topology, - // trigger topology detection before updating the CE caps - // - if ((pKernelNvlink != NULL) && !knvlinkIsForcedConfig(pGpu, pKernelNvlink) && - kmigmgrIsMIGNvlinkP2PSupported(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu))) - { - knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); - } - - portMemSet(pCeCapsParams, 0, sizeof(*pCeCapsParams)); - - RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); - NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, - pGpu->hInternalClient, - pGpu->hInternalSubdevice, - NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS, - pCeCapsParams, - sizeof(*pCeCapsParams))); - - KCE_ITER_CLIENT_BEGIN(pGpu, pKCe, hClient) - if (pKCe->bStubbed) - continue; - - pCeCapsParams->present |= BIT(kceInst); - - NvU8 *pKCeCaps = pCeCapsParams->capsTbl[kceInst]; - - if (pKernelNvlink != NULL) - kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps); - KCE_ITER_END - - return NV_OK; -} - /*! * Determine appropriate CEs for sysmem read/write and P2P over NVLINK. * diff --git a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c index 4ca3a2c18..224712a54 100644 --- a/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c +++ b/src/nvidia/src/kernel/gpu/ce/kernel_ce_shared.c @@ -28,6 +28,7 @@ #include "kernel/gpu/subdevice/subdevice.h" #include "kernel/gpu/mig_mgr/kernel_mig_manager.h" #include "kernel/gpu/fifo/kernel_fifo.h" +#include "kernel/gpu/nvlink/kernel_nvlink.h" #include "gpu/bus/kern_bus.h" #include "gpu/ce/kernel_ce.h" #include "gpu/ce/kernel_ce_private.h" @@ -161,3 +162,61 @@ subdeviceCtrlCmdCeGetCapsV2_IMPL return kceGetDeviceCaps(pGpu, pKCe, rmEngineType, NvP64_VALUE(pCeCapsParams->capsTbl)); } } + +NV_STATUS +subdeviceCtrlCmdCeGetAllCaps_IMPL +( + Subdevice *pSubdevice, + NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS *pCeCapsParams +) +{ + RM_API *pRmApi; + OBJGPU *pGpu = GPU_RES_GET_GPU(pSubdevice); + NvHandle hClient = RES_GET_CLIENT_HANDLE(pSubdevice); + + ct_assert(ENG_CE__SIZE_1 <= sizeof(pCeCapsParams->capsTbl) / sizeof(pCeCapsParams->capsTbl[0])); + + if (!RMCFG_FEATURE_PLATFORM_GSP) + { + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + // + // Since some CE capabilities depend on the nvlink topology, + // trigger topology detection before updating the CE caps + // + if ((pKernelNvlink != NULL) && !knvlinkIsForcedConfig(pGpu, pKernelNvlink) && + kmigmgrIsMIGNvlinkP2PSupported(pGpu, GPU_GET_KERNEL_MIG_MANAGER(pGpu))) + { + knvlinkCoreGetRemoteDeviceInfo(pGpu, pKernelNvlink); + } + } + + portMemSet(pCeCapsParams, 0, sizeof(*pCeCapsParams)); + + pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, + pGpu->hInternalClient, + pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS, + pCeCapsParams, + sizeof(*pCeCapsParams))); + + { + KernelCE *pKCe; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + + KCE_ITER_CLIENT_BEGIN(pGpu, pKCe, hClient) + if (pKCe->bStubbed) + continue; + + pCeCapsParams->present |= BIT(kceInst); + + NvU8 *pKCeCaps = pCeCapsParams->capsTbl[kceInst]; + + if (pKernelNvlink != NULL) + kceGetNvlinkCaps(pGpu, pKCe, pKCeCaps); + KCE_ITER_END + } + + return NV_OK; +} diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c index a9e287ce7..9f8f0d2b2 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel.c @@ -216,7 +216,17 @@ kchannelConstruct_IMPL pKernelChannel->privilegeLevel = DRF_VAL(_KERNELCHANNEL, _ALLOC_INTERNALFLAGS, _PRIVILEGE, pChannelGpfifoParams->internalFlags); } - pKernelChannel->ProcessID = pChannelGpfifoParams->ProcessID; + + // In GSP, all vGPU channel's will simply consider GFID as the processID + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu) && IS_GFID_VF(callingContextGfid)) + { + pKernelChannel->ProcessID = callingContextGfid; + } + else + { + pKernelChannel->ProcessID = pChannelGpfifoParams->ProcessID; + } + pKernelChannel->SubProcessID = pChannelGpfifoParams->SubProcessID; } else diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c index b0e36d038..15a77d21d 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_channel_group_api.c @@ -57,7 +57,7 @@ kchangrpapiConstruct_IMPL NvHandle hVASpace = NV01_NULL_OBJECT; Device *pDevice = NULL; NvU32 gfid = GPU_GFID_PF; - RsShared *pShared; + RsShared *pShared = NULL; RsClient *pClient; NvBool bLockAcquired = NV_FALSE; Heap *pHeap = GPU_GET_HEAP(pGpu); diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c index 56e94a648..ca4394814 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_fifo.c @@ -310,8 +310,9 @@ _kfifoChidMgrAllocChidHeaps // should not be in the same page // kfifoGetUserdSizeAlign_HAL(pKernelFifo, &userdBar1Size, NULL); + NvBool bIsolationEnabled = (pKernelFifo->bUsePerRunlistChram && pKernelFifo->bDisableChidIsolation) ? NV_FALSE : NV_TRUE; pChidMgr->pGlobalChIDHeap->eheapSetOwnerIsolation(pChidMgr->pGlobalChIDHeap, - NV_TRUE, + bIsolationEnabled, RM_PAGE_SIZE / userdBar1Size); // Disable USERD allocation isolation for guest if disabled from vmioplugin @@ -1653,6 +1654,7 @@ kfifoGetChannelIterator_IMPL { portMemSet(pIt, 0, sizeof(*pIt)); pIt->physicalChannelID = 0; + pIt->pFifoDataBlock = NULL; pIt->runlistId = 0; pIt->numRunlists = 1; if (kfifoIsPerRunlistChramEnabled(pKernelFifo)) @@ -1702,30 +1704,49 @@ NV_STATUS kfifoGetNextKernelChannel_IMPL } pIt->numChannels = kfifoChidMgrGetNumChannels(pGpu, pKernelFifo, pChidMgr); + + if (pIt->pFifoDataBlock == NULL) + { + pIt->pFifoDataBlock = pChidMgr->pFifoDataHeap->eheapGetBlock( + pChidMgr->pFifoDataHeap, + pIt->physicalChannelID, + NV_TRUE); + } + while (pIt->physicalChannelID < pIt->numChannels) { - pKernelChannel = kfifoChidMgrGetKernelChannel(pGpu, pKernelFifo, - pChidMgr, - pIt->physicalChannelID); - pIt->physicalChannelID++; + if (pIt->pFifoDataBlock->owner == NVOS32_BLOCK_TYPE_FREE) + { + pIt->physicalChannelID = pIt->pFifoDataBlock->end + 1; + } + else + { + pIt->physicalChannelID++; + pKernelChannel = (KernelChannel *)pIt->pFifoDataBlock->pData; - // - // This iterator can be used during an interrupt, when a KernelChannel may - // be in the process of being destroyed. If a KernelChannel expects a pChannel - // but does not have one, it means it's being destroyed and we don't want to - // return it. - // - if (pKernelChannel == NULL) - continue; - if (!kchannelIsValid_HAL(pKernelChannel)) - continue; - *ppKernelChannel = pKernelChannel; - return NV_OK; + // + // This iterator can be used during an interrupt, when a KernelChannel may + // be in the process of being destroyed. If a KernelChannel expects a pChannel + // but does not have one, it means it's being destroyed and we don't want to + // return it. + // + if (pKernelChannel != NULL && kchannelIsValid_HAL(pKernelChannel)) + { + // Prepare iterator to check next block in pChidMgr->pFifoDataHeap + pIt->pFifoDataBlock = pIt->pFifoDataBlock->next; + *ppKernelChannel = pKernelChannel; + return NV_OK; + } + } + + // Check next block in pChidMgr->pFifoDataHeap + pIt->pFifoDataBlock = pIt->pFifoDataBlock->next; } pIt->runlistId++; - // Reset channel index to 0 for next runlist + // Reset iterator for next runlist pIt->physicalChannelID = 0; + pIt->pFifoDataBlock = NULL; } return NV_ERR_OBJECT_NOT_FOUND; diff --git a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c index bdd41cce3..34e1ae792 100644 --- a/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c +++ b/src/nvidia/src/kernel/gpu/fifo/kernel_idle_channels.c @@ -213,6 +213,11 @@ RmIdleChannels numChannelsPerGpu[gpuIdx]); pPerGpuChannels = portMemAllocNonPaged((sizeof *pPerGpuChannels) * numChannelsPerGpu[gpuIdx]); + NV_CHECK_OR_ELSE(LEVEL_ERROR, + ((pPerGpuClients != NULL) && + (pPerGpuDevices != NULL) && + (pPerGpuChannels != NULL)), + rmStatus = NV_ERR_NO_MEMORY; goto done); for (chanIdx = 0; chanIdx < numChannels && perGpuIdx < numChannelsPerGpu[gpuIdx]; diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 5a26f7aeb..9b2a3e381 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -2046,6 +2046,28 @@ gpuStateInit_IMPL goto gpuStateInit_exit; } + // Set a property indicating that VF BAR0 MMU TLB Invalidation register emulation is required or not. + if (hypervisorIsVgxHyper()) + { + if ( + IsdADA(pGpu) || + 0) + { + NvU32 data32 = NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DEFAULT; + + // Registry override to change default mode, i.e, emulate VF MMU TLB Invalidation register + if ((osReadRegistryDword(pGpu, NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, &data32) == NV_OK) && + (data32 == NV_REG_STR_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE_DISABLE)) + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, NV_FALSE); + } + } + else + { + pGpu->setProperty(pGpu, PDB_PROP_GPU_BUG_3007008_EMULATE_VF_MMU_TLB_INVALIDATE, NV_FALSE); + } + } + // Set a property indicating that the state initialization has been done pGpu->setProperty(pGpu, PDB_PROP_GPU_STATE_INITIALIZED, NV_TRUE); @@ -3759,10 +3781,13 @@ NV_STATUS gpuConstructEngineTable_IMPL // Initialize per-GPU per-engine list of non-stall interrupt event nodes. for (engineIdx = 0; engineIdx < (NvU32)RM_ENGINE_TYPE_LAST; engineIdx++) { - pGpu->engineNonstallIntr[engineIdx].pEventNode = NULL; - pGpu->engineNonstallIntr[engineIdx].pSpinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged()); - if (pGpu->engineNonstallIntr[engineIdx].pSpinlock == NULL) - return NV_ERR_INSUFFICIENT_RESOURCES; + NV_STATUS status = gpuEngineEventNotificationListCreate(pGpu, + &pGpu->engineNonstallIntrEventNotifications[engineIdx]); + if (status != NV_OK) + { + gpuDestroyEngineTable(pGpu); + return status; + } } return NV_OK; @@ -3816,7 +3841,9 @@ NV_STATUS gpuUpdateEngineTable_IMPL } void gpuDestroyEngineTable_IMPL(OBJGPU *pGpu) { - NvU32 engineIdx = 0; + for (NvU32 engineIdx = 0; engineIdx < (NvU32)RM_ENGINE_TYPE_LAST; engineIdx++) + gpuEngineEventNotificationListDestroy(pGpu, + pGpu->engineNonstallIntrEventNotifications[engineIdx]); if (pGpu->engineDB.pType) { @@ -3825,16 +3852,6 @@ void gpuDestroyEngineTable_IMPL(OBJGPU *pGpu) pGpu->engineDB.pType = NULL; pGpu->engineDB.bValid = NV_FALSE; } - - for (engineIdx = 0; engineIdx < (NvU32)RM_ENGINE_TYPE_LAST; engineIdx++) - { - NV_ASSERT(pGpu->engineNonstallIntr[engineIdx].pEventNode == NULL); - - if (pGpu->engineNonstallIntr[engineIdx].pSpinlock != NULL) - { - portSyncSpinlockDestroy(pGpu->engineNonstallIntr[engineIdx].pSpinlock); - } - } } NvBool gpuCheckEngineTable_IMPL diff --git a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c index f509a5466..3a48a16ba 100644 --- a/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c +++ b/src/nvidia/src/kernel/gpu/gpu_fabric_probe.c @@ -354,7 +354,7 @@ _gpuFabricProbeSchedule pGpuFabricProbeInfo->probeRetryDelay); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) tmrEventScheduleRel failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u tmrEventScheduleRel failed\n", gpuGetInstance(pGpu)); return status; } @@ -367,7 +367,7 @@ _gpuFabricProbeSchedule pGpuFabricProbeInfo->probeRetryDelay += pGpuFabricProbeInfo->probeRetryDelay; } - NV_PRINTF(LEVEL_INFO, "GPU (ID: %d) Num retried probes %lld \n", + NV_PRINTF(LEVEL_INFO, "GPU%u Num retried probes %lld \n", gpuGetInstance(pGpu), pGpuFabricProbeInfo->numProbes); return NV_OK; @@ -394,7 +394,7 @@ _gpuFabricProbeConstructReq status = gpuGetGidInfo(pGpu, &pUuid, &uuidLength, flags); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Failed to update GPU UUID\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Failed to update GPU UUID\n", gpuGetInstance(pGpu)); return status; } @@ -410,35 +410,34 @@ _gpuFabricProbeConstructReq return status; } -static NV_STATUS -_gpuFabricProbeSend +static void +_gpuFabricProbeSend_WORKITEM ( - OBJGPU *pGpu, - OBJTMR *pTmr, - TMR_EVENT *pEvent + NvU32 gpuInstance, + void *pArgs ) { - NV_STATUS status; + OBJGPU *pGpu = gpumgrGetGpu(gpuInstance); KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); - GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo = - (GPU_FABRIC_PROBE_INFO *)pEvent->pUserData; + GPU_FABRIC_PROBE_INFO *pGpuFabricProbeInfo = pGpu->pGpuFabricProbeInfo; + NV_STATUS status; if (pKernelNvlink->bIsGpuDegraded || (pKernelNvlink->discoveredLinks == 0)) { NV_PRINTF(LEVEL_ERROR, - "GPU (ID: %d) Degraded. Not sending probe\n", + "GPU%u Degraded. Not sending probe\n", gpuGetInstance(pGpu)); _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_NOT_SUPPORTED); - return NV_ERR_NOT_SUPPORTED; + return; } if (pGpuFabricProbeInfo->bProbeRespRcvd) { NV_PRINTF(LEVEL_INFO, - "GPU (ID: %d) Probe Resp rcvd. Not sending probe\n", + "GPU%u Probe Resp rcvd. Not sending probe\n", gpuGetInstance(pGpu)); - return NV_OK; + return; } status = knvlinkSendInbandData(pGpu, @@ -446,7 +445,7 @@ _gpuFabricProbeSend &pGpuFabricProbeInfo->sendDataParams); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Send Inband data failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Send Inband data failed\n", gpuGetInstance(pGpu)); // // Deliberately ignoring return value as we want probes to be @@ -457,10 +456,33 @@ _gpuFabricProbeSend status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Schedule Probe failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Schedule Probe failed\n", gpuGetInstance(pGpu)); _gpuFabricProbeForceCompletionError(pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); - return status; + return; + } +} + +static NV_STATUS +_gpuFabricProbeScheduleWq +( + OBJGPU *pGpu, + OBJTMR *pTmr, + TMR_EVENT *pEvent +) +{ + OBJOS *pOS = GPU_GET_OS(pGpu); + NV_STATUS status = NV_OK; + + NV_ASSERT_OR_RETURN(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)), NV_ERR_INVALID_STATE); + + status = pOS->osQueueWorkItemWithFlags(pGpu, _gpuFabricProbeSend_WORKITEM, NULL, + OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU%u OS Schedule Probe failed\n", + gpuGetInstance(pGpu)); + _gpuFabricProbeForceCompletionError(pGpu->pGpuFabricProbeInfo, NV_ERR_OPERATING_SYSTEM); } return status; @@ -547,7 +569,7 @@ _gpuFabricProbeReceive if (pProbeRespMsg->msgHdr.requestId != pProbeReqMsg->msgHdr.requestId) { NV_PRINTF(LEVEL_INFO, - "GPU (ID: %d) Probe resp invalid reqId %lld respId %lld\n", + "GPU%u Probe resp invalid reqId %lld respId %lld\n", gpuGetInstance(pGpu), pProbeReqMsg->msgHdr.requestId, pProbeRespMsg->msgHdr.requestId); @@ -620,7 +642,6 @@ gpuFabricProbeResume ) { OBJGPU *pGpu; - OBJTMR *pTmr; NV_STATUS status = NV_OK; if (pGpuFabricProbeInfo == NULL) @@ -632,16 +653,14 @@ gpuFabricProbeResume NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu))); - pTmr = GPU_GET_TIMER(pGpu); - NV_ASSERT(pGpuFabricProbeInfo->pTmrEvent != NULL); if (!gpuFabricProbeIsReceived(pGpuFabricProbeInfo)) { - status = _gpuFabricProbeSend(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); + status = _gpuFabricProbeSchedule(pGpuFabricProbeInfo); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Resume and Sending probe request failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Resume and Sending probe request failed\n", gpuGetInstance(pGpu)); } } @@ -689,11 +708,10 @@ gpuFabricProbeStart pGpuFabricProbeInfo->pGpu = pGpu; status = tmrEventCreate(pTmr, &pGpuFabricProbeInfo->pTmrEvent, - _gpuFabricProbeSend, pGpuFabricProbeInfo, - TMR_FLAGS_NONE); + _gpuFabricProbeScheduleWq, NULL, TMR_FLAGS_NONE); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Timer create failure\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Timer create failure\n", gpuGetInstance(pGpu)); goto fail; } @@ -710,7 +728,7 @@ gpuFabricProbeStart status = _gpuFabricProbeConstructReq(&pProbeReqMsg->probeReq, pGpu); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Init Probe request failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Init Probe request failed\n", gpuGetInstance(pGpu)); goto fail; } @@ -720,7 +738,7 @@ gpuFabricProbeStart sizeof(pProbeReqMsg->probeReq)); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Init of Inband msg hdr failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Init of Inband msg hdr failed\n", gpuGetInstance(pGpu)); goto fail; } @@ -737,16 +755,22 @@ gpuFabricProbeStart &inbandMsgCbParams); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Registering Inband Cb failed\n", + NV_PRINTF(LEVEL_ERROR, "GPU%u Registering Inband Cb failed\n", gpuGetInstance(pGpu)); goto fail; } - status = _gpuFabricProbeSend(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); + // + // Queue the probe work item directly (without timer delay). + // A small timer delay is likely to fire and be unable to acquire the lock + // (because we'll still be holding it). The timer event will be used if the + // probe work item needs to be rescheduled with a delay. + // + status = _gpuFabricProbeScheduleWq(pGpu, pTmr, pGpuFabricProbeInfo->pTmrEvent); if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) Sending probe request failed\n", - gpuGetInstance(pGpu)); + NV_PRINTF(LEVEL_ERROR, "GPU%u failed to schedule probe work item (status = 0x%x)\n", + gpuGetInstance(pGpu), status); goto fail; } @@ -810,7 +834,7 @@ gpuFabricProbeIsSupported { if (pGpu->fabricProbeRetryDelay == 0) { - NV_PRINTF(LEVEL_INFO, "GPU (ID: %d) Probe handling is disabled\n", + NV_PRINTF(LEVEL_INFO, "GPU%u Probe handling is disabled\n", gpuGetInstance(pGpu)); return NV_FALSE; } diff --git a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c index 08d79e062..076ea39c9 100644 --- a/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c +++ b/src/nvidia/src/kernel/gpu/gr/kernel_graphics.c @@ -2122,7 +2122,8 @@ deviceCtrlCmdKGrGetCaps_IMPL ) { OBJGPU *pGpu = GPU_RES_GET_GPU(pDevice); - NvBool bCapsPopulated = NV_FALSE; + NvU8 *pGrCaps = NvP64_VALUE(pParams->capsTbl); + NvBool bCapsPopulated = NV_FALSE; LOCK_ASSERT_AND_RETURN(rmapiLockIsOwner()); @@ -2147,7 +2148,7 @@ deviceCtrlCmdKGrGetCaps_IMPL if (!bCapsPopulated) { NV_CHECK_OK_OR_ELSE(status, LEVEL_ERROR, - kgraphicsGetCaps(pGpu, pKernelGraphics, pParams->capsTbl), + kgraphicsGetCaps(pGpu, pKernelGraphics, pGrCaps), SLI_LOOP_RETURN(status);); bCapsPopulated = NV_TRUE; diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c new file mode 100644 index 000000000..0ba69346f --- /dev/null +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c @@ -0,0 +1,111 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/*! + * Provides AD102+ specific KernelGsp HAL implementations. + */ + +#include "gpu/gsp/kernel_gsp.h" + +#include "gpu/falcon/kernel_falcon.h" +#include "gpu/sec2/kernel_sec2.h" + +#include "published/ada/ad102/dev_gc6_island.h" +#include "published/ada/ad102/dev_gc6_island_addendum.h" + +static NvBool +_kgspIsScrubberCompleted +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NvU32 data = GPU_REG_RD32(pGpu, NV_PGC6_BSI_VPR_SECURE_SCRATCH_15); + NvU32 handoff = DRF_VAL(_PGC6, _BSI_VPR_SECURE_SCRATCH_15, _SCRUBBER_HANDOFF, data); + return (handoff >= NV_PGC6_BSI_VPR_SECURE_SCRATCH_15_SCRUBBER_HANDOFF_DONE); +} + +NV_STATUS +kgspExecuteScrubberIfNeeded_AD102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + NV_STATUS status; + KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); + + // skip executing Scrubber if it has already run + if (_kgspIsScrubberCompleted(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_INFO, "skipping executing Scrubber as it already ran\n"); + return NV_OK; + } + + NV_PRINTF(LEVEL_INFO, "executing Scrubber\n"); + NV_ASSERT_OR_RETURN(pKernelGsp->pScrubberUcode != NULL, NV_ERR_INVALID_STATE); + + kflcnReset_HAL(pGpu, staticCast(pKernelSec2, KernelFalcon)); + + status = kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, + pKernelGsp->pScrubberUcode, staticCast(pKernelSec2, KernelFalcon), + NULL, NULL); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Scrubber: 0x%x\n", status); + return status; + } + + if (!_kgspIsScrubberCompleted(pGpu, pKernelGsp)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute Scrubber: done bit not set\n"); + return NV_ERR_GENERIC; + } + + return status; +} + +NvU64 +kgspGetWprHeapSize_AD102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + if (pGpu->bVgpuGspPluginOffloadEnabled) + { + // + // Memory calculations which we used to size the WPR heap: + // Memory needed for libOS kernel - 10MB(RM) + 32MB(VF partitions) + 8MB(global page) = 50MB + // Memory needed from FW's Heap - 17MB for RM + 15MB * 32(VF) = 497MB + // Total Memory needed = 497MB + 50MB = 547MB + // (Added extra 2 Mb due to alignment) + // @TODO: Change total Heap size to 546MB once fix for making global page to 4MB submitted. + // + return 550 * 1024 * 1024; + } + else + { + return 80 * 1024 * 1024; + } +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 72d8c7046..7a12e97e6 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -193,6 +193,14 @@ kgspBootstrapRiscvOSEarly_GA102 // Fb configuration is done so setup libos arg list kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); + // Execute Scrubber if needed + if (pKernelGsp->pScrubberUcode != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, + kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp), + exit); + } + RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; { diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index 5b8ddc94b..f46f8881e 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -392,6 +392,14 @@ kgspBootstrapRiscvOSEarly_TU102 // Load init args into mailbox regs kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); + // Execute Scrubber if needed + if (pKernelGsp->pScrubberUcode != NULL) + { + NV_ASSERT_OK_OR_GOTO(status, + kgspExecuteScrubberIfNeeded_HAL(pGpu, pKernelGsp), + exit); + } + { status = kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, memdescGetPhysAddr(pKernelGsp->pWprMetaDescriptor, AT_GPU, 0)); @@ -572,10 +580,6 @@ kgspCalculateFbLayout_TU102 pWprMeta->gspFwRsvdStart = pWprMeta->nonWprHeapOffset; - // Make sure carveout size is less than 256MB - NV_ASSERT_OR_RETURN((pWprMeta->fbSize - pWprMeta->gspFwRsvdStart) < (256 * 1024 * 1024), - NV_ERR_OUT_OF_RANGE); - // Physical address of GSP-RM firmware in system memory. pWprMeta->sysmemAddrOfRadix3Elf = memdescGetPhysAddr(pKernelGsp->pGspUCodeRadix3Descriptor, AT_GPU, 0); @@ -594,11 +598,21 @@ kgspCalculateFbLayout_TU102 pWprMeta->sysmemAddrOfSignature = memdescGetPhysAddr(pKernelGsp->pSignatureMemdesc, AT_GPU, 0); pWprMeta->sizeOfSignature = memdescGetSize(pKernelGsp->pSignatureMemdesc); } + pWprMeta->bootCount = 0; pWprMeta->verified = 0; pWprMeta->revision = GSP_FW_WPR_META_REVISION; pWprMeta->magic = GSP_FW_WPR_META_MAGIC; + if (pGpu->bVgpuGspPluginOffloadEnabled) + { + pKernelGsp->pWprMeta->driverModel = 1; + } + else + { + pKernelGsp->pWprMeta->driverModel = 0; + } + #if 0 NV_PRINTF(LEVEL_ERROR, "WPR meta data offset: 0x%016llx\n", pWprMeta->gspFwWprStart); NV_PRINTF(LEVEL_ERROR, " magic: 0x%016llx\n", pWprMeta->magic); diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c index 30053fb3d..26efefcfe 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c @@ -486,7 +486,7 @@ kgspExtractVbiosFromRom_TU102 { NV_PRINTF(LEVEL_ERROR, "ERoT Req/Grant for EEPROM access failed, status=%u\n", status); - return status; + goto out; } } diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index 6e540b3bf..cd8d6e719 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -35,9 +35,7 @@ #include "virtualization/vgpuconfigapi.h" #include "kernel/gpu/disp/kern_disp.h" #include "gpu/external_device/external_device.h" - #include "class/cl2080.h" // NV20_SUBDEVICE_0 - #include "liblogdecode.h" #include "libelf.h" #include "nverror.h" @@ -1293,6 +1291,241 @@ _kgspFreeRpcInfrastructure } } +/*! + * Convert init arg name to 64bit id value. + * + * @param[in] name String representing name of init arg + */ +static NvU64 +_kgspGenerateInitArgId(const char *name) +{ + NvU64 id = 0; + NvU8 c; + NvU32 i; + + // Convert at most 8 characters from name into id. + for (i = 0; i < (sizeof(NvU64) / sizeof(NvU8)); ++i) + { + c = (NvU8)*name++; + if (c == '\0') + { + break; + } + id = (id << 8) | c; + } + + return id; +} + +/*! + * Free vgpu partition LIBOS task logging structures + */ +static void +_kgspFreeLibosVgpuPartitionLoggingStructures +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 gfid +) +{ + libosLogDestroy(&pKernelGsp->logDecodeVgpuPartition[gfid - 1]); + + // release the vgpu task log buffer memory + RM_LIBOS_LOG_MEM *pGspPluginVgpuTaskLog = &pKernelGsp->gspPluginVgpuTaskLogMem[gfid - 1]; + + if (pGspPluginVgpuTaskLog->pTaskLogBuffer != NULL) + { + memdescUnmapInternal(pGpu, pGspPluginVgpuTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + + pGspPluginVgpuTaskLog->pTaskLogBuffer = NULL; + } + + if (pGspPluginVgpuTaskLog->pTaskLogDescriptor != NULL) + { + memdescFree(pGspPluginVgpuTaskLog->pTaskLogDescriptor); + memdescDestroy(pGspPluginVgpuTaskLog->pTaskLogDescriptor); + pGspPluginVgpuTaskLog->pTaskLogDescriptor = NULL; + } + + // release the init task log buffer memory + RM_LIBOS_LOG_MEM *pGspPluginInitTaskLog = &pKernelGsp->gspPluginInitTaskLogMem[gfid - 1]; + + if (pGspPluginInitTaskLog->pTaskLogBuffer != NULL) + { + memdescUnmapInternal(pGpu, pGspPluginInitTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + + pGspPluginInitTaskLog->pTaskLogBuffer = NULL; + } + + if (pGspPluginInitTaskLog->pTaskLogDescriptor != NULL) + { + memdescFree(pGspPluginInitTaskLog->pTaskLogDescriptor); + memdescDestroy(pGspPluginInitTaskLog->pTaskLogDescriptor); + pGspPluginInitTaskLog->pTaskLogDescriptor = NULL; + } +} + +/*! + * Free vgpu partition LIBOS task logging structures + */ +NV_STATUS +kgspFreeVgpuPartitionLogging_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 gfid +) +{ + if (gfid > MAX_PARTITIONS_WITH_GFID) + { + return NV_ERR_INVALID_ARGUMENT; + } + else + { + // Make sure there is no lingering debug output. + kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); + + _kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid); + return NV_OK; + } +} + +/*! + * Initialize vgpu partition LIBOS task logging structures + */ +NV_STATUS +kgspInitVgpuPartitionLogging_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + NvU32 gfid, + NvU64 initTaskLogBUffOffset, + NvU64 initTaskLogBUffSize, + NvU64 vgpuTaskLogBUffOffset, + NvU64 vgpuTaskLogBuffSize +) +{ + NV_STATUS nvStatus = NV_OK; + RM_LIBOS_LOG_MEM *pGspPluginVgpuTaskLog = NULL; + RM_LIBOS_LOG_MEM *pGspPluginInitTaskLog = NULL; + char vm_string[8], sourceName[SOURCE_NAME_MAX_LENGTH]; + + if (gfid > MAX_PARTITIONS_WITH_GFID) + { + return NV_ERR_INVALID_ARGUMENT; + } + + // Source name is used to generate a tag that is a unique identifier for nvlog buffers. + // As the source name 'GSP' is already in use, we will need a custom source name. + nvDbgSnprintf(sourceName, SOURCE_NAME_MAX_LENGTH, "V%02d", gfid); + libosLogCreateEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], sourceName); + + // Setup logging for vgpu task in vgpu partition + { + pGspPluginVgpuTaskLog = &pKernelGsp->gspPluginVgpuTaskLogMem[gfid - 1]; + NvP64 pVa = NvP64_NULL; + + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pGspPluginVgpuTaskLog->pTaskLogDescriptor, + pGpu, + vgpuTaskLogBuffSize, + RM_PAGE_SIZE, + NV_TRUE, ADDR_FBMEM, NV_MEMORY_CACHED, + MEMDESC_FLAGS_NONE), + error_cleanup); + + + memdescDescribe(pGspPluginVgpuTaskLog->pTaskLogDescriptor, ADDR_FBMEM, vgpuTaskLogBUffOffset, vgpuTaskLogBuffSize); + + pVa = memdescMapInternal(pGpu, pGspPluginVgpuTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + + if (pVa != NvP64_NULL) + { + pGspPluginVgpuTaskLog->pTaskLogBuffer = pVa; + portMemSet(pGspPluginVgpuTaskLog->pTaskLogBuffer, 0, vgpuTaskLogBuffSize); + + pGspPluginVgpuTaskLog->id8 = _kgspGenerateInitArgId("LOGVGPU"); + + nvDbgSnprintf(vm_string, sizeof(vm_string), "VGPU%d", gfid); + + libosLogAddLogEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], + pGspPluginVgpuTaskLog->pTaskLogBuffer, + memdescGetSize(pGspPluginVgpuTaskLog->pTaskLogDescriptor), + pGpu->gpuInstance, + (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), + gpuGetChipImpl(pGpu), + vm_string, + ".fwlogging_vgpu"); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to map memory for vgpu task log buffer for vGPU partition \n"); + nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto error_cleanup; + } + } + + // Setup logging for init task in vgpu partition + { + pGspPluginInitTaskLog = &pKernelGsp->gspPluginInitTaskLogMem[gfid - 1]; + NvP64 pVa = NvP64_NULL; + + NV_ASSERT_OK_OR_GOTO(nvStatus, + memdescCreate(&pGspPluginInitTaskLog->pTaskLogDescriptor, + pGpu, + initTaskLogBUffSize, + RM_PAGE_SIZE, + NV_TRUE, ADDR_FBMEM, NV_MEMORY_CACHED, + MEMDESC_FLAGS_NONE), + error_cleanup); + + memdescDescribe(pGspPluginInitTaskLog->pTaskLogDescriptor, ADDR_FBMEM, initTaskLogBUffOffset, initTaskLogBUffSize); + + pVa = memdescMapInternal(pGpu, pGspPluginInitTaskLog->pTaskLogDescriptor, TRANSFER_FLAGS_NONE); + + if (pVa != NvP64_NULL) + { + pGspPluginInitTaskLog->pTaskLogBuffer = pVa; + portMemSet(pGspPluginInitTaskLog->pTaskLogBuffer, 0, initTaskLogBUffSize); + + pGspPluginInitTaskLog->id8 = _kgspGenerateInitArgId("LOGINIT"); + + nvDbgSnprintf(vm_string, sizeof(vm_string), "INIT%d", gfid); + + libosLogAddLogEx(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], + pGspPluginInitTaskLog->pTaskLogBuffer, + memdescGetSize(pGspPluginInitTaskLog->pTaskLogDescriptor), + pGpu->gpuInstance, + (gpuGetChipArch(pGpu) >> GPU_ARCH_SHIFT), + gpuGetChipImpl(pGpu), + vm_string, + ".fwlogging_init"); + } + else + { + NV_PRINTF(LEVEL_ERROR, "Failed to map memory for init task log buffer for vGPU partition \n"); + nvStatus = NV_ERR_INSUFFICIENT_RESOURCES; + goto error_cleanup; + } + } + + { + libosLogInit(&pKernelGsp->logDecodeVgpuPartition[gfid - 1], pKernelGsp->pLogElf, pKernelGsp->logElfDataSize); + // nvlog buffers are now setup using the appropriate sourceName to avoid tag-value clash. + // Now sourceName can be modified to preserve the 'GSP-VGPUx' logging convention. + portStringCopy(pKernelGsp->logDecodeVgpuPartition[gfid - 1].sourceName, + SOURCE_NAME_MAX_LENGTH, + "GSP", SOURCE_NAME_MAX_LENGTH); + } + +error_cleanup: + if (nvStatus != NV_OK) + _kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid); + + return nvStatus; +} + /*! * Free LIBOS task logging structures */ @@ -1339,32 +1572,6 @@ _kgspFreeLibosLoggingStructures pKernelGsp->pLogElf = NULL; } -/*! - * Convert init arg name to 64bit id value. - * - * @param[in] name String representing name of init arg - */ -static NvU64 -_kgspGenerateInitArgId(const char *name) -{ - NvU64 id = 0; - NvU8 c; - NvU32 i; - - // Convert at most 8 characters from name into id. - for (i = 0; i < (sizeof(NvU64) / sizeof(NvU8)); ++i) - { - c = (NvU8)*name++; - if (c == '\0') - { - break; - } - id = (id << 8) | c; - } - - return id; -} - /*! * Initialize LIBOS task logging structures */ @@ -1386,10 +1593,12 @@ _kgspInitLibosLoggingStructures { {"LOGINIT", "INIT", 0x10000, ".fwlogging_init"}, // 64KB for stack traces #if defined(DEVELOP) || defined(DEBUG) - {"LOGVGPU", "VGPU", 0x40000, ".fwlogging_vgpu"}, // 256KB VGPU debug log on develop/debug builds + // The interrupt task is in the rm elf, so they share the same logging elf too + {"LOGINTR", "INTR", 0x40000, ".fwlogging_rm"}, // 256KB ISR debug log on develop/debug builds {"LOGRM", "RM", 0x40000, ".fwlogging_rm"} // 256KB RM debug log on develop/debug builds #else - {"LOGVGPU", "VGPU", 0x10000, ".fwlogging_vgpu"}, // 64KB VGPU debug log on release builds + // The interrupt task is in the rm elf, so they share the same logging elf too + {"LOGINTR", "INTR", 0x10000, ".fwlogging_rm"}, // 64KB ISR debug log on develop/debug builds {"LOGRM", "RM", 0x10000, ".fwlogging_rm"} // 64KB RM debug log on release builds #endif }; @@ -1480,6 +1689,8 @@ _kgspInitLibosLoggingStructures error_cleanup); pKernelGsp->pLogElf = portMemAllocNonPaged(logSize); + pKernelGsp->logElfDataSize = logSize; + if (pKernelGsp->pLogElf == NULL) { NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory for log elf"); @@ -1769,6 +1980,34 @@ kgspInitRm_IMPL goto done; } + // Prepare Scrubber ucode image if pre-scrubbed memory is insufficient + if (pKernelGsp->pScrubberUcode == NULL) + { + NvU64 neededSize = pKernelGsp->pWprMeta->fbSize - pKernelGsp->pWprMeta->gspFwRsvdStart; + NvU64 prescrubbedSize = kgspGetPrescrubbedTopFbSize(pGpu, pKernelGsp); + + if (neededSize > prescrubbedSize) + { + NV_PRINTF(LEVEL_INFO, + "allocating Scrubber ucode as pre-scrubbed memory (0x%llx bytes) is insufficient (0x%llx bytes needed)\n", + prescrubbedSize, neededSize); + + status = kgspAllocateScrubberUcodeImage(pGpu, pKernelGsp, + &pKernelGsp->pScrubberUcode); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to allocate Scrubber ucode: 0x%x\n", status); + goto done; + } + } + else + { + NV_PRINTF(LEVEL_INFO, + "skipping allocating Scrubber ucode as pre-scrubbed memory (0x%llx bytes) is sufficient (0x%llx bytes needed)\n", + prescrubbedSize, neededSize); + } + } + NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspInitLogging(pGpu, pKernelGsp, pGspFw), done); // Wait for GFW_BOOT OK status @@ -1805,8 +2044,16 @@ done: if (status != NV_OK) { - // Preserve any captured gsp-rm logs + KernelPmu *pKernelPmu = GPU_GET_KERNEL_PMU(pGpu); + + // Preserve any captured GSP-RM logs libosPreserveLogs(&pKernelGsp->logDecode); + + if (pKernelPmu != NULL) + { + // If PMU init fails, kgsp init will also fail + libosPreserveLogs(&pKernelPmu->logDecode); + } } if (gpusLockedMask != 0) @@ -1925,6 +2172,7 @@ kgspDestruct_IMPL pKernelGsp->pBooterUnloadUcode = NULL; kgspFreeBootArgs_HAL(pGpu, pKernelGsp); + _kgspFreeLibosLoggingStructures(pGpu, pKernelGsp); _kgspFreeRpcInfrastructure(pGpu, pKernelGsp); _kgspFreeBootBinaryImage(pGpu, pKernelGsp); @@ -1957,6 +2205,15 @@ kgspDumpGspLogs_IMPL libosExtractLogs(&pKernelGsp->logDecode, bSyncNvLog); } + if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu)) + { + // Dump logs from vGPU partition + for (NvU32 i = 0; i < MAX_PARTITIONS_WITH_GFID; i++) + { + libosExtractLogs(&pKernelGsp->logDecodeVgpuPartition[i], bSyncNvLog); + } + } + } /*! @@ -2490,7 +2747,6 @@ _kgspFwContainerGetSection NV_CHECK_OR_RETURN(LEVEL_ERROR, pSectionName != NULL, NV_ERR_INVALID_ARGUMENT); NV_CHECK_OR_RETURN(LEVEL_ERROR, ppSectionData != NULL, NV_ERR_INVALID_ARGUMENT); NV_CHECK_OR_RETURN(LEVEL_ERROR, pSectionSize != NULL, NV_ERR_INVALID_ARGUMENT); - NV_CHECK_OR_RETURN(LEVEL_ERROR, elfDataSize >= sizeof(LibosElf64Header), NV_ERR_INVALID_DATA); sectionNameLength = portStringLength(pSectionName); @@ -2520,6 +2776,7 @@ _kgspFwContainerGetSection // Iterate through all of the section headers to find the signatures pElfSectionHeader = (const LibosElf64SectionHeader*) &pGspBuf[elfSectionHeaderMaxIdx + 1 - sizeof(*pElfSectionHeader)]; + for (idx = pElfHeader->shnum - 1; idx >= 0; idx--, pElfSectionHeader--) { NvU64 currentSectionNameMaxLength; diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c index 8ea5b9706..607ff7dc1 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c @@ -466,3 +466,28 @@ kgspAllocateBooterUnloadUcodeImage_IMPL return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, ppBooterUnloadUcode); } + +// +// Note: Scrubber is not a Booter ucode, however it is a SEC2 ucode that uses +// a similar loading and signature patching scheme, so we may use the same +// helper functions. +// +NV_STATUS +kgspAllocateScrubberUcodeImage_IMPL +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + KernelGspFlcnUcode **ppScrubberUcode // out +) +{ + KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); + const BINDATA_ARCHIVE *pBinArchive; + + NV_ASSERT_OR_RETURN(pKernelSec2 != NULL, NV_ERR_INVALID_STATE); + NV_ASSERT_OR_RETURN(ppScrubberUcode != NULL, NV_ERR_INVALID_ARGUMENT); + + pBinArchive = ksec2GetBinArchiveSecurescrubUcode_HAL(pGpu, pKernelSec2); + NV_ASSERT_OR_RETURN(pBinArchive != NULL, NV_ERR_NOT_SUPPORTED); + + return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, ppScrubberUcode); +} diff --git a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c index d26fd4bc3..6eb9c7a2e 100644 --- a/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c +++ b/src/nvidia/src/kernel/gpu/intr/arch/ampere/intr_ga100.c @@ -60,7 +60,8 @@ intrGetUvmSharedLeafEnDisableMask_GA100 NvU32 intrVectorTimerSwrl = NV_INTR_VECTOR_INVALID; NvU64 mask = 0; - // GSP RM services both MMU non-replayable fault and FIFO interrupts + // GSP RM services both MMU non-replayable fault and FIFO interrupts with + // vgpu plugin offload enabled. Otherwise, GSP RM only services FIFO interrupts if (IS_GSP_CLIENT(pGpu)) { return ~mask; @@ -73,7 +74,7 @@ intrGetUvmSharedLeafEnDisableMask_GA100 intrVectorTimerSwrl = intrGetVectorFromEngineId(pGpu, pIntr, MC_ENGINE_IDX_TMR_SWRL, NV_FALSE); } - if (intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) + if (intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID && intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) { // Ascertain that they're in the same subtree and same leaf NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_SUBTREE(intrVectorNonReplayableFault) == @@ -82,10 +83,6 @@ intrGetUvmSharedLeafEnDisableMask_GA100 NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl)); } - // Ascertain that they're in the first leaf - NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == - NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); - // // Compile-time ascertain that we only have 1 client subtree (we assume // this since we cache only 64 bits). @@ -99,10 +96,22 @@ intrGetUvmSharedLeafEnDisableMask_GA100 ct_assert((NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_END(NV_CPU_INTR_UVM_SHARED_SUBTREE_LAST) - 1) == NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); - mask = NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); + // On GSP we service non replayable faults in the bottom half, so we shouldn't mask them + if (intrVectorNonReplayableFault != NV_INTR_VECTOR_INVALID) + { + // Ascertain that it's in the first leaf + NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorNonReplayableFault) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + + mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorNonReplayableFault)); + } if (intrVectorTimerSwrl != NV_INTR_VECTOR_INVALID) { + // Ascertain that it's in the first leaf + NV_ASSERT(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(intrVectorTimerSwrl) == + NV_CTRL_INTR_SUBTREE_TO_LEAF_IDX_START(NV_CPU_INTR_UVM_SHARED_SUBTREE_START)); + mask |= NVBIT32(NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(intrVectorTimerSwrl)); } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c index 6aae2f42d..ee66b4ea8 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/addrtree.c @@ -41,7 +41,7 @@ static void _addrtreeConvertLevelFrameToNodeIndex(PMA_ADDRTREE *pTree, NvU32 lev ADDRTREE_NODE **ppNode, NvU32 *pIndex); PMA_PAGESTATUS _pmaAddrtreeReadLevelAndSkipUnavailable(void *pMap, NvU32 levelNum, NvU64 frameNum, PMA_PAGESTATUS searchState, NvBool bAllowFree, - NvU64 *pNumFramesToSkip); + NvU64 *pNumFramesToSkip, NvBool bReverse); static NvU64 alignUpToMod(NvU64 frame, NvU64 alignment, NvU64 mod) { @@ -510,6 +510,7 @@ _addrtreeNodeMaskAvailable( ADDRTREE_NODE *node, NvU64 mask, PMA_PAGESTATUS state, + NvBool bReverse, NvU64 *pDiff ) { @@ -534,13 +535,21 @@ _addrtreeNodeMaskAvailable( allocated &= mask; - // - // Skip past all unavailable and return last child index - // which does not satisfy the given state - // This will underflow for allocated == 0, but in that case, - // *pDiff should not be read anyway - // - *pDiff = 64 - portUtilCountLeadingZeros64(allocated) - 1; + if (!bReverse) + { + // + // Skip past all unavailable and return last child index + // which does not satisfy the given state + // This will underflow for allocated == 0, but in that case, + // *pDiff should not be read anyway + // + *pDiff = 64 - portUtilCountLeadingZeros64(allocated) - 1; + } + else + { + // Return the first child index that doesn't satisfy given state + *pDiff = portUtilCountTrailingZeros64(allocated); + } return (allocated == 0); } @@ -575,7 +584,8 @@ _pmaAddrtreeReadLevelAndSkipUnavailable NvU64 frameNum, PMA_PAGESTATUS searchState, NvBool bAllowFree, - NvU64 *pNumFramesToSkip + NvU64 *pNumFramesToSkip, + NvBool bReverse ) { NvU32 index; @@ -618,7 +628,10 @@ _pmaAddrtreeReadLevelAndSkipUnavailable _addrtreeConvertFrame(pTree, n->level, newFrame, levelNum, &targetFrameStartForThisNode); _addrtreeConvertFrame(pTree, n->level, 1ULL, levelNum, &numTargetFramesPerAncestor); - *pNumFramesToSkip = numTargetFramesPerAncestor - (frameNum - targetFrameStartForThisNode); + if (!bReverse) + *pNumFramesToSkip = numTargetFramesPerAncestor - (frameNum - targetFrameStartForThisNode); + else + *pNumFramesToSkip = frameNum - targetFrameStartForThisNode + 1; } else { // // This node is in a state we're searching for. @@ -693,7 +706,7 @@ _pmaAddrtreeAvailable { childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); - if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, &nodeIndexDiff)) + if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_FALSE, &nodeIndexDiff)) { *pDiff = node->frame + nodeIndexDiff; return NV_FALSE; @@ -724,6 +737,75 @@ _pmaAddrtreeAvailable return NV_TRUE; } +// +// For the given state, between frameStart and (frameStart + numFrames - 1) +// for a given level, this function returns +// +// NV_TRUE if the range is available +// NV_FALSE if the range is not available +// and the frame number of the first frame which does not +// satisfy the given state in the variable pDiff +// +// XXX: Caution! This will not properly pick up nodes only in state `state` +// If it were used for discontig scanning, it would be wrong! +// +static NvBool +_pmaAddrtreeAvailableReverse +( + PMA_ADDRTREE *pTree, + NvU32 level, + PMA_PAGESTATUS state, + NvU64 frameStart, + NvU64 numFrames, + NvU64 *pDiff +) +{ + NvU64 i, startIdx, endIdx, childrenMask; + PMA_PAGESTATUS foundState; + NvU64 nodeIndexDiff; + ADDRTREE_NODE *node; + + NV_ASSERT(level != 0); // TODO handle the root node case + + startIdx = _addrtreeGetNodeIdx(pTree, level, frameStart); + endIdx = _addrtreeGetNodeIdx(pTree, level, (frameStart + numFrames - 1)); + + // For reverse alloc, begin checking from the start so that we can skip the most frames in the overall search + for (i = startIdx; i <= endIdx; i++) + { + node = &(pTree->levels[level].pNodeList[i]); + if (_addrtreeNodeValid(pTree, node, &foundState)) + { + childrenMask = _addrtreeComputeMask(node, frameStart, numFrames); + + if (!_addrtreeNodeMaskAvailable(node, childrenMask, state, NV_TRUE, &nodeIndexDiff)) + { + *pDiff = node->frame + nodeIndexDiff; + return NV_FALSE; + } + } + else + { + if ((foundState != STATE_FREE) && (foundState != state)) + { + // This node is completely allocated. + // Return the frame number of the first frame in this node + *pDiff = node->frame; + return NV_FALSE; + } + else + { + // + // This node is completely free or in a state we're looking for, + // continue checking + // + continue; + } + } + } + + return NV_TRUE; +} static NvBool _pmaAddrtreeContigSearchLoop @@ -766,7 +848,7 @@ _pmaAddrtreeContigSearchLoop // Read endStatus first so we don't have to waste time traversing the // tree again to read startStatus if endStatus is not even usable // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, state, NV_TRUE, &framesToSkip); + endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, state, NV_TRUE, &framesToSkip, NV_FALSE); if (framesToSkip > 1) { freeStart = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); @@ -774,7 +856,7 @@ _pmaAddrtreeContigSearchLoop continue; } - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip); + startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_FALSE); if (framesToSkip > 1) { freeStart += NV_ALIGN_UP(framesToSkip, frameAlignment); @@ -825,6 +907,103 @@ _pmaAddrtreeContigSearchLoop return found; } +static NvBool +_pmaAddrtreeContigSearchLoopReverse +( + PMA_ADDRTREE *pTree, + NvU32 level, + PMA_PAGESTATUS state, + NvU64 addrBase, + NvU64 localStart, + NvU64 localEnd, + NvU64 numFrames, + NvU64 frameAlignment, + NvU64 *freeList +) +{ + NvBool found = NV_FALSE; + NvU64 freeStart; + NvU64 diff; + PMA_PAGESTATUS startStatus, endStatus; + + if ((state != STATE_FREE) && (state != STATE_UNPIN)) + { + NV_PRINTF(LEVEL_INFO, "Scanning for state %d is not supported\n", state); + return found; + } + + freeStart = localEnd + 1 - numFrames; // First frame from end able to accommodate num_frames allocation. + freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); + while (!found) + { + NvU64 framesToSkip = 0; + + if (freeStart < localStart || (NvS64)freeStart < 0) // Account for underflow + { + // freeStart too close to local search start. Re-starting search + break; + } + + // + // For reverse allocation, read startStatus first so we don't have to waste time + // traversing the tree again to read endStatus if startStatus is not even usable + // + startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_TRUE, &framesToSkip, NV_TRUE); + if (framesToSkip > 1) { + NvU64 newEndFrame = freeStart - framesToSkip; + freeStart = newEndFrame + 1 - numFrames; + freeStart = NV_ALIGN_DOWN(freeStart, frameAlignment); + continue; + } + + endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart + numFrames - 1, state, NV_TRUE, &framesToSkip, NV_TRUE); + if (framesToSkip > 1) { + freeStart -= NV_ALIGN_UP(framesToSkip, frameAlignment); + continue; + } + + if ((startStatus == STATE_FREE) || (startStatus == state)) + { + if ((endStatus == STATE_FREE) || (endStatus == state)) + { + if (_pmaAddrtreeAvailableReverse(pTree, level, state, freeStart, numFrames, &diff)) + { + found = NV_TRUE; + // Subtract off padding when returning + *freeList = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - + (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); + //NV_PRINTF(LEVEL_INFO, "found! 0x%llx\n", freeStart); + } + else + { + //NV_PRINTF(LEVEL_INFO, "Frame number of allocated frame = 0x%llx\n", + // diff); + // + // Find the next aligned free frame and set it as the end + // frame for next iteration's scan. + // + freeStart = NV_ALIGN_DOWN(diff - numFrames, frameAlignment); + } + } + else + { + // Start point isn't free, so bump to check the next aligned frame + freeStart -= frameAlignment; + } + } + else + { + // + // End point isn't usable, so jump to after the end to check again + // However, align the new start point properly before next iteration. + // + freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); + } + } + + return found; +} + static NV_STATUS _pmaAddrtreeScanContiguous ( @@ -837,7 +1016,8 @@ _pmaAddrtreeScanContiguous NvU32 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, - NvBool bSkipEvict + NvBool bSkipEvict, + NvBool bReverseAlloc ) { NvU64 localStart, localEnd, frameAlignment; @@ -878,9 +1058,17 @@ _pmaAddrtreeScanContiguous //NV_PRINTF(LEVEL_INFO, "Scanning level %d with addrBase 0x%llx in frame range 0x%llx..0x%llx, " // "pages to allocate 0x%llx (pageSize=0x%x, alignment=0x%x)\n", // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); + if (!bReverseAlloc) + { + found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, + numPages, frameAlignment, freeList); + } + else + { + found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, + numPages, frameAlignment, freeList); + } - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); if (found) { *numPagesAlloc = numPages; @@ -893,8 +1081,16 @@ _pmaAddrtreeScanContiguous } // Loop back to the beginning and continue searching for evictable pages - found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - numPages, frameAlignment, freeList); + if (!bReverseAlloc) + { + found = _pmaAddrtreeContigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, + numPages, frameAlignment, freeList); + } + else + { + found = _pmaAddrtreeContigSearchLoopReverse(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, + numPages, frameAlignment, freeList); + } if (found) return NV_ERR_IN_USE; else @@ -917,7 +1113,8 @@ pmaAddrtreeScanContiguous NvU32 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, - NvBool bSkipEvict + NvBool bSkipEvict, + NvBool bReverseAlloc ) { if (NV_UNLIKELY(pageSize == _PMA_128KB)) { @@ -939,7 +1136,8 @@ pmaAddrtreeScanContiguous _PMA_64KB, alignment, numPagesAlloc, - bSkipEvict); + bSkipEvict, + bReverseAlloc); *numPagesAlloc /= 2; @@ -957,7 +1155,8 @@ pmaAddrtreeScanContiguous pageSize, alignment, numPagesAlloc, - bSkipEvict); + bSkipEvict, + bReverseAlloc); } } @@ -972,7 +1171,8 @@ _pmaAddrtreeDiscontigSearchLoop NvU64 localEnd, NvU64 numFrames, NvU64 frameAlignment, - NvU64 *freeList + NvU64 *freeList, + NvBool bReverseAlloc ) { NvU64 found = 0; @@ -985,7 +1185,7 @@ _pmaAddrtreeDiscontigSearchLoop return found; } - freeStart = localStart; + freeStart = !bReverseAlloc ? localStart : localEnd; // // We only need one frame at a time on this level, @@ -995,13 +1195,13 @@ _pmaAddrtreeDiscontigSearchLoop { NvU64 framesToSkip = 0; - if (freeStart > localEnd) break; + if (freeStart > localEnd || freeStart < localStart || (NvS64)freeStart < 0) break; // // For discontig, we MUST only pick up the exact state. // Otherwise we give away pages for eviction that we already stored off to be allocated. // - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_FALSE, &framesToSkip); + startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, freeStart, state, NV_FALSE, &framesToSkip, bReverseAlloc); if (startStatus == state) { @@ -1009,7 +1209,7 @@ _pmaAddrtreeDiscontigSearchLoop freeList[found++] = addrBase + ((freeStart << pTree->levels[level+1].pageSizeShift) - (pTree->numPaddingFrames << PMA_PAGE_SHIFT)); } - freeStart += framesToSkip; + freeStart = !bReverseAlloc ? (freeStart + framesToSkip) : (freeStart - framesToSkip); } return found; @@ -1027,7 +1227,8 @@ _pmaAddrtreeScanDiscontiguous NvU32 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, - NvBool bSkipEvict + NvBool bSkipEvict, + NvBool bReverseAlloc ) { NvU64 localStart, localEnd; @@ -1073,7 +1274,7 @@ _pmaAddrtreeScanDiscontiguous // (level - 1), addrBase, localStart, localEnd, numPages, pageSize, alignment); foundFree = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_FREE, addrBase, localStart, localEnd, - numPages, alignment, freeList); + numPages, alignment, freeList, bReverseAlloc); // numPagesAlloc must be set for partial allocations @@ -1093,7 +1294,7 @@ _pmaAddrtreeScanDiscontiguous // This next search picks up only evictable pages and not free pages // foundEvictable = _pmaAddrtreeDiscontigSearchLoop(pTree, level - 1, STATE_UNPIN, addrBase, localStart, localEnd, - (numPages - foundFree), alignment, (freeList + foundFree)); + (numPages - foundFree), alignment, (freeList + foundFree), bReverseAlloc); if ((foundFree + foundEvictable) == numPages) return NV_ERR_IN_USE; @@ -1117,7 +1318,8 @@ pmaAddrtreeScanDiscontiguous NvU32 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, - NvBool bSkipEvict + NvBool bSkipEvict, + NvBool bReverseAlloc ) { if (NV_UNLIKELY(pageSize == _PMA_128KB)) { @@ -1148,7 +1350,8 @@ pmaAddrtreeScanDiscontiguous _PMA_64KB, alignment, &localNumPagesAlloc, - bSkipEvict); + bSkipEvict, + bReverseAlloc); // Give back the first of every two 64KB frames *numPagesAlloc += localNumPagesAlloc / 2; @@ -1158,7 +1361,21 @@ pmaAddrtreeScanDiscontiguous return status; } - rangeStart = freeList[i] + _PMA_128KB; + if (!bReverseAlloc) + rangeStart = freeList[i] + _PMA_128KB; + else + { + rangeEnd = freeList[i] - 1; + if (rangeEnd < rangeStart || (NvS64)rangeEnd < 0) + { + // Extended the current implementation to reverse alloc here but + // isn't this logic incorrect for tryEvict case? As we are closing + // off the region for tryEvict case after an allocation is made. + // Also we don't check evictable for remaining pages after the + // first NV_ERR_IN_USE is returned. + if (i < numPages - 1) return NV_ERR_NO_MEMORY; + } + } } return status; @@ -1175,7 +1392,8 @@ pmaAddrtreeScanDiscontiguous pageSize, alignment, numPagesAlloc, - bSkipEvict); + bSkipEvict, + bReverseAlloc); } } @@ -1874,7 +2092,7 @@ NV_STATUS pmaAddrtreeScanContiguousNumaEviction // Read endStatus first so we don't have to waste time traversing the // tree again to read startStatus if endStatus is not even usable // - endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, STATE_UNPIN, NV_FALSE, &framesToSkip); + endStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, endFrame, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); if (framesToSkip > 1) { frameNum = NV_ALIGN_UP(endFrame + framesToSkip, frameAlignment); @@ -1882,7 +2100,7 @@ NV_STATUS pmaAddrtreeScanContiguousNumaEviction continue; } - startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, frameNum, STATE_UNPIN, NV_FALSE, &framesToSkip); + startStatus = _pmaAddrtreeReadLevelAndSkipUnavailable(pTree, level, frameNum, STATE_UNPIN, NV_FALSE, &framesToSkip, NV_FALSE); if (framesToSkip > 1) { frameNum += NV_ALIGN_UP(framesToSkip, frameAlignment); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c index 72c74f8ec..9f2d89da1 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c @@ -70,7 +70,7 @@ void pmaNumaSetReclaimSkipThreshold(PMA *pPma, NvU32 data) } #endif -typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU32, NvU64, NvU64*, NvBool); +typedef NV_STATUS (*scanFunc)(void *, NvU64, NvU64, NvU64, NvU64, NvU64*, NvU32, NvU64, NvU64*, NvBool, NvBool); static void _pmaRollback @@ -547,7 +547,6 @@ pmaRegisterRegion return status; } - NV_STATUS pmaAllocatePages ( @@ -560,7 +559,7 @@ pmaAllocatePages { NvS32 regionList[PMA_REGION_SIZE]; NV_STATUS status, prediction; - NvU32 flags, evictFlag, contigFlag, persistFlag, alignFlag, pinFlag, rangeFlag, blacklistOffFlag, partialFlag, skipScrubFlag; + NvU32 flags, evictFlag, contigFlag, persistFlag, alignFlag, pinFlag, rangeFlag, blacklistOffFlag, partialFlag, skipScrubFlag, reverseFlag; NvU32 regId, regionIdx; NvU64 numPagesAllocatedThisTime, numPagesLeftToAllocate, numPagesAllocatedSoFar; NvU64 addrBase, addrLimit; @@ -612,10 +611,16 @@ pmaAllocatePages blacklistOffFlag = !!(flags & PMA_ALLOCATE_TURN_BLACKLIST_OFF); partialFlag = !!(flags & PMA_ALLOCATE_ALLOW_PARTIAL); skipScrubFlag = !!(flags & PMA_ALLOCATE_NO_ZERO); + reverseFlag = !!(flags & PMA_ALLOCATE_REVERSE_ALLOC); // Fork out new code path for NUMA sub-allocation from OS if (pPma->bNuma) { + if (reverseFlag) + { + NV_PRINTF(LEVEL_ERROR, "Reverse allocation not supported on NUMA.\n"); + return NV_ERR_INVALID_ARGUMENT; + } return pmaNumaAllocate(pPma, allocationCount, pageSize, allocationOptions, pPages); } @@ -806,7 +811,7 @@ pmaAllocatePages_retry: numPagesAllocatedThisTime = 0; status = (*useFunc)(pMap, addrBase, rangeStart, rangeEnd, numPagesLeftToAllocate, - curPages, pageSize, alignment, &numPagesAllocatedThisTime, !tryEvict); + curPages, pageSize, alignment, &numPagesAllocatedThisTime, !tryEvict, (NvBool)reverseFlag); NV_ASSERT(numPagesAllocatedThisTime <= numPagesLeftToAllocate); diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c index c7f4fe7f6..27ff0e76f 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c @@ -675,11 +675,21 @@ pmaSelector } } - if (regionCount > 1) + if (regionCount > 0) { NvU32 j = regionCount; - if (flags & PMA_ALLOCATE_PREFER_SLOWEST) + if (flags & PMA_ALLOCATE_REVERSE_ALLOC) + { + // Find insertion point (highest memory address to lowest) + while ((j > 0) && + (pPma->pRegDescriptors[i]->limit > pPma->pRegDescriptors[regionList[j-1]]->limit)) + { + regionList[j] = regionList[j-1]; + j--; + } + } + else if (flags & PMA_ALLOCATE_PREFER_SLOWEST) { // Find insertion point (slowest to fastest) while ((j > 0) && @@ -1106,6 +1116,32 @@ pmaBuildList bBlockValid = NV_FALSE; } } + + // No point checking further if we are already out of memory + if (status == NV_ERR_NO_MEMORY) + break; + + // Check if last frame was part of a block. + if (bBlockValid) + { + // Block found having required PMA page state. Store it in the list + pRangeCurr = (PRANGELISTTYPE) portMemAllocNonPaged(sizeof(RANGELISTTYPE)); + if (pRangeCurr) + { + pRangeCurr->base = addrBase + blockStart * PMA_GRANULARITY; + pRangeCurr->limit = addrBase + blockEnd * PMA_GRANULARITY + PMA_GRANULARITY - 1; + pRangeCurr->pNext = pRangeList; + pRangeList = pRangeCurr; + } + else + { + // Allocation failed + pmaFreeList(pPma, &pRangeList); + pRangeList = NULL; + status = NV_ERR_NO_MEMORY; + break; + } + } } *ppList = pRangeList; diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c index d3807a32a..d5bf38bf2 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/regmap.c @@ -760,84 +760,51 @@ pmaRegmapRead(void *pMap, NvU64 frameNum, NvBool readAttrib) return (PMA_PAGESTATUS)val; } - -// -// Note that these functions only return the free regions but doesn't reserve them -// therefore locks should not be released after they return until you mark them allocated -// -NV_STATUS -pmaRegmapScanContiguous +static NvS64 _scanContiguousSearchLoop ( - void *pMap, - NvU64 addrBase, - NvU64 rangeStart, - NvU64 rangeEnd, - NvU64 numPages, - NvU64 *freeList, - NvU32 pageSize, - NvU64 alignment, - NvU64 *numPagesAlloc, - NvBool bSkipEvict + PMA_REGMAP *pRegmap, + NvU64 numFrames, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvBool bSearchEvictable ) { - NvU64 freeStart, numFrames, localStart, localEnd, framesPerPage; - NvU64 frameAlignment, alignedAddrBase, frameAlignmentPadding; - NvBool found; - PMA_PAGESTATUS startStatus, endStatus; - PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + NvU64 freeStart; + PMA_PAGESTATUS startStatus, endStatus, state; + NvS64 checkDiff; + NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); - framesPerPage = pageSize >> PMA_PAGE_SHIFT; - numFrames = framesPerPage * numPages; - frameAlignment = alignment >> PMA_PAGE_SHIFT; - - // - // Find how much is the base address short of the alignment requirements - // and adjust that value in the scanning range before starting the scan. - // - alignedAddrBase = NV_ALIGN_UP(addrBase, alignment); - frameAlignmentPadding = (alignedAddrBase - addrBase) >> PMA_PAGE_SHIFT; - - // Handle restricted allocations - if (rangeStart != 0 || rangeEnd != 0) + if (!bSearchEvictable) { - localStart = rangeStart >> PMA_PAGE_SHIFT; - localEnd = NV_MIN(rangeEnd >> PMA_PAGE_SHIFT, pRegmap->totalFrames - 1); + // Look for available frames + state = STATE_FREE; + checkDiff = ALL_FREE; + useFunc = _pmaRegmapAvailable; } else { - localStart = 0; - localEnd = pRegmap->totalFrames - 1; + // Look for evictable frames + state = STATE_UNPIN; + checkDiff = EVICTABLE; + useFunc = _pmaRegmapEvictable; } - localStart = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); freeStart = localStart; - found = 0; - - NV_PRINTF(LEVEL_INFO, - "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", - addrBase, localStart, localEnd, numPages); - - while (!found) + while ((freeStart + numFrames - 1) <= localEnd) { - if ((freeStart + numFrames - 1) > localEnd) - { - // freeStart + numFrames too close to local search end. Re-starting search - break; - } - startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); - if (endStatus == STATE_FREE) + if (endStatus == STATE_FREE || endStatus == state) { - if (startStatus == STATE_FREE) + if (startStatus == STATE_FREE || startStatus == state) { - NvS64 diff = _pmaRegmapAvailable(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == ALL_FREE) + NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); + if (diff == checkDiff) { - found = NV_TRUE; - *freeList = addrBase + (freeStart << PMA_PAGE_SHIFT); - *numPagesAlloc = numPages; + return (NvS64)freeStart; } else { @@ -868,57 +835,71 @@ pmaRegmapScanContiguous } } - if (found) return NV_OK; + return -1; +} - *numPagesAlloc = 0; +static NvS64 _scanContiguousSearchLoopReverse +( + PMA_REGMAP *pRegmap, + NvU64 numFrames, + NvU64 localStart, + NvU64 localEnd, + NvU64 frameAlignment, + NvU64 frameAlignmentPadding, + NvBool bSearchEvictable +) +{ + NvU64 freeStart; + PMA_PAGESTATUS startStatus, endStatus, state; + NvS64 checkDiff; + NvS64 (*useFunc)(PMA_REGMAP *, NvU64, NvU64); - if (bSkipEvict) return NV_ERR_NO_MEMORY; - - // Loop back to the beginning and continue searching - - freeStart = localStart; - while (!found) + if (!bSearchEvictable) { - if ((freeStart + numFrames - 1) > localEnd) - { - // Failed searching for STATE_FREE or STATE_UNPIN - return NV_ERR_NO_MEMORY; - } + // Look for available frames + state = STATE_FREE; + checkDiff = ALL_FREE; + useFunc = _pmaRegmapAvailable; + } + else + { + // Look for evictable frames + state = STATE_UNPIN; + checkDiff = EVICTABLE; + useFunc = _pmaRegmapEvictable; + } + // First frame from end able to accommodate num_frames allocation. + freeStart = localEnd + 1 - numFrames; + freeStart -= (freeStart - localStart) % frameAlignment; + + while (freeStart >= localStart && (NvS64)freeStart >= 0) + { startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); endStatus = pmaRegmapRead(pRegmap, (freeStart + numFrames - 1), NV_TRUE); - if (endStatus == STATE_FREE || endStatus == STATE_UNPIN) + if (startStatus == STATE_FREE || startStatus == state) { - if (startStatus == STATE_FREE || startStatus == STATE_UNPIN) + if (endStatus == STATE_FREE || endStatus == state) { - NvS64 diff = _pmaRegmapEvictable(pRegmap, freeStart, (freeStart + numFrames - 1)); - if (diff == EVICTABLE) + NvS64 diff = (*useFunc)(pRegmap, freeStart, (freeStart + numFrames - 1)); + if (diff == checkDiff) { - found = NV_TRUE; - *freeList = addrBase + (freeStart << PMA_PAGE_SHIFT); + return (NvS64)freeStart; } else { - // - // The previous search should have found an all free region - // and we wouldn't be looking for an evictable one. - // - NV_ASSERT(diff != ALL_FREE); NV_ASSERT(diff >= 0); - // - // Find the next aligned free frame and set it as the start - // frame for next iteration's scan. - // - freeStart = alignUpToMod(diff + 1, frameAlignment, frameAlignmentPadding); - NV_ASSERT(freeStart != 0); + // Set end point to one frame before the first unavailable frame found + freeStart = diff - numFrames; + freeStart -= (freeStart - localStart) % frameAlignment; } } else { - // Start point isn't usable, so bump to the next aligned frame to check again - freeStart += frameAlignment; + // Start point isn't free, so bump to check the next aligned frame + freeStart -= frameAlignment; } } else @@ -927,11 +908,109 @@ pmaRegmapScanContiguous // End point isn't usable, so jump to after the end to check again // However, align the new start point properly before next iteration. // - freeStart += NV_ALIGN_UP(numFrames, frameAlignment); + freeStart -= NV_ALIGN_UP(numFrames, frameAlignment); } } - return NV_ERR_IN_USE; + return -1; +} + +// +// Note that these functions only return the free regions but doesn't reserve them +// therefore locks should not be released after they return until you mark them allocated +// +NV_STATUS +pmaRegmapScanContiguous +( + void *pMap, + NvU64 addrBase, + NvU64 rangeStart, + NvU64 rangeEnd, + NvU64 numPages, + NvU64 *freeList, + NvU32 pageSize, + NvU64 alignment, + NvU64 *numPagesAlloc, + NvBool bSkipEvict, + NvBool bReverseAlloc +) +{ + NvU64 numFrames, localStart, localEnd, framesPerPage; + NvU64 frameAlignment, alignedAddrBase, frameAlignmentPadding; + NvS64 frameFound; + PMA_REGMAP *pRegmap = (PMA_REGMAP *)pMap; + + framesPerPage = pageSize >> PMA_PAGE_SHIFT; + numFrames = framesPerPage * numPages; + frameAlignment = alignment >> PMA_PAGE_SHIFT; + + // + // Find how much is the base address short of the alignment requirements + // and adjust that value in the scanning range before starting the scan. + // + alignedAddrBase = NV_ALIGN_UP(addrBase, alignment); + frameAlignmentPadding = (alignedAddrBase - addrBase) >> PMA_PAGE_SHIFT; + + // Handle restricted allocations + if (rangeStart != 0 || rangeEnd != 0) + { + localStart = rangeStart >> PMA_PAGE_SHIFT; + localEnd = NV_MIN(rangeEnd >> PMA_PAGE_SHIFT, pRegmap->totalFrames - 1); + } + else + { + localStart = 0; + localEnd = pRegmap->totalFrames - 1; + } + localStart = alignUpToMod(localStart, frameAlignment, frameAlignmentPadding); + + NV_PRINTF(LEVEL_INFO, + "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", + addrBase, localStart, localEnd, numPages); + + if (!bReverseAlloc) + { + frameFound = _scanContiguousSearchLoop(pRegmap, numFrames, localStart, localEnd, + frameAlignment, frameAlignmentPadding, NV_FALSE); + } + else + { + frameFound = _scanContiguousSearchLoopReverse(pRegmap, numFrames, localStart, localEnd, + frameAlignment, frameAlignmentPadding, NV_FALSE); + } + + if (frameFound >= 0) + { + *freeList = addrBase + ((NvU64)frameFound << PMA_PAGE_SHIFT); + *numPagesAlloc = numPages; + return NV_OK; + } + + *numPagesAlloc = 0; + + if (bSkipEvict) return NV_ERR_NO_MEMORY; + + // Loop back to the beginning and continue searching + if (!bReverseAlloc) + { + frameFound = _scanContiguousSearchLoop(pRegmap, numFrames, localStart, localEnd, + frameAlignment, frameAlignmentPadding, NV_TRUE); + } + else + { + frameFound = _scanContiguousSearchLoopReverse(pRegmap, numFrames, localStart, localEnd, + frameAlignment, frameAlignmentPadding, NV_TRUE); + } + + if (frameFound >= 0) + { + *freeList = addrBase + ((NvU64)frameFound << PMA_PAGE_SHIFT); + return NV_ERR_IN_USE; + } + else + { + return NV_ERR_NO_MEMORY; + } } NV_STATUS @@ -946,7 +1025,8 @@ pmaRegmapScanDiscontiguous NvU32 pageSize, NvU64 alignment, NvU64 *numPagesAlloc, - NvBool bSkipEvict + NvBool bSkipEvict, + NvBool bReverseAlloc ) { NvU64 freeStart, found, framesPerPage, localStart, localEnd; @@ -984,8 +1064,17 @@ pmaRegmapScanDiscontiguous } localStart = alignUpToMod(localStart, framesPerPage, frameAlignmentPadding); - freeStart = localStart; found = 0; + if (!bReverseAlloc) + { + freeStart = localStart; + } + else + { + // First frame from end able to accommodate page allocation. + freeStart = localEnd + 1 - framesPerPage; + freeStart -= (freeStart - localStart) % framesPerPage; + } NV_PRINTF(LEVEL_INFO, "Scanning with addrBase 0x%llx in frame range 0x%llx..0x%llx, pages to allocate 0x%llx\n", @@ -995,7 +1084,14 @@ pmaRegmapScanDiscontiguous // two-pass algorithm while (found != numPages) { - if ((freeStart + framesPerPage - 1) > localEnd) break; + if (!bReverseAlloc) + { + if ((freeStart + framesPerPage - 1) > localEnd) break; + } + else + { + if (freeStart < localStart || (NvS64)freeStart < 0) break; + } startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); @@ -1011,17 +1107,33 @@ pmaRegmapScanDiscontiguous } } } - freeStart += framesPerPage; + freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); } *numPagesAlloc = found; if(found == numPages) return NV_OK; if(bSkipEvict) return NV_ERR_NO_MEMORY; - freeStart = localStart; + if (!bReverseAlloc) + { + freeStart = localStart; + } + else + { + // First frame from end able to accommodate page allocation. + freeStart = localEnd + 1 - framesPerPage; + freeStart -= (freeStart - localStart) % framesPerPage; + } while (found != numPages) { - if ((freeStart + framesPerPage - 1) > localEnd) return NV_ERR_NO_MEMORY; + if (!bReverseAlloc) + { + if ((freeStart + framesPerPage - 1) > localEnd) return NV_ERR_NO_MEMORY; + } + else + { + if (freeStart < localStart || (NvS64)freeStart < 0) return NV_ERR_NO_MEMORY; + } startStatus = pmaRegmapRead(pRegmap, freeStart, NV_TRUE); endStatus = pmaRegmapRead(pRegmap, (freeStart + framesPerPage - 1), NV_TRUE); @@ -1037,7 +1149,7 @@ pmaRegmapScanDiscontiguous } } } - freeStart += framesPerPage; + freeStart = !bReverseAlloc ? (freeStart + framesPerPage) : (freeStart - framesPerPage); } return NV_ERR_IN_USE; diff --git a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c index b33971318..305b42331 100644 --- a/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c +++ b/src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c @@ -6717,9 +6717,10 @@ kmigmgrGetNextComputeSize_IMPL for (i = 1; i < NV_ARRAY_ELEMENTS(computeSizeFlags) - 1; i++) if (computeSizeFlags[i] == computeSize) - break; + return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; - return (bGetNextSmallest) ? computeSizeFlags[i + 1] : computeSizeFlags[i - 1]; + // Requested input flag was not found + return KMIGMGR_COMPUTE_SIZE_INVALID; } } diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c index 045c5ce0e..df95330a7 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/turing/kern_gmmu_tu102.c @@ -400,12 +400,13 @@ NvBool kgmmuIsNonReplayableFaultPending_TU102 ( OBJGPU *pGpu, - KernelGmmu *pKernelGmmu + KernelGmmu *pKernelGmmu, + THREAD_STATE_NODE *pThreadState ) { NvU32 reg = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_REG(NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE); NvU32 bit = NV_CTRL_INTR_GPU_VECTOR_TO_LEAF_BIT(NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE); - NvU32 pending = GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(reg), NULL /* threadstate */); + NvU32 pending = GPU_VREG_RD32_EX(pGpu, NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(reg), pThreadState); return pending & NVBIT(bit); } diff --git a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c index c55e75202..c0fcb170c 100644 --- a/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c +++ b/src/nvidia/src/kernel/gpu/mmu/arch/volta/kern_gmmu_gv100.c @@ -406,7 +406,7 @@ kgmmuReportFaultBufferOverflow_GV100 faultBufferSize = kgmmuReadMmuFaultBufferSize_HAL(pGpu, pKernelGmmu, NON_REPLAYABLE_FAULT_BUFFER, GPU_GFID_PF); - if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu)) + if (kgmmuIsNonReplayableFaultPending_HAL(pGpu, pKernelGmmu, NULL)) { if (IsVOLTA(pGpu)) { diff --git a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c index bc799f735..dee4d997b 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c +++ b/src/nvidia/src/kernel/gpu/nvlink/arch/hopper/kernel_nvlink_gh100.c @@ -27,6 +27,7 @@ #include "gpu/gpu.h" #include "gpu/mem_mgr/mem_mgr.h" #include "nverror.h" +#include "objtmr.h" /*! * @brief Check if ALI is supported for the given device @@ -250,6 +251,66 @@ knvlinkDiscoverPostRxDetLinks_GH100 return status; } +NV_STATUS +ioctrlFaultUpTmrHandler +( + OBJGPU *pGpu, + OBJTMR *pTmr, + TMR_EVENT *pEvent +) +{ + //NvU32 linkId = *(NvU32*)pData; + NV_STATUS status = NV_OK; + KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu); + NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS *nvlinkPostFaultUpParams + = portMemAllocNonPaged(sizeof(NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS)); + PNVLINK_ID pFaultLink; + pFaultLink = listHead(&pKernelNvlink->faultUpLinks); + + nvlinkPostFaultUpParams->linkId = pFaultLink->linkId; + status = knvlinkExecGspRmRpc(pGpu, pKernelNvlink, + NV2080_CTRL_CMD_NVLINK_POST_FAULT_UP, + (void *)nvlinkPostFaultUpParams, + sizeof(NV2080_CTRL_NVLINK_POST_FAULT_UP_PARAMS)); + + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "Failed to send Faultup RPC\n"); + } + + listRemove(&pKernelNvlink->faultUpLinks, pFaultLink); + portMemFree(nvlinkPostFaultUpParams); + + return status; +} + +NV_STATUS +knvlinkHandleFaultUpInterrupt_GH100 +( + OBJGPU *pGpu, + KernelNvlink *pKernelNvlink, + NvU32 linkId +) +{ + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); + PNVLINK_ID pFaultLink; + NV_STATUS status = NV_OK; + + pFaultLink = listAppendNew(&pKernelNvlink->faultUpLinks); + NV_ASSERT_OR_RETURN(pFaultLink != NULL, NV_ERR_GENERIC); + pFaultLink->linkId = linkId; + + status = tmrEventScheduleRel(pTmr, pKernelNvlink->nvlinkLinks[linkId].pTmrEvent, NVLINK_RETRAIN_TIME); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "GPU (ID: %d) tmrEventScheduleRel failed for linkid %d\n", + gpuGetInstance(pGpu), linkId); + return NV_ERR_GENERIC; + } + + return status; +} + NV_STATUS knvlinkLogAliDebugMessages_GH100 ( diff --git a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c index 6c8fe73d9..5b92cd2cb 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c +++ b/src/nvidia/src/kernel/gpu/nvlink/common_nvlinkapi.c @@ -304,7 +304,7 @@ static _getNvlinkStatus } } - if (pLinkAndClockValues->bLinkConnectedToPeer) + if (nvlinkLinks[i].bConnected) { // Tag as Peer link bPeerLink = NV_TRUE; @@ -699,7 +699,8 @@ subdeviceCtrlCmdBusGetNvlinkStatus_IMPL if (status != NV_OK) { NV_PRINTF(LEVEL_INFO, "Nvlink is not ready yet!\n"); - return NV_ERR_NOT_READY; + status = NV_ERR_NOT_READY; + goto done; } } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c index 133846c33..5d35cb3a8 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlink.c @@ -1076,6 +1076,43 @@ knvlinkPrepareForXVEReset_IMPL retStatus = (retStatus == NV_OK) ? status : retStatus; } +#if defined(INCLUDE_NVLINK_LIB) + else + { + NvU32 linkId; + + // + // The connections have been successfully reset, update connected and disconnected + // links masks on both the devices + // + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + pKernelNvlink->disconnectedLinkMask |= NVBIT(linkId); + pKernelNvlink->connectedLinksMask &= ~NVBIT(linkId); + + if (pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.deviceType != + NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU) + { + continue; + } + + OBJGPU *pRemoteGpu = gpumgrGetGpuFromBusInfo( + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.domain, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bus, + pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.device); + + if (!API_GPU_IN_RESET_SANITY_CHECK(pRemoteGpu)) + { + KernelNvlink *pRemoteKernelNvlink = GPU_GET_KERNEL_NVLINK(pRemoteGpu); + NvU32 remoteLinkId = pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.linkNumber; + + pRemoteKernelNvlink->disconnectedLinkMask |= NVBIT(remoteLinkId); + pRemoteKernelNvlink->connectedLinksMask &= ~NVBIT(remoteLinkId); + } + } + FOR_EACH_INDEX_IN_MASK_END; + } +#endif // // knvlinkCoreResetDeviceLinks() only resets the links which have diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index c1d4a9fbd..ebb7186e4 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -91,7 +91,6 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL // if (!knvlinkPoweredUpForD3_HAL(pGpu, pKernelNvlink)) { - // // Optimization: Check for nvlink proxy only when system fabric is externally // managed. This would avoid RPCs in non-nvswitch cases. @@ -128,8 +127,8 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL { NV_PRINTF(LEVEL_ERROR, "Failed to floorsweep valid nvlink config!\n"); return NV_ERR_NOT_READY; - } - } + } + } // We only need to look at links that are still considered disconnected FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->disconnectedLinkMask) @@ -145,7 +144,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL continue; } - bUpdateConnStatus = NV_FALSE; + bUpdateConnStatus = NV_FALSE; if (pKernelNvlink->nvlinkLinks[linkId].core_link) { @@ -210,7 +209,7 @@ knvlinkCoreGetRemoteDeviceInfo_IMPL pKernelNvlink->nvlinkLinks[linkId].core_link, &conn_info, flags); } - // RPC into GSP-RM to update the link connected status only if its required + // RPC into GSP-RM to update the link connected status only if its required if (pKernelNvlink->nvlinkLinks[linkId].remoteEndInfo.bConnected != conn_info.bConnected) bUpdateConnStatus = NV_TRUE; @@ -581,11 +580,13 @@ knvlinkTrainP2pLinksToActive_IMPL #if defined(INCLUDE_NVLINK_LIB) - OBJSYS *pSys = SYS_GET_INSTANCE(); - NvU32 version = pKernelNvlink0->ipVerNvlink; - NvBool bTrainLinks = NV_FALSE; - NvU32 count = 0; - NvU32 i; + OBJSYS *pSys = SYS_GET_INSTANCE(); + KernelNvlink *pKernelNvlink1 = GPU_GET_KERNEL_NVLINK(pGpu1); + NvU32 version = pKernelNvlink0->ipVerNvlink; + NvBool bTrainLinks = NV_FALSE; + NvU32 count = 0; + NvU32 remoteLink; + NvU32 i; nvlink_link *pLinks[NVLINK_MAX_LINKS_SW] = { 0 }; @@ -638,18 +639,23 @@ knvlinkTrainP2pLinksToActive_IMPL // if (IsAMPEREorBetter(pGpu0)) { - NvU32 linkMask = 0; + NvU32 localMask = 0; + NvU32 remoteMask = 0; FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink0->enabledLinks) { if (KNVLINK_IS_LINK_CONNECTED_TO_GPU(pKernelNvlink0, i, pGpu1)) { - linkMask |= BIT(i); + remoteLink = pKernelNvlink0->nvlinkLinks[i].remoteEndInfo.linkNumber; + + localMask |= BIT(i); + remoteMask |= BIT(remoteLink); } } FOR_EACH_INDEX_IN_MASK_END; - if ((linkMask & pKernelNvlink0->initializedLinks) == linkMask) + if (((pKernelNvlink0->initializedLinks & localMask) == localMask) && + ((pKernelNvlink1->initializedLinks & remoteMask) == remoteMask)) { NV_PRINTF(LEVEL_INFO, "P2P links are all trained already, return\n"); return NV_OK; diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c index e43ed049e..30248304c 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkstate.c @@ -340,6 +340,7 @@ knvlinkStateLoad_IMPL !kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); NvU32 preInitializedLinks; NvU32 i; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); // // If we are on the resume path, nvlinkIsPresent will not be called, @@ -652,6 +653,21 @@ knvlinkStateLoad_IMPL FOR_EACH_INDEX_IN_MASK_END; } + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink->enabledLinks) + { + status = tmrEventCreate(pTmr, &pKernelNvlink->nvlinkLinks[i].pTmrEvent, + ioctrlFaultUpTmrHandler, NULL, + TMR_FLAGS_NONE); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, + "Failed to create TmrEvent for Link %d\n", i); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + listInit(&pKernelNvlink->faultUpLinks, portMemAllocatorGetGlobalNonPaged()); + knvlinkStateLoad_end: if (status != NV_OK) @@ -922,6 +938,8 @@ knvlinkStatePostUnload_IMPL FOR_EACH_INDEX_IN_MASK_END; #endif + listDestroy(&pKernelNvlink->faultUpLinks); + knvlinkStatePostUnload_end: _knvlinkPurgeState(pGpu, pKernelNvlink); @@ -946,13 +964,28 @@ _knvlinkPurgeState { KernelIoctrl *pKernelIoctrl = NULL; NvU32 ioctrlIdx; - #if defined(INCLUDE_NVLINK_LIB) + NvU32 linkId; + OBJTMR *pTmr = GPU_GET_TIMER(pGpu); KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu); NvBool bMIGNvLinkP2PDisabled = ((pKernelMIGManager != NULL) && !kmigmgrIsMIGNvlinkP2PSupported(pGpu, pKernelMIGManager)); - + + FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) + { + if ((pKernelNvlink->nvlinkLinks[linkId].pTmrEvent != NULL) && (pTmr != NULL)) + { + if (tmrEventOnList(pTmr, pKernelNvlink->nvlinkLinks[linkId].pTmrEvent)) + { + tmrEventCancel(pTmr, pKernelNvlink->nvlinkLinks[linkId].pTmrEvent); + } + tmrEventDestroy(pTmr, pKernelNvlink->nvlinkLinks[linkId].pTmrEvent); + pKernelNvlink->nvlinkLinks[linkId].pTmrEvent = NULL; + } + } + FOR_EACH_INDEX_IN_MASK_END; + // RM disables NVLink at runtime in Hopper so device un-registration can't be skipped if (!IsGH100orBetter(pGpu)) { @@ -976,8 +1009,6 @@ _knvlinkPurgeState { if (pKernelNvlink->pNvlinkDev) { - NvU32 linkId; - // Un-register the links from nvlink core library FOR_EACH_INDEX_IN_MASK(32, linkId, pKernelNvlink->enabledLinks) { @@ -1088,6 +1119,9 @@ knvlinkSetDegradedMode_IMPL if (pRemoteKernelNvlink->bIsGpuDegraded == NV_FALSE) { pKernelNvlink->bIsGpuDegraded = NV_TRUE; + NV_PRINTF(LEVEL_ERROR, + "GPU%d marked Degraded for error on linkId %d \n", + pGpu->gpuInstance, linkId); // shutdown all the links on this GPU status = knvlinkCoreShutdownDeviceLinks(pGpu, pKernelNvlink, NV_TRUE); diff --git a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c index 8f7ee0d03..868d15a56 100644 --- a/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c +++ b/src/nvidia/src/kernel/gpu/pmu/kern_pmu.c @@ -79,7 +79,7 @@ kpmuInitLibosLoggingStructures_IMPL "NVRISCV", NULL); // Finish PMU log init (setting the lossless-print flag and resolve-pointers flag) - libosLogInitEx(&pKernelPmu->logDecode, pKernelPmu->pLogElf, NV_TRUE, NV_TRUE, pKernelPmu->logElfSize); + libosLogInitEx(&pKernelPmu->logDecode, pKernelPmu->pLogElf, NV_TRUE, NV_TRUE, NV_TRUE, pKernelPmu->logElfSize); if (nvStatus != NV_OK) kpmuFreeLibosLoggingStructures(pGpu, pKernelPmu); diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c index 477d137bf..de1f711f9 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c @@ -38,6 +38,7 @@ #include "nvVer.h" #include "gpu/bif/kernel_bif.h" #include "gpu/bus/kern_bus.h" +#include "gpu/disp/kern_disp.h" #include "gpu/mmu/kern_gmmu.h" #include "kernel/gpu/intr/intr.h" #include "kernel/gpu/mc/kernel_mc.h" @@ -278,6 +279,18 @@ getGpuInfos(Subdevice *pSubdevice, NV2080_CTRL_GPU_GET_INFO_V2_PARAMS *pParams, } break; } + case NV2080_CTRL_GPU_INFO_INDEX_DISPLAY_ENABLED: + { + if (GPU_GET_KERNEL_DISPLAY(pGpu) != NULL) + { + data = NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_YES; + } + else + { + data = NV2080_CTRL_GPU_INFO_DISPLAY_ENABLED_NO; + } + break; + } case NV2080_CTRL_GPU_INFO_INDEX_MOBILE_CONFIG_ENABLED: { if (IsMobile(pGpu)) diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 5958e0aff..54e772752 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -726,6 +726,9 @@ static NvBool _gpumgrIsRmFirmwareDefaultChip(NvU32 pmcBoot42) static NvBool _gpumgrIsVgxRmFirmwareDefaultChip(NvU32 pmcBoot42) { + if (DRF_VAL(_PMC, _BOOT_42, _ARCHITECTURE, pmcBoot42) == NV_PMC_BOOT_42_ARCHITECTURE_AD100) + return NV_TRUE; + return NV_FALSE; } @@ -2261,7 +2264,7 @@ gpumgrServiceInterrupts_IMPL(NvU32 gpuMask, MC_ENGINE_BITVECTOR *engineMask, NvB if (gpuIsGpuFullPower(pGpu)) { Intr *pIntr = GPU_GET_INTR(pGpu); - + // // On SLI, one OBJGPU's StateInit functions could attempt to service // interrupts on another OBJGPU which has not yet started StateInit. @@ -3041,7 +3044,7 @@ gpumgrAddSystemMIGInstanceTopo_IMPL { pGpuMgr->MIGTopologyInfo[i].bValid = NV_TRUE; pGpuMgr->MIGTopologyInfo[i].domainBusDevice = domainBusDevice; - + // Set MIG enablement to disabled by default pGpuMgr->MIGTopologyInfo[i].bMIGEnabled = NV_FALSE; break; @@ -3143,9 +3146,9 @@ gpumgrIsSystemMIGEnabled_IMPL * @returns NV_TRUE if entry found * NV_FALSE otherwise */ -void +void gpumgrSetSystemMIGEnabled_IMPL -( +( NvU64 domainBusDevice, NvBool bMIGEnabled ) @@ -3261,7 +3264,7 @@ gpumgrGetGpuBridgeType(void) { OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); - + return pGpuMgr->gpuBridgeType; } @@ -3283,7 +3286,7 @@ gpumgrInitPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) /** * @brief Destroy the PCIE P2P info cache */ -void +void gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) { PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext; @@ -3310,7 +3313,7 @@ gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) * @param[in] gpuMask NvU32 value * @param[in] p2pWriteCapsStatus NvU8 value * @param[in] pP2PReadCapsStatus NvU8 value - * + * * @return NV_OK or NV_ERR_NO_MEMORY */ NV_STATUS @@ -3460,7 +3463,7 @@ gpumgrGetPcieP2PCapsFromCache_IMPL OBJSYS *pSys = SYS_GET_INSTANCE(); OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); NvBool bFound; - + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); bFound = _gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapsStatus, pP2PReadCapsStatus); diff --git a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c index 56d26245a..86d6ce4d1 100644 --- a/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c +++ b/src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c @@ -432,11 +432,19 @@ gvaspaceReserveSplitVaSpace_IMPL if (bServerRm || bClientRm) { + OBJVASPACE *pVAS = staticCast(pGVAS, OBJVASPACE); + pGVAS->vaStartServerRMOwned = NV_MIN(pGVAS->vaLimitInternal - SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE + 1, SPLIT_VAS_SERVER_RM_MANAGED_VA_START); + + if (pVAS->vasStart > pGVAS->vaStartServerRMOwned) + { + pGVAS->vaStartServerRMOwned = pVAS->vasStart + SPLIT_VAS_SERVER_RM_MANAGED_VA_START; + } + pGVAS->vaLimitServerRMOwned = pGVAS->vaStartServerRMOwned + - SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; + SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1; // Base and limit + 1 should be aligned to 512MB. if (!NV_IS_ALIGNED(pGVAS->vaStartServerRMOwned, NVBIT64(GMMU_PD1_VADDR_BIT_LO))) diff --git a/src/nvidia/src/kernel/mem_mgr/video_mem.c b/src/nvidia/src/kernel/mem_mgr/video_mem.c index 1fd1c0984..c45b668b1 100644 --- a/src/nvidia/src/kernel/mem_mgr/video_mem.c +++ b/src/nvidia/src/kernel/mem_mgr/video_mem.c @@ -210,6 +210,12 @@ _vidmemPmaAllocate allocOptions.flags |= PMA_ALLOCATE_PROTECTED_REGION; } + // Check memory alloc direction. + if (pAllocData->flags & NVOS32_ALLOC_FLAGS_FORCE_REVERSE_ALLOC) + { + allocOptions.flags |= PMA_ALLOCATE_REVERSE_ALLOC; + } + // Fixed address allocations. if (pAllocData->flags & NVOS32_ALLOC_FLAGS_FIXED_ADDRESS_ALLOCATE) { diff --git a/src/nvidia/src/kernel/os/os_stubs.c b/src/nvidia/src/kernel/os/os_stubs.c index 83d81f7d0..8ea7a0329 100644 --- a/src/nvidia/src/kernel/os/os_stubs.c +++ b/src/nvidia/src/kernel/os/os_stubs.c @@ -314,6 +314,11 @@ void stubOsInternalReserveFreeCallback(NvU64 offset, NvU32 gpuId) return; } +NV_STATUS osGetCurrentProcessGfid(NvU32 *pGfid) +{ + return NV_ERR_NOT_SUPPORTED; +} + #if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \ (RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY) NV_STATUS osTegraSocGpioGetPinState( diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index ce8854d26..7c30a5bd8 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -183,6 +183,9 @@ void RmInitCpuInfo(void) case AARCH64_VENDOR_PART(ARM, CORTEX_A57): pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; break; + case AARCH64_VENDOR_PART(ARM, NEOVERSE_N2): + pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV9A_GENERIC; + break; default: pSys->cpuInfo.type = NV0000_CTRL_SYSTEM_CPU_TYPE_ARMV8A_GENERIC; portDbgPrintf( diff --git a/src/nvidia/src/kernel/platform/cpu_arm_def.h b/src/nvidia/src/kernel/platform/cpu_arm_def.h index dfa8da2a5..9c23b6726 100644 --- a/src/nvidia/src/kernel/platform/cpu_arm_def.h +++ b/src/nvidia/src/kernel/platform/cpu_arm_def.h @@ -88,6 +88,7 @@ extern void CP_WRITE_CSSELR_REGISTER(NvU32 val); #define CP_MIDR_PRIMARY_PART_NUM_ALTRA 0x000 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN96XX 0x0b2 #define CP_MIDR_PRIMARY_PART_NUM_OCTEON_CN98XX 0x0b1 +#define CP_MIDR_PRIMARY_PART_NUM_NEOVERSE_N2 0xd49 // Cache Size Identification Register #define CP_CCSIDR "ccsidr_el1" diff --git a/src/nvidia/src/kernel/rmapi/alloc_free.c b/src/nvidia/src/kernel/rmapi/alloc_free.c index e0fb32169..58c150119 100644 --- a/src/nvidia/src/kernel/rmapi/alloc_free.c +++ b/src/nvidia/src/kernel/rmapi/alloc_free.c @@ -76,6 +76,32 @@ rmapiResourceDescToLegacyFlags } } +NvU32 +serverAllocClientHandleBase +( + RsServer *pServer, + NvBool bInternalHandle, + API_SECURITY_INFO *pSecInfo +) +{ + NvU32 handleBase; + NvU32 gfid = (NvU32)((NvU64)pSecInfo->pProcessToken); + + if (bInternalHandle) + { + handleBase = pServer->internalHandleBase; + } + else + { + handleBase = pServer->clientHandleBase; + + if (RMCFG_FEATURE_PLATFORM_GSP && IS_GFID_VF(gfid)) + handleBase = RS_CLIENT_GET_VF_HANDLE_BASE(gfid); + } + + return handleBase; +} + NV_STATUS serverAllocApiCopyIn ( diff --git a/src/nvidia/src/kernel/rmapi/event_notification.c b/src/nvidia/src/kernel/rmapi/event_notification.c index a5f3c726a..bb7c18dca 100644 --- a/src/nvidia/src/kernel/rmapi/event_notification.c +++ b/src/nvidia/src/kernel/rmapi/event_notification.c @@ -43,6 +43,41 @@ #include "virtualization/hypervisor/hypervisor.h" +typedef struct +{ + EVENTNOTIFICATION *pEventNotify; + Memory *pMemory; + ListNode eventNotificationListNode; + ListNode pendingEventNotifyListNode; +} ENGINE_EVENT_NOTIFICATION; + +// +// These lists are intrusive to avoid memory allocation during insertion while +// in a non-preemptible context (holding a spinlock/in an ISR). +// +MAKE_INTRUSIVE_LIST(EngineEventNotificationList, ENGINE_EVENT_NOTIFICATION, + eventNotificationListNode); +MAKE_INTRUSIVE_LIST(PendingEventNotifyList, ENGINE_EVENT_NOTIFICATION, + pendingEventNotifyListNode); + +// Linked list of per engine non-stall event notifications +struct GpuEngineEventNotificationList +{ + PORT_SPINLOCK *pSpinlock; + + // List insertion and removal happens under pSpinlock + EngineEventNotificationList eventNotificationList; + + // Filled while pSpinlock is held, drained outside of the lock in ISR + PendingEventNotifyList pendingEventNotifyList; + + // + // Set to non-zero under pSpinlock, set to zero outside of the lock in ISR + // Insertions/removals on eventNotificationList are blocked while non-zero + // + volatile NvU32 pendingEventNotifyCount; +}; + static NV_STATUS _insertEventNotification ( PEVENTNOTIFICATION *ppEventNotification, @@ -70,180 +105,303 @@ static NV_STATUS _removeEventNotification // //--------------------------------------------------------------------------- -static NV_STATUS engineNonStallEventOp +NV_STATUS gpuEngineEventNotificationListCreate ( OBJGPU *pGpu, - RM_ENGINE_TYPE rmEngineId, - PEVENTNOTIFICATION pEventNotify, - Memory *pMemory, - NvBool bInsert + GpuEngineEventNotificationList **ppEventNotificationList ) { - ENGINE_EVENT_NODE *pTempNode; - NvBool bFound = NV_FALSE; + NV_STATUS status = NV_OK; - if (bInsert) + PORT_MEM_ALLOCATOR *pAllocator = portMemAllocatorGetGlobalNonPaged(); + GpuEngineEventNotificationList *pEventNotificationList = + portMemAllocNonPaged(sizeof(*pEventNotificationList)); + NV_ASSERT_OR_RETURN(pEventNotificationList != NULL, NV_ERR_NO_MEMORY); + + portMemSet(pEventNotificationList, 0, sizeof(*pEventNotificationList)); + + pEventNotificationList->pSpinlock = portSyncSpinlockCreate(pAllocator); + NV_ASSERT_OR_ELSE(pEventNotificationList->pSpinlock != NULL, { - pTempNode = portMemAllocNonPaged(sizeof(ENGINE_EVENT_NODE)); + status = NV_ERR_INSUFFICIENT_RESOURCES; + goto exit; + }); - if (pTempNode == NULL) - return NV_ERR_NO_MEMORY; + listInitIntrusive(&pEventNotificationList->eventNotificationList); + listInitIntrusive(&pEventNotificationList->pendingEventNotifyList); - // Acquire engine list spinlock before adding to engine event list - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - pTempNode->pNext = pGpu->engineNonstallIntr[rmEngineId].pEventNode; - pTempNode->pEventNotify = pEventNotify; - pTempNode->pMemory = pMemory; + portAtomicSetU32(&pEventNotificationList->pendingEventNotifyCount, 0); - pGpu->engineNonstallIntr[rmEngineId].pEventNode = pTempNode; + *ppEventNotificationList = pEventNotificationList; - // Release engine list spinlock - portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - } - else +exit: + if (status != NV_OK) + gpuEngineEventNotificationListDestroy(pGpu, pEventNotificationList); + return status; +} + +void gpuEngineEventNotificationListDestroy +( + OBJGPU *pGpu, + GpuEngineEventNotificationList *pEventNotificationList +) +{ + if (pEventNotificationList == NULL) + return; + + NV_ASSERT(pEventNotificationList->pendingEventNotifyCount == 0); + + NV_ASSERT(listCount(&pEventNotificationList->pendingEventNotifyList) == 0); + listDestroy(&pEventNotificationList->pendingEventNotifyList); + + NV_ASSERT(listCount(&pEventNotificationList->eventNotificationList) == 0); + listDestroy(&pEventNotificationList->eventNotificationList); + + if (pEventNotificationList->pSpinlock != NULL) + portSyncSpinlockDestroy(pEventNotificationList->pSpinlock); + + portMemFree(pEventNotificationList); +} + +static void _gpuEngineEventNotificationListLockPreemptible +( + GpuEngineEventNotificationList *pEventNotificationList +) +{ + do { - ENGINE_EVENT_NODE *pEngNode, *pPrevNode = NULL; + portSyncSpinlockAcquire(pEventNotificationList->pSpinlock); - // Acquire engine list spinlock before traversing engine event list - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); + // + // Only return with the lock held once there are no pending + // notifications to process. No more pending notifications can be queued + // while the spinlock is held, and we drop the lock to re-enable + // preemption, to guarantee that _gpuEngineEventNotificationListNotify() + // can make forward progress to drain the pending notifications list. + // + if (pEventNotificationList->pendingEventNotifyCount == 0) + return; - pEngNode = pGpu->engineNonstallIntr[rmEngineId].pEventNode; - while (pEngNode) - { - if (pEngNode->pEventNotify == pEventNotify) - { - if (pPrevNode == NULL) - pGpu->engineNonstallIntr[rmEngineId].pEventNode = pEngNode->pNext; - else - pPrevNode->pNext = pEngNode->pNext; + portSyncSpinlockRelease(pEventNotificationList->pSpinlock); - pTempNode = pEngNode; - bFound = NV_TRUE; - break; - } - else - { - pPrevNode = pEngNode; - } - pEngNode = pEngNode->pNext; - } + // + // Spin waiting for the pending notifications to drain. + // This can only be done in a preemptible context (i.e., add + // or remove notification in a thread context). + // + while (pEventNotificationList->pendingEventNotifyCount > 0) + osSpinLoop(); + } while (NV_TRUE); +} - // Release engine list spinlock - portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); +static inline void _gpuEngineEventNotificationListUnlockPreemptible +( + GpuEngineEventNotificationList *pEventNotificationList +) +{ + portSyncSpinlockRelease(pEventNotificationList->pSpinlock); +} - if (bFound) - { - portMemFree(pTempNode); - } - else - { - NV_ASSERT_FAILED("failed to find non-stall event!"); - return NV_ERR_INVALID_STATE; - } +static NV_STATUS _gpuEngineEventNotificationInsert +( + GpuEngineEventNotificationList *pEventNotificationList, + EVENTNOTIFICATION *pEventNotify, + Memory *pMemory +) +{ + NV_CHECK_OR_RETURN(LEVEL_ERROR, pEventNotify != NULL, + NV_ERR_INVALID_ARGUMENT); + + // Allocate the new node outside of the spinlock + ENGINE_EVENT_NOTIFICATION *pEngineEventNotification = + portMemAllocNonPaged(sizeof(*pEngineEventNotification)); + + NV_CHECK_OR_RETURN(LEVEL_ERROR, pEngineEventNotification != NULL, + NV_ERR_NO_MEMORY); + + portMemSet(pEngineEventNotification, 0, sizeof(*pEngineEventNotification)); + + pEngineEventNotification->pEventNotify = pEventNotify; + pEngineEventNotification->pMemory = pMemory; + + // Take the lock to add the node to the list + _gpuEngineEventNotificationListLockPreemptible(pEventNotificationList); + { + listPrependExisting(&pEventNotificationList->eventNotificationList, + pEngineEventNotification); } + _gpuEngineEventNotificationListUnlockPreemptible(pEventNotificationList); return NV_OK; } -static NV_STATUS _engineNonStallIntrNotifyImpl(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId, NvHandle hEvent) +static void _gpuEngineEventNotificationRemove +( + GpuEngineEventNotificationList *pEventNotificationList, + EVENTNOTIFICATION *pEventNotify +) { - ENGINE_EVENT_NODE *pTempHead; - Memory *pSemMemory; - NvU32 semValue; - NvU32 *pTempKernelMapping = NULL; - NV_STATUS rmStatus = NV_OK; + ENGINE_EVENT_NOTIFICATION *pEngineEventNotification = NULL; + + _gpuEngineEventNotificationListLockPreemptible(pEventNotificationList); + { + EngineEventNotificationListIter it = + listIterAll(&pEventNotificationList->eventNotificationList); + while (listIterNext(&it)) + { + if (it.pValue->pEventNotify == pEventNotify) + { + pEngineEventNotification = it.pValue; + listRemove(&pEventNotificationList->eventNotificationList, + pEngineEventNotification); + break; + } + } + } + _gpuEngineEventNotificationListUnlockPreemptible(pEventNotificationList); + + NV_ASSERT(pEngineEventNotification != NULL); + portMemFree(pEngineEventNotification); +} + +static NV_STATUS _gpuEngineEventNotificationListNotify +( + OBJGPU *pGpu, + GpuEngineEventNotificationList *pEventNotificationList, + NvHandle hEvent +) +{ + NV_STATUS status = NV_OK; + PendingEventNotifyList *pPending = + &pEventNotificationList->pendingEventNotifyList; // // Acquire engine list spinlock before traversing the list. Note that this // is called without holding locks from ISR for Linux. This spinlock is used - // to protect per GPU per engine event node list. + // to protect the per GPU per engine event node list. // - portSyncSpinlockAcquire(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - - pTempHead = pGpu->engineNonstallIntr[rmEngineId].pEventNode; - while (pTempHead) + portSyncSpinlockAcquire(pEventNotificationList->pSpinlock); { - if (!pTempHead->pEventNotify) + // We don't expect this to be called multiple times in parallel + NV_ASSERT_OR_ELSE(pEventNotificationList->pendingEventNotifyCount == 0, { - rmStatus = NV_ERR_INVALID_STATE; - break; - } + portSyncSpinlockRelease(pEventNotificationList->pSpinlock); + return NV_ERR_INVALID_STATE; + }); - if (hEvent && pTempHead->pEventNotify->hEvent != hEvent) - goto nextEvent; - - pSemMemory = pTempHead->pMemory; - - if (pSemMemory && pSemMemory->vgpuNsIntr.isSemaMemValidationEnabled && - pSemMemory->pMemDesc && pSemMemory->pMemDesc->Allocated) + EngineEventNotificationListIter it = + listIterAll(&pEventNotificationList->eventNotificationList); + while (listIterNext(&it)) { - pTempKernelMapping = (NvU32 *)NvP64_VALUE(memdescGetKernelMapping(pSemMemory->pMemDesc)); - if (pTempKernelMapping == NULL) - { - NV_PRINTF(LEVEL_WARNING, "Per-vGPU semaphore location mapping is NULL. Skipping the current node.\n"); - pTempHead = pTempHead->pNext; + ENGINE_EVENT_NOTIFICATION *pEngineEventNotification = it.pValue; + if (hEvent && + pEngineEventNotification->pEventNotify->hEvent != hEvent) continue; - } - semValue = MEM_RD32(pTempKernelMapping + (pSemMemory->vgpuNsIntr.nsSemOffset / sizeof(NvU32))); - if (pSemMemory->vgpuNsIntr.nsSemValue == semValue) + Memory *pSemMemory = pEngineEventNotification->pMemory; + if (pSemMemory && + pSemMemory->vgpuNsIntr.isSemaMemValidationEnabled && + pSemMemory->pMemDesc && pSemMemory->pMemDesc->Allocated) { - pTempHead = pTempHead->pNext; - continue; - } - - pSemMemory->vgpuNsIntr.nsSemValue = semValue; - - { - OBJSYS *pSys = SYS_GET_INSTANCE(); - OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); - - if (pHypervisor != NULL) + NvU32 *pTempKernelMapping = + (NvU32 *)NvP64_VALUE( + memdescGetKernelMapping(pSemMemory->pMemDesc)); + if (pTempKernelMapping == NULL) { - NV_STATUS intrStatus = hypervisorInjectInterrupt(pHypervisor, &pSemMemory->vgpuNsIntr); + NV_PRINTF(LEVEL_WARNING, + "Per-vGPU semaphore location mapping is NULL." + " Skipping the current node.\n"); + continue; + } - // - // If we have successfully inject MSI into guest, - // then we can jump to the next semaphore location, - // otherwise, we need to call osNotifyEvent below to - // wake up plugin - // - if (intrStatus == NV_OK) + NvU32 semValue = MEM_RD32(pTempKernelMapping + + (pSemMemory->vgpuNsIntr.nsSemOffset / + sizeof(NvU32))); + + if (pSemMemory->vgpuNsIntr.nsSemValue == semValue) + continue; + + pSemMemory->vgpuNsIntr.nsSemValue = semValue; + + { + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys); + + if (pHypervisor != NULL) { - pTempHead = pTempHead->pNext; - continue; + NV_STATUS intrStatus = + hypervisorInjectInterrupt(pHypervisor, + &pSemMemory->vgpuNsIntr); + + // + // If we have successfully injected MSI into guest, + // then we can jump to the next semaphore location; + // otherwise, we need to call osNotifyEvent below to + // wake up the plugin. + // + if (intrStatus == NV_OK) + continue; } } } + + // + // Queue up this event notification to be completed outside of the + // critical section, as the osNotifyEvent implementation may need + // to be preemptible. + // + listAppendExisting(pPending, pEngineEventNotification); } - if (osNotifyEvent(pGpu, pTempHead->pEventNotify, 0, 0, NV_OK) != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to notify event for engine 0x%x (0x%x)\n", - gpuGetNv2080EngineType(rmEngineId), rmEngineId); - NV_ASSERT(0); - rmStatus = NV_ERR_INVALID_STATE; - break; - } + portAtomicSetU32(&pEventNotificationList->pendingEventNotifyCount, + listCount(pPending)); + } + portSyncSpinlockRelease(pEventNotificationList->pSpinlock); - nextEvent: - pTempHead = pTempHead->pNext; + // + // Iterate through the pending notifications and call the OS to send them. + // Note that osNotifyEvent may need to be preemptible, so this is done + // outside of the spinlock-protected critical section. + // + PendingEventNotifyListIter it = listIterAll(pPending); + while (listIterNext(&it)) + { + NV_ASSERT_OK_OR_CAPTURE_FIRST_ERROR(status, + osNotifyEvent(pGpu, it.pValue->pEventNotify, 0, 0, NV_OK)); } - portSyncSpinlockRelease(pGpu->engineNonstallIntr[rmEngineId].pSpinlock); - return rmStatus; + // Remove all entries from the pending event notify list + ENGINE_EVENT_NOTIFICATION *pIter, *pNext; + for (pIter = listHead(pPending); pIter != NULL; pIter = pNext) + { + pNext = listNext(pPending, pIter); + listRemove(pPending, pIter); + } + + NV_ASSERT(listCount(pPending) == 0); + + // Mark the event notifications as drained so preemptible code can continue + portAtomicSetU32(&pEventNotificationList->pendingEventNotifyCount, 0); + + return status; } NV_STATUS engineNonStallIntrNotify(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId) { - return _engineNonStallIntrNotifyImpl(pGpu, rmEngineId, 0); + NV_ASSERT_OR_RETURN(rmEngineId < NV_ARRAY_ELEMENTS(pGpu->engineNonstallIntrEventNotifications), + NV_ERR_INVALID_ARGUMENT); + return _gpuEngineEventNotificationListNotify(pGpu, + pGpu->engineNonstallIntrEventNotifications[rmEngineId], 0); } NV_STATUS engineNonStallIntrNotifyEvent(OBJGPU *pGpu, RM_ENGINE_TYPE rmEngineId, NvHandle hEvent) { - return _engineNonStallIntrNotifyImpl(pGpu, rmEngineId, hEvent); + NV_ASSERT_OR_RETURN(rmEngineId < NV_ARRAY_ELEMENTS(pGpu->engineNonstallIntrEventNotifications), + NV_ERR_INVALID_ARGUMENT); + return _gpuEngineEventNotificationListNotify(pGpu, + pGpu->engineNonstallIntrEventNotifications[rmEngineId], hEvent); } static NV_STATUS @@ -482,8 +640,9 @@ NV_STATUS registerEventNotification free_entry); } - rmStatus = engineNonStallEventOp(pGpu, rmEngineId, - *ppEventNotification, pSemMemory, NV_TRUE); + rmStatus = _gpuEngineEventNotificationInsert( + pGpu->engineNonstallIntrEventNotifications[rmEngineId], + *ppEventNotification, pSemMemory); if (rmStatus != NV_OK) goto free_entry; @@ -684,8 +843,9 @@ NV_STATUS unregisterEventNotificationWithData rmEngineId = globalRmEngineId; } - rmStatus = engineNonStallEventOp(pGpu, rmEngineId, - pTargetEvent, NULL, NV_FALSE); + _gpuEngineEventNotificationRemove( + pGpu->engineNonstallIntrEventNotifications[rmEngineId], + pTargetEvent); } free_entry: diff --git a/src/nvidia/src/kernel/rmapi/param_copy.c b/src/nvidia/src/kernel/rmapi/param_copy.c index 694cf6a9d..7a9f9ea13 100644 --- a/src/nvidia/src/kernel/rmapi/param_copy.c +++ b/src/nvidia/src/kernel/rmapi/param_copy.c @@ -122,8 +122,11 @@ NV_STATUS rmapiParamsAcquire done: if (rmStatus != NV_OK) // There was an error, be sure to free the buffer { - portMemFree(pKernelParams); - pKernelParams = NULL; + if (pKernelParams != NULL) + { + portMemFree(pKernelParams); + pKernelParams = NULL; + } } NV_ASSERT(pParamCopy->ppKernelParams != NULL); diff --git a/src/nvidia/src/libraries/containers/eheap/eheap_old.c b/src/nvidia/src/libraries/containers/eheap/eheap_old.c index ec0707842..4a03dc639 100644 --- a/src/nvidia/src/libraries/containers/eheap/eheap_old.c +++ b/src/nvidia/src/libraries/containers/eheap/eheap_old.c @@ -1189,7 +1189,7 @@ eheapTraverse NvU64 firstBlockBegin, firstBlockEnd; // we'll never call the traversal fn twice on the same (sub)extent. pBlock = (direction > 0) ? pHeap->pBlockList : pHeap->pBlockList->prev; - NV_ASSERT(pBlock); + NV_ASSERT_OR_RETURN(pBlock != NULL, NV_ERR_INVALID_STATE); // // Cursor invalidates mean we can't compare with 'pHeap->pBlockList'. @@ -1238,7 +1238,7 @@ eheapTraverse } - NV_ASSERT(pBlock); // 1. list is circular, 2. cursorOffset should always be found unless the list is badly malformed. + NV_ASSERT_OR_RETURN(pBlock != NULL, NV_ERR_INVALID_STATE); // 1. list is circular, 2. cursorOffset should always be found unless the list is badly malformed. // // Back to first block? Defined as being at a block for which the diff --git a/src/nvidia/src/libraries/nvport/core/core.c b/src/nvidia/src/libraries/nvport/core/core.c index 3ecce65b0..1bdfdb283 100644 --- a/src/nvidia/src/libraries/nvport/core/core.c +++ b/src/nvidia/src/libraries/nvport/core/core.c @@ -28,8 +28,9 @@ typedef struct _PORT_STATE } PORT_STATE; static PORT_STATE portState; - -#if PORT_IS_MODULE_SUPPORTED(atomic) +// RISC-V implementation of atomics requires initialization +// Disable initCount atomic operations for RISC-V builds +#if PORT_IS_MODULE_SUPPORTED(atomic) && !NVCPU_IS_RISCV64 #define PORT_DEC(x) portAtomicDecrementS32((volatile NvS32 *)&x) #define PORT_INC(x) portAtomicIncrementS32((volatile NvS32 *)&x) #else @@ -46,6 +47,9 @@ NV_STATUS portInitialize() #if PORT_IS_MODULE_SUPPORTED(debug) portDbgInitialize(); #endif +#if PORT_IS_MODULE_SUPPORTED(atomic) + portAtomicInit(); +#endif #if PORT_IS_MODULE_SUPPORTED(sync) portSyncInitialize(); #endif diff --git a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c index e161a9649..10da3c9c0 100644 --- a/src/nvidia/src/libraries/nvport/memory/memory_tracking.c +++ b/src/nvidia/src/libraries/nvport/memory/memory_tracking.c @@ -34,10 +34,44 @@ #error "DEBUG module must be present for memory tracking" #endif -#if !PORT_IS_MODULE_SUPPORTED(atomic) +#if PORT_MEM_TRACK_USE_LIMIT +#include "os/os.h" +#define PORT_MEM_LIMIT_MAX_PIDS 32 +#endif + +#if NVOS_IS_LIBOS +#define PORT_MEM_THREAD_SAFE_ALLOCATIONS 0 +#else +#define PORT_MEM_THREAD_SAFE_ALLOCATIONS 1 +#endif + +#if PORT_MEM_THREAD_SAFE_ALLOCATIONS && !PORT_IS_MODULE_SUPPORTED(atomic) #error "ATOMIC module must be present for memory tracking" #endif +#if PORT_MEM_THREAD_SAFE_ALLOCATIONS +#define PORT_MEM_ATOMIC_ADD_SIZE portAtomicAddSize +#define PORT_MEM_ATOMIC_SUB_SIZE portAtomicSubSize +#define PORT_MEM_ATOMIC_DEC_U32 portAtomicDecrementU32 +#define PORT_MEM_ATOMIC_INC_U32 portAtomicIncrementU32 +#define PORT_MEM_ATOMIC_SET_U32 portAtomicSetU32 +#define PORT_MEM_ATOMIC_CAS_SIZE portAtomicCompareAndSwapSize +#define PORT_MEM_ATOMIC_CAS_U32 portAtomicCompareAndSwapU32 +#else +// +// We can just stub out the atomic operations for non-atomic ones and not waste +// waste cycles on synchronization +// +#define PORT_MEM_ATOMIC_ADD_SIZE(pVal, val) (*((NvSPtr *)pVal) += val) +#define PORT_MEM_ATOMIC_SUB_SIZE(pVal, val) (*((NvSPtr *)pVal) -= val) +#define PORT_MEM_ATOMIC_DEC_U32(pVal) (--(*((NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_INC_U32(pVal) (++(*((NvU32 *)pVal))) +#define PORT_MEM_ATOMIC_SET_U32(pVal, val) (*((NvU32 *)pVal) = val) +#define PORT_MEM_ATOMIC_CAS_SIZE(pVal, newVal, oldVal) \ + ((*pVal == oldVal) ? ((*((NvSPtr *)pVal) = newVal), NV_TRUE) : NV_FALSE) +#define PORT_MEM_ATOMIC_CAS_U32(pVal, newVal, oldVal) \ + ((*pVal == oldVal) ? ((*((NvU32 *)pVal) = newVal), NV_TRUE) : NV_FALSE) +#endif // !PORT_MEM_THREAD_SAFE_ALLOCATIONS struct PORT_MEM_ALLOCATOR_IMPL { @@ -60,6 +94,11 @@ struct PORT_MEM_ALLOCATOR_IMPL // Simple implementation of a spinlock that is going to be used where sync module is not included. #if !PORT_IS_MODULE_SUPPORTED(sync) + +#if NVCPU_IS_RISCV64 +#error "Sync module should be enabled for RISC-V builds" +#endif + typedef volatile NvU32 PORT_SPINLOCK; static NvLength portSyncSpinlockSize = sizeof(PORT_SPINLOCK); static NV_STATUS portSyncSpinlockInitialize(PORT_SPINLOCK *pSpinlock) @@ -69,11 +108,11 @@ static NV_STATUS portSyncSpinlockInitialize(PORT_SPINLOCK *pSpinlock) } static void portSyncSpinlockAcquire(PORT_SPINLOCK *pSpinlock) { - while (!portAtomicCompareAndSwapU32(pSpinlock, 1, 0)); + while (!PORT_MEM_ATOMIC_CAS_U32(pSpinlock, 1, 0)); } static void portSyncSpinlockRelease(PORT_SPINLOCK *pSpinlock) { - portAtomicSetU32(pSpinlock, 0); + PORT_MEM_ATOMIC_SET_U32(pSpinlock, 0); } static void portSyncSpinlockDestroy(PORT_SPINLOCK *pSpinlock) { @@ -141,13 +180,13 @@ _portMemCounterInc NvU32 activeAllocs; NvLength activeSize = 0; - activeAllocs = portAtomicIncrementU32(&pCounter->activeAllocs); - portAtomicIncrementU32(&pCounter->totalAllocs); + activeAllocs = PORT_MEM_ATOMIC_INC_U32(&pCounter->activeAllocs); + PORT_MEM_ATOMIC_INC_U32(&pCounter->totalAllocs); if (PORT_MEM_TRACK_USE_FENCEPOSTS) { - activeSize = portAtomicAddSize(&pCounter->activeSize, size); + activeSize = PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->activeSize, size); } - portAtomicAddSize(&pCounter->totalSize, size); + PORT_MEM_ATOMIC_ADD_SIZE(&pCounter->totalSize, size); // Atomically compare the peak value with the active, and update if greater. while (1) @@ -155,14 +194,14 @@ _portMemCounterInc NvU32 peakAllocs = pCounter->peakAllocs; if (activeAllocs <= peakAllocs) break; - portAtomicCompareAndSwapU32(&pCounter->peakAllocs, activeAllocs, peakAllocs); + PORT_MEM_ATOMIC_CAS_U32(&pCounter->peakAllocs, activeAllocs, peakAllocs); } while (1) { NvLength peakSize = pCounter->peakSize; if (activeSize <= peakSize) break; - portAtomicCompareAndSwapSize(&pCounter->peakSize, activeSize, peakSize); + PORT_MEM_ATOMIC_CAS_SIZE(&pCounter->peakSize, activeSize, peakSize); } } static NV_INLINE void @@ -172,11 +211,11 @@ _portMemCounterDec void *pMem ) { - portAtomicDecrementU32(&pCounter->activeAllocs); + PORT_MEM_ATOMIC_DEC_U32(&pCounter->activeAllocs); if (PORT_MEM_TRACK_USE_FENCEPOSTS) { - portAtomicSubSize(&pCounter->activeSize, - ((PORT_MEM_FENCE_HEAD *)pMem-1)->blockSize); + PORT_MEM_ATOMIC_SUB_SIZE(&pCounter->activeSize, + ((PORT_MEM_FENCE_HEAD *)pMem-1)->blockSize); } } @@ -264,7 +303,7 @@ _portMemListAdd PORT_MEM_LIST *pList = &pHead->list; pList->pNext = pList; pList->pPrev = pList; - if (!portAtomicCompareAndSwapSize(&pTracking->pFirstAlloc, pList, NULL)) + if (!PORT_MEM_ATOMIC_CAS_SIZE(&pTracking->pFirstAlloc, pList, NULL)) { PORT_LOCKED_LIST_LINK(pTracking->pFirstAlloc, pList, pTracking->listLock); } @@ -279,11 +318,11 @@ _portMemListRemove PORT_MEM_HEADER *pHead = (PORT_MEM_HEADER*)pMem - 1; PORT_MEM_LIST *pList = &pHead->list; - if (!portAtomicCompareAndSwapSize(&pList->pNext, NULL, pList)) + if (!PORT_MEM_ATOMIC_CAS_SIZE(&pList->pNext, NULL, pList)) { PORT_LOCKED_LIST_UNLINK(pTracking->pFirstAlloc, pList, pTracking->listLock); } - portAtomicCompareAndSwapSize(&pTracking->pFirstAlloc, pList->pNext, pList); + PORT_MEM_ATOMIC_CAS_SIZE(&pTracking->pFirstAlloc, pList->pNext, pList); } static NV_INLINE PORT_MEM_HEADER * @@ -485,8 +524,89 @@ static struct PORT_MEM_GLOBALS } alloc; NvU32 initCount; NvU32 totalAllocators; +#if PORT_MEM_TRACK_USE_LIMIT + NvBool bLimitEnabled; + NvU64 limitPid[PORT_MEM_LIMIT_MAX_PIDS]; + NvU64 counterPid[PORT_MEM_LIMIT_MAX_PIDS]; +#endif } portMemGlobals; +// +// Per-process heap limiting implementation +// +#if PORT_MEM_TRACK_USE_LIMIT +static NV_INLINE void +_portMemLimitInc(NvU32 pid, void *pMem, NvU64 size) +{ + if (portMemGlobals.bLimitEnabled) + { + PORT_MEM_HEADER *pMemHeader = PORT_MEM_SUB_HEADER_PTR(pMem); + pMemHeader->pid = pid; + + if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) + { + NvU32 pidIdx = pid - 1; + pMemHeader->blockSize = size; + PORT_MEM_ATOMIC_ADD_SIZE(&portMemGlobals.counterPid[pidIdx], size); + } + } +} + +static NV_INLINE void +_portMemLimitDec(void *pMem) +{ + if (portMemGlobals.bLimitEnabled) + { + PORT_MEM_HEADER *pMemHeader = PORT_MEM_SUB_HEADER_PTR(pMem); + NvU32 pid = pMemHeader->pid; + + if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) + { + NvU32 pidIdx = pid - 1; + if (portMemGlobals.counterPid[pidIdx] < pMemHeader->blockSize) + { + // TODO: How do we protect against double frees? + PORT_MEM_PRINT_ERROR("memory free error: counter underflow\n"); + PORT_BREAKPOINT_CHECKED(); + } + else + { + PORT_MEM_ATOMIC_SUB_SIZE(&portMemGlobals.counterPid[pidIdx], pMemHeader->blockSize); + } + } + } +} + +static NV_INLINE NvBool +_portMemLimitExceeded(NvU32 pid, NvU64 size) +{ + NvBool bExceeded = NV_FALSE; + + if (portMemGlobals.bLimitEnabled) + { + if ((pid > 0) && (pid <= PORT_MEM_LIMIT_MAX_PIDS)) + { + NvU32 pidIdx = pid - 1; + if ((size + portMemGlobals.counterPid[pidIdx]) > portMemGlobals.limitPid[pidIdx]) + { + PORT_MEM_PRINT_ERROR("memory allocation denied; PID %d exceeded per-process heap limit of 0x%llx\n", + pid, portMemGlobals.limitPid[pidIdx]); + bExceeded = NV_TRUE; + } + } + } + return bExceeded; +} + +#define PORT_MEM_LIMIT_INC(pid, pMem, size) _portMemLimitInc(pid, pMem, size) +#define PORT_MEM_LIMIT_DEC(pMem) _portMemLimitDec(pMem) +#define PORT_MEM_LIMIT_EXCEEDED(pid, size) _portMemLimitExceeded(pid, size) +#else +#define PORT_MEM_LIMIT_INC(pid, pMem, size) +#define PORT_MEM_LIMIT_DEC(pMem) +#define PORT_MEM_LIMIT_EXCEEDED(pid, size) (NV_FALSE) +#endif // PORT_MEM_TRACK_USE_LIMIT + static NV_INLINE PORT_MEM_ALLOCATOR_TRACKING * _portMemGetTracking ( @@ -506,7 +626,7 @@ portMemInitialize(void) #if PORT_MEM_TRACK_USE_CALLERINFO PORT_MEM_CALLERINFO_TYPE_PARAM = PORT_MEM_CALLERINFO_MAKE; #endif - if (portAtomicIncrementU32(&portMemGlobals.initCount) != 1) + if (PORT_MEM_ATOMIC_INC_U32(&portMemGlobals.initCount) != 1) return; portMemGlobals.mainTracking.pAllocator = NULL; @@ -516,6 +636,13 @@ portMemInitialize(void) PORT_MEM_LIST_INIT(&portMemGlobals.mainTracking); PORT_MEM_LOCK_INIT(portMemGlobals.trackingLock); +#if PORT_MEM_TRACK_USE_LIMIT + // Initialize process heap limit to max int (i.e. no limit) + portMemGlobals.bLimitEnabled = NV_FALSE; + portMemSet(&portMemGlobals.limitPid, NV_U8_MAX, sizeof(portMemGlobals.limitPid)); + portMemSet(&portMemGlobals.counterPid, 0, sizeof(portMemGlobals.counterPid)); +#endif + portMemGlobals.alloc.paged._portAlloc = _portMemAllocatorAllocPagedWrapper; portMemGlobals.alloc.nonPaged._portAlloc = _portMemAllocatorAllocNonPagedWrapper; portMemGlobals.alloc.paged._portFree = _portMemAllocatorFreeWrapper; @@ -552,7 +679,7 @@ void portMemShutdown(NvBool bForceSilent) { PORT_UNREFERENCED_VARIABLE(bForceSilent); - if (portAtomicDecrementU32(&portMemGlobals.initCount) != 0) + if (PORT_MEM_ATOMIC_DEC_U32(&portMemGlobals.initCount) != 0) return; #if (PORT_MEM_TRACK_PRINT_LEVEL > PORT_MEM_TRACK_PRINT_LEVEL_SILENT) @@ -753,9 +880,19 @@ portMemInitializeAllocatorTracking PORT_MEM_COUNTER_INIT(&pTracking->counter); PORT_MEM_LIST_INIT(pTracking); PORT_MEM_CALLERINFO_INIT_TRACKING(pTracking); - portAtomicIncrementU32(&portMemGlobals.totalAllocators); + PORT_MEM_ATOMIC_INC_U32(&portMemGlobals.totalAllocators); } +#if PORT_MEM_TRACK_USE_LIMIT +void +portMemInitializeAllocatorTrackingLimit(NvU32 pid, NvU64 limit, NvBool bLimitEnabled) +{ + NvU32 pidIdx = pid - 1; + portMemGlobals.limitPid[pidIdx] = limit; + portMemGlobals.bLimitEnabled = bLimitEnabled; +} +#endif + void * _portMemAllocatorAlloc ( @@ -764,12 +901,31 @@ _portMemAllocatorAlloc PORT_MEM_CALLERINFO_COMMA_TYPE_PARAM ) { +#if PORT_MEM_TRACK_USE_LIMIT + NvU32 pid = 0; +#endif void *pMem = NULL; if (pAlloc == NULL) { PORT_BREAKPOINT_CHECKED(); return NULL; } + +#if PORT_MEM_TRACK_USE_LIMIT + if (portMemGlobals.bLimitEnabled) + { + if (osGetCurrentProcessGfid(&pid) != NV_OK) + { + PORT_BREAKPOINT_CHECKED(); + return NULL; + } + } +#endif + + // Check if per-process memory limit will be exhausted by this allocation + if (PORT_MEM_LIMIT_EXCEEDED(pid, length)) + return NULL; + if (length > 0) { NvLength paddedLength; @@ -794,6 +950,7 @@ _portMemAllocatorAlloc pMem = PORT_MEM_ADD_HEADER_PTR(pMem); _portMemTrackAlloc(_portMemGetTracking(pAlloc), pMem, length PORT_MEM_CALLERINFO_COMMA_PARAM); + PORT_MEM_LIMIT_INC(pid, pMem, length); } return pMem; } @@ -811,6 +968,7 @@ _portMemAllocatorFree } if (pMem != NULL) { + PORT_MEM_LIMIT_DEC(pMem); _portMemTrackFree(_portMemGetTracking(pAlloc), pMem); pMem = PORT_MEM_SUB_HEADER_PTR(pMem); pAlloc->_portFree(pAlloc, pMem); @@ -1073,7 +1231,7 @@ _portMemTrackingRelease PORT_LOCKED_LIST_UNLINK(&portMemGlobals.mainTracking, pTracking, portMemGlobals.trackingLock); PORT_MEM_LIST_DESTROY(pTracking); - portAtomicDecrementU32(&portMemGlobals.totalAllocators); + PORT_MEM_ATOMIC_DEC_U32(&portMemGlobals.totalAllocators); } static void diff --git a/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c b/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c index ab9e7e666..e787b9571 100644 --- a/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c +++ b/src/nvidia/src/libraries/prereq_tracker/prereq_tracker.c @@ -242,6 +242,8 @@ prereqRetract_IMPL PrereqListIter it; NV_STATUS status = NV_OK; + NV_ASSERT_OR_RETURN(pTracker != NULL, + NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(pTracker->bInitialized, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN((prereqId < PREREQ_ID_VECTOR_SIZE), diff --git a/src/nvidia/src/libraries/resserv/src/rs_server.c b/src/nvidia/src/libraries/resserv/src/rs_server.c index 3c49dffea..901e7b146 100644 --- a/src/nvidia/src/libraries/resserv/src/rs_server.c +++ b/src/nvidia/src/libraries/resserv/src/rs_server.c @@ -68,7 +68,7 @@ static NV_STATUS _serverFindNextAvailableClientHandleInBucket(RsServer *pServer, * @param[in] pServer * @param[in] hClient */ -static NV_STATUS _serverCreateEntryAndLockForNewClient(RsServer *pServer, NvHandle *phClient, NvBool bInternalHandle, CLIENT_ENTRY **ppClientEntry ); +static NV_STATUS _serverCreateEntryAndLockForNewClient(RsServer *pServer, NvHandle *phClient, NvBool bInternalHandle, CLIENT_ENTRY **ppClientEntry, API_SECURITY_INFO *pSecInfo); /** * Lock and retrieve the RsClient associated with a client handle. @@ -521,7 +521,7 @@ serverAllocClient } #endif - status = _serverCreateEntryAndLockForNewClient(pServer, &hClient, !!(pParams->allocState & ALLOC_STATE_INTERNAL_CLIENT_HANDLE), &pClientEntry); + status = _serverCreateEntryAndLockForNewClient(pServer, &hClient, !!(pParams->allocState & ALLOC_STATE_INTERNAL_CLIENT_HANDLE), &pClientEntry, pParams->pSecInfo); if (status != NV_OK) { @@ -777,6 +777,18 @@ done: serverResLock_Epilogue(pServer, LOCK_ACCESS_WRITE, pParams->pLockInfo, &releaseFlags); return status; } + +NvU32 +serverAllocClientHandleBase +( + RsServer *pServer, + NvBool bInternalHandle, + API_SECURITY_INFO *pSecInfo +) +{ + return bInternalHandle ? pServer->internalHandleBase : + pServer->clientHandleBase; +} #endif NV_STATUS @@ -2119,24 +2131,23 @@ _serverFindNextAvailableClientHandleInBucket return NV_OK; } - static NV_STATUS _serverCreateEntryAndLockForNewClient ( - RsServer *pServer, - NvHandle *phClient, - NvBool bInternalHandle, - CLIENT_ENTRY **ppClientEntry + RsServer *pServer, + NvHandle *phClient, + NvBool bInternalHandle, + CLIENT_ENTRY **ppClientEntry, + API_SECURITY_INFO *pSecInfo ) { CLIENT_ENTRY *pClientEntry; NV_STATUS status = NV_OK; NvHandle hClient = *phClient; CLIENT_ENTRY **ppClientNext = 0; - PORT_RWLOCK *pLock=NULL; - NvU32 handleBase = bInternalHandle ? pServer->internalHandleBase : - pServer->clientHandleBase; + PORT_RWLOCK *pLock = NULL; + NvU32 handleBase = serverAllocClientHandleBase(pServer, bInternalHandle, pSecInfo); if (hClient == 0) { diff --git a/src/nvidia/src/libraries/tls/tls.c b/src/nvidia/src/libraries/tls/tls.c index a7867a6a2..0fbba2fb5 100644 --- a/src/nvidia/src/libraries/tls/tls.c +++ b/src/nvidia/src/libraries/tls/tls.c @@ -130,6 +130,18 @@ NvU32 osGetMaximumCoreCount(void); #endif #endif +#if NVOS_IS_LIBOS +// +// On LibOS we have at most one passive thread (task_rm) and one ISR +// (task_interrupt) active at once (on same CPU core). Since these two will +// use different maps, we don't need to protect them with spinlocks. +// +#define TLS_SPINLOCK_ACQUIRE(x) +#define TLS_SPINLOCK_RELEASE(x) +#else +#define TLS_SPINLOCK_ACQUIRE(x) portSyncSpinlockAcquire(x) +#define TLS_SPINLOCK_RELEASE(x) portSyncSpinlockRelease(x) +#endif // NVOS_IS_LIBOS #if !PORT_IS_FUNC_SUPPORTED(portSyncExSafeToSleep) #define portSyncExSafeToSleep() NV_TRUE @@ -426,9 +438,9 @@ _tlsThreadEntryGet() else { NvU64 threadId = portThreadGetCurrentThreadId(); - portSyncSpinlockAcquire(tlsDatabase.pLock); - pThreadEntry = mapFind(&tlsDatabase.threadEntries, threadId); - portSyncSpinlockRelease(tlsDatabase.pLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pLock); + pThreadEntry = mapFind(&tlsDatabase.threadEntries, threadId); + TLS_SPINLOCK_RELEASE(tlsDatabase.pLock); } return pThreadEntry; } @@ -448,11 +460,11 @@ _tlsThreadEntryGetOrAlloc() { pThreadEntry->key.threadId = portThreadGetCurrentThreadId(); mapInitIntrusive(&pThreadEntry->map); - portSyncSpinlockAcquire(tlsDatabase.pLock); - mapInsertExisting(&tlsDatabase.threadEntries, - pThreadEntry->key.threadId, - pThreadEntry); - portSyncSpinlockRelease(tlsDatabase.pLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pLock); + mapInsertExisting(&tlsDatabase.threadEntries, + pThreadEntry->key.threadId, + pThreadEntry); + TLS_SPINLOCK_RELEASE(tlsDatabase.pLock); } } @@ -510,9 +522,9 @@ _tlsEntryRelease { NV_ASSERT(portMemExSafeForNonPagedAlloc()); mapDestroy(&pThreadEntry->map); - portSyncSpinlockAcquire(tlsDatabase.pLock); - mapRemove(&tlsDatabase.threadEntries, pThreadEntry); - portSyncSpinlockRelease(tlsDatabase.pLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pLock); + mapRemove(&tlsDatabase.threadEntries, pThreadEntry); + TLS_SPINLOCK_RELEASE(tlsDatabase.pLock); PORT_FREE(tlsDatabase.pAllocator, pThreadEntry); } } @@ -555,29 +567,29 @@ static void _tlsIsrEntriesDestroy() } static void _tlsIsrEntriesInsert(ThreadEntry *pThreadEntry) { - portSyncSpinlockAcquire(tlsDatabase.pIsrLock); - mapInsertExisting(&tlsDatabase.isrEntries, pThreadEntry->key.sp, pThreadEntry); - portSyncSpinlockRelease(tlsDatabase.pIsrLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pIsrLock); + mapInsertExisting(&tlsDatabase.isrEntries, pThreadEntry->key.sp, pThreadEntry); + TLS_SPINLOCK_RELEASE(tlsDatabase.pIsrLock); } static ThreadEntry *_tlsIsrEntriesRemove(NvU64 sp) { ThreadEntry *pThreadEntry; - portSyncSpinlockAcquire(tlsDatabase.pIsrLock); - pThreadEntry = mapFind(&tlsDatabase.isrEntries, sp); - mapRemove(&tlsDatabase.isrEntries, pThreadEntry); - portSyncSpinlockRelease(tlsDatabase.pIsrLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pIsrLock); + pThreadEntry = mapFind(&tlsDatabase.isrEntries, sp); + mapRemove(&tlsDatabase.isrEntries, pThreadEntry); + TLS_SPINLOCK_RELEASE(tlsDatabase.pIsrLock); return pThreadEntry; } static ThreadEntry *_tlsIsrEntriesFind(NvU64 approxSp) { ThreadEntry *pThreadEntry; - portSyncSpinlockAcquire(tlsDatabase.pIsrLock); + TLS_SPINLOCK_ACQUIRE(tlsDatabase.pIsrLock); #if STACK_GROWS_DOWNWARD - pThreadEntry = mapFindGEQ(&tlsDatabase.isrEntries, approxSp); + pThreadEntry = mapFindGEQ(&tlsDatabase.isrEntries, approxSp); #else - pThreadEntry = mapFindLEQ(&tlsDatabase.isrEntries, approxSp); + pThreadEntry = mapFindLEQ(&tlsDatabase.isrEntries, approxSp); #endif - portSyncSpinlockRelease(tlsDatabase.pIsrLock); + TLS_SPINLOCK_RELEASE(tlsDatabase.pIsrLock); return pThreadEntry; } diff --git a/src/nvidia/srcs.mk b/src/nvidia/srcs.mk index 92a1da512..64b96cc7b 100644 --- a/src/nvidia/srcs.mk +++ b/src/nvidia/srcs.mk @@ -415,6 +415,7 @@ SRCS += src/kernel/gpu/gr/kernel_graphics_manager.c SRCS += src/kernel/gpu/gr/kernel_graphics_object.c SRCS += src/kernel/gpu/gr/kernel_sm_debugger_session.c SRCS += src/kernel/gpu/gr/kernel_sm_debugger_session_ctrl.c +SRCS += src/kernel/gpu/gsp/arch/ada/kernel_gsp_ad102.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_falcon_ga102.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga100.c SRCS += src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c diff --git a/version.mk b/version.mk index 3dcd3e7e0..1d96e93a6 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 525.60.13 +NVIDIA_VERSION = 525.78.01 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))