From 965db985520c0c2aefa56dc2e81f9bfa67e91375 Mon Sep 17 00:00:00 2001 From: Andy Ritger Date: Fri, 27 May 2022 16:40:24 -0700 Subject: [PATCH] 515.48.07 --- CHANGELOG.md | 31 + README.md | 618 +- kernel-open/Kbuild | 3 +- kernel-open/common/inc/nv-linux.h | 13 +- kernel-open/common/inc/nv-proto.h | 2 - kernel-open/common/inc/nv.h | 14 +- kernel-open/conftest.sh | 95 +- .../nvidia-drm/nvidia-dma-resv-helper.h | 46 + .../nvidia-drm/nvidia-drm-prime-fence.c | 13 +- kernel-open/nvidia-drm/nvidia-drm.Kbuild | 3 + .../nvidia-modeset/nvidia-modeset-linux.c | 8 + kernel-open/nvidia-uvm/uvm_linux.h | 2 +- kernel-open/nvidia-uvm/uvm_maxwell_ce.c | 2 +- kernel-open/nvidia/linux_nvswitch.c | 4 +- kernel-open/nvidia/nv-acpi.c | 452 +- kernel-open/nvidia/nv-dma.c | 61 +- kernel-open/nvidia/nv-dmabuf.c | 13 + kernel-open/nvidia/nv-reg.h | 45 +- kernel-open/nvidia/nv.c | 23 +- src/common/displayport/inc/dp_connectorimpl.h | 4 + src/common/displayport/inc/dp_deviceimpl.h | 2 + src/common/displayport/inc/dp_groupimpl.h | 4 + src/common/displayport/inc/dp_messages.h | 11 + .../displayport/inc/dp_regkeydatabase.h | 8 +- .../displayport/src/dp_connectorimpl.cpp | 116 +- src/common/displayport/src/dp_deviceimpl.cpp | 59 + src/common/displayport/src/dp_evoadapter.cpp | 4 +- src/common/displayport/src/dp_messages.cpp | 18 +- src/common/inc/displayport/displayport.h | 4 + src/common/inc/displayport/dpcd.h | 1 + src/common/inc/displayport/dpcd20.h | 11 + src/common/inc/nvBldVer.h | 21 +- src/common/inc/nvPNPVendorIds.h | 2 +- src/common/inc/nvSha1.h | 2 +- src/common/inc/nvUnixVersion.h | 2 +- .../swref/published/ampere/ga100/dev_fuse.h | 4 + .../ampere/ga100/dev_nv_xve_addendum.h | 9 +- .../published/ampere/ga102/dev_gc6_island.h | 7 +- .../ampere/ga102/dev_gc6_island_addendum.h | 3 + .../swref/published/maxwell/gm107/dev_fuse.h | 31 + .../published/turing/tu102/dev_gc6_island.h | 5 +- .../turing/tu102/dev_gc6_island_addendum.h | 3 + src/common/modeset/timing/nvt_dsc_pps.c | 23 +- src/common/modeset/timing/nvt_dsc_pps.h | 7 + src/common/modeset/timing/nvt_edid.c | 2 +- src/common/nvswitch/kernel/inc/rom_nvswitch.h | 6 +- .../inc/ctrl/ctrl2080/ctrl2080internal.h | 15 + src/common/sdk/nvidia/inc/nverror.h | 6 +- src/common/sdk/nvidia/inc/nvfixedtypes.h | 2 +- .../unix/common/utils/nv_memory_tracker.c | 2 +- .../uproc/os/libos-v2.0.0/debug/lines.c | 2 +- src/nvidia-modeset/Makefile | 1 + src/nvidia-modeset/src/nvkms-hdmi.c | 2 +- src/nvidia/Makefile | 1 + .../arch/nvalloc/common/inc/flcnretval.h | 7 + src/nvidia/arch/nvalloc/unix/include/nv-reg.h | 45 +- src/nvidia/arch/nvalloc/unix/include/nv.h | 14 +- src/nvidia/arch/nvalloc/unix/src/osapi.c | 60 +- src/nvidia/generated/g_bindata.c | 16 - ...a_kgspGetBinArchiveBooterLoadUcode_GA100.c | 6100 ++++++++-------- ...a_kgspGetBinArchiveBooterLoadUcode_GA102.c | 6503 ++++++++--------- ...a_kgspGetBinArchiveBooterLoadUcode_TU102.c | 6118 ++++++++-------- ...a_kgspGetBinArchiveBooterLoadUcode_TU116.c | 6104 ++++++++-------- ...kgspGetBinArchiveBooterReloadUcode_GA100.c | 1371 ---- ...kgspGetBinArchiveBooterReloadUcode_GA102.c | 1443 ---- ...kgspGetBinArchiveBooterReloadUcode_TU102.c | 1317 ---- ...kgspGetBinArchiveBooterReloadUcode_TU116.c | 1317 ---- ...kgspGetBinArchiveBooterUnloadUcode_GA100.c | 1812 +++-- ...kgspGetBinArchiveBooterUnloadUcode_GA102.c | 1999 +++-- ...kgspGetBinArchiveBooterUnloadUcode_TU102.c | 1706 +++-- ...kgspGetBinArchiveBooterUnloadUcode_TU116.c | 1706 +++-- src/nvidia/generated/g_gpu_mgr_nvoc.h | 39 + src/nvidia/generated/g_gpu_nvoc.c | 16 + src/nvidia/generated/g_gpu_nvoc.h | 38 + src/nvidia/generated/g_kernel_bif_nvoc.c | 38 +- src/nvidia/generated/g_kernel_bif_nvoc.h | 35 +- src/nvidia/generated/g_kernel_gsp_nvoc.c | 27 - src/nvidia/generated/g_kernel_gsp_nvoc.h | 69 +- src/nvidia/generated/g_nv_name_released.h | 1 + src/nvidia/generated/g_subdevice_nvoc.c | 455 +- src/nvidia/generated/g_subdevice_nvoc.h | 8 + src/nvidia/inc/libraries/containers/list.h | 2 +- src/nvidia/inc/libraries/nvport/crypto.h | 4 +- src/nvidia/inc/libraries/nvport/debug.h | 2 +- src/nvidia/inc/libraries/nvport/sync.h | 2 +- .../kernel/gpu/arch/ampere/kern_gpu_ga100.c | 14 + .../kernel/gpu/arch/maxwell/kern_gpu_gm107.c | 13 + .../gpu/bif/arch/ampere/kernel_bif_ga100.c | 24 + src/nvidia/src/kernel/gpu/bif/kernel_bif.c | 66 +- src/nvidia/src/kernel/gpu/disp/kern_disp.c | 3 + src/nvidia/src/kernel/gpu/gpu.c | 6 + src/nvidia/src/kernel/gpu/gpu_rmapi.c | 66 +- .../gpu/gsp/arch/ampere/kernel_gsp_ga102.c | 42 +- .../gsp/arch/turing/kernel_gsp_booter_tu102.c | 29 - .../gsp/arch/turing/kernel_gsp_frts_tu102.c | 186 +- .../gpu/gsp/arch/turing/kernel_gsp_tu102.c | 84 +- .../gsp/arch/turing/kernel_gsp_vbios_tu102.c | 2 +- src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c | 80 +- .../src/kernel/gpu/gsp/kernel_gsp_booter.c | 48 +- .../src/kernel/gpu/gsp/message_queue_cpu.c | 27 +- src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c | 11 +- .../gpu/nvlink/kernel_nvlinkcorelibtrain.c | 24 + .../src/kernel/gpu/subdevice/subdevice.c | 4 + src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c | 259 +- .../kernel/platform/chipset/chipset_info.c | 2 +- .../kernel/platform/chipset/chipset_pcie.c | 6 +- src/nvidia/src/kernel/platform/cpu.c | 2 +- src/nvidia/src/kernel/platform/p2p/p2p_caps.c | 24 +- src/nvidia/src/kernel/rmapi/nv_gpu_ops.c | 10 +- src/nvidia/src/lib/protobuf/prbenc.c | 4 +- .../src/libraries/containers/btree/btree.c | 2 +- .../nvport/crypto/crypto_random_xorshift.c | 6 +- utils.mk | 10 +- version.mk | 2 +- 114 files changed, 18493 insertions(+), 22785 deletions(-) create mode 100644 CHANGELOG.md create mode 100644 src/common/inc/swref/published/maxwell/gm107/dev_fuse.h delete mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c delete mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c delete mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c delete mode 100644 src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 000000000..3c0476cb3 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,31 @@ +# Changelog + +## Release 515 Entries + +### [515.48.07] 2022-05-31 + +#### Added + +- List of compatible GPUs in README.md. + +#### Fixed + +- Fix various README capitalizations, [#8 by @lx-is](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/8) +- Automatically tag bug report issues, [#15 by @thebeanogamer](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/15) +- Improve conftest.sh Script, [#37 by @Nitepone](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/37) +- Update HTTP link to HTTPS, [#101 by @alcaparra](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/101) +- moved array sanity check to before the array access, [#117 by @RealAstolfo](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/117) +- Fixed some typos, [#122 by @FEDOyt](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/122) +- Fixed capitalization, [#123 by @keroeslux](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/123) +- Fix typos in NVDEC Engine Descriptor, [#126 from @TrickyDmitriy](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/126) +- Extranous apostrohpes in a makefile script [sic], [#14 by @kiroma](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/14) +- HDMI no audio @4K above 60Hz, [#75 by @adolfotregosa](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/75) +- dp_configcaps.cpp:405: array index sanity check in wrong place?, [#110 by @dcb314](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/110) +- NVRM kgspInitRm_IMPL: missing NVDEC0 engine, cannot initialize GSP-RM, [#116 by @kfazz](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/116) +- ERROR: modpost: "backlight_device_register" [...nvidia-modeset.ko] undefined, [#135 by @sndirsch](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/135) +- aarch64 build fails, [#151 by @frezbo](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/151) + +### [515.43.04] 2022-05-11 + +- Initial release. + diff --git a/README.md b/README.md index 5c6e146c9..6726493de 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # NVIDIA Linux Open GPU Kernel Module Source This is the source release of the NVIDIA Linux open GPU kernel modules, -version 515.43.04. +version 515.48.07. ## How to Build @@ -17,7 +17,7 @@ as root: Note that the kernel modules built here must be used with gsp.bin firmware and user-space NVIDIA GPU driver components from a corresponding -515.43.04 driver release. This can be achieved by installing +515.48.07 driver release. This can be achieved by installing the NVIDIA GPU driver from the .run file using the `--no-kernel-modules` option. E.g., @@ -162,3 +162,617 @@ for the target kernel. - `src/nvidia/` The OS-agnostic code for nvidia.ko - `src/nvidia-modeset/` The OS-agnostic code for nvidia-modeset.ko - `src/common/` Utility code used by one or more of nvidia.ko and nvidia-modeset.ko + + +## Compatible GPUs + +The open-gpu-kernel-modules can be used on any Turing or later GPU +(see the table below). However, in the 515.48.07 release, +GeForce and Workstation support is still considered alpha-quality. + +To enable use of the open kernel modules on GeForce and Workstation GPUs, +set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module +parameter to 1. For more details, see the NVIDIA GPU driver end user +README here: + +https://us.download.nvidia.com/XFree86/Linux-x86_64/515.48.07/README/kernel_open.html + +In the below table, if three IDs are listed, the first is the PCI Device +ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI +Subsystem Device ID. + +| Product Name | PCI ID | +| ----------------------------------------------- | -------------- | +| NVIDIA TITAN RTX | 1E02 | +| NVIDIA GeForce RTX 2080 Ti | 1E04 | +| NVIDIA GeForce RTX 2080 Ti | 1E07 | +| Quadro RTX 6000 | 1E30 | +| Quadro RTX 8000 | 1E30 1028 129E | +| Quadro RTX 8000 | 1E30 103C 129E | +| Quadro RTX 8000 | 1E30 10DE 129E | +| Quadro RTX 6000 | 1E36 | +| Quadro RTX 8000 | 1E78 10DE 13D8 | +| Quadro RTX 6000 | 1E78 10DE 13D9 | +| NVIDIA GeForce RTX 2080 SUPER | 1E81 | +| NVIDIA GeForce RTX 2080 | 1E82 | +| NVIDIA GeForce RTX 2070 SUPER | 1E84 | +| NVIDIA GeForce RTX 2080 | 1E87 | +| NVIDIA GeForce RTX 2060 | 1E89 | +| NVIDIA GeForce RTX 2080 | 1E90 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1025 1375 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08A1 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08A2 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EA | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EB | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EC | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08ED | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EE | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EF | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 093B | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 093C | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8572 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8573 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8602 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8606 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 86C6 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 86C7 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 87A6 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 87A7 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 131F | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 137F | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 141F | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 1751 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1660 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1661 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1662 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 75A6 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 75A7 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 86A6 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 86A7 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1462 1274 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1462 1277 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 152D 1220 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1558 95E1 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1558 97E1 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2002 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2005 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2007 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 3000 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 3001 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1D05 1069 | +| NVIDIA GeForce RTX 2070 Super | 1E91 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8607 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8736 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8738 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8772 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 878A | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 878B | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1043 1E61 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 1511 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 75B3 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 75B4 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 76B2 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 76B3 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 78A2 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 78A3 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 86B2 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 86B3 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12AE | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12B0 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12C6 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 17AA 22C3 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 17AA 22C5 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 2009 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 200A | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 3002 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 8086 3012 | +| NVIDIA GeForce RTX 2080 Super | 1E93 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1025 1401 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1025 149C | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1028 09D2 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8607 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 86C7 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8736 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8738 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8772 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 87A6 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 87A7 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 75B1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 75B2 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 76B0 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 76B1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 78A0 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 78A1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 86B0 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 86B1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12AE | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12B0 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12B4 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12C6 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1558 50D3 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1558 70D1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 17AA 22C3 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 17AA 22C5 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 2009 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 200A | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 3002 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1D05 1089 | +| Quadro RTX 5000 | 1EB0 | +| Quadro RTX 4000 | 1EB1 | +| Quadro RTX 5000 | 1EB5 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 1375 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 1401 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 149C | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1028 09C3 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8736 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8738 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8772 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8780 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8782 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8783 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8785 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1043 1DD1 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 1274 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 12B0 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 12C6 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 17AA 22B8 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 17AA 22BA | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2005 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2007 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2008 | +| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 200A | +| Quadro RTX 4000 | 1EB6 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 1028 09C3 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8736 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8738 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8772 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8780 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8782 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8783 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8785 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 1274 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 1277 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 12B0 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 12C6 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 17AA 22B8 | +| Quadro RTX 4000 with Max-Q Design | 1EB6 17AA 22BA | +| NVIDIA GeForce RTX 2070 SUPER | 1EC2 | +| NVIDIA GeForce RTX 2070 SUPER | 1EC7 | +| NVIDIA GeForce RTX 2080 | 1ED0 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1025 132D | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08ED | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08EE | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08EF | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8572 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8573 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8600 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8605 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1043 138F | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1043 15C1 | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 17AA 3FEE | +| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 17AA 3FFE | +| NVIDIA GeForce RTX 2070 Super | 1ED1 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 1025 1432 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 103C 8746 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 103C 878A | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 1043 165F | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 144D C192 | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FCE | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FCF | +| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FD0 | +| NVIDIA GeForce RTX 2080 Super | 1ED3 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1025 1432 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1028 09D1 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 103C 8746 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 103C 878A | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1D61 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1E51 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1F01 | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FCE | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FCF | +| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FD0 | +| Quadro RTX 5000 | 1EF5 | +| NVIDIA GeForce RTX 2070 | 1F02 | +| NVIDIA GeForce RTX 2060 | 1F03 | +| NVIDIA GeForce RTX 2060 SUPER | 1F06 | +| NVIDIA GeForce RTX 2070 | 1F07 | +| NVIDIA GeForce RTX 2060 | 1F08 | +| NVIDIA GeForce GTX 1650 | 1F0A | +| NVIDIA GeForce RTX 2070 | 1F10 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1025 132D | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1025 1342 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08A1 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08A2 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EA | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EB | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EC | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08ED | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EE | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EF | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 093B | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 093C | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8572 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8573 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8602 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8606 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 132F | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 136F | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 1881 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 1E6E | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1658 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1663 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1664 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 75A4 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 75A5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 86A4 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 86A5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1462 1274 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1462 1277 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1558 95E1 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1558 97E1 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2002 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2005 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2007 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 3000 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 3001 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 105E | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 1070 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 2087 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 8086 2087 | +| NVIDIA GeForce RTX 2060 | 1F11 | +| NVIDIA GeForce RTX 2060 | 1F12 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1028 098F | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 8741 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 8744 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 878E | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 880E | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1043 1E11 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1043 1F11 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1462 12D9 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3801 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3802 | +| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3803 | +| NVIDIA GeForce RTX 2070 | 1F14 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1401 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1432 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1442 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1446 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 147D | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1028 09E2 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1028 09F3 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8607 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 86C6 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 86C7 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8736 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8738 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8746 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8772 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 878A | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 878B | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 87A6 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 87A7 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1043 174F | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 1512 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 75B5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 75B6 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 76B4 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 76B5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 78A4 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 78A5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 86B4 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 86B5 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12AE | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12B0 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12C6 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1558 50D3 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1558 70D1 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 200C | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 2011 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 3002 | +| NVIDIA GeForce RTX 2060 | 1F15 | +| Quadro RTX 3000 | 1F36 | +| Quadro RTX 3000 with Max-Q Design | 1F36 1028 0990 | +| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8736 | +| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8738 | +| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8772 | +| Quadro RTX 3000 with Max-Q Design | 1F36 1043 13CF | +| Quadro RTX 3000 with Max-Q Design | 1F36 1414 0032 | +| NVIDIA GeForce RTX 2060 SUPER | 1F42 | +| NVIDIA GeForce RTX 2060 SUPER | 1F47 | +| NVIDIA GeForce RTX 2070 | 1F50 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08ED | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08EE | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08EF | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8572 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8573 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8574 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8600 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8605 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 17AA 3FEE | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 17AA 3FFE | +| NVIDIA GeForce RTX 2060 | 1F51 | +| NVIDIA GeForce RTX 2070 | 1F54 | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 103C 878A | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FCE | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FCF | +| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FD0 | +| NVIDIA GeForce RTX 2060 | 1F55 | +| Quadro RTX 3000 | 1F76 | +| Matrox D-Series D2450 | 1F76 102B 2800 | +| Matrox D-Series D2480 | 1F76 102B 2900 | +| NVIDIA GeForce GTX 1650 | 1F82 | +| NVIDIA GeForce GTX 1650 | 1F91 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 863E | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 86E7 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 86E8 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1043 12CF | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1043 156F | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1414 0032 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 144D C822 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 127E | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1281 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1284 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1285 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 129C | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 229F | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3802 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3806 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3F1A | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1A58 1001 | +| NVIDIA GeForce GTX 1650 Ti | 1F95 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 1479 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147A | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147B | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147C | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 86E7 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 86E8 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 8815 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1043 1DFF | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1043 1E1F | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 144D C838 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12BD | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12C5 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12D2 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 22C0 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 22C1 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 3837 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 3F95 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1003 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1006 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1007 | +| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1E83 3E30 | +| NVIDIA GeForce GTX 1650 | 1F96 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F96 1462 1297 | +| NVIDIA GeForce MX450 | 1F97 | +| NVIDIA GeForce MX450 | 1F98 | +| NVIDIA GeForce GTX 1650 | 1F99 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 1479 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147A | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147B | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147C | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 103C 8815 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 13B2 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 1402 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 1902 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12BD | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12C5 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12D2 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 17AA 22DA | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 17AA 3F93 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1E83 3E30 | +| NVIDIA GeForce MX450 | 1F9C | +| NVIDIA GeForce GTX 1650 | 1F9D | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 128D | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 130D | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 149C | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 185C | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 189C | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 12F4 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 1302 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 131B | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 1326 | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 132A | +| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 132E | +| NVIDIA GeForce MX550 | 1F9F | +| NVIDIA GeForce MX550 | 1FA0 | +| NVIDIA T1000 | 1FB0 1028 12DB | +| NVIDIA T1000 | 1FB0 103C 12DB | +| NVIDIA T1000 | 1FB0 103C 8A80 | +| NVIDIA T1000 | 1FB0 10DE 12DB | +| NVIDIA DGX Display | 1FB0 10DE 1485 | +| NVIDIA T1000 | 1FB0 17AA 12DB | +| NVIDIA T600 | 1FB1 1028 1488 | +| NVIDIA T600 | 1FB1 103C 1488 | +| NVIDIA T600 | 1FB1 103C 8A80 | +| NVIDIA T600 | 1FB1 10DE 1488 | +| NVIDIA T600 | 1FB1 17AA 1488 | +| NVIDIA T400 | 1FB2 1028 1489 | +| NVIDIA T400 | 1FB2 103C 1489 | +| NVIDIA T400 | 1FB2 103C 8A80 | +| NVIDIA T400 | 1FB2 10DE 1489 | +| NVIDIA T400 | 1FB2 17AA 1489 | +| NVIDIA T600 Laptop GPU | 1FB6 | +| NVIDIA T550 Laptop GPU | 1FB7 | +| Quadro T2000 | 1FB8 | +| Quadro T2000 with Max-Q Design | 1FB8 1028 097E | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8736 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8738 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8772 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8780 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8782 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8783 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 8785 | +| Quadro T2000 with Max-Q Design | 1FB8 103C 87F0 | +| Quadro T2000 with Max-Q Design | 1FB8 1462 1281 | +| Quadro T2000 with Max-Q Design | 1FB8 1462 12BD | +| Quadro T2000 with Max-Q Design | 1FB8 17AA 22C0 | +| Quadro T2000 with Max-Q Design | 1FB8 17AA 22C1 | +| Quadro T1000 | 1FB9 | +| Quadro T1000 with Max-Q Design | 1FB9 1025 1479 | +| Quadro T1000 with Max-Q Design | 1FB9 1025 147A | +| Quadro T1000 with Max-Q Design | 1FB9 1025 147B | +| Quadro T1000 with Max-Q Design | 1FB9 1025 147C | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8736 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8738 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8772 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8780 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8782 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8783 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 8785 | +| Quadro T1000 with Max-Q Design | 1FB9 103C 87F0 | +| Quadro T1000 with Max-Q Design | 1FB9 1462 12BD | +| Quadro T1000 with Max-Q Design | 1FB9 17AA 22C0 | +| Quadro T1000 with Max-Q Design | 1FB9 17AA 22C1 | +| NVIDIA T600 Laptop GPU | 1FBA | +| NVIDIA T500 | 1FBB | +| NVIDIA T1200 Laptop GPU | 1FBC | +| NVIDIA GeForce GTX 1650 | 1FDD | +| NVIDIA T1000 8GB | 1FF0 1028 1612 | +| NVIDIA T1000 8GB | 1FF0 103C 1612 | +| NVIDIA T1000 8GB | 1FF0 103C 8A80 | +| NVIDIA T1000 8GB | 1FF0 10DE 1612 | +| NVIDIA T1000 8GB | 1FF0 17AA 1612 | +| NVIDIA T400 4GB | 1FF2 1028 1613 | +| NVIDIA T400 4GB | 1FF2 103C 1613 | +| NVIDIA T400 4GB | 1FF2 103C 8A80 | +| NVIDIA T400 4GB | 1FF2 10DE 1613 | +| NVIDIA T400 4GB | 1FF2 17AA 1613 | +| Quadro T1000 | 1FF9 | +| NVIDIA A100-SXM4-40GB | 20B0 | +| NVIDIA A100-PG509-200 | 20B0 10DE 1450 | +| NVIDIA A100-SXM4-80GB | 20B2 10DE 1463 | +| NVIDIA A100-SXM4-80GB | 20B2 10DE 147F | +| NVIDIA PG506-242 | 20B3 10DE 14A7 | +| NVIDIA PG506-243 | 20B3 10DE 14A8 | +| NVIDIA A100 80GB PCIe | 20B5 10DE 1533 | +| NVIDIA A100 80GB PCIe | 20B5 10DE 1642 | +| NVIDIA PG506-232 | 20B6 10DE 1492 | +| NVIDIA A30 | 20B7 10DE 1532 | +| NVIDIA A100-PCIE-40GB | 20F1 10DE 145F | +| NVIDIA GeForce GTX 1660 Ti | 2182 | +| NVIDIA GeForce GTX 1660 | 2184 | +| NVIDIA GeForce GTX 1650 SUPER | 2187 | +| NVIDIA GeForce GTX 1650 | 2188 | +| NVIDIA GeForce GTX 1660 Ti | 2191 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1028 0949 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 85FB | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 85FE | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 86D6 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 8741 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 8744 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 878D | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 87AF | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 87B3 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 171F | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 17EF | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 18D1 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1414 0032 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 128A | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 128B | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12C6 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12CB | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12CC | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12D9 | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 380C | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 381D | +| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 381E | +| NVIDIA GeForce GTX 1650 Ti | 2192 | +| NVIDIA GeForce GTX 1660 SUPER | 21C4 | +| NVIDIA GeForce GTX 1660 Ti | 21D1 | +| NVIDIA GeForce RTX 3090 Ti | 2203 | +| NVIDIA GeForce RTX 3090 | 2204 | +| NVIDIA GeForce RTX 3080 | 2206 | +| NVIDIA GeForce RTX 3080 Ti | 2208 | +| NVIDIA GeForce RTX 3080 | 220A | +| NVIDIA CMP 90HX | 220D | +| NVIDIA GeForce RTX 3080 | 2216 | +| NVIDIA RTX A6000 | 2230 1028 1459 | +| NVIDIA RTX A6000 | 2230 103C 1459 | +| NVIDIA RTX A6000 | 2230 10DE 1459 | +| NVIDIA RTX A6000 | 2230 17AA 1459 | +| NVIDIA RTX A5000 | 2231 1028 147E | +| NVIDIA RTX A5000 | 2231 103C 147E | +| NVIDIA RTX A5000 | 2231 10DE 147E | +| NVIDIA RTX A5000 | 2231 17AA 147E | +| NVIDIA RTX A4500 | 2232 1028 163C | +| NVIDIA RTX A4500 | 2232 103C 163C | +| NVIDIA RTX A4500 | 2232 10DE 163C | +| NVIDIA RTX A4500 | 2232 17AA 163C | +| NVIDIA RTX A5500 | 2233 1028 165A | +| NVIDIA RTX A5500 | 2233 103C 165A | +| NVIDIA RTX A5500 | 2233 10DE 165A | +| NVIDIA RTX A5500 | 2233 17AA 165A | +| NVIDIA A40 | 2235 10DE 145A | +| NVIDIA A10 | 2236 10DE 1482 | +| NVIDIA A10G | 2237 10DE 152F | +| NVIDIA A10M | 2238 10DE 1677 | +| NVIDIA GeForce RTX 3060 Ti | 2414 | +| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 | +| NVIDIA RTX A5500 Laptop GPU | 2438 | +| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2460 | +| NVIDIA GeForce RTX 3070 Ti | 2482 | +| NVIDIA GeForce RTX 3070 | 2484 | +| NVIDIA GeForce RTX 3060 Ti | 2486 | +| NVIDIA GeForce RTX 3060 | 2487 | +| NVIDIA GeForce RTX 3070 | 2488 | +| NVIDIA GeForce RTX 3060 Ti | 2489 | +| NVIDIA CMP 70HX | 248A | +| NVIDIA GeForce RTX 3080 Laptop GPU | 249C | +| NVIDIA GeForce RTX 3060 Laptop GPU | 249C 1D05 1194 | +| NVIDIA GeForce RTX 3070 Laptop GPU | 249D | +| NVIDIA GeForce RTX 3070 Ti Laptop GPU | 24A0 | +| NVIDIA GeForce RTX 3060 Laptop GPU | 24A0 1D05 1192 | +| NVIDIA RTX A4000 | 24B0 1028 14AD | +| NVIDIA RTX A4000 | 24B0 103C 14AD | +| NVIDIA RTX A4000 | 24B0 10DE 14AD | +| NVIDIA RTX A4000 | 24B0 17AA 14AD | +| NVIDIA RTX A4000H | 24B1 10DE 1658 | +| NVIDIA RTX A5000 Laptop GPU | 24B6 | +| NVIDIA RTX A4000 Laptop GPU | 24B7 | +| NVIDIA RTX A3000 Laptop GPU | 24B8 | +| NVIDIA RTX A3000 12GB Laptop GPU | 24B9 | +| NVIDIA RTX A4500 Laptop GPU | 24BA | +| NVIDIA RTX A3000 12GB Laptop GPU | 24BB | +| NVIDIA GeForce RTX 3080 Laptop GPU | 24DC | +| NVIDIA GeForce RTX 3070 Laptop GPU | 24DD | +| NVIDIA GeForce RTX 3070 Ti Laptop GPU | 24E0 | +| NVIDIA RTX A4500 Embedded GPU | 24FA | +| NVIDIA GeForce RTX 3060 | 2503 | +| NVIDIA GeForce RTX 3060 | 2504 | +| NVIDIA GeForce RTX 3050 | 2507 | +| NVIDIA GeForce RTX 3050 OEM | 2508 | +| NVIDIA GeForce RTX 3060 Laptop GPU | 2520 | +| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 2523 | +| NVIDIA RTX A2000 | 2531 1028 151D | +| NVIDIA RTX A2000 | 2531 103C 151D | +| NVIDIA RTX A2000 | 2531 10DE 151D | +| NVIDIA RTX A2000 | 2531 17AA 151D | +| NVIDIA GeForce RTX 3060 Laptop GPU | 2560 | +| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 2563 | +| NVIDIA RTX A2000 12GB | 2571 1028 1611 | +| NVIDIA RTX A2000 12GB | 2571 103C 1611 | +| NVIDIA RTX A2000 12GB | 2571 10DE 1611 | +| NVIDIA RTX A2000 12GB | 2571 17AA 1611 | +| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A0 | +| NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 8928 | +| NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 89F9 | +| NVIDIA GeForce RTX 3060 Laptop GPU | 25A0 1D05 1196 | +| NVIDIA GeForce RTX 3050 Laptop GPU | 25A2 | +| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A2 1028 0BAF | +| NVIDIA GeForce RTX 3060 Laptop GPU | 25A2 1D05 1195 | +| NVIDIA GeForce RTX 3050 Laptop GPU | 25A5 | +| NVIDIA GeForce MX570 | 25A6 | +| NVIDIA GeForce RTX 2050 | 25A7 | +| NVIDIA GeForce RTX 2050 | 25A9 | +| NVIDIA GeForce MX570 A | 25AA | +| NVIDIA A16 | 25B6 10DE 14A9 | +| NVIDIA A2 | 25B6 10DE 157E | +| NVIDIA RTX A2000 Laptop GPU | 25B8 | +| NVIDIA RTX A1000 Laptop GPU | 25B9 | +| NVIDIA RTX A2000 8GB Laptop GPU | 25BA | +| NVIDIA RTX A500 Laptop GPU | 25BB | +| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25E0 | +| NVIDIA GeForce RTX 3050 Laptop GPU | 25E2 | +| NVIDIA GeForce RTX 3050 Laptop GPU | 25E5 | +| NVIDIA RTX A1000 Embedded GPU | 25F9 | +| NVIDIA RTX A2000 Embedded GPU | 25FA | diff --git a/kernel-open/Kbuild b/kernel-open/Kbuild index 032dd9c02..d976f60a1 100644 --- a/kernel-open/Kbuild +++ b/kernel-open/Kbuild @@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc EXTRA_CFLAGS += -I$(src) EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM -EXTRA_CFLAGS += -DNV_VERSION_STRING=\"515.43.04\" +EXTRA_CFLAGS += -DNV_VERSION_STRING=\"515.48.07\" EXTRA_CFLAGS += -Wno-unused-function @@ -94,6 +94,7 @@ EXTRA_CFLAGS += -ffreestanding ifeq ($(ARCH),arm64) EXTRA_CFLAGS += -mgeneral-regs-only -march=armv8-a + EXTRA_CFLAGS += $(call cc-option,-mno-outline-atomics,) endif ifeq ($(ARCH),x86_64) diff --git a/kernel-open/common/inc/nv-linux.h b/kernel-open/common/inc/nv-linux.h index d7f7377c3..eeba17df5 100644 --- a/kernel-open/common/inc/nv-linux.h +++ b/kernel-open/common/inc/nv-linux.h @@ -1647,23 +1647,12 @@ extern NvBool nv_ats_supported; * and any other baggage we want to carry along * */ -#define NV_MAXNUM_DISPLAY_DEVICES 8 - -typedef struct -{ - acpi_handle dev_handle; - int dev_id; -} nv_video_t; - typedef struct { nvidia_stack_t *sp; struct acpi_device *device; - - nv_video_t pNvVideo[NV_MAXNUM_DISPLAY_DEVICES]; - + struct acpi_handle *handle; int notify_handler_installed; - int default_display_mask; } nv_acpi_t; #endif diff --git a/kernel-open/common/inc/nv-proto.h b/kernel-open/common/inc/nv-proto.h index c1443e2ee..ebb2873e4 100644 --- a/kernel-open/common/inc/nv-proto.h +++ b/kernel-open/common/inc/nv-proto.h @@ -35,8 +35,6 @@ extern nvidia_module_t nv_fops; void nv_acpi_register_notifier (nv_linux_state_t *); void nv_acpi_unregister_notifier (nv_linux_state_t *); -int nv_acpi_init (void); -int nv_acpi_uninit (void); NvU8 nv_find_pci_capability (struct pci_dev *, NvU8); diff --git a/kernel-open/common/inc/nv.h b/kernel-open/common/inc/nv.h index 76fa10414..e1bfbb0d7 100644 --- a/kernel-open/common/inc/nv.h +++ b/kernel-open/common/inc/nv.h @@ -576,11 +576,9 @@ typedef enum ((nv)->iso_iommu_present) /* - * NVIDIA ACPI event IDs to be passed into the core NVIDIA - * driver for various events like display switch events, - * AC/battery events, etc.. + * NVIDIA ACPI event ID to be passed into the core NVIDIA driver for + * AC/DC event. */ -#define NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT 0x8001 #define NV_SYSTEM_ACPI_BATTERY_POWER_EVENT 0x8002 /* @@ -589,14 +587,6 @@ typedef enum #define NV_SYSTEM_GPU_ADD_EVENT 0x9001 #define NV_SYSTEM_GPU_REMOVE_EVENT 0x9002 -/* - * Status bit definitions for display switch hotkey events. - */ -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_LCD 0x01 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_CRT 0x02 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_TV 0x04 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_DFP 0x08 - /* * NVIDIA ACPI sub-event IDs (event types) to be passed into * to core NVIDIA driver for ACPI events. diff --git a/kernel-open/conftest.sh b/kernel-open/conftest.sh index 8a5f78eb9..dae07d2b4 100755 --- a/kernel-open/conftest.sh +++ b/kernel-open/conftest.sh @@ -1120,6 +1120,23 @@ compile_test() { compile_check_conftest "$CODE" "NV_MDEV_SET_IOMMU_DEVICE_PRESENT" "" "functions" ;; + mdev_parent_ops_has_open_device) + # Determine if 'mdev_parent_ops' structure has a 'open_device' + # field. + # + # Added by commit 2fd585f4ed9d ("vfio: Provide better generic support + # for open/release vfio_device_ops") in 5.15 (2021-08-05) + # + CODE=" + #include + #include + int conftest_mdev_parent_ops_has_open_device(void) { + return offsetof(struct mdev_parent_ops, open_device); + }" + + compile_check_conftest "$CODE" "NV_MDEV_PARENT_OPS_HAS_OPEN_DEVICE" "" "types" + ;; + pci_irq_vector_helpers) # # Determine if pci_alloc_irq_vectors(), pci_free_irq_vectors() @@ -1154,23 +1171,6 @@ compile_test() { compile_check_conftest "$CODE" "NV_VFIO_DEVICE_GFX_PLANE_INFO_PRESENT" "" "types" ;; - vfio_device_migration_info) - # - # determine if the 'struct vfio_device_migration_info' type is present. - # - # Proposed interface for vGPU Migration - # ("[PATCH v3 0/5] Add migration support for VFIO device ") - # https://lists.gnu.org/archive/html/qemu-devel/2019-02/msg05176.html - # Upstreamed commit a8a24f3f6e38 (vfio: UAPI for migration interface - # for device state) in v5.8 (2020-05-29) - # - CODE=" - #include - struct vfio_device_migration_info info;" - - compile_check_conftest "$CODE" "NV_VFIO_DEVICE_MIGRATION_INFO_PRESENT" "" "types" - ;; - vfio_device_migration_has_start_pfn) # # Determine if the 'vfio_device_migration_info' structure has @@ -5304,6 +5304,67 @@ compile_test() { compile_check_conftest "$CODE" "NV_ACPI_BUS_GET_DEVICE_PRESENT" "" "functions" ;; + dma_resv_add_fence) + # + # Determine if the dma_resv_add_fence() function is present. + # + # dma_resv_add_excl_fence() and dma_resv_add_shared_fence() were + # removed and replaced with dma_resv_add_fence() by commit + # 73511edf8b19 ("dma-buf: specify usage while adding fences to + # dma_resv obj v7") in linux-next, expected in v5.19-rc1. + # + CODE=" + #if defined(NV_LINUX_DMA_RESV_H_PRESENT) + #include + #endif + void conftest_dma_resv_add_fence(void) { + dma_resv_add_fence(); + }" + + compile_check_conftest "$CODE" "NV_DMA_RESV_ADD_FENCE_PRESENT" "" "functions" + ;; + + dma_resv_reserve_fences) + # + # Determine if the dma_resv_reserve_fences() function is present. + # + # dma_resv_reserve_shared() was removed and replaced with + # dma_resv_reserve_fences() by commit c8d4c18bfbc4 + # ("dma-buf/drivers: make reserving a shared slot mandatory v4") in + # linux-next, expected in v5.19-rc1. + # + CODE=" + #if defined(NV_LINUX_DMA_RESV_H_PRESENT) + #include + #endif + void conftest_dma_resv_reserve_fences(void) { + dma_resv_reserve_fences(); + }" + + compile_check_conftest "$CODE" "NV_DMA_RESV_RESERVE_FENCES_PRESENT" "" "functions" + ;; + + reservation_object_reserve_shared_has_num_fences_arg) + # + # Determine if reservation_object_reserve_shared() has 'num_fences' + # argument. + # + # reservation_object_reserve_shared() function prototype was updated + # to take 'num_fences' argument by commit ca05359f1e64 ("dma-buf: + # allow reserving more than one shared fence slot") in v4.21-rc1 + # (2018-12-14). + # + CODE=" + #include + void conftest_reservation_object_reserve_shared_has_num_fences_arg( + struct reservation_object *obj, + unsigned int num_fences) { + (void) reservation_object_reserve_shared(obj, num_fences); + }" + + compile_check_conftest "$CODE" "NV_RESERVATION_OBJECT_RESERVE_SHARED_HAS_NUM_FENCES_ARG" "" "types" + ;; + # When adding a new conftest entry, please use the correct format for # specifying the relevant upstream Linux kernel commit. # diff --git a/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h b/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h index ad8800d25..b520b260a 100644 --- a/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h +++ b/kernel-open/nvidia-drm/nvidia-dma-resv-helper.h @@ -65,11 +65,57 @@ static inline void nv_dma_resv_fini(nv_dma_resv_t *obj) #endif } +static inline void nv_dma_resv_lock(nv_dma_resv_t *obj, + struct ww_acquire_ctx *ctx) +{ +#if defined(NV_LINUX_DMA_RESV_H_PRESENT) + dma_resv_lock(obj, ctx); +#else + ww_mutex_lock(&obj->lock, ctx); +#endif +} + +static inline void nv_dma_resv_unlock(nv_dma_resv_t *obj) +{ +#if defined(NV_LINUX_DMA_RESV_H_PRESENT) + dma_resv_unlock(obj); +#else + ww_mutex_unlock(&obj->lock); +#endif +} + +static inline int nv_dma_resv_reserve_fences(nv_dma_resv_t *obj, + unsigned int num_fences, + NvBool shared) +{ +#if defined(NV_DMA_RESV_RESERVE_FENCES_PRESENT) + return dma_resv_reserve_fences(obj, num_fences); +#else + if (shared) { +#if defined(NV_LINUX_DMA_RESV_H_PRESENT) + return dma_resv_reserve_shared(obj, num_fences); +#elif defined(NV_RESERVATION_OBJECT_RESERVE_SHARED_HAS_NUM_FENCES_ARG) + return reservation_object_reserve_shared(obj, num_fences); +#else + unsigned int i; + for (i = 0; i < num_fences; i++) { + reservation_object_reserve_shared(obj); + } +#endif + } + return 0; +#endif +} + static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj, nv_dma_fence_t *fence) { #if defined(NV_LINUX_DMA_RESV_H_PRESENT) +#if defined(NV_DMA_RESV_ADD_FENCE_PRESENT) + dma_resv_add_fence(obj, fence, DMA_RESV_USAGE_WRITE); +#else dma_resv_add_excl_fence(obj, fence); +#endif #else reservation_object_add_excl_fence(obj, fence); #endif diff --git a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c b/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c index d76ecf372..c1257f37f 100644 --- a/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c +++ b/kernel-open/nvidia-drm/nvidia-drm-prime-fence.c @@ -499,9 +499,18 @@ int nv_drm_gem_fence_attach_ioctl(struct drm_device *dev, goto fence_context_create_fence_failed; } - nv_dma_resv_add_excl_fence(&nv_gem->resv, fence); + nv_dma_resv_lock(&nv_gem->resv, NULL); - ret = 0; + ret = nv_dma_resv_reserve_fences(&nv_gem->resv, 1, false); + if (ret == 0) { + nv_dma_resv_add_excl_fence(&nv_gem->resv, fence); + } else { + NV_DRM_DEV_LOG_ERR( + nv_dev, + "Failed to reserve fence. Error code: %d", ret); + } + + nv_dma_resv_unlock(&nv_gem->resv); fence_context_create_fence_failed: nv_drm_gem_object_unreference_unlocked(&nv_gem_fence_context->base); diff --git a/kernel-open/nvidia-drm/nvidia-drm.Kbuild b/kernel-open/nvidia-drm/nvidia-drm.Kbuild index 46615d66d..e1ddf454d 100644 --- a/kernel-open/nvidia-drm/nvidia-drm.Kbuild +++ b/kernel-open/nvidia-drm/nvidia-drm.Kbuild @@ -115,3 +115,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_plane_atomic_check_has_atomic_state_arg NV_CONFTEST_TYPE_COMPILE_TESTS += drm_device_has_pdev NV_CONFTEST_TYPE_COMPILE_TESTS += drm_crtc_state_has_no_vblank NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_config_has_allow_fb_modifiers +NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_add_fence +NV_CONFTEST_TYPE_COMPILE_TESTS += dma_resv_reserve_fences +NV_CONFTEST_TYPE_COMPILE_TESTS += reservation_object_reserve_shared_has_num_fences_arg diff --git a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c index 75a84712b..8440b3c0c 100644 --- a/kernel-open/nvidia-modeset/nvidia-modeset-linux.c +++ b/kernel-open/nvidia-modeset/nvidia-modeset-linux.c @@ -976,6 +976,7 @@ NvBool nvkms_allow_write_combining(void) return __rm_ops.system_info.allow_write_combining; } +#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) /************************************************************************* * Implementation of sysfs interface to control backlight *************************************************************************/ @@ -1034,11 +1035,13 @@ static const struct backlight_ops nvkms_backlight_ops = { .update_status = nvkms_update_backlight_status, .get_brightness = nvkms_get_backlight_brightness, }; +#endif /* IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) */ struct nvkms_backlight_device* nvkms_register_backlight(NvU32 gpu_id, NvU32 display_id, void *drv_priv, NvU32 current_brightness) { +#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) char name[18]; struct backlight_properties props = { .brightness = current_brightness, @@ -1093,15 +1096,20 @@ done: nvkms_free(gpu_info, NV_MAX_GPUS * sizeof(*gpu_info)); return nvkms_bd; +#else + return NULL; +#endif /* IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) */ } void nvkms_unregister_backlight(struct nvkms_backlight_device *nvkms_bd) { +#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) if (nvkms_bd->dev) { backlight_device_unregister(nvkms_bd->dev); } nvkms_free(nvkms_bd, sizeof(*nvkms_bd)); +#endif /* IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) */ } /************************************************************************* diff --git a/kernel-open/nvidia-uvm/uvm_linux.h b/kernel-open/nvidia-uvm/uvm_linux.h index 693ed5513..ddbcc67b2 100644 --- a/kernel-open/nvidia-uvm/uvm_linux.h +++ b/kernel-open/nvidia-uvm/uvm_linux.h @@ -232,7 +232,7 @@ static inline const struct cpumask *uvm_cpumask_of_node(int node) #define __GFP_NORETRY 0 #endif -#define NV_UVM_GFP_FLAGS (GFP_KERNEL | __GFP_NORETRY) +#define NV_UVM_GFP_FLAGS (GFP_KERNEL) #if !defined(NV_ADDRESS_SPACE_INIT_ONCE_PRESENT) void address_space_init_once(struct address_space *mapping); diff --git a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c index 08404b48d..f96e97918 100644 --- a/kernel-open/nvidia-uvm/uvm_maxwell_ce.c +++ b/kernel-open/nvidia-uvm/uvm_maxwell_ce.c @@ -151,7 +151,7 @@ static void maxwell_membar_after_transfer(uvm_push_t *push) // Flush on transfers only works when paired with a semaphore release. Use a // host WFI + MEMBAR. - // http://nvbugs/1709888 + // Bug 1709888 gpu->parent->host_hal->wait_for_idle(push); if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) diff --git a/kernel-open/nvidia/linux_nvswitch.c b/kernel-open/nvidia/linux_nvswitch.c index ab2fb9886..081d4474d 100644 --- a/kernel-open/nvidia/linux_nvswitch.c +++ b/kernel-open/nvidia/linux_nvswitch.c @@ -1805,12 +1805,12 @@ nvswitch_exit return; } - nvswitch_procfs_exit(); - nvswitch_ctl_exit(); pci_unregister_driver(&nvswitch_pci_driver); + nvswitch_procfs_exit(); + cdev_del(&nvswitch.cdev); unregister_chrdev_region(nvswitch.devno, NVSWITCH_MINOR_COUNT); diff --git a/kernel-open/nvidia/nv-acpi.c b/kernel-open/nvidia/nv-acpi.c index 1169c1465..6b8632a55 100644 --- a/kernel-open/nvidia/nv-acpi.c +++ b/kernel-open/nvidia/nv-acpi.c @@ -35,29 +35,13 @@ static NV_STATUS nv_acpi_extract_buffer (const union acpi_object *, void *, N static NV_STATUS nv_acpi_extract_package (const union acpi_object *, void *, NvU32, NvU32 *); static NV_STATUS nv_acpi_extract_object (const union acpi_object *, void *, NvU32, NvU32 *); -static int nv_acpi_add (struct acpi_device *); -static int nv_acpi_remove (struct acpi_device *device); -static void nv_acpi_event (acpi_handle, u32, void *); static void nv_acpi_powersource_hotplug_event(acpi_handle, u32, void *); static acpi_status nv_acpi_find_methods (acpi_handle, u32, void *, void **); static NV_STATUS nv_acpi_nvif_method (NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *); static NV_STATUS nv_acpi_wmmx_method (NvU32, NvU8 *, NvU16 *); -static const struct acpi_device_id nv_video_device_ids[] = { - { - .id = ACPI_VIDEO_HID, - .driver_data = 0, - }, - { - .id = "", - .driver_data = 0, - }, -}; - -static struct acpi_driver *nv_acpi_driver; static acpi_handle nvif_handle = NULL; -static acpi_handle nvif_parent_gpu_handle = NULL; static acpi_handle wmmx_handle = NULL; // Used for AC Power Source Hotplug Handling @@ -81,16 +65,6 @@ static NvBool battery_present = NV_FALSE; #define ACPI_VIDEO_CLASS "video" #endif -static const struct acpi_driver nv_acpi_driver_template = { - .name = "NVIDIA ACPI Video Driver", - .class = ACPI_VIDEO_CLASS, - .ids = nv_video_device_ids, - .ops = { - .add = nv_acpi_add, - .remove = nv_acpi_remove, - }, -}; - static int nv_acpi_get_device_handle(nv_state_t *nv, acpi_handle *dev_handle) { nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv); @@ -151,351 +125,6 @@ void nv_acpi_unregister_notifier(nv_linux_state_t *nvl) unregister_acpi_notifier(&nvl->acpi_nb); } -int nv_acpi_init(void) -{ - /* - * This function will register the RM with the Linux - * ACPI subsystem. - */ - int status; - nvidia_stack_t *sp = NULL; - NvU32 acpi_event_config = 0; - NV_STATUS rmStatus; - - status = nv_kmem_cache_alloc_stack(&sp); - if (status != 0) - { - return status; - } - - rmStatus = rm_read_registry_dword(sp, NULL, - NV_REG_REGISTER_FOR_ACPI_EVENTS, &acpi_event_config); - nv_kmem_cache_free_stack(sp); - - if ((rmStatus == NV_OK) && (acpi_event_config == 0)) - return 0; - - if (nv_acpi_driver != NULL) - return -EBUSY; - - rmStatus = os_alloc_mem((void **)&nv_acpi_driver, - sizeof(struct acpi_driver)); - if (rmStatus != NV_OK) - return -ENOMEM; - - memcpy((void *)nv_acpi_driver, (void *)&nv_acpi_driver_template, - sizeof(struct acpi_driver)); - - status = acpi_bus_register_driver(nv_acpi_driver); - if (status < 0) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_init: acpi_bus_register_driver() failed (%d)!\n", status); - os_free_mem(nv_acpi_driver); - nv_acpi_driver = NULL; - } - - return status; -} - -int nv_acpi_uninit(void) -{ - nvidia_stack_t *sp = NULL; - NvU32 acpi_event_config = 0; - NV_STATUS rmStatus; - int rc; - - rc = nv_kmem_cache_alloc_stack(&sp); - if (rc != 0) - { - return rc; - } - - rmStatus = rm_read_registry_dword(sp, NULL, - NV_REG_REGISTER_FOR_ACPI_EVENTS, &acpi_event_config); - nv_kmem_cache_free_stack(sp); - - if ((rmStatus == NV_OK) && (acpi_event_config == 0)) - return 0; - - if (nv_acpi_driver == NULL) - return -ENXIO; - - acpi_bus_unregister_driver(nv_acpi_driver); - os_free_mem(nv_acpi_driver); - - nv_acpi_driver = NULL; - - return 0; -} - -static int nv_acpi_add(struct acpi_device *device) -{ - /* - * This function will cause RM to initialize the things it needs for acpi interaction - * on the display device. - */ - int status = -1; - NV_STATUS rmStatus = NV_ERR_GENERIC; - nv_acpi_t *pNvAcpiObject = NULL; - union acpi_object control_argument_0 = { ACPI_TYPE_INTEGER }; - struct acpi_object_list control_argument_list = { 0, NULL }; - nvidia_stack_t *sp = NULL; - struct list_head *node, *next; - unsigned long long device_id = 0; - int device_counter = 0; - - status = nv_kmem_cache_alloc_stack(&sp); - if (status != 0) - { - return status; - } - - // allocate data structure we need - rmStatus = os_alloc_mem((void **) &pNvAcpiObject, sizeof(nv_acpi_t)); - if (rmStatus != NV_OK) - { - nv_kmem_cache_free_stack(sp); - nv_printf(NV_DBG_ERRORS, - "NVRM: nv_acpi_add: failed to allocate ACPI device management data!\n"); - return -ENOMEM; - } - - os_mem_set((void *)pNvAcpiObject, 0, sizeof(nv_acpi_t)); - - device->driver_data = pNvAcpiObject; - pNvAcpiObject->device = device; - - pNvAcpiObject->sp = sp; - - // grab handles to all the important nodes representing devices - - list_for_each_safe(node, next, &device->children) - { - struct acpi_device *dev = - list_entry(node, struct acpi_device, node); - - if (!dev) - continue; - - if (device_counter == NV_MAXNUM_DISPLAY_DEVICES) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: nv_acpi_add: Total number of devices cannot exceed %d\n", - NV_MAXNUM_DISPLAY_DEVICES); - break; - } - - status = - acpi_evaluate_integer(dev->handle, "_ADR", NULL, &device_id); - if (ACPI_FAILURE(status)) - /* Couldnt query device_id for this device */ - continue; - - device_id = (device_id & 0xffff); - - if ((device_id != 0x100) && /* Not a known CRT device-id */ - (device_id != 0x200) && /* Not a known TV device-id */ - (device_id != 0x0110) && (device_id != 0x0118) && (device_id != 0x0400) && /* Not an LCD*/ - (device_id != 0x0111) && (device_id != 0x0120) && (device_id != 0x0300)) /* Not a known DVI device-id */ - { - /* This isnt a known device Id. - Do default switching on this system. */ - pNvAcpiObject->default_display_mask = 1; - break; - } - - pNvAcpiObject->pNvVideo[device_counter].dev_id = device_id; - pNvAcpiObject->pNvVideo[device_counter].dev_handle = dev->handle; - - device_counter++; - - } - - // arg 0, bits 1:0, 0 = enable events - control_argument_0.integer.type = ACPI_TYPE_INTEGER; - control_argument_0.integer.value = 0x0; - - // listify it - control_argument_list.count = 1; - control_argument_list.pointer = &control_argument_0; - - // _DOS method takes 1 argument and returns nothing - status = acpi_evaluate_object(device->handle, "_DOS", &control_argument_list, NULL); - - if (ACPI_FAILURE(status)) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_add: failed to enable display switch events (%d)!\n", status); - } - - status = acpi_install_notify_handler(device->handle, ACPI_DEVICE_NOTIFY, - nv_acpi_event, pNvAcpiObject); - - if (ACPI_FAILURE(status)) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_add: failed to install event notification handler (%d)!\n", status); - } - else - { - try_module_get(THIS_MODULE); - pNvAcpiObject->notify_handler_installed = 1; - } - - return 0; -} - -static int nv_acpi_remove(struct acpi_device *device) -{ - /* - * This function will cause RM to relinquish control of the VGA ACPI device. - */ - acpi_status status; - union acpi_object control_argument_0 = { ACPI_TYPE_INTEGER }; - struct acpi_object_list control_argument_list = { 0, NULL }; - nv_acpi_t *pNvAcpiObject = device->driver_data; - - - pNvAcpiObject->default_display_mask = 0; - - // arg 0, bits 1:0, 1 = disable events - control_argument_0.integer.type = ACPI_TYPE_INTEGER; - control_argument_0.integer.value = 0x1; - - // listify it - control_argument_list.count = 1; - control_argument_list.pointer = &control_argument_0; - - // _DOS method takes 1 argument and returns nothing - status = acpi_evaluate_object(device->handle, "_DOS", &control_argument_list, NULL); - - if (ACPI_FAILURE(status)) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_remove: failed to disable display switch events (%d)!\n", status); - } - - if (pNvAcpiObject->notify_handler_installed) - { - // remove event notifier - status = acpi_remove_notify_handler(device->handle, ACPI_DEVICE_NOTIFY, nv_acpi_event); - } - - if (pNvAcpiObject->notify_handler_installed && - ACPI_FAILURE(status)) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_remove: failed to remove event notification handler (%d)!\n", status); - } - else - { - nv_kmem_cache_free_stack(pNvAcpiObject->sp); - os_free_mem((void *)pNvAcpiObject); - module_put(THIS_MODULE); - device->driver_data = NULL; - } - - return status; -} - -/* - * The ACPI specification defines IDs for various ACPI video - * extension events like display switch events, AC/battery - * events, docking events, etc.. - * Whenever an ACPI event is received by the corresponding - * event handler installed within the core NVIDIA driver, the - * code can verify the event ID before processing it. - */ -#define ACPI_DISPLAY_DEVICE_CHANGE_EVENT 0x80 -#define NVIF_NOTIFY_DISPLAY_DETECT 0xCB -#define NVIF_DISPLAY_DEVICE_CHANGE_EVENT NVIF_NOTIFY_DISPLAY_DETECT -static void nv_acpi_event(acpi_handle handle, u32 event_type, void *data) -{ - /* - * This function will handle acpi events from the linux kernel, used - * to detect notifications from the VGA device. - */ - nv_acpi_t *pNvAcpiObject = data; - u32 event_val = 0; - unsigned long long state; - int status = 0; - int device_counter = 0; - - if (event_type == NVIF_DISPLAY_DEVICE_CHANGE_EVENT) - { - /* We are getting NVIF events on this machine. We arent putting a very - extensive handling in-place to communicate back with SBIOS, know - the next enabled devices, and then do the switch. We just - pass a default display switch event, so that X-driver decides - the switching policy itself. */ - rm_system_event(pNvAcpiObject->sp, NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT, 0); - } - if (event_type == ACPI_DISPLAY_DEVICE_CHANGE_EVENT) - { - if (pNvAcpiObject->default_display_mask != 1) - { - while ((device_counter < NV_MAXNUM_DISPLAY_DEVICES) && - (pNvAcpiObject->pNvVideo[device_counter].dev_handle)) - { - acpi_handle dev_handle = pNvAcpiObject->pNvVideo[device_counter].dev_handle; - int dev_id = pNvAcpiObject->pNvVideo[device_counter].dev_id; - - status = acpi_evaluate_integer(dev_handle, - "_DGS", - NULL, - &state); - if (ACPI_FAILURE(status)) - { - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_event: failed to query _DGS method for display device 0x%x\n", - dev_id); - } - else if (state) - { - /* Check if the device is a CRT ...*/ - if (dev_id == 0x0100) - { - event_val |= NV_HOTKEY_STATUS_DISPLAY_ENABLE_CRT; - } - /* device-id for a TV */ - else if (dev_id == 0x0200) - { - event_val |= NV_HOTKEY_STATUS_DISPLAY_ENABLE_TV; - } - else if ((dev_id == 0x0110) || /* device id for internal LCD */ - (dev_id == 0x0118) || /* alternate ACPI ID for the - internal LCD */ - (dev_id == 0x0400)) /* ACPI spec 3.0 specified - device id for a internal LCD*/ - { - event_val |= NV_HOTKEY_STATUS_DISPLAY_ENABLE_LCD; - } - else if ((dev_id == 0x0111) || /* the set - of possible device-ids for a DFP */ - (dev_id == 0x0120) || - (dev_id == 0x0300)) /* ACPI spec 3.0 specified - device id for non-LVDS DFP */ - { - event_val |= NV_HOTKEY_STATUS_DISPLAY_ENABLE_DFP; - } - } - device_counter++; - } - } - - nv_printf(NV_DBG_INFO, - "NVRM: nv_acpi_event: Event-type 0x%x, Event-val 0x%x\n", - event_type, event_val); - - rm_system_event(pNvAcpiObject->sp, NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT, event_val); - } - - // no unsubscription or re-enable necessary. Once DOD has been set, we are go. - // once we are subscribed to ACPI events, we don't have to re-subscribe unless - // unsubscribe. -} - NV_STATUS NV_API_CALL nv_acpi_get_powersource(NvU32 *ac_plugged) { unsigned long long val; @@ -543,14 +172,14 @@ static void nv_acpi_powersource_hotplug_event(acpi_handle handle, u32 event_type */ /* Do the necessary allocations and install notifier "handler" on the device-node "device" */ -static nv_acpi_t* nv_install_notifier(struct acpi_device *device, acpi_notify_handler handler) +static nv_acpi_t* nv_install_notifier(struct acpi_handle *handle, acpi_notify_handler handler) { nvidia_stack_t *sp = NULL; nv_acpi_t *pNvAcpiObject = NULL; NV_STATUS rmStatus = NV_ERR_GENERIC; acpi_status status = -1; - if (!device) + if (!handle) return NULL; if (nv_kmem_cache_alloc_stack(&sp) != 0) @@ -564,11 +193,11 @@ static nv_acpi_t* nv_install_notifier(struct acpi_device *device, acpi_notify_ha os_mem_set((void *)pNvAcpiObject, 0, sizeof(nv_acpi_t)); - // store a device reference in our object - pNvAcpiObject->device = device; + // store a handle reference in our object + pNvAcpiObject->handle = handle; pNvAcpiObject->sp = sp; - status = acpi_install_notify_handler(device->handle, ACPI_DEVICE_NOTIFY, + status = acpi_install_notify_handler(handle, ACPI_DEVICE_NOTIFY, handler, pNvAcpiObject); if (!ACPI_FAILURE(status)) { @@ -592,7 +221,7 @@ static void nv_uninstall_notifier(nv_acpi_t *pNvAcpiObject, acpi_notify_handler if (pNvAcpiObject && pNvAcpiObject->notify_handler_installed) { - status = acpi_remove_notify_handler(pNvAcpiObject->device->handle, ACPI_DEVICE_NOTIFY, handler); + status = acpi_remove_notify_handler(pNvAcpiObject->handle, ACPI_DEVICE_NOTIFY, handler); if (ACPI_FAILURE(status)) { nv_printf(NV_DBG_INFO, @@ -616,56 +245,22 @@ static void nv_uninstall_notifier(nv_acpi_t *pNvAcpiObject, acpi_notify_handler void NV_API_CALL nv_acpi_methods_init(NvU32 *handlesPresent) { -#if defined(NV_ACPI_BUS_GET_DEVICE_PRESENT) - struct acpi_device *device = NULL; - int retVal = -1; -#endif - - if (!handlesPresent) // Caller passed us invalid pointer. return; - *handlesPresent = 0; NV_ACPI_WALK_NAMESPACE(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX, nv_acpi_find_methods, NULL, NULL); -#if defined(NV_ACPI_BUS_GET_DEVICE_PRESENT) if (nvif_handle) { *handlesPresent = NV_ACPI_NVIF_HANDLE_PRESENT; - do - { - if (!nvif_parent_gpu_handle) /* unknown error */ - break; - - retVal = acpi_bus_get_device(nvif_parent_gpu_handle, &device); - - if (ACPI_FAILURE(retVal) || !device) - break; - - if (device->driver_data) - { - nvif_parent_gpu_handle = NULL; - break; /* Someone else has already populated this device - nodes' structures. So nothing more to be done */ - } - - device->driver_data = nv_install_notifier(device, nv_acpi_event); - - - if (!device->driver_data) - nvif_parent_gpu_handle = NULL; - - } while (0); } -#endif if (wmmx_handle) *handlesPresent = *handlesPresent | NV_ACPI_WMMX_HANDLE_PRESENT; -#if defined(NV_ACPI_BUS_GET_DEVICE_PRESENT) if (psr_handle) { // Since _PSR is not a per-GPU construct we only need to register a @@ -673,15 +268,9 @@ void NV_API_CALL nv_acpi_methods_init(NvU32 *handlesPresent) // devices if (psr_nv_acpi_object == NULL) { - retVal = acpi_bus_get_device(psr_device_handle, &device); - - if (!(ACPI_FAILURE(retVal) || !device)) - { - psr_nv_acpi_object = nv_install_notifier(device, nv_acpi_powersource_hotplug_event); - } + psr_nv_acpi_object = nv_install_notifier(psr_device_handle, nv_acpi_powersource_hotplug_event); } } -#endif return; } @@ -698,7 +287,6 @@ acpi_status nv_acpi_find_methods( if (!acpi_get_handle(handle, "NVIF", &method_handle)) { nvif_handle = method_handle; - nvif_parent_gpu_handle = handle; } if (!acpi_get_handle(handle, "WMMX", &method_handle)) @@ -717,8 +305,6 @@ acpi_status nv_acpi_find_methods( void NV_API_CALL nv_acpi_methods_uninit(void) { - struct acpi_device *device = NULL; - nvif_handle = NULL; wmmx_handle = NULL; @@ -730,20 +316,6 @@ void NV_API_CALL nv_acpi_methods_uninit(void) psr_device_handle = NULL; psr_nv_acpi_object = NULL; } - - if (nvif_parent_gpu_handle == NULL) - return; - -#if defined(NV_ACPI_BUS_GET_DEVICE_PRESENT) - acpi_bus_get_device(nvif_parent_gpu_handle, &device); - - nv_uninstall_notifier(device->driver_data, nv_acpi_event); -#endif - - device->driver_data = NULL; - nvif_parent_gpu_handle = NULL; - - return; } static NV_STATUS nv_acpi_extract_integer( @@ -1763,16 +1335,6 @@ NvBool NV_API_CALL nv_acpi_is_battery_present(void) #else // NV_LINUX_ACPI_EVENTS_SUPPORTED -int nv_acpi_init(void) -{ - return 0; -} - -int nv_acpi_uninit(void) -{ - return 0; -} - void NV_API_CALL nv_acpi_methods_init(NvU32 *handlePresent) { *handlePresent = 0; diff --git a/kernel-open/nvidia/nv-dma.c b/kernel-open/nvidia/nv-dma.c index 71ac10c94..201d3b76e 100644 --- a/kernel-open/nvidia/nv-dma.c +++ b/kernel-open/nvidia/nv-dma.c @@ -25,6 +25,7 @@ #include "os-interface.h" #include "nv-linux.h" +#include "nv-reg.h" #define NV_DMA_DEV_PRINTF(debuglevel, dma_dev, format, ... ) \ nv_printf(debuglevel, "NVRM: %s: " format, \ @@ -32,6 +33,8 @@ NULL), \ ## __VA_ARGS__) +NvU32 nv_dma_remap_peer_mmio = NV_DMA_REMAP_PEER_MMIO_ENABLE; + NV_STATUS nv_create_dma_map_scatterlist (nv_dma_map_t *dma_map); void nv_destroy_dma_map_scatterlist(nv_dma_map_t *dma_map); NV_STATUS nv_map_dma_map_scatterlist (nv_dma_map_t *dma_map); @@ -766,11 +769,16 @@ NV_STATUS NV_API_CALL nv_dma_unmap_alloc return status; } -static NvBool nv_dma_is_map_resource_implemented +static NvBool nv_dma_use_map_resource ( nv_dma_device_t *dma_dev ) { + if (nv_dma_remap_peer_mmio == NV_DMA_REMAP_PEER_MMIO_DISABLE) + { + return NV_FALSE; + } + #if defined(NV_DMA_MAP_RESOURCE_PRESENT) const struct dma_map_ops *ops = get_dma_ops(dma_dev->dev); @@ -833,7 +841,7 @@ NV_STATUS NV_API_CALL nv_dma_map_peer return NV_ERR_INVALID_REQUEST; } - if (nv_dma_is_map_resource_implemented(dma_dev)) + if (nv_dma_use_map_resource(dma_dev)) { status = nv_dma_map_mmio(dma_dev, page_count, va); } @@ -858,7 +866,7 @@ void NV_API_CALL nv_dma_unmap_peer NvU64 va ) { - if (nv_dma_is_map_resource_implemented(dma_dev)) + if (nv_dma_use_map_resource(dma_dev)) { nv_dma_unmap_mmio(dma_dev, page_count, va); } @@ -873,29 +881,28 @@ NV_STATUS NV_API_CALL nv_dma_map_mmio ) { #if defined(NV_DMA_MAP_RESOURCE_PRESENT) - NvU64 mmio_addr; - BUG_ON(!va); - mmio_addr = *va; - - *va = dma_map_resource(dma_dev->dev, mmio_addr, page_count * PAGE_SIZE, - DMA_BIDIRECTIONAL, 0); - if (dma_mapping_error(dma_dev->dev, *va)) + if (nv_dma_use_map_resource(dma_dev)) { - NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev, - "Failed to DMA map MMIO range [0x%llx-0x%llx]\n", - mmio_addr, mmio_addr + page_count * PAGE_SIZE - 1); - return NV_ERR_OPERATING_SYSTEM; + NvU64 mmio_addr = *va; + *va = dma_map_resource(dma_dev->dev, mmio_addr, page_count * PAGE_SIZE, + DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(dma_dev->dev, *va)) + { + NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev, + "Failed to DMA map MMIO range [0x%llx-0x%llx]\n", + mmio_addr, mmio_addr + page_count * PAGE_SIZE - 1); + return NV_ERR_OPERATING_SYSTEM; + } } - - /* - * The default implementation passes through the source address - * without failing. Adjust it using the DMA start address to keep RM's - * validation schemes happy. - */ - if (!nv_dma_is_map_resource_implemented(dma_dev)) + else { + /* + * If dma_map_resource is not available, pass through the source address + * without failing. Further, adjust it using the DMA start address to + * keep RM's validation schemes happy. + */ *va = *va + dma_dev->addressable_range.start; } @@ -915,15 +922,13 @@ void NV_API_CALL nv_dma_unmap_mmio ) { #if defined(NV_DMA_MAP_RESOURCE_PRESENT) - if (!nv_dma_is_map_resource_implemented(dma_dev)) - { - va = va - dma_dev->addressable_range.start; - } - nv_dma_nvlink_addr_decompress(dma_dev, &va, page_count, NV_TRUE); - dma_unmap_resource(dma_dev->dev, va, page_count * PAGE_SIZE, - DMA_BIDIRECTIONAL, 0); + if (nv_dma_use_map_resource(dma_dev)) + { + dma_unmap_resource(dma_dev->dev, va, page_count * PAGE_SIZE, + DMA_BIDIRECTIONAL, 0); + } #endif } diff --git a/kernel-open/nvidia/nv-dmabuf.c b/kernel-open/nvidia/nv-dmabuf.c index 1d2073b8c..f4f4d195b 100644 --- a/kernel-open/nvidia/nv-dmabuf.c +++ b/kernel-open/nvidia/nv-dmabuf.c @@ -48,6 +48,7 @@ typedef struct nv_dma_buf_file_private nv_dma_buf_mem_handle_t *handles; NvU64 bar1_va_ref_count; void *mig_info; + NvBool can_mmap; } nv_dma_buf_file_private_t; static void @@ -562,6 +563,8 @@ nv_dma_buf_mmap( struct vm_area_struct *vma ) { + // TODO: Check can_mmap flag + return -ENOTSUPP; } @@ -674,6 +677,7 @@ nv_dma_buf_create( priv->total_objects = params->totalObjects; priv->total_size = params->totalSize; priv->nv = nv; + priv->can_mmap = NV_FALSE; rc = nv_kmem_cache_alloc_stack(&sp); if (rc != 0) @@ -792,6 +796,15 @@ nv_dma_buf_reuse( return NV_ERR_OPERATING_SYSTEM; } + + + + + + + + + priv = buf->priv; if (priv == NULL) diff --git a/kernel-open/nvidia/nv-reg.h b/kernel-open/nvidia/nv-reg.h index 43cebbb1c..1e67890f1 100644 --- a/kernel-open/nvidia/nv-reg.h +++ b/kernel-open/nvidia/nv-reg.h @@ -301,23 +301,6 @@ #define __NV_ENABLE_MSI EnableMSI #define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI) -/* - * Option: RegisterForACPIEvents - * - * Description: - * - * When this option is enabled, the NVIDIA driver will register with the - * ACPI subsystem to receive notification of ACPI events. - * - * Possible values: - * - * 1 - register for ACPI events (default) - * 0 - do not register for ACPI events - */ - -#define __NV_REGISTER_FOR_ACPI_EVENTS RegisterForACPIEvents -#define NV_REG_REGISTER_FOR_ACPI_EVENTS NV_REG_STRING(__NV_REGISTER_FOR_ACPI_EVENTS) - /* * Option: EnablePCIeGen3 * @@ -819,6 +802,30 @@ #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE +/* + * Option: NVreg_DmaRemapPeerMmio + * + * Description: + * + * When this option is enabled, the NVIDIA driver will use device driver + * APIs provided by the Linux kernel for DMA-remapping part of a device's + * MMIO region to another device, creating e.g., IOMMU mappings as necessary. + * When this option is disabled, the NVIDIA driver will instead only apply a + * fixed offset, which may be zero, to CPU physical addresses to produce the + * DMA address for the peer's MMIO region, and no IOMMU mappings will be + * created. + * + * This option only affects peer MMIO DMA mappings, and not system memory + * mappings. + * + * Possible Values: + * 0 = disable dynamic DMA remapping of peer MMIO regions + * 1 = enable dynamic DMA remapping of peer MMIO regions (default) + */ +#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio +#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO) +#define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 +#define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) @@ -834,7 +841,6 @@ NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0); NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666); NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1); NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); -NV_DEFINE_REG_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS, 1); NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0); NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1); NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT); @@ -871,6 +877,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); +NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); /* *----------------registry database definition---------------------- @@ -893,7 +900,6 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI), - NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE), @@ -918,6 +924,7 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO), {NULL, NULL} }; diff --git a/kernel-open/nvidia/nv.c b/kernel-open/nvidia/nv.c index dbcd8c04f..0b06d0c73 100644 --- a/kernel-open/nvidia/nv.c +++ b/kernel-open/nvidia/nv.c @@ -114,6 +114,7 @@ nv_linux_state_t *nv_linux_devices; * And one for the control device */ nv_linux_state_t nv_ctl_device = { { 0 } }; +extern NvU32 nv_dma_remap_peer_mmio; nv_kthread_q_t nv_kthread_q; nv_kthread_q_t nv_deferred_close_kthread_q; @@ -571,6 +572,12 @@ nv_registry_keys_init(nv_stack_t *sp) WARN_ON(status != NV_OK); } } + + status = rm_read_registry_dword(sp, nv, NV_DMA_REMAP_PEER_MMIO, &data); + if (status == NV_OK) + { + nv_dma_remap_peer_mmio = data; + } } static void __init @@ -2660,7 +2667,6 @@ nvidia_ctl_open( nv_linux_state_t *nvl = &nv_ctl_device; nv_state_t *nv = NV_STATE_PTR(nvl); nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); - static int count = 0; nv_printf(NV_DBG_INFO, "NVRM: nvidia_ctl_open\n"); @@ -2672,13 +2678,6 @@ nvidia_ctl_open( if (NV_ATOMIC_READ(nvl->usage_count) == 0) { nv->flags |= (NV_FLAG_OPEN | NV_FLAG_CONTROL); - - if ((nv_acpi_init() < 0) && - (count++ < NV_MAX_RECURRING_WARNING_MESSAGES)) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: failed to register with the ACPI subsystem!\n"); - } } NV_ATOMIC_INC(nvl->usage_count); @@ -2702,7 +2701,6 @@ nvidia_ctl_close( nv_state_t *nv = NV_STATE_PTR(nvl); nv_linux_file_private_t *nvlfp = NV_GET_LINUX_FILE_PRIVATE(file); nvidia_stack_t *sp = nvlfp->sp; - static int count = 0; unsigned int i; nv_printf(NV_DBG_INFO, "NVRM: nvidia_ctl_close\n"); @@ -2711,13 +2709,6 @@ nvidia_ctl_close( if (NV_ATOMIC_DEC_AND_TEST(nvl->usage_count)) { nv->flags &= ~NV_FLAG_OPEN; - - if ((nv_acpi_uninit() < 0) && - (count++ < NV_MAX_RECURRING_WARNING_MESSAGES)) - { - nv_printf(NV_DBG_ERRORS, - "NVRM: failed to unregister from the ACPI subsystem!\n"); - } } up(&nvl->ldata_lock); diff --git a/src/common/displayport/inc/dp_connectorimpl.h b/src/common/displayport/inc/dp_connectorimpl.h index b649e0d1f..0504a551e 100644 --- a/src/common/displayport/inc/dp_connectorimpl.h +++ b/src/common/displayport/inc/dp_connectorimpl.h @@ -320,6 +320,9 @@ namespace DisplayPort // bool bDscMstEnablePassThrough; + // Reduce number of 2H1OR LTs which fixes bug 3534707 + bool bDscOptimizeLTBug3534707; + // // Synaptics branch device doesn't support Virtual Peer Devices so DSC // capability of downstream device should be decided based on device's own @@ -505,6 +508,7 @@ namespace DisplayPort void populateDscGpuCaps(DSC_INFO* dscInfo); void populateForcedDscParams(DSC_INFO* dscInfo, DSC_INFO::FORCED_DSC_PARAMS* forcedParams); void populateDscSinkCaps(DSC_INFO* dscInfo, DeviceImpl * dev); + void populateDscBranchCaps(DSC_INFO* dscInfo, DeviceImpl * dev); void populateDscModesetInfo(MODESET_INFO * pModesetInfo, const DpModesetParams * pModesetParams); bool train(const LinkConfiguration & lConfig, bool force, LinkTrainingType trainType = NORMAL_LINK_TRAINING); diff --git a/src/common/displayport/inc/dp_deviceimpl.h b/src/common/displayport/inc/dp_deviceimpl.h index 19c2ac0c7..b3ab32d24 100644 --- a/src/common/displayport/inc/dp_deviceimpl.h +++ b/src/common/displayport/inc/dp_deviceimpl.h @@ -425,7 +425,9 @@ namespace DisplayPort NvBool isDSCPossible(); bool isFECSupported(); bool readAndParseDSCCaps(); + bool readAndParseBranchSpecificDSCCaps(); bool parseDscCaps(const NvU8 *buffer, NvU32 bufferSize); + bool parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize); bool setDscEnable(bool enable); bool getDscEnable(bool *pEnable); unsigned getDscVersionMajor(); diff --git a/src/common/displayport/inc/dp_groupimpl.h b/src/common/displayport/inc/dp_groupimpl.h index a4680aa1c..aa9b021b4 100644 --- a/src/common/displayport/inc/dp_groupimpl.h +++ b/src/common/displayport/inc/dp_groupimpl.h @@ -53,6 +53,8 @@ namespace DisplayPort bool bWaitForDeAllocACT; bool bDeferredPayloadAlloc; ModesetInfo lastModesetInfo; + DSC_MODE dscModeRequest; // DSC mode requested during NAB + DSC_MODE dscModeActive; // DSC mode currently active, set in NAE DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID singleHeadMultiStreamID; DP_SINGLE_HEAD_MULTI_STREAM_MODE singleHeadMultiStreamMode; DP_COLORFORMAT colorFormat; @@ -76,6 +78,8 @@ namespace DisplayPort hdcpEnabled(false), hdcpPreviousStatus(false), bWaitForDeAllocACT(false), + dscModeRequest(DSC_MODE_NONE), + dscModeActive(DSC_MODE_NONE), singleHeadMultiStreamID(DP_SINGLE_HEAD_MULTI_STREAM_PIPELINE_ID_PRIMARY), singleHeadMultiStreamMode(DP_SINGLE_HEAD_MULTI_STREAM_MODE_NONE), bIsCurrentModesetGroup(false), diff --git a/src/common/displayport/inc/dp_messages.h b/src/common/displayport/inc/dp_messages.h index 04d320421..5cc740428 100644 --- a/src/common/displayport/inc/dp_messages.h +++ b/src/common/displayport/inc/dp_messages.h @@ -116,6 +116,8 @@ namespace DisplayPort bool isBeingDestroyed; bool isPaused; + bool bNoReplyTimerForBusyWaiting; + List messageReceivers; List notYetSentDownRequest; // Down Messages yet to be processed List notYetSentUpReply; // Up Reply Messages yet to be processed @@ -153,6 +155,13 @@ namespace DisplayPort mergerDownReply.mailboxInterrupt(); } + void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase) + { + DP_ASSERT(dpRegkeyDatabase.bInitialized && + "All regkeys are invalid because dpRegkeyDatabase is not initialized!"); + bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting; + } + MessageManager(DPCDHAL * hal, Timer * timer) : timer(timer), hal(hal), splitterDownRequest(hal, timer), @@ -236,6 +245,7 @@ namespace DisplayPort MessageManager * parent; bool transmitReply; bool bTransmitted; + bool bBusyWaiting; unsigned requestIdentifier; unsigned messagePriority; unsigned sinkPort; @@ -261,6 +271,7 @@ namespace DisplayPort parent(0), transmitReply(false), bTransmitted(false), + bBusyWaiting(false), requestIdentifier(requestIdentifier), messagePriority(messagePriority), sinkPort(0xFF) diff --git a/src/common/displayport/inc/dp_regkeydatabase.h b/src/common/displayport/inc/dp_regkeydatabase.h index 5e4664460..b91507dd0 100644 --- a/src/common/displayport/inc/dp_regkeydatabase.h +++ b/src/common/displayport/inc/dp_regkeydatabase.h @@ -65,11 +65,13 @@ // #define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315" -// // Enable DSC Pass through support in MST mode. -// #define NV_DP_DSC_MST_ENABLE_PASS_THROUGH "DP_DSC_MST_ENABLE_PASS_THROUGH" +// Regkey to reduce number of 2H1OR LTs which fixes bug 3534707 +#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707 "DP_DSC_OPTIMIZE_LT_BUG_3534707" + +#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING" // // Data Base used to store all the regkey values. // The actual data base is declared statically in dp_evoadapter.cpp. @@ -102,6 +104,8 @@ struct DP_REGKEY_DATABASE bool bBypassEDPRevCheck; bool bDscMstCapBug3143315; bool bDscMstEnablePassThrough; + bool bDscOptimizeLTBug3534707; + bool bNoReplyTimerForBusyWaiting; }; #endif //INCLUDED_DP_REGKEYDATABASE_H diff --git a/src/common/displayport/src/dp_connectorimpl.cpp b/src/common/displayport/src/dp_connectorimpl.cpp index dbeb2b453..9bc2d423e 100644 --- a/src/common/displayport/src/dp_connectorimpl.cpp +++ b/src/common/displayport/src/dp_connectorimpl.cpp @@ -189,6 +189,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled; this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315; this->bDscMstEnablePassThrough = dpRegkeyDatabase.bDscMstEnablePassThrough; + this->bDscOptimizeLTBug3534707 = dpRegkeyDatabase.bDscOptimizeLTBug3534707; } void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled) @@ -630,6 +631,12 @@ create: { // Read and parse DSC caps only if panel supports DSC newDev->readAndParseDSCCaps(); + + // Read and Parse Branch Specific DSC Caps + if (!newDev->isVideoSink() && !newDev->isAudioSink()) + { + newDev->readAndParseBranchSpecificDSCCaps(); + } } // Decide if DSC stream can be sent to new device @@ -655,13 +662,13 @@ create: if (this->bDscMstEnablePassThrough) { // - // Check the device's own and its parent's DSC capability. - // - Sink device will do DSC cecompression when + // Check the device's own and its parent's DSC capability. + // - Sink device will do DSC cecompression when // 1. Sink device is capable of DSC decompression and parent // supports DSC pass through. // - // - Sink device's parent will do DSC decompression - // 1. If sink device supports DSC decompression but it's parent does not support + // - Sink device's parent will do DSC decompression + // 1. If sink device supports DSC decompression but it's parent does not support // DSC Pass through, but supports DSC decompression. // 2. If the device does not support DSC decompression, but parent supports it. // @@ -672,7 +679,7 @@ create: if (newDev->parent->isDSCPassThroughSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a DSC Pass through capable branch // newDev->devDoingDscDecompression = newDev; @@ -681,12 +688,12 @@ create: else if (newDev->parent->isDSCSupported()) { // - // This condition takes care of DSC capable sink devices + // This condition takes care of DSC capable sink devices // connected behind a branch device that is not capable // of DSC pass through but can do DSC decompression. // newDev->bDSCPossible = true; - newDev->devDoingDscDecompression = newDev->parent; + newDev->devDoingDscDecompression = newDev->parent; } } else @@ -695,11 +702,11 @@ create: newDev->devDoingDscDecompression = newDev; newDev->bDSCPossible = true; } - } + } else if (newDev->parent && newDev->parent->isDSCSupported()) { // - // This condition takes care of sink devices not capable of DSC + // This condition takes care of sink devices not capable of DSC // but parent is capable of DSC decompression. // newDev->bDSCPossible = true; @@ -709,7 +716,7 @@ create: else { // - // Revert to old code if DSC Pass through support is not requested. + // Revert to old code if DSC Pass through support is not requested. // This code will be deleted once DSC Pass through support will be enabled // by default which will be done when 2Head1OR MST (GR-133) will be in production. // @@ -1726,6 +1733,15 @@ void ConnectorImpl::populateDscGpuCaps(DSC_INFO* dscInfo) dscInfo->gpuCaps.lineBufferBitDepth = lineBufferBitDepth; } +void ConnectorImpl::populateDscBranchCaps(DSC_INFO* dscInfo, DeviceImpl * dev) +{ + dscInfo->branchCaps.overallThroughputMode0 = dev->dscCaps.branchDSCOverallThroughputMode0; + dscInfo->branchCaps.overallThroughputMode1 = dev->dscCaps.branchDSCOverallThroughputMode1; + dscInfo->branchCaps.maxLineBufferWidth = dev->dscCaps.branchDSCMaximumLineBufferWidth; + + return; +} + void ConnectorImpl::populateDscSinkCaps(DSC_INFO* dscInfo, DeviceImpl * dev) { // Early return if dscInfo or dev is NULL @@ -1846,6 +1862,12 @@ void ConnectorImpl::populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INF // Sink DSC capabilities populateDscSinkCaps(dscInfo, dev); + // Branch Specific DSC Capabilities + if (!dev->isVideoSink() && !dev->isAudioSink()) + { + populateDscBranchCaps(dscInfo, dev); + } + // GPU DSC capabilities populateDscGpuCaps(dscInfo); @@ -2621,11 +2643,6 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr } } - if (bEnableDsc) - { - DP_LOG(("DPCONN> DSC Mode = %s", (modesetParams.modesetInfo.mode == DSC_SINGLE) ? "SINGLE" : "DUAL")); - } - for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev)) { Address::StringBuffer buffer; @@ -2641,6 +2658,12 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr GroupImpl* targetImpl = (GroupImpl*)target; targetImpl->bIsCurrentModesetGroup = true; + if (bEnableDsc) + { + DP_LOG(("DPCONN> DSC Mode = %s", (modesetParams.modesetInfo.mode == DSC_SINGLE) ? "SINGLE" : "DUAL")); + targetImpl->dscModeRequest = modesetParams.modesetInfo.mode; + } + DP_ASSERT(!(targetImpl->isHeadAttached() && targetImpl->bIsHeadShutdownNeeded) && "Head should have been shut down but it is still active!"); targetImpl->headInFirmware = false; @@ -2788,6 +2811,10 @@ void ConnectorImpl::notifyAttachEnd(bool modesetCancelled) currentModesetDeviceGroup->setHeadAttached(false); } + // set dscModeActive to what was requested in NAB and clear dscModeRequest + currentModesetDeviceGroup->dscModeActive = currentModesetDeviceGroup->dscModeRequest; + currentModesetDeviceGroup->dscModeRequest = DSC_MODE_NONE; + currentModesetDeviceGroup->setHeadAttached(true); RmDfpCache dfpCache = {0}; dfpCache.updMask = 0; @@ -2934,6 +2961,7 @@ void ConnectorImpl::notifyDetachEnd(bool bKeepOdAlive) dpMemZero(¤tModesetDeviceGroup->lastModesetInfo, sizeof(ModesetInfo)); currentModesetDeviceGroup->setHeadAttached(false); currentModesetDeviceGroup->headInFirmware = false; + currentModesetDeviceGroup->dscModeActive = DSC_MODE_NONE; // Mark head as disconnected bNoLtDoneAfterHeadDetach = true; @@ -3980,18 +4008,36 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) GroupImpl * groupAttached = 0; for (ListElement * e = activeGroups.begin(); e != activeGroups.end(); e = e->next) { - DP_ASSERT(bIsUefiSystem || (!groupAttached && "Multiple attached heads")); + DP_ASSERT(bIsUefiSystem); groupAttached = (GroupImpl * )e; - if ((groupAttached->lastModesetInfo.mode == DSC_DUAL) && groupAttached->bIsCurrentModesetGroup) + if (bDscOptimizeLTBug3534707) { - // - // If current modeset group requires 2Head1OR mode, we should retrain link. - // For SST, there will be only one group per connector. - // For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL. - // - bTwoHeadOneOrLinkRetrain = true; - break; + if ((groupAttached->dscModeRequest == DSC_DUAL) && (groupAttached->dscModeActive != DSC_DUAL)) + { + // + // If current modeset group requires 2Head1OR and + // - group is not active yet (first modeset on the group) + // - group is active but not in 2Head1OR mode (last modeset on the group did not require 2Head1OR) + // then re-train the link + // This is because for 2Head1OR mode, we need to set some LT parametes for slave SOR after + // successful LT on primary SOR without which 2Head1OR modeset will lead to HW hang. + // + bTwoHeadOneOrLinkRetrain = true; + break; + } + } + else + { + if (groupAttached->lastModesetInfo.mode == DSC_DUAL && groupAttached->bIsCurrentModesetGroup) + { + // + // If current modeset group requires 2Head1OR mode, we should retrain link. + // For SST, there will be only one group per connector. + // For MST, we need to re-run LT in case the current modeset group requires DSC_DUAL. + bTwoHeadOneOrLinkRetrain = true; + break; + } } } @@ -4077,10 +4123,10 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) { // // Check if we are already trained to the desired link config? - // Even if we are, we need to redo LT if FEC is enabled or DSC mode is DSC_DUAL - // since if current modeset requires 2H1OR, LT done during assessLink will not - // have 2H1Or flag set or if last modeset required DSC but not 2H1OR, still 2H1Or - // flag will not be set and modeset will lead to HW hang. + // Make sure requested FEC state matches with the current FEC state of link. + // If 2Head1OR mode is requested, retrain if group is not active or + // last modeset on active group was not in 2Head1OR mode. + // bTwoHeadOneOrLinkRetrain tracks this requirement. // // @@ -4093,7 +4139,8 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) if ((activeLinkConfig == lowestSelected) && (!isLinkInD3()) && (!isLinkLost()) && - !(this->bFECEnable) && + ((!bDscOptimizeLTBug3534707 && !this->bFECEnable) || + (bDscOptimizeLTBug3534707 && (this->bFECEnable == activeLinkConfig.bEnableFEC))) && !bTwoHeadOneOrLinkRetrain) { if (bSkipRedundantLt || main->isInternalPanelDynamicMuxCapable()) @@ -4209,11 +4256,9 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig) // // Make sure link is physically active and healthy, otherwise re-train. - // We need to retrain if the link is in 2Head1OR MST mode. For example, - // if we plug in a 2Head1OR panel to an active link that is already driving - // a MST panel in DSC mode, RM will assign a secondary OR to the 2Head1OR panel. - // But since there is no change required in linkConfig DPlib will skip - // LT, resutling in not adding secondary OR to LT; this will lead to HW hang. + // Make sure requested FEC state matches with the current FEC state of link. + // If 2Head1OR mode is requested, retrain if group is not active or last modeset on active group + // was not in 2Head1OR mode. bTwoHeadOneOrLinkRetrain tracks this requirement. // bRetrainToEnsureLinkStatus = (isLinkActive() && isLinkInD3()) || isLinkLost() || @@ -5660,7 +5705,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) if (hal->getSupportsMultistream() && main->hasMultistream()) { bool bDeleteFirmwareVC = false; - + const DP_REGKEY_DATABASE& dpRegkeyDatabase = main->getRegkeyDatabase(); DP_LOG(("DP> Multistream panel detected, building message manager")); // @@ -5669,6 +5714,7 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected) // messageManager = new MessageManager(hal, timer); messageManager->registerReceiver(&ResStatus); + messageManager->applyRegkeyOverrides(dpRegkeyDatabase); // // Create a discovery manager to initiate detection diff --git a/src/common/displayport/src/dp_deviceimpl.cpp b/src/common/displayport/src/dp_deviceimpl.cpp index 21c97c637..7285a92bf 100644 --- a/src/common/displayport/src/dp_deviceimpl.cpp +++ b/src/common/displayport/src/dp_deviceimpl.cpp @@ -1687,6 +1687,50 @@ bool DeviceImpl::parseDscCaps(const NvU8 *buffer, NvU32 bufferSize) return true; } +bool DeviceImpl::parseBranchSpecificDscCaps(const NvU8 *buffer, NvU32 bufferSize) +{ + if (bufferSize < 3) + { + DP_LOG((" Branch DSC caps buffer must be greater than or equal to 3")); + return false; + } + + dscCaps.branchDSCOverallThroughputMode0 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, _VALUE, buffer[0x0]); + if (dscCaps.branchDSCOverallThroughputMode0 == 1) + { + dscCaps.branchDSCOverallThroughputMode0 = 680; + } + else if (dscCaps.branchDSCOverallThroughputMode0 >= 2) + { + dscCaps.branchDSCOverallThroughputMode0 = 600 + dscCaps.branchDSCOverallThroughputMode0 * 50; + } + + dscCaps.branchDSCOverallThroughputMode1 = DRF_VAL(_DPCD20, _BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1, _VALUE, buffer[0x1]); + if (dscCaps.branchDSCOverallThroughputMode1 == 1) + { + dscCaps.branchDSCOverallThroughputMode1 = 680; + } + else if (dscCaps.branchDSCOverallThroughputMode1 >= 2) + { + dscCaps.branchDSCOverallThroughputMode1 = 600 + dscCaps.branchDSCOverallThroughputMode1 * 50; + } + + dscCaps.branchDSCMaximumLineBufferWidth = DRF_VAL(_DPCD20, _BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH, _VALUE, buffer[0x2]); + if (dscCaps.branchDSCMaximumLineBufferWidth != 0) + { + if (dscCaps.branchDSCMaximumLineBufferWidth >= 16) + { + dscCaps.branchDSCMaximumLineBufferWidth = dscCaps.branchDSCMaximumLineBufferWidth * 320; + } + else + { + dscCaps.branchDSCMaximumLineBufferWidth = 0; + DP_LOG(("Value of branch DSC maximum line buffer width is invalid, so setting it to 0.")); + } + } + return true; +} + bool DeviceImpl::readAndParseDSCCaps() { // Allocate a buffer of 16 bytes to read DSC caps @@ -1703,6 +1747,21 @@ bool DeviceImpl::readAndParseDSCCaps() return parseDscCaps(&rawDscCaps[0], sizeof(rawDscCaps)); } +bool DeviceImpl::readAndParseBranchSpecificDSCCaps() +{ + unsigned sizeCompleted = 0; + unsigned nakReason = NakUndefined; + NvU8 rawBranchSpecificDscCaps[3]; + + if(AuxBus::success != this->getDpcdData(NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0, + &rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps), &sizeCompleted, &nakReason)) + { + return false; + } + + return parseBranchSpecificDscCaps(&rawBranchSpecificDscCaps[0], sizeof(rawBranchSpecificDscCaps)); +} + bool DeviceImpl::getDscEnable(bool *pEnable) { AuxBus::status status = AuxBus::success; diff --git a/src/common/displayport/src/dp_evoadapter.cpp b/src/common/displayport/src/dp_evoadapter.cpp index 1a8e1e645..03ea09d6f 100644 --- a/src/common/displayport/src/dp_evoadapter.cpp +++ b/src/common/displayport/src/dp_evoadapter.cpp @@ -94,7 +94,9 @@ const struct {NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL}, {NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL}, {NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL}, - {NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL} + {NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL}, + {NV_DP_DSC_OPTIMIZE_LT_BUG_3534707, &dpRegkeyDatabase.bDscOptimizeLTBug3534707, DP_REG_VAL_BOOL}, + {NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL} }; EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) : diff --git a/src/common/displayport/src/dp_messages.cpp b/src/common/displayport/src/dp_messages.cpp index 0baaf364c..a5671731e 100644 --- a/src/common/displayport/src/dp_messages.cpp +++ b/src/common/displayport/src/dp_messages.cpp @@ -63,6 +63,11 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData) DP_USED(sb); NvU64 startTime, elapsedTime; + + if (bNoReplyTimerForBusyWaiting) + { + message->bBusyWaiting = true; + } post(message, &completion); startTime = timer->getTimeUs(); do @@ -152,14 +157,13 @@ void MessageManager::Message::splitterTransmitted(OutgoingTransactionManager * f if (from == &parent->splitterDownRequest) { - // - // Start the countdown timer for the reply - // - parent->timer->queueCallback(this, "SPLI", DPCD_MESSAGE_REPLY_TIMEOUT); - - // + // Client will busy-waiting for the message to complete, we don't need the countdown timer. + if (!bBusyWaiting) + { + // Start the countdown timer for the reply + parent->timer->queueCallback(this, "SPLI", DPCD_MESSAGE_REPLY_TIMEOUT); + } // Tell the message manager he may begin sending the next message - // parent->transmitAwaitingDownRequests(); } else // UpReply diff --git a/src/common/inc/displayport/displayport.h b/src/common/inc/displayport/displayport.h index 1f9f8d061..de37a1cd9 100644 --- a/src/common/inc/displayport/displayport.h +++ b/src/common/inc/displayport/displayport.h @@ -262,6 +262,10 @@ typedef struct DscCaps unsigned dscPeakThroughputMode1; unsigned dscMaxSliceWidth; + unsigned branchDSCOverallThroughputMode0; + unsigned branchDSCOverallThroughputMode1; + unsigned branchDSCMaximumLineBufferWidth; + BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement; } DscCaps; diff --git a/src/common/inc/displayport/dpcd.h b/src/common/inc/displayport/dpcd.h index cb26349df..0e3909535 100644 --- a/src/common/inc/displayport/dpcd.h +++ b/src/common/inc/displayport/dpcd.h @@ -1083,6 +1083,7 @@ number of Downstream ports will be limited to 32. #define NV_DPCD_EDP_DISPLAY_CTL_COLOR_ENGINE_EN_DISABLED (0x00000000) /* RWXUV */ #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL 5:4 /* RWXUF */ #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS (0x00000000) /* RWXUV */ +#define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_AUTONOMOUS_1 (0x00000001) /* RWXUV */ #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_DISABLE (0x00000002) /* RWXUV */ #define NV_DPCD_EDP_DISPLAY_CTL_OVERDRIVE_CTL_ENABLE (0x00000003) /* RWXUV */ #define NV_DPCD_EDP_DISPLAY_CTL_VBLANK_BKLGHT_UPDATE_EN 7:7 /* RWXUF */ diff --git a/src/common/inc/displayport/dpcd20.h b/src/common/inc/displayport/dpcd20.h index 10e759f88..aac81fd37 100644 --- a/src/common/inc/displayport/dpcd20.h +++ b/src/common/inc/displayport/dpcd20.h @@ -44,3 +44,14 @@ #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_NO (0x00000000) #define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE_YES (0x00000001) + +/// BRANCH SPECIFIC DSC CAPS +#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0 (0x000000A0) +#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_0_VALUE 7:0 + +#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1 (0x000000A1) +#define NV_DPCD20_BRANCH_DSC_OVERALL_THROUGHPUT_MODE_1_VALUE 7:0 + +#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH (0x000000A2) +#define NV_DPCD20_BRANCH_DSC_MAXIMUM_LINE_BUFFER_WIDTH_VALUE 7:0 + diff --git a/src/common/inc/nvBldVer.h b/src/common/inc/nvBldVer.h index 0979ac51b..4ba73475e 100644 --- a/src/common/inc/nvBldVer.h +++ b/src/common/inc/nvBldVer.h @@ -36,25 +36,26 @@ // and then checked back in. You cannot make changes to these sections without // corresponding changes to the buildmeister script #ifndef NV_BUILD_BRANCH - #define NV_BUILD_BRANCH r515_95 + #define NV_BUILD_BRANCH r516_10 #endif #ifndef NV_PUBLIC_BRANCH - #define NV_PUBLIC_BRANCH r515_95 + #define NV_PUBLIC_BRANCH r516_10 #endif #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) -#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_95-155" -#define NV_BUILD_CHANGELIST_NUM (31261195) +#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r516_10-205" +#define NV_BUILD_CHANGELIST_NUM (31396299) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_95-155" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31261195) +#define NV_BUILD_NAME "rel/gpu_drv/r515/r516_10-205" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31396299) #else /* Windows builds */ -#define NV_BUILD_BRANCH_VERSION "r515_95-3" -#define NV_BUILD_CHANGELIST_NUM (31249857) +#define NV_BUILD_BRANCH_VERSION "r516_10-10" +#define NV_BUILD_CHANGELIST_NUM (31385161) #define NV_BUILD_TYPE "Official" -#define NV_BUILD_NAME "516.01" -#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31249857) +#define NV_BUILD_NAME "516.26" +#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31385161) +#define NV_BUILD_BRANCH_BASE_VERSION R515 #endif // End buildmeister python edited section diff --git a/src/common/inc/nvPNPVendorIds.h b/src/common/inc/nvPNPVendorIds.h index 97cf29771..357db5b18 100644 --- a/src/common/inc/nvPNPVendorIds.h +++ b/src/common/inc/nvPNPVendorIds.h @@ -29,7 +29,7 @@ * type const char*. * * References: - * http://www.uefi.org/pnp_id_list + * https://uefi.org/pnp_id_list * */ diff --git a/src/common/inc/nvSha1.h b/src/common/inc/nvSha1.h index 6c9a010c6..4e3e4974a 100644 --- a/src/common/inc/nvSha1.h +++ b/src/common/inc/nvSha1.h @@ -26,7 +26,7 @@ * byte array, using the Secure Hashing Algorithm 1 (SHA-1) as defined * in FIPS PUB 180-1 published April 17, 1995: * - * http://www.itl.nist.gov/fipspubs/fip180-1.htm + * https://www.itl.nist.gov/fipspubs/fip180-1.htm * * Some common test cases (see Appendices A and B of the above document): * diff --git a/src/common/inc/nvUnixVersion.h b/src/common/inc/nvUnixVersion.h index 46f1cf50c..06c823e2b 100644 --- a/src/common/inc/nvUnixVersion.h +++ b/src/common/inc/nvUnixVersion.h @@ -4,7 +4,7 @@ #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \ (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1) -#define NV_VERSION_STRING "515.43.04" +#define NV_VERSION_STRING "515.48.07" #else diff --git a/src/common/inc/swref/published/ampere/ga100/dev_fuse.h b/src/common/inc/swref/published/ampere/ga100/dev_fuse.h index 6931a44c9..253241a16 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_fuse.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_fuse.h @@ -130,4 +130,8 @@ #define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */ #define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */ +#define NV_FUSE_STATUS_OPT_DISPLAY 0x00820C04 /* R-I4R */ +#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */ +#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */ + #endif // __ga100_dev_fuse_h__ diff --git a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h index b49a496f2..2933606f5 100644 --- a/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h +++ b/src/common/inc/swref/published/ampere/ga100/dev_nv_xve_addendum.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a @@ -42,4 +42,11 @@ // #define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_ROOT_PORT_SPEED 3:0 +// +// On some platforms it's beneficial to enable relaxed ordering after vetting +// it's safe to do so. To automate this process on virtualized platforms, allow +// RO to be requested through this emulated config space bit. +// +#define NV_XVE_PASSTHROUGH_EMULATED_CONFIG_RELAXED_ORDERING_ENABLE 4:4 + #endif diff --git a/src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h b/src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h index c4f7805c6..3170e8b51 100644 --- a/src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h +++ b/src/common/inc/swref/published/ampere/ga102/dev_gc6_island.h @@ -29,8 +29,9 @@ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */ -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */ -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 0x001183a4 /* RW-4R */ +#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */ #endif // __ga102_dev_gc6_island_h__ diff --git a/src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h b/src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h index ac2531921..11000ddbb 100644 --- a/src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h +++ b/src/common/inc/swref/published/ampere/ga102/dev_gc6_island_addendum.h @@ -33,6 +33,9 @@ #define NV_USABLE_FB_SIZE_IN_MB NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 #define NV_USABLE_FB_SIZE_IN_MB_VALUE 31:0 #define NV_USABLE_FB_SIZE_IN_MB_VALUE_INIT 0 +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26 +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0 +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1 #endif // __ga102_dev_gc6_island_addendum_h__ diff --git a/src/common/inc/swref/published/maxwell/gm107/dev_fuse.h b/src/common/inc/swref/published/maxwell/gm107/dev_fuse.h new file mode 100644 index 000000000..36cfccdab --- /dev/null +++ b/src/common/inc/swref/published/maxwell/gm107/dev_fuse.h @@ -0,0 +1,31 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __gm107_dev_fuse_h__ +#define __gm107_dev_fuse_h__ + +#define NV_FUSE_STATUS_OPT_DISPLAY 0x00021C04 /* R-I4R */ +#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */ +#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */ + +#endif // __gm107_dev_fuse_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h index b241ac440..51f6c4725 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gc6_island.h @@ -29,7 +29,8 @@ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */ -#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_03(i) (0x00118214+(i)*4) /* RW-4A */ +#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(i) (0x00118234+(i)*4) /* RW-4A */ +#define NV_PGC6_BSI_SECURE_SCRATCH_14 0x001180f8 /* RW-4R */ #endif // __tu102_dev_gc6_island_h__ diff --git a/src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h b/src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h index 6e3acb67b..3d007fc29 100644 --- a/src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h +++ b/src/common/inc/swref/published/turing/tu102/dev_gc6_island_addendum.h @@ -30,6 +30,9 @@ #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(0) #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS 7:0 #define NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT_PROGRESS_COMPLETED 0x000000FF +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF 26:26 +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_INIT 0x0 +#define NV_PGC6_BSI_SECURE_SCRATCH_14_BOOT_STAGE_3_HANDOFF_VALUE_DONE 0x1 #endif // __tu102_dev_gc6_island_addendum_h__ diff --git a/src/common/modeset/timing/nvt_dsc_pps.c b/src/common/modeset/timing/nvt_dsc_pps.c index cc2f3fd16..b0cbaa634 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.c +++ b/src/common/modeset/timing/nvt_dsc_pps.c @@ -84,6 +84,7 @@ #define MAX_BITS_PER_PIXEL 32 // Max HBlank pixel count #define MAX_HBLANK_PIXELS 7680 +#define MHZ_TO_HZ 1000000 /* ------------------------ Datatypes -------------------------------------- */ @@ -1570,12 +1571,26 @@ _validateInput return NVT_STATUS_INVALID_PARAMETER; } + if ((pDscInfo->branchCaps.overallThroughputMode0 != 0) && + (pModesetInfo->pixelClockHz > pDscInfo->branchCaps.overallThroughputMode0 * MHZ_TO_HZ)) + { + DSC_Print("ERROR - Pixel clock cannot be greater than Branch DSC Overall Throughput Mode 0"); + return NVT_STATUS_INVALID_PARAMETER; + } + if (pModesetInfo->activeWidth == 0) { DSC_Print("ERROR - Invalid active width for mode."); return NVT_STATUS_INVALID_PARAMETER; } + if (pDscInfo->branchCaps.maxLineBufferWidth != 0 && + pModesetInfo->activeWidth > pDscInfo->branchCaps.maxLineBufferWidth) + { + DSC_Print("ERROR - Active width cannot be greater than DSC Decompressor max line buffer width"); + return NVT_STATUS_INVALID_PARAMETER; + } + if (pModesetInfo->activeHeight == 0) { DSC_Print("ERROR - Invalid active height for mode."); @@ -1919,7 +1934,13 @@ DSC_GeneratePPS if (*pBitsPerPixelX16 != 0) { *pBitsPerPixelX16 = DSC_AlignDownForBppPrecision(*pBitsPerPixelX16, pDscInfo->sinkCaps.bitsPerPixelPrecision); - if (*pBitsPerPixelX16 > in->bits_per_pixel) + + // The calculation of in->bits_per_pixel here in PPSlib, which is the maximum bpp that is allowed by available bandwidth, + // which is applicable to DP alone and not to HDMI FRL. + // Before calling PPS lib to generate PPS data, HDMI library has done calculation according to HDMI2.1 spec + // to determine if FRL rate is sufficient for the requested bpp. So restricting the condition to DP alone. + if ((pWARData && (pWARData->connectorType == DSC_DP)) && + (*pBitsPerPixelX16 > in->bits_per_pixel)) { DSC_Print("ERROR - Invalid bits per pixel value specified."); ret = NVT_STATUS_INVALID_PARAMETER; diff --git a/src/common/modeset/timing/nvt_dsc_pps.h b/src/common/modeset/timing/nvt_dsc_pps.h index 651d420c2..d03ca2fac 100644 --- a/src/common/modeset/timing/nvt_dsc_pps.h +++ b/src/common/modeset/timing/nvt_dsc_pps.h @@ -196,6 +196,13 @@ typedef struct NvU32 maxBitsPerPixelX16; }sinkCaps; + struct BRANCH_DSC_CAPS + { + NvU32 overallThroughputMode0; + NvU32 overallThroughputMode1; + NvU32 maxLineBufferWidth; + }branchCaps; + struct GPU_DSC_CAPS { // Mask of all color formats for which encoding supported by GPU diff --git a/src/common/modeset/timing/nvt_edid.c b/src/common/modeset/timing/nvt_edid.c index 6fe3fb577..4e5f34c63 100644 --- a/src/common/modeset/timing/nvt_edid.c +++ b/src/common/modeset/timing/nvt_edid.c @@ -2410,7 +2410,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion) CommonEDIDBuffer[0x7F] = 0; CommonEDIDBuffer[0xFF] = 0; - // We also need to zero out any "EDID Other Monitor Descriptors" (http://en.wikipedia.org/wiki/Extended_display_identification_data) + // We also need to zero out any "EDID Other Monitor Descriptors" (https://en.wikipedia.org/wiki/Extended_display_identification_data) for (edidBufferIndex = 54; edidBufferIndex <= 108; edidBufferIndex += 18) { if (CommonEDIDBuffer[edidBufferIndex] == 0 && CommonEDIDBuffer[edidBufferIndex+1] == 0) diff --git a/src/common/nvswitch/kernel/inc/rom_nvswitch.h b/src/common/nvswitch/kernel/inc/rom_nvswitch.h index 01a6014d5..4f5e3288d 100644 --- a/src/common/nvswitch/kernel/inc/rom_nvswitch.h +++ b/src/common/nvswitch/kernel/inc/rom_nvswitch.h @@ -64,7 +64,7 @@ // // AT24CM02 EEPROM -// http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8828-SEEPROM-AT24CM02-Datasheet.pdf +// https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8828-SEEPROM-AT24CM02-Datasheet.pdf // #define AT24CM02_INDEX_SIZE 18 // Addressing bits @@ -72,7 +72,7 @@ // // AT24C02C EEPROM -// http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8700-SEEPROM-AT24C01C-02C-Datasheet.pdf +// https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8700-SEEPROM-AT24C01C-02C-Datasheet.pdf // #define AT24C02C_INDEX_SIZE 8 // Addressing bits @@ -80,7 +80,7 @@ // // AT24C02D EEPROM -// http://ww1.microchip.com/downloads/en/devicedoc/atmel-8871f-seeprom-at24c01d-02d-datasheet.pdf +// https://ww1.microchip.com/downloads/en/devicedoc/atmel-8871f-seeprom-at24c01d-02d-datasheet.pdf // 2kb EEPROM used on LR10 P4790 B00 platform // diff --git a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h index 249795c96..7e54366ac 100644 --- a/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h +++ b/src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h @@ -2208,4 +2208,19 @@ typedef struct NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS { NvU8 p2pWriteCapsStatus; } NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS; +/*! + * NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO + * + * Enable/disable PCIe Relaxed Ordering. + * + */ +#define NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO (0x20800ab9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID" */ + +#define NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS_MESSAGE_ID (0xb9U) + +typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS { + // Enable/disable PCIe relaxed ordering + NvBool enableRo; +} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS; + /* ctrl2080internal_h */ diff --git a/src/common/sdk/nvidia/inc/nverror.h b/src/common/sdk/nvidia/inc/nverror.h index 0d32daae7..b60dc0787 100644 --- a/src/common/sdk/nvidia/inc/nverror.h +++ b/src/common/sdk/nvidia/inc/nverror.h @@ -99,7 +99,11 @@ #define GSP_RPC_TIMEOUT (119) #define GSP_ERROR (120) #define C2C_ERROR (121) -#define ROBUST_CHANNEL_LAST_ERROR (C2C_ERROR) +#define SPI_PMU_RPC_READ_FAIL (122) +#define SPI_PMU_RPC_WRITE_FAIL (123) +#define SPI_PMU_RPC_ERASE_FAIL (124) +#define INFOROM_FS_ERROR (125) +#define ROBUST_CHANNEL_LAST_ERROR (INFOROM_FS_ERROR) // Indexed CE reference diff --git a/src/common/sdk/nvidia/inc/nvfixedtypes.h b/src/common/sdk/nvidia/inc/nvfixedtypes.h index 53b6882ce..73c7923f6 100644 --- a/src/common/sdk/nvidia/inc/nvfixedtypes.h +++ b/src/common/sdk/nvidia/inc/nvfixedtypes.h @@ -306,7 +306,7 @@ typedef NvUFXP64 NvUFXP52_12; * 2^(_EXPONENT - _EXPONENT_BIAS) * * (1 + _MANTISSA / (1 << 23)) */ -// [1] : http://en.wikipedia.org/wiki/Single_precision_floating-point_format +// [1] : https://en.wikipedia.org/wiki/Single_precision_floating-point_format #define NV_TYPES_SINGLE_SIGN 31:31 #define NV_TYPES_SINGLE_SIGN_POSITIVE 0x00000000 #define NV_TYPES_SINGLE_SIGN_NEGATIVE 0x00000001 diff --git a/src/common/unix/common/utils/nv_memory_tracker.c b/src/common/unix/common/utils/nv_memory_tracker.c index 7b467d9ad..cecf5d193 100644 --- a/src/common/unix/common/utils/nv_memory_tracker.c +++ b/src/common/unix/common/utils/nv_memory_tracker.c @@ -54,7 +54,7 @@ typedef union { /* * Unused. For alignment purposes only. Guarantee alignment to * twice pointer size. That is the alignment guaranteed by glibc: - * http://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html + * https://www.gnu.org/software/libc/manual/html_node/Aligned-Memory-Blocks.html * which seems reasonable to match here. */ NvU8 align __attribute__((aligned(sizeof(void*) * 2))); diff --git a/src/common/uproc/os/libos-v2.0.0/debug/lines.c b/src/common/uproc/os/libos-v2.0.0/debug/lines.c index 3a43f3230..9f1fd2aff 100644 --- a/src/common/uproc/os/libos-v2.0.0/debug/lines.c +++ b/src/common/uproc/os/libos-v2.0.0/debug/lines.c @@ -56,7 +56,7 @@ static void libosDwarfBuildTables(libosDebugResolver *pThis); static void dwarfBuildARangeTable(libosDebugResolver *pThis); static void dwarfSetARangeTableLineUnit(libosDebugResolver *pThis, DwarfStream unit, NvU64 address); -// http://www.dwarfstd.org/doc/dwarf-2.0.0.pdf +// https://www.dwarfstd.org/doc/dwarf-2.0.0.pdf // Debug Line information related structures // (for branch history and call stacks) diff --git a/src/nvidia-modeset/Makefile b/src/nvidia-modeset/Makefile index c63b86bcd..965e647b9 100644 --- a/src/nvidia-modeset/Makefile +++ b/src/nvidia-modeset/Makefile @@ -85,6 +85,7 @@ endif ifeq ($(TARGET_ARCH),aarch64) CFLAGS += -mgeneral-regs-only CFLAGS += -march=armv8-a + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics) endif CFLAGS += -fno-pic diff --git a/src/nvidia-modeset/src/nvkms-hdmi.c b/src/nvidia-modeset/src/nvkms-hdmi.c index a67b78001..2c3e727a4 100644 --- a/src/nvidia-modeset/src/nvkms-hdmi.c +++ b/src/nvidia-modeset/src/nvkms-hdmi.c @@ -1492,7 +1492,7 @@ static void LogEdidCea861Info(NVEvoInfoStringPtr pInfoString, /* * IEEE vendor registration IDs are tracked here: - * http://standards.ieee.org/develop/regauth/oui/oui.txt + * https://standards.ieee.org/develop/regauth/oui/oui.txt */ for (vsdbIndex = 0; vsdbIndex < pExt861->total_vsdb; vsdbIndex++) { const NvU32 ieeeId = pExt861->vsdb[vsdbIndex].ieee_id; diff --git a/src/nvidia/Makefile b/src/nvidia/Makefile index 9bdb826ad..2a3773131 100644 --- a/src/nvidia/Makefile +++ b/src/nvidia/Makefile @@ -67,6 +67,7 @@ ifeq ($(TARGET_ARCH),aarch64) CFLAGS += -mgeneral-regs-only CFLAGS += -march=armv8-a CFLAGS += -mstrict-align + CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics) endif CFLAGS += -fno-pic diff --git a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h index 33d48ff22..2a1c5bbb1 100644 --- a/src/nvidia/arch/nvalloc/common/inc/flcnretval.h +++ b/src/nvidia/arch/nvalloc/common/inc/flcnretval.h @@ -276,4 +276,11 @@ typedef NvU8 FLCN_STATUS; // Lane Margining errors #define FLCN_ERR_LM_INVALID_RECEIVER_NUMBER (0xF5U) +// APM errors +#define FLCN_ERR_APM_NOT_FUSED_FOR_EK (0xF6U) +#define FLCN_ERR_APM_BROM_SIGN_FAIL (0xF7U) +// Booter Reload on SEC2-RTOS errors +#define FLCN_ERR_AUTH_GSP_RM_HANDOFF_FAILED (0xF8U) +#define FLCN_ERR_INVALID_WPRMETA_MAGIC_OR_REVISION (0xF9U) + #endif // FLCNRETVAL_H diff --git a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h index 569a57495..31d3560f5 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv-reg.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv-reg.h @@ -301,23 +301,6 @@ #define __NV_ENABLE_MSI EnableMSI #define NV_REG_ENABLE_MSI NV_REG_STRING(__NV_ENABLE_MSI) -/* - * Option: RegisterForACPIEvents - * - * Description: - * - * When this option is enabled, the NVIDIA driver will register with the - * ACPI subsystem to receive notification of ACPI events. - * - * Possible values: - * - * 1 - register for ACPI events (default) - * 0 - do not register for ACPI events - */ - -#define __NV_REGISTER_FOR_ACPI_EVENTS RegisterForACPIEvents -#define NV_REG_REGISTER_FOR_ACPI_EVENTS NV_REG_STRING(__NV_REGISTER_FOR_ACPI_EVENTS) - /* * Option: EnablePCIeGen3 * @@ -817,6 +800,30 @@ #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_ENABLE 0x00000001 #define NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DEFAULT NV_REG_OPENRM_ENABLE_UNSUPPORTED_GPUS_DISABLE +/* + * Option: NVreg_DmaRemapPeerMmio + * + * Description: + * + * When this option is enabled, the NVIDIA driver will use device driver + * APIs provided by the Linux kernel for DMA-remapping part of a device's + * MMIO region to another device, creating e.g., IOMMU mappings as necessary. + * When this option is disabled, the NVIDIA driver will instead only apply a + * fixed offset, which may be zero, to CPU physical addresses to produce the + * DMA address for the peer's MMIO region, and no IOMMU mappings will be + * created. + * + * This option only affects peer MMIO DMA mappings, and not system memory + * mappings. + * + * Possible Values: + * 0 = disable dynamic DMA remapping of peer MMIO regions + * 1 = enable dynamic DMA remapping of peer MMIO regions (default) + */ +#define __NV_DMA_REMAP_PEER_MMIO DmaRemapPeerMmio +#define NV_DMA_REMAP_PEER_MMIO NV_REG_STRING(__NV_DMA_REMAP_PEER_MMIO) +#define NV_DMA_REMAP_PEER_MMIO_DISABLE 0x00000000 +#define NV_DMA_REMAP_PEER_MMIO_ENABLE 0x00000001 #if defined(NV_DEFINE_REGISTRY_KEY_TABLE) @@ -832,7 +839,6 @@ NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_GID, 0); NV_DEFINE_REG_ENTRY(__NV_DEVICE_FILE_MODE, 0666); NV_DEFINE_REG_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS, 1); NV_DEFINE_REG_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE, ~0); -NV_DEFINE_REG_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS, 1); NV_DEFINE_REG_ENTRY(__NV_ENABLE_PCIE_GEN3, 0); NV_DEFINE_REG_ENTRY(__NV_ENABLE_MSI, 1); NV_DEFINE_REG_ENTRY(__NV_TCE_BYPASS_MODE, NV_TCE_BYPASS_MODE_DEFAULT); @@ -863,6 +869,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_RM_MSG, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_GPU_BLACKLIST, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL); NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL); +NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE); /* *----------------registry database definition---------------------- @@ -885,7 +892,6 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_USE_PAGE_ATTRIBUTE_TABLE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_MSI), - NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_REGISTER_FOR_ACPI_EVENTS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_PCIE_GEN3), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_MEMORY_POOL_SIZE), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_KMALLOC_HEAP_MAX_SIZE), @@ -908,6 +914,7 @@ nv_parm_t nv_parms[] = { NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_GPU_FIRMWARE_LOGS), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT), NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS), + NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO), {NULL, NULL} }; diff --git a/src/nvidia/arch/nvalloc/unix/include/nv.h b/src/nvidia/arch/nvalloc/unix/include/nv.h index 07dc0f83e..ac075eeab 100644 --- a/src/nvidia/arch/nvalloc/unix/include/nv.h +++ b/src/nvidia/arch/nvalloc/unix/include/nv.h @@ -571,11 +571,9 @@ typedef enum ((nv)->iso_iommu_present) /* - * NVIDIA ACPI event IDs to be passed into the core NVIDIA - * driver for various events like display switch events, - * AC/battery events, etc.. + * NVIDIA ACPI event ID to be passed into the core NVIDIA driver for + * AC/DC event. */ -#define NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT 0x8001 #define NV_SYSTEM_ACPI_BATTERY_POWER_EVENT 0x8002 /* @@ -584,14 +582,6 @@ typedef enum #define NV_SYSTEM_GPU_ADD_EVENT 0x9001 #define NV_SYSTEM_GPU_REMOVE_EVENT 0x9002 -/* - * Status bit definitions for display switch hotkey events. - */ -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_LCD 0x01 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_CRT 0x02 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_TV 0x04 -#define NV_HOTKEY_STATUS_DISPLAY_ENABLE_DFP 0x08 - /* * NVIDIA ACPI sub-event IDs (event types) to be passed into * to core NVIDIA driver for ACPI events. diff --git a/src/nvidia/arch/nvalloc/unix/src/osapi.c b/src/nvidia/arch/nvalloc/unix/src/osapi.c index c24402196..8a61cd15f 100644 --- a/src/nvidia/arch/nvalloc/unix/src/osapi.c +++ b/src/nvidia/arch/nvalloc/unix/src/osapi.c @@ -1112,10 +1112,6 @@ NV_STATUS RmSystemEvent( switch (event_type) { - case NV_SYSTEM_ACPI_DISPLAY_SWITCH_EVENT: - // Legacy kepler case, do nothing. - break; - case NV_SYSTEM_ACPI_BATTERY_POWER_EVENT: { Nv2080PowerEventNotification powerParams; @@ -3052,6 +3048,38 @@ NV_STATUS rm_update_device_mapping_info( return RmStatus; } +static void rm_is_device_rm_firmware_capable( + nv_state_t *pNv, + NvU32 pmcBoot42, + NvBool *pbIsFirmwareCapable, + NvBool *pbEnableByDefault +) +{ + NvBool bIsFirmwareCapable = NV_FALSE; + NvBool bEnableByDefault = NV_FALSE; + NvU16 pciDeviceId = pNv->pci_info.device_id; + + if (NV_IS_SOC_DISPLAY_DEVICE(pNv)) + { + bIsFirmwareCapable = NV_TRUE; + } + else + { + bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pciDeviceId, + pmcBoot42, + &bEnableByDefault); + } + + if (pbIsFirmwareCapable != NULL) + { + *pbIsFirmwareCapable = bIsFirmwareCapable; + } + if (pbEnableByDefault != NULL) + { + *pbEnableByDefault = bEnableByDefault; + } +} + static NvBool NV_API_CALL rm_is_legacy_device( NvU16 device_id, NvU16 subsystem_vendor, @@ -3138,7 +3166,31 @@ NV_STATUS NV_API_CALL rm_is_supported_device( rmStatus = halmgrGetHalForGpu(pHalMgr, pmc_boot_0, pmc_boot_42, &myHalPublicID); if (rmStatus != NV_OK) + { + NvBool bIsFirmwareCapable; + + rm_is_device_rm_firmware_capable(pNv, + pmc_boot_42, + &bIsFirmwareCapable, + NULL); + if (!bIsFirmwareCapable) + { + nv_printf(NV_DBG_ERRORS, + "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n" + "NVRM: installed in this system is not supported by open\n" + "NVRM: nvidia.ko because it does not include the required GPU\n" + "NVRM: System Processor (GSP).\n" + "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n" + "NVRM: Firmware' sections in the driver README, available on\n" + "NVRM: the Linux graphics driver download page at\n" + "NVRM: www.nvidia.com.\n", + pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot, + pNv->pci_info.function, pNv->pci_info.vendor_id, + pNv->pci_info.device_id, NV_VERSION_STRING); + goto threadfree; + } goto print_unsupported; + } goto threadfree; diff --git a/src/nvidia/generated/g_bindata.c b/src/nvidia/generated/g_bindata.c index 1e4c2499e..dac58964e 100644 --- a/src/nvidia/generated/g_bindata.c +++ b/src/nvidia/generated/g_bindata.c @@ -58,10 +58,6 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" @@ -84,10 +80,6 @@ struct BINDATA_STORAGE_PVT_ALL #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" @@ -108,10 +100,6 @@ BINDATA_CONST struct BINDATA_STORAGE_PVT_ALL g_bindata_pvt = #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" @@ -135,10 +123,6 @@ const NvU32 g_bindata_pvt_count = sizeof(g_bindata_pvt) / sizeof(BINDATA_STORAGE #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c" #include "g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c" -#include "g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c" #include "g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c" diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c index af40f7cb0..75711b7b7 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA100.c @@ -35,1516 +35,1500 @@ // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 24092 +// COMPRESSED SIZE (bytes): 23832 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data[] = { - 0xed, 0xfc, 0x43, 0x90, 0x68, 0x3d, 0xdb, 0x00, 0xec, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xdd, - 0xbb, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0xb1, 0xdb, 0xb6, 0x6d, 0xdb, 0xf6, 0x79, 0xbe, 0x53, - 0x75, 0x26, 0xef, 0xe4, 0x4c, 0xff, 0xbf, 0x6a, 0x5f, 0x93, 0x3b, 0x49, 0xd5, 0xca, 0xca, 0x20, - 0x6b, 0x55, 0xa5, 0xee, 0x24, 0x92, 0x00, 0x08, 0x33, 0x19, 0x00, 0x71, 0x00, 0xe0, 0x00, 0xdd, - 0x47, 0xf9, 0xef, 0x2d, 0x3f, 0x80, 0x92, 0x00, 0x88, 0xff, 0xd7, 0x00, 0x01, 0x0e, 0xf0, 0xff, - 0xad, 0x46, 0x00, 0x00, 0x00, 0xfe, 0x24, 0x03, 0xf8, 0xd2, 0x03, 0x00, 0xbc, 0x01, 0xbd, 0x01, - 0xbc, 0x03, 0xc5, 0x00, 0x00, 0x01, 0xf4, 0xee, 0xec, 0xfe, 0xfe, 0xfe, 0xc2, 0x47, 0x00, 0x00, - 0x02, 0xfc, 0xe6, 0x81, 0x34, 0x1d, 0x01, 0x30, 0xa7, 0xaf, 0x03, 0x36, 0x25, 0x03, 0xd0, 0xa4, - 0xaf, 0x03, 0xfd, 0x17, 0x48, 0xd3, 0xd7, 0x81, 0xff, 0x0b, 0x78, 0xff, 0x3d, 0x0b, 0x90, 0x9e, - 0x07, 0xdc, 0xb2, 0x0b, 0xdc, 0x9b, 0x97, 0xbf, 0x9b, 0x9e, 0x07, 0x98, 0x9e, 0x01, 0xd4, 0xb2, - 0x0b, 0xd8, 0xb2, 0x0e, 0xe4, 0xbb, 0x0b, 0x00, 0x00, 0xcf, 0x28, 0x09, 0x80, 0xf0, 0x9a, 0x07, - 0xd0, 0x9d, 0x1c, 0xf7, 0x5f, 0x97, 0x2d, 0xef, 0x01, 0x2d, 0xef, 0xfe, 0x11, 0x00, 0xc1, 0x20, - 0xff, 0x35, 0xc1, 0x03, 0xb6, 0x67, 0x00, 0xe0, 0x02, 0xfd, 0x5f, 0x09, 0xf8, 0xbf, 0x12, 0x20, - 0xd0, 0xff, 0xaf, 0x0d, 0xec, 0xff, 0x4a, 0xff, 0x75, 0x0b, 0x94, 0x02, 0x0f, 0xb1, 0xf3, 0x7f, - 0x43, 0xf8, 0x7e, 0x07, 0x8d, 0x00, 0xd0, 0x07, 0xf8, 0xce, 0x05, 0xe9, 0x8a, 0x07, 0x6a, 0x4d, - 0x46, 0xf8, 0xaf, 0xfe, 0xf3, 0x01, 0xe0, 0xfb, 0xdf, 0xc0, 0xde, 0x80, 0xba, 0x8b, 0x3f, 0x01, - 0xe3, 0xfa, 0xc6, 0xa1, 0x23, 0x08, 0x68, 0x01, 0xf2, 0xf3, 0xde, 0x00, 0xe2, 0xfe, 0x8b, 0xbd, - 0xbf, 0x4f, 0x0c, 0x5f, 0x3f, 0x92, 0x80, 0xf9, 0x79, 0x7c, 0xef, 0x00, 0xff, 0x07, 0x1d, 0xe4, - 0xf2, 0x16, 0xfb, 0x0b, 0x3a, 0xfe, 0x67, 0x52, 0xe2, 0x10, 0x2d, 0x97, 0x59, 0xc9, 0xbf, 0xe8, - 0xc9, 0x1e, 0xaf, 0xcb, 0x97, 0xfa, 0xca, 0x70, 0x40, 0xfc, 0x2d, 0xeb, 0xbd, 0xeb, 0xa4, 0x2b, - 0x65, 0x34, 0x86, 0x3a, 0xa4, 0x03, 0xb2, 0xda, 0x3b, 0xd5, 0xfa, 0x9a, 0x62, 0xa3, 0x6d, 0x43, - 0xd8, 0x02, 0x3b, 0x89, 0x25, 0x00, 0xb2, 0x3e, 0x94, 0xaf, 0xa1, 0x06, 0xdb, 0x73, 0xbd, 0xac, - 0x50, 0xf1, 0x62, 0xa8, 0xfa, 0xe4, 0xf0, 0x4a, 0x5b, 0x98, 0x3b, 0x11, 0x5d, 0xcf, 0x6a, 0xb8, - 0xeb, 0x04, 0x52, 0xe3, 0x4e, 0x10, 0x8c, 0x53, 0x66, 0x20, 0x72, 0x76, 0xd1, 0x57, 0xee, 0x80, - 0x04, 0x5e, 0xd4, 0x15, 0x8a, 0x02, 0xc6, 0x60, 0x86, 0x43, 0x03, 0xa3, 0xde, 0xaf, 0x49, 0x7b, - 0x5d, 0xcd, 0x91, 0xd0, 0x19, 0x0b, 0x48, 0x11, 0x22, 0x05, 0xb3, 0x13, 0x86, 0xef, 0xa0, 0xa5, - 0xf4, 0xe1, 0x09, 0xa9, 0xd8, 0x7c, 0x5c, 0x7e, 0xee, 0x01, 0x4c, 0xaf, 0xb8, 0xeb, 0x32, 0x20, - 0xf5, 0xd7, 0x18, 0x12, 0x36, 0xcb, 0xa9, 0xfc, 0xf0, 0xc9, 0xbb, 0xc4, 0xef, 0x3e, 0xa1, 0xbf, - 0x86, 0xc1, 0x7f, 0x7e, 0x64, 0x0d, 0x58, 0xdb, 0xba, 0xe0, 0xcc, 0x15, 0x23, 0xa2, 0xc5, 0x38, - 0x3b, 0xf0, 0xbd, 0x7a, 0xb4, 0x24, 0x9a, 0xc6, 0x0d, 0xdd, 0x9f, 0x86, 0xb4, 0x44, 0xa6, 0x5a, - 0x49, 0x32, 0x0e, 0x7c, 0x52, 0x35, 0x45, 0xa3, 0x14, 0x18, 0x0c, 0xdd, 0x88, 0xb2, 0x65, 0x55, - 0x50, 0x65, 0x34, 0xba, 0x61, 0xd1, 0x73, 0xe5, 0xdd, 0x3a, 0xf9, 0x26, 0x84, 0xd9, 0x21, 0x3e, - 0x60, 0x6d, 0xb4, 0x80, 0xab, 0x36, 0x32, 0x3b, 0x8f, 0x92, 0xb6, 0x4a, 0xe1, 0xe3, 0x9d, 0x1a, - 0xdb, 0x24, 0xff, 0xea, 0xfa, 0x39, 0x6d, 0xca, 0xac, 0xdd, 0x4b, 0xa5, 0xed, 0x55, 0xa7, 0x9b, - 0x54, 0xf0, 0x94, 0x85, 0x89, 0x03, 0xac, 0xd4, 0x35, 0x2a, 0xf3, 0x8e, 0x45, 0x4b, 0x27, 0xf3, - 0x68, 0x4a, 0x99, 0x75, 0x3c, 0xc0, 0x15, 0x68, 0x75, 0x05, 0xf9, 0xd8, 0x53, 0x8c, 0xd9, 0x21, - 0xa9, 0x69, 0x9e, 0x8d, 0xcc, 0x9a, 0x9e, 0x14, 0x6f, 0xad, 0x46, 0xd2, 0xd7, 0x77, 0x37, 0x64, - 0x64, 0x7e, 0xeb, 0x7d, 0x11, 0xaf, 0x77, 0x6f, 0x84, 0x32, 0xf0, 0x5b, 0xa8, 0x94, 0xb8, 0x17, - 0x5a, 0x9f, 0xd5, 0x3f, 0xe9, 0xaf, 0xf0, 0xab, 0x6a, 0x6b, 0x51, 0xab, 0xd4, 0xaa, 0x38, 0xae, - 0x3e, 0xff, 0xe0, 0xf5, 0x3e, 0x84, 0x06, 0xc1, 0xcc, 0x2b, 0x3f, 0x03, 0xa4, 0xbe, 0xe6, 0x78, - 0xa5, 0xd6, 0x89, 0x24, 0xc7, 0x9f, 0xd0, 0x05, 0xa0, 0x1a, 0x79, 0xe9, 0xd7, 0xb4, 0xd2, 0x02, - 0x75, 0x68, 0x45, 0x8a, 0x3a, 0x70, 0x7f, 0xf7, 0x9c, 0x36, 0xbd, 0x43, 0xa9, 0xaa, 0xba, 0xcd, - 0xc5, 0x4d, 0x77, 0xd7, 0xd0, 0x36, 0xde, 0x36, 0x6a, 0x84, 0xf3, 0x4a, 0x5c, 0x43, 0x3a, 0x14, - 0x50, 0x71, 0x5c, 0x26, 0x6e, 0xd1, 0xe4, 0x42, 0xad, 0xde, 0x27, 0xd9, 0x8a, 0xa8, 0x96, 0x7a, - 0x06, 0x36, 0xa4, 0x7c, 0xf2, 0x9c, 0x49, 0xdc, 0x18, 0x4c, 0xba, 0x8b, 0x15, 0xd0, 0xde, 0xfe, - 0xe7, 0xc0, 0x41, 0x9d, 0x60, 0x28, 0x1e, 0x93, 0x83, 0x64, 0xd6, 0xbf, 0xbf, 0xe4, 0xd5, 0xfb, - 0x20, 0x34, 0xb2, 0x24, 0x73, 0xea, 0x31, 0x20, 0x34, 0x53, 0x4d, 0xfe, 0xda, 0x4a, 0x71, 0xfb, - 0x4b, 0x7c, 0x5e, 0x72, 0x8e, 0x4e, 0xe7, 0x01, 0x1f, 0x94, 0x93, 0x4b, 0xdd, 0xe1, 0xda, 0x4b, - 0x65, 0x46, 0x8c, 0xeb, 0x34, 0x6e, 0x32, 0x53, 0xb4, 0xe9, 0x67, 0xbc, 0x3b, 0x01, 0xb2, 0x69, - 0x07, 0x46, 0xee, 0x19, 0xef, 0x85, 0xc3, 0xde, 0x44, 0x9c, 0x61, 0x4b, 0x18, 0xdd, 0x84, 0x52, - 0xfb, 0xba, 0x12, 0x69, 0x53, 0x7f, 0x7e, 0x33, 0x70, 0x31, 0x56, 0x45, 0x01, 0x2b, 0xb1, 0xea, - 0xb2, 0x2b, 0xb2, 0xae, 0xf0, 0xcf, 0x77, 0x1f, 0xb8, 0x92, 0x7f, 0x7e, 0x1a, 0x7f, 0x7e, 0x3b, - 0x3e, 0x5e, 0xe4, 0x9a, 0x98, 0x16, 0x69, 0x4a, 0xc3, 0x34, 0x68, 0xa9, 0xc8, 0x57, 0x39, 0xe1, - 0x4f, 0xa8, 0xf2, 0x31, 0xb7, 0x48, 0xb1, 0x7d, 0x3a, 0x02, 0x0d, 0x30, 0x02, 0x63, 0x71, 0xd3, - 0x97, 0x7b, 0x6b, 0x0e, 0x37, 0x32, 0xba, 0xcd, 0x83, 0x2c, 0x0d, 0xa3, 0x05, 0x2b, 0xec, 0x5a, - 0x77, 0xe7, 0xaa, 0x46, 0xf6, 0x5d, 0x65, 0xb7, 0xf3, 0x27, 0x9a, 0xf1, 0x17, 0xe6, 0x44, 0x3f, - 0xbe, 0x12, 0xfd, 0x15, 0xbc, 0x03, 0xc7, 0x47, 0x24, 0x87, 0xdd, 0x4d, 0x63, 0x00, 0x7f, 0xa7, - 0x10, 0x22, 0x9c, 0x9e, 0x4c, 0xa7, 0xb0, 0x1f, 0xe1, 0x78, 0xab, 0x0b, 0x39, 0xa2, 0x6f, 0x64, - 0x96, 0xee, 0xe0, 0xcb, 0x96, 0x3c, 0x1d, 0x73, 0xa2, 0xeb, 0xcb, 0xee, 0xf5, 0x9c, 0x9f, 0x2a, - 0xa0, 0x0a, 0x8f, 0x5c, 0x3a, 0x47, 0x97, 0x0d, 0xbf, 0x26, 0x6a, 0xcf, 0x9b, 0x2a, 0xd7, 0xe3, - 0x07, 0xa2, 0x47, 0x4b, 0xa1, 0x91, 0xbb, 0x57, 0xff, 0x26, 0x69, 0x8f, 0x2c, 0xeb, 0x27, 0xd0, - 0x95, 0xb5, 0xee, 0xd0, 0xca, 0xec, 0xd3, 0xda, 0xb0, 0xd9, 0xca, 0x53, 0x61, 0x20, 0xab, 0x9b, - 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BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 36352, // uncompressed data size (bytes) - 24092, // compressed data size (bytes) + 23832, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1607,1516 +1591,1500 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 36352 -// COMPRESSED SIZE (bytes): 24090 +// COMPRESSED SIZE (bytes): 23829 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_image_prod_data[] = { - 0xed, 0xfc, 0x43, 0x90, 0x68, 0x3d, 0xdb, 0x00, 0xec, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xd6, - 0x6e, 0xdb, 0xb6, 0x6d, 0xdb, 0xdd, 0xbb, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xe6, 0x79, 0xbe, 0x53, - 0x75, 0x26, 0xef, 0xe4, 0x4c, 0xff, 0xbf, 0x6a, 0x5f, 0x93, 0xa0, 0x6a, 0x65, 0xa5, 0x6a, 0x25, - 0x2b, 0x83, 0x3b, 0x89, 0x24, 0x00, 0xc2, 0x4c, 0x06, 0x40, 0x1c, 0x00, 0x38, 0x40, 0xf7, 0x51, - 0xfe, 0x7b, 0xf3, 0x0f, 0xa0, 0x24, 0x00, 0xe2, 0xff, 0x55, 0x40, 0x80, 0x03, 0xfc, 0x7f, 0x8b, - 0x11, 0x00, 0x00, 0x80, 0x3f, 0xc9, 0x00, 0xbe, 0xf4, 0x00, 0x00, 0x6f, 0x40, 0x6f, 0x00, 0xef, - 0x40, 0x31, 0x00, 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0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, + 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, + 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, + 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0xff, 0x27, 0xfc, 0x3f, 0x00, 0xd8, 0xe2, 0x6e, + 0x15, 0x00, 0x8e, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3127,7 +3095,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 36352, // uncompressed data size (bytes) - 24090, // compressed data size (bytes) + 23829, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3183,31 +3151,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x18, 0x97, 0x69, 0x1c, 0xf9, 0x7c, 0xb1, 0xa1, 0xac, 0xbe, 0x29, - 0x3b, 0x10, 0x8e, 0x68, 0x8d, 0xe5, 0xf1, 0x82, 0xbe, 0x17, 0xe7, 0xbb, 0xf4, 0x35, 0x95, 0x09, - 0x89, 0xff, 0xc9, 0x08, 0x76, 0x52, 0x16, 0xd4, 0xa9, 0xb4, 0x79, 0xa2, 0x8e, 0x17, 0xd0, 0x9e, - 0x9f, 0x36, 0x39, 0x9c, 0xd4, 0x30, 0x29, 0x8e, 0x11, 0x49, 0xda, 0x59, 0x93, 0xce, 0xa7, 0x5d, - 0x04, 0x33, 0xc4, 0xf6, 0x94, 0x3b, 0xd7, 0x73, 0xee, 0xde, 0xc6, 0x8d, 0x09, 0x30, 0xd8, 0xaf, - 0x7a, 0x49, 0x8b, 0x50, 0x7d, 0x1a, 0x8d, 0x36, 0xa2, 0xdb, 0xf1, 0xbc, 0xcd, 0xba, 0x5b, 0x57, - 0x61, 0x25, 0x86, 0x30, 0xc6, 0x94, 0xdc, 0xce, 0xdc, 0xac, 0x9d, 0x03, 0x2b, 0x97, 0xcd, 0xff, - 0xc6, 0x95, 0x65, 0x3a, 0xb5, 0x14, 0x9a, 0x74, 0xdd, 0xb4, 0x4d, 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0xe2, 0x0c, 0x9c, 0x25, 0xc9, 0xe2, 0x94, 0xef, 0x9c, 0x97, 0x6b, 0xa3, + 0x19, 0xf8, 0x36, 0xbf, 0x21, 0xae, 0x2d, 0x4e, 0x02, 0xff, 0x26, 0xe9, 0xe9, 0x0d, 0x75, 0x1c, + 0xa8, 0xdb, 0x1e, 0xa1, 0xaa, 0x01, 0x0c, 0x05, 0x27, 0x69, 0x84, 0x21, 0xaa, 0xa9, 0x80, 0x96, + 0x1b, 0x25, 0x35, 0x3b, 0x21, 0x6f, 0x20, 0x56, 0xd7, 0xb9, 0xdb, 0xa4, 0x0a, 0x61, 0x2f, 0x07, + 0xaf, 0x25, 0x6e, 0xd1, 0xa9, 0x21, 0xfc, 0x6b, 0x25, 0xfb, 0x3f, 0x36, 0x8f, 0xc5, 0xae, 0x04, + 0xb0, 0xc2, 0x8a, 0x86, 0x8b, 0x23, 0x45, 0x9d, 0xc0, 0x71, 0x33, 0xf2, 0x4b, 0xd1, 0x91, 0x1c, + 0x79, 0x36, 0xcf, 0x64, 0x53, 0x4a, 0x5a, 0xdb, 0xd6, 0x83, 0x94, 0xcb, 0x16, 0xb3, 0x1e, 0xf6, + 0xe5, 0x8a, 0xf3, 0x67, 0xc9, 0x0d, 0xa9, 0x84, 0xd9, 0x69, 0x9d, 0x1b, 0xf1, 0x71, 0xc4, 0x8d, + 0xf6, 0x2f, 0x2c, 0x79, 0x16, 0xcb, 0x93, 0x97, 0xfe, 0x7b, 0xec, 0x7c, 0x16, 0xbd, 0x95, 0xec, + 0x4e, 0xdc, 0x09, 0x13, 0xaa, 0x2c, 0xf9, 0xac, 0x81, 0xa4, 0x25, 0x77, 0xa3, 0x60, 0x4c, 0x7b, + 0xe5, 0x37, 0xc9, 0x71, 0x3e, 0x6e, 0xc0, 0x7f, 0xa1, 0x96, 0xf4, 0xb8, 0xa5, 0xec, 0x56, 0x8a, + 0x75, 0x90, 0x00, 0x4b, 0x21, 0x54, 0xba, 0x62, 0x73, 0x3e, 0x4c, 0xd5, 0x17, 0xc1, 0x81, 0x11, + 0xfd, 0xb4, 0x1e, 0xfd, 0x51, 0xc7, 0x33, 0x18, 0x8c, 0x61, 0xd2, 0x46, 0xa4, 0x2b, 0xb3, 0x36, + 0x89, 0x45, 0x73, 0x8a, 0xbd, 0x9c, 0xfb, 0x3b, 0x1d, 0xf0, 0x9a, 0x64, 0xd0, 0x73, 0xf6, 0xfd, + 0xaa, 0xec, 0xd9, 0x71, 0x3f, 0x41, 0x76, 0x66, 0x47, 0xe4, 0x33, 0xd8, 0xa8, 0x55, 0x3b, 0xea, + 0x40, 0xce, 0xe2, 0xeb, 0x04, 0x87, 0x54, 0x9a, 0x76, 0x4e, 0xa0, 0x0e, 0xc2, 0xa8, 0xa8, 0x80, + 0x26, 0x5e, 0xf8, 0xed, 0xcc, 0x40, 0x99, 0xfe, 0x27, 0xbf, 0xfa, 0xa9, 0x40, 0xf4, 0xec, 0xe3, + 0xa6, 0xff, 0xa8, 0x0e, 0x04, 0xee, 0x5a, 0x70, 0x9d, 0x79, 0xb8, 0x9e, 0xfc, 0xb1, 0x89, 0x0c, + 0x68, 0xb5, 0xfc, 0x8a, 0xcd, 0x3f, 0xac, 0xb1, 0xb9, 0xa8, 0x2f, 0x22, 0xae, 0x64, 0xd0, 0x01, + 0x21, 0xe7, 0xc1, 0x36, 0xc9, 0x07, 0xd9, 0x52, 0x88, 0x1f, 0x76, 0x10, 0x09, 0xcc, 0x5c, 0xbf, + 0xd8, 0x29, 0xff, 0xd9, 0x41, 0xb8, 0x4d, 0x44, 0x98, 0x68, 0xd8, 0x72, 0x40, 0x9b, 0x02, 0x14, + 0x0c, 0x3e, 0xaf, 0xe0, 0x03, 0xf5, 0x2d, 0xca, 0xff, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3240,31 +3208,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xa8, 0x3f, 0x96, 0x00, 0x76, 0x81, 0x01, 0x91, 0x3e, 0x7a, 0x81, - 0x8b, 0xdc, 0xa8, 0x69, 0x88, 0xbb, 0x18, 0xdc, 0x91, 0x9b, 0x11, 0x2d, 0x97, 0xc9, 0x35, 0x63, - 0x10, 0x46, 0x17, 0xf0, 0xb3, 0x95, 0xa4, 0x98, 0x8b, 0x0c, 0x14, 0x98, 0x83, 0xdf, 0x9e, 0x69, - 0x98, 0xcd, 0x6c, 0xe2, 0x97, 0x27, 0x94, 0x45, 0x93, 0x04, 0xdc, 0x17, 0x5b, 0x17, 0x6c, 0xa2, - 0x73, 0xd4, 0xf3, 0xa1, 0x70, 0xd7, 0x43, 0x64, 0xbb, 0x83, 0x1b, 0x81, 0xa3, 0xb5, 0x94, 0x29, - 0xfb, 0x81, 0x17, 0x41, 0x66, 0x2e, 0x5a, 0xd3, 0x93, 0x13, 0x78, 0x3c, 0x19, 0xb2, 0xce, 0x0a, - 0xd4, 0xea, 0x56, 0x62, 0xaa, 0xb6, 0x2c, 0x6d, 0x56, 0x7c, 0x5c, 0x96, 0xc9, 0x09, 0xe3, 0x6c, - 0xe6, 0x19, 0x3a, 0x1a, 0xe2, 0xba, 0xdb, 0x9c, 0x9c, 0x62, 0x55, 0x22, 0x26, 0xb9, 0xb3, 0xd8, - 0x26, 0x67, 0xb3, 0x92, 0x72, 0x4b, 0xb2, 0x7a, 0x26, 0x13, 0x91, 0x3d, 0xad, 0xd0, 0xf1, 0x1d, - 0x74, 0x68, 0xc9, 0x6e, 0x14, 0xa5, 0xf4, 0x46, 0x6d, 0x26, 0xaf, 0xc2, 0xe2, 0x48, 0xf0, 0x72, - 0x48, 0xa2, 0xab, 0xcf, 0x79, 0x07, 0xd9, 0x2c, 0x1e, 0xb0, 0xb7, 0x8c, 0xaa, 0x05, 0xd3, 0x91, - 0x9c, 0x2c, 0xe7, 0xf7, 0xd3, 0x11, 0xed, 0x39, 0x5e, 0xa7, 0x33, 0x3d, 0x1d, 0xa8, 0x3d, 0x9f, - 0xd7, 0xfd, 0x5b, 0x9e, 0x50, 0xc2, 0x4b, 0x18, 0x5f, 0x6c, 0xd4, 0x78, 0xac, 0xa1, 0x36, 0x51, - 0x25, 0xfe, 0xb1, 0xf7, 0xb5, 0x76, 0xe6, 0xeb, 0x1c, 0x71, 0x79, 0xd0, 0x4d, 0x0e, 0x55, 0x9c, - 0x73, 0xd4, 0x35, 0x14, 0x89, 0x87, 0xb4, 0xb9, 0x43, 0x64, 0xc5, 0x20, 0xa5, 0xee, 0x6e, 0x83, - 0x63, 0x83, 0x04, 0xa9, 0xb8, 0xcf, 0x2c, 0x9d, 0x70, 0xe3, 0x67, 0x35, 0x24, 0xb5, 0xd3, 0xa0, - 0x18, 0x21, 0xfb, 0xd1, 0x45, 0x5e, 0xd6, 0xd0, 0x02, 0x76, 0xa2, 0x1c, 0xaa, 0x35, 0x12, 0x9b, - 0x04, 0x8a, 0x00, 0xe3, 0xc3, 0xda, 0x84, 0x9e, 0xf7, 0xf5, 0xce, 0x78, 0xb3, 0x9f, 0x4c, 0x3b, - 0x0c, 0xc7, 0xa6, 0x89, 0x7c, 0x39, 0x17, 0x68, 0x9c, 0xda, 0xa6, 0x76, 0x38, 0x39, 0x8b, 0x61, - 0x87, 0x78, 0x64, 0x5c, 0x76, 0x77, 0x76, 0xe9, 0xa4, 0x67, 0x31, 0x43, 0x2f, 0xa8, 0xce, 0xe6, - 0x68, 0x8d, 0xdb, 0x9a, 0x36, 0x81, 0xaf, 0x76, 0xf4, 0x0e, 0x6f, 0x9a, 0xaf, 0xc1, 0x31, 0x71, - 0x57, 0xda, 0xd1, 0x01, 0x3d, 0xb3, 0x10, 0xd5, 0x8f, 0xf0, 0x41, 0x47, 0x60, 0x64, 0x90, 0x40, - 0x81, 0x29, 0xc6, 0xe3, 0x27, 0xa2, 0x8c, 0x72, 0xa4, 0x50, 0xd8, 0x3e, 0x89, 0xf4, 0x81, 0x4d, - 0xfc, 0x33, 0x26, 0x98, 0x25, 0x27, 0xd0, 0xfd, 0x2b, 0x60, 0x69, 0x6a, 0x6b, 0xff, 0x7f, 0x13, - 0x45, 0x88, 0x71, 0x39, 0x6d, 0xf9, 0xc0, 0x35, 0x96, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x5e, 0x0d, 0x4b, 0x7c, 0x9d, 0x68, 0x4f, 0x49, 0x2a, 0x62, 0xd5, + 0x70, 0x54, 0x8c, 0xa4, 0x23, 0xc6, 0x6f, 0x7c, 0x84, 0x29, 0x6d, 0x91, 0x04, 0x14, 0x15, 0xb3, + 0x0e, 0x71, 0xbd, 0x62, 0x7a, 0x6f, 0x9d, 0xd7, 0x7c, 0x4c, 0xf4, 0xc6, 0xbd, 0x59, 0xed, 0x53, + 0xb4, 0xb5, 0x1b, 0x2d, 0x47, 0x21, 0x55, 0xc4, 0x56, 0xb1, 0x17, 0xb7, 0x19, 0xdb, 0x11, 0xb6, + 0x5d, 0xb3, 0x12, 0xdf, 0x5e, 0xac, 0x98, 0xdb, 0x0c, 0x03, 0xc3, 0x88, 0x81, 0xbc, 0xde, 0xf3, + 0x4c, 0x4b, 0x9b, 0xde, 0x04, 0x52, 0x4c, 0xfa, 0xe6, 0xe5, 0x36, 0x53, 0xe4, 0xa9, 0x85, 0xa1, + 0xf2, 0x99, 0x46, 0x78, 0x94, 0xb7, 0x88, 0xe0, 0xfb, 0x2d, 0xf7, 0x3f, 0x83, 0x20, 0x60, 0xd2, + 0x52, 0x4e, 0xf0, 0xc5, 0xbc, 0xf5, 0xcc, 0xd8, 0x42, 0xaf, 0xce, 0x3d, 0x46, 0xe3, 0x7f, 0xc5, + 0x8f, 0x2e, 0x9c, 0x6f, 0x3a, 0x89, 0xd3, 0x0a, 0x3a, 0x27, 0x7f, 0x9e, 0xb9, 0x9e, 0x83, 0x1f, + 0xb3, 0x50, 0xb8, 0x52, 0x21, 0x24, 0xa0, 0xe6, 0x4a, 0x8d, 0xa4, 0x91, 0x75, 0xb9, 0x76, 0x2f, + 0xd5, 0xba, 0x87, 0xf4, 0xf2, 0x65, 0x9f, 0x48, 0xa0, 0xb1, 0x56, 0x29, 0xd9, 0x18, 0x18, 0xb8, + 0xbc, 0xaf, 0xe1, 0x40, 0x35, 0xb0, 0x97, 0x1a, 0x77, 0x6b, 0x33, 0x60, 0x44, 0xc7, 0xd3, 0xb7, + 0xab, 0x19, 0x4f, 0xc4, 0xd4, 0xe0, 0x92, 0x7c, 0x7e, 0x85, 0xc4, 0xf0, 0x95, 0x04, 0xe7, 0xbb, + 0x9d, 0x8d, 0x7b, 0x9e, 0xf2, 0x0c, 0xc9, 0xc6, 0x2c, 0x13, 0xf6, 0xb7, 0xc1, 0x40, 0x5b, 0x4d, + 0xc9, 0x0e, 0xa2, 0x42, 0x72, 0x47, 0x7d, 0xe9, 0xd5, 0x97, 0xb0, 0x5a, 0xbf, 0x46, 0x8f, 0x1d, + 0x77, 0x28, 0x22, 0x39, 0x31, 0x6c, 0x80, 0xc6, 0x2f, 0x56, 0x0b, 0xd1, 0x93, 0x47, 0xcb, 0x93, + 0xc0, 0xd7, 0xbe, 0xfe, 0x21, 0xfd, 0xf2, 0x11, 0x78, 0x6a, 0x5d, 0x4e, 0x44, 0x7f, 0x99, 0x2a, + 0x50, 0x8a, 0x5b, 0x9c, 0x34, 0x50, 0xe1, 0x77, 0xfe, 0xe9, 0x4f, 0xce, 0xc3, 0xf5, 0xb4, 0x4f, + 0xa6, 0x3e, 0x0e, 0x72, 0xc7, 0x51, 0xd9, 0x02, 0xb7, 0x28, 0x7f, 0x27, 0x98, 0xad, 0x14, 0xdd, + 0x3f, 0xbc, 0x01, 0x86, 0xd3, 0xe4, 0x7b, 0x79, 0x9c, 0xa7, 0x08, 0x29, 0xc1, 0x09, 0x62, 0x18, + 0xc8, 0x5e, 0xa1, 0x34, 0xf0, 0xf2, 0x48, 0x9b, 0xc2, 0x43, 0xa9, 0xb6, 0x34, 0xa4, 0x2e, 0x21, + 0xed, 0x94, 0xaa, 0xbb, 0x66, 0x50, 0x5a, 0x45, 0x07, 0x70, 0xd8, 0x46, 0xd7, 0x0e, 0xe3, 0x12, + 0xee, 0x19, 0xad, 0x3e, 0x33, 0x9e, 0xbd, 0x39, 0x61, 0x0c, 0xc7, 0x39, 0x0c, 0x71, 0x01, 0xe3, + 0x4a, 0x8d, 0xd7, 0x6c, 0xa0, 0x34, 0xb0, 0x74, 0x05, 0x0f, 0xcb, 0x02, 0x33, 0x3f, 0x80, 0x71, + 0xe0, 0xf4, 0x09, 0x2b, 0x0d, 0x86, 0xd6, 0xd1, 0xb5, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c index a25f0ca2a..c66c9a3aa 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_GA102.c @@ -34,1597 +34,1586 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37120 -// COMPRESSED SIZE (bytes): 25363 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 25192 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data[] = { - 0xed, 0xfd, 0x43, 0xb4, 0xf0, 0x4c, 0xd7, 0x00, 0x6c, 0x1e, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdf, 0xc7, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xe7, 0xff, 0xc6, 0xef, 0xe4, - 0xef, 0x49, 0xaf, 0x1e, 0xf4, 0x73, 0xcd, 0x32, 0xca, 0x4a, 0xb2, 0x6a, 0x27, 0x7b, 0x57, 0xed, - 0x14, 0x00, 0xc0, 0xff, 0x7f, 0xb3, 0xc1, 0x60, 0x1f, 0x6d, 0xfa, 0x16, 0x6c, 0x59, 0x03, 0xe1, - 0xdf, 0x42, 0xee, 0x0c, 0x3d, 0xc8, 0xc5, 0x63, 0x15, 0x3e, 0x7d, 0xdc, 0x16, 0xc7, 0x2a, 0x76, - 0x66, 0x22, 0xdc, 0x92, 0xb4, 0xe0, 0x26, 0xcc, 0x99, 0xa8, 0xf5, 0x75, 0x8e, 0x09, 0xb5, 0x8b, - 0x50, 0x89, 0x93, 0xba, 0xef, 0x08, 0x28, 0x7a, 0x76, 0xc0, 0xeb, 0xf2, 0xa3, 0xbe, 0x36, 0x1a, - 0x14, 0x7f, 0xcf, 0xfa, 0xe8, 0x3a, 0xed, 0x4a, 0x1d, 0x8b, 0xa5, 0x0e, 0xed, 0x80, 0xac, 0xf6, - 0x49, 0xb3, 0xb9, 0xa1, 0xd8, 0x6c, 0xdb, 0x14, 0xb6, 0xc4, 0x4e, 0x66, 0x09, 0x84, 0xac, 0x0f, - 0xe3, 0x6b, 0xa8, 0xc1, 0xf6, 0xda, 0x28, 0x2b, 0x54, 0xbc, 0x1c, 0xae, 0x3e, 0x3d, 0xba, 0xd6, - 0x11, 0xe6, 0x4e, 0x42, 0xd7, 0xb7, 0x1e, 0xe9, 0x3a, 0x85, 0xd4, 0xbc, 0x17, 0x04, 0xe3, 0x94, - 0x19, 0x8c, 0x9a, 0x5b, 0xf2, 0x93, 0x3b, 0x24, 0x81, 0x17, 0x75, 0x83, 0xa2, 0x80, 0x31, 0x9c, - 0xe5, 0xd0, 0xc4, 0xa8, 0xf7, 0x5f, 0xe2, 0x58, 0x19, 0x0d, 0x0b, 0x26, 0x62, 0xb7, 0xbe, 0x5c, - 0x47, 0xd4, 0x6c, 0x9e, 0x90, 0x38, 0x6c, 0x29, 0x7d, 0x7c, 0x46, 0x2a, 0xb6, 0x98, 0x90, 0x9f, - 0x7f, 0x04, 0xd3, 0x2f, 0xee, 0x42, 0xae, 0x4e, 0x7c, 0x9d, 0xed, 0xbd, 0x4d, 0xe3, 0x07, 0xfb, - 0x92, 0x20, 0xac, 0xa4, 0xa1, 0x4c, 0x1c, 0xa8, 0x61, 0x08, 0x58, 0x18, 0x5d, 0x07, 0xd6, 0xb1, - 0x29, 0x38, 0x77, 0xc3, 0x88, 0x04, 0xce, 0xa6, 0xb3, 0x18, 0xa3, 0xb5, 0x3b, 0xe6, 0x08, 0xb9, - 0xb0, 0x44, 0xed, 0xc4, 0x4a, 0x5f, 0x59, 0xd7, 0x83, 0xdb, 0x40, 0x55, 0x23, 0x82, 0x24, 0x70, - 0xca, 0xf2, 0xcb, 0x00, 0xc4, 0x6e, 0x59, 0x13, 0x54, 0x19, 0x8b, 0x69, 0x58, 0xf2, 0x5a, 0xfd, - 0xb0, 0x49, 0xb9, 0x0d, 0x65, 0x86, 0x80, 0xa1, 0x1e, 0x5f, 0x1d, 0x75, 0x3d, 0x3d, 0x69, 0x0e, - 0xe0, 0x74, 0xae, 0xf5, 0xa5, 0x8a, 0xfc, 0x2d, 0x33, 0x1d, 0x87, 0xb0, 0xcc, 0x4a, 0x46, 0x07, - 0xa7, 0xb2, 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0xff, 0xdf, 0xfd, 0x7f, 0x00, + 0xe6, 0xb0, 0x2b, 0xca, 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1634,8 +1623,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37120, // uncompressed data size (bytes) - 25363, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 25192, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1657,8 +1646,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x05, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x9c, 0xaf, 0x89, 0x9b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1686,1596 +1675,1586 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 37120 -// COMPRESSED SIZE (bytes): 25360 +// DATA SIZE (bytes): 36864 +// COMPRESSED SIZE (bytes): 25188 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_image_prod_data[] = { - 0xed, 0xdd, 0x43, 0xb0, 0x68, 0x3b, 0xd4, 0x20, 0xe0, 0x63, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, - 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x8d, 0x7b, 0x74, 0x8f, 0x6d, 0xdb, 0xb6, 0xfa, 0x1f, 0xbf, 0x49, - 0xf7, 0xa4, 0xab, 0x07, 0x7d, 0xbf, 0x59, 0x46, 0xbb, 0x52, 0xa9, 0xa4, 0x56, 0x56, 0xb2, 0xb2, - 0x01, 0x00, 0xfe, 0xff, 0xa6, 0xd3, 0x7d, 0xd9, 0x2d, 0xf6, 0xf4, 0xa9, 0x17, 0x0f, 0x6f, 0x3d, - 0xdd, 0xe5, 0x7f, 0x50, 0x1e, 0x0b, 0xb3, 0xd0, 0xa1, 0x04, 0x60, 0x8f, 0x04, 0xd9, 0xf7, 0x76, - 0x66, 0xaf, 0x3e, 0x48, 0xdd, 0xfd, 0x68, 0x50, 0x9d, 0x42, 0x78, 0xc4, 0x86, 0x3c, 0x6f, 0x68, - 0xfb, 0xa3, 0x45, 0x38, 0xb2, 0xb7, 0x40, 0x0f, 0x19, 0x0c, 0x34, 0xec, 0xac, 0xa3, 0xb4, 0xb8, - 0xd8, 0xc8, 0xde, 0x97, 0xb7, 0x7f, 0x50, 0x1a, 0x4b, 0x7c, 0xf9, 0xc1, 0x9c, 0x53, 0xbc, 0x44, - 0x70, 0x56, 0xdc, 0xf2, 0xd4, 0x7e, 0x2c, 0xe1, 0x80, 0x7c, 0x10, 0x40, 0x58, 0x01, 0x83, 0x9d, - 0xdb, 0xbf, 0xb3, 0x18, 0x90, 0x2f, 0x40, 0xd7, 0x56, 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0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xe7, 0x3f, 0xff, + 0xf9, 0xcf, 0x7f, 0xfe, 0xf3, 0x9f, 0xff, 0xfc, 0xdf, 0xf7, 0x7f, 0x01, 0x8e, 0x22, 0x30, 0x2a, + 0x00, 0x90, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3285,8 +3264,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 37120, // uncompressed data size (bytes) - 25360, // compressed data size (bytes) + 36864, // uncompressed data size (bytes) + 25188, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3308,8 +3287,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x05, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0xa4, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x9c, 0xaf, 0x89, 0x9b, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x01, 0x62, 0x6d, 0x08, 0x13, 0x4c, 0x24, 0x43, 0x69, + 0x20, 0x00, 0x00, 0x5e, 0xa1, 0x3e, 0xdc, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3342,55 +3321,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0xdb, 0xe8, 0xf7, 0xf0, 0x27, 0xbd, 0x22, 0x57, 0xa9, 0xdf, 0x76, - 0x6d, 0x56, 0x21, 0xbd, 0x9b, 0x4d, 0xf0, 0x28, 0x31, 0x0c, 0x22, 0xd9, 0x16, 0x2b, 0xc7, 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kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 421, // compressed data size (bytes) + 420, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3482,7 +3461,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_GA102_patch_loc_data[] = { - 0x10, 0x65, 0x00, 0x00, + 0x10, 0x64, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c index 107fb2b23..85a74b510 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU102.c @@ -34,1541 +34,1526 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35840 -// COMPRESSED SIZE (bytes): 24474 +// DATA SIZE (bytes): 35584 +// COMPRESSED SIZE (bytes): 24227 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data[] = { 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0x92, 0x9c, 0x63, 0x5c, 0x38, 0xcf, 0x65, 0x75, 0xd8, 0x9a, 0x16, 0x24, + 0x88, 0x26, 0x4c, 0x12, 0x8f, 0xb9, 0xad, 0x81, 0x02, 0xdb, 0xa6, 0x38, 0x06, 0x66, 0x8d, 0x8b, + 0x87, 0xac, 0xf2, 0x59, 0xb0, 0x84, 0xcd, 0xa9, 0xf6, 0xf5, 0xcc, 0x36, 0x08, 0x95, 0x63, 0x12, + 0xc9, 0x59, 0x22, 0xf2, 0x56, 0x37, 0x05, 0x54, 0x29, 0x16, 0x38, 0xf6, 0x75, 0xac, 0x52, 0x3f, + 0xc0, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xff, 0x1b, 0xff, 0x07, 0x4b, 0x13, 0x9e, 0xc7, 0x00, + 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1578,8 +1563,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35840, // uncompressed data size (bytes) - 24474, // compressed data size (bytes) + 35584, // uncompressed data size (bytes) + 24227, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1601,8 +1586,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x6e, 0x8b, 0xb6, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1630,1541 +1615,1526 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35840 -// COMPRESSED SIZE (bytes): 24478 +// DATA SIZE (bytes): 35584 +// COMPRESSED SIZE (bytes): 24227 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_image_prod_data[] = { - 0xed, 0xfc, 0x43, 0x90, 0x28, 0x4d, 0xd7, 0x00, 0xea, 0xb6, 0x6d, 0x5b, 0xbb, 0x6d, 0x9b, 0xbb, - 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x76, 0xf7, 0x79, 0xff, 0x3b, - 0xbb, 0xdf, 0xec, 0x0c, 0x4f, 0xc4, 0x7e, 0x26, 0x99, 0x59, 0x11, 0x55, 0xab, 0x06, 0x95, 0x19, - 0xb5, 0xaa, 0x22, 0x97, 0x38, 0x00, 0xc2, 0x4c, 0x3a, 0x40, 0x2c, 0x00, 0x28, 0x40, 0xf7, 0x51, - 0xde, 0x7b, 0xf3, 0x0f, 0xa0, 0x38, 0x00, 0xe2, 0xff, 0x1d, 0x80, 0x00, 0x05, 0xf8, 0xff, 0x0d, - 0xc3, 0x01, 0x00, 0x00, 0x7f, 0x92, 0x00, 0x7c, 0xe8, 0x00, 0x00, 0xde, 0x80, 0xde, 0x00, 0xde, - 0x81, 0xa2, 0x01, 0x80, 0x00, 0x7a, 0x77, 0x76, 0x7f, 0x7f, 0x7f, 0xe1, 0xc3, 0x01, 0x00, 0x01, - 0x7e, 0x73, 0x41, 0x1a, 0x8f, 0x00, 0x98, 0xd2, 0xd6, 0x01, 0x1b, 0x93, 0x00, 0xa8, 0xd3, 0xd6, - 0x81, 0xfe, 0x6b, 0x48, 0xd2, 0xd6, 0x81, 0xff, 0x6b, 0xf0, 0xfe, 0x3b, 0x17, 0x20, 0x2d, 0x17, - 0xb8, 0x79, 0x17, 0xb8, 0x37, 0x37, 0x6f, 0x37, 0x2d, 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0x74, 0x70, 0x36, 0x52, 0x22, 0x5e, 0xc1, 0x0e, 0x63, 0xcc, + 0x16, 0x89, 0xbe, 0x62, 0xe0, 0x81, 0x04, 0x9f, 0xff, 0xe0, 0x2b, 0xfc, 0xdc, 0xca, 0xbf, 0x1f, + 0xc1, 0xca, 0x51, 0x87, 0xb7, 0x49, 0xdf, 0x2b, 0xbd, 0x5b, 0xf0, 0x76, 0xad, 0x1f, 0x59, 0xb6, + 0x56, 0x52, 0xf1, 0x99, 0x9f, 0xc9, 0x1d, 0x42, 0x22, 0xdb, 0xad, 0xac, 0xc9, 0x39, 0xc2, 0x01, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, + 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, + 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, + 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xbf, 0xf1, 0xff, 0x00, 0x36, 0x68, 0x17, 0x1f, 0x00, + 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3174,8 +3144,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35840, // uncompressed data size (bytes) - 24478, // compressed data size (bytes) + 35584, // uncompressed data size (bytes) + 24227, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3197,8 +3167,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x6e, 0x8b, 0xb6, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3231,7 +3201,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_data[] = { - 0x42, 0x6d, 0x89, 0xe4, 0xc4, 0xbe, 0xa1, 0xcd, 0x38, 0x66, 0xf1, 0xfc, 0x68, 0x01, 0x7d, 0xf0, + 0xc5, 0x93, 0x0d, 0xa9, 0xd2, 0x70, 0x67, 0x4d, 0x95, 0xba, 0x6b, 0x89, 0xcf, 0xd5, 0xbb, 0x09, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3264,7 +3234,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_sig_prod_data[] = { - 0xcd, 0x10, 0x11, 0x8c, 0xd2, 0x97, 0x21, 0xe1, 0xbc, 0xcc, 0x59, 0x48, 0x8c, 0x99, 0x8f, 0xa1, + 0xb7, 0xa4, 0x87, 0x23, 0xda, 0x77, 0x45, 0x37, 0x33, 0xd3, 0xc5, 0x34, 0xa5, 0x94, 0xd3, 0xaf, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3297,7 +3267,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU102_patch_loc_data[] = { - 0x00, 0x62, 0x00, 0x00, + 0x00, 0x61, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c index 1300477da..869417bc1 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterLoadUcode_TU116.c @@ -34,1541 +34,1520 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35840 -// COMPRESSED SIZE (bytes): 24474 +// DATA SIZE (bytes): 35584 +// COMPRESSED SIZE (bytes): 24132 // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data[] = { - 0xed, 0xda, 0x53, 0xac, 0x28, 0x4d, 0x17, 0x30, 0xe8, 0x6d, 0x1b, 0x67, 0xdb, 0xb6, 0x6d, 0xdb, - 0xb6, 0x6d, 0xdb, 0xb6, 0x6d, 0xdb, 0x3c, 0xdb, 0xb6, 0x6d, 0xdb, 0x36, 0xe6, 0xfd, 0xe7, 0x6e, - 0xbe, 0x9b, 0xc9, 0x5c, 0x4e, 0x72, 0x9e, 0xa4, 0xb2, 0x6a, 0x75, 0xd2, 0xbd, 0xfa, 0xa2, 0xba, - 0xd2, 0x55, 0x29, 0x09, 0x00, 0x84, 0x99, 0x0c, 0x80, 0x38, 0x00, 0x50, 0x80, 0xee, 0xa3, 0xfc, - 0xf7, 0x96, 0x1f, 0x40, 0x09, 0x00, 0xc4, 0xff, 0x73, 0x01, 0x02, 0x14, 0xe0, 0xff, 0x4e, 0x23, - 0x00, 0x00, 0x00, 0x7f, 0x92, 0x01, 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0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, - 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0x7f, 0xfe, 0x7f, 0xe3, - 0xff, 0x02, 0xe1, 0x4c, 0x5a, 0x95, 0x00, 0x8c, 0x00, 0x00, + 0xe7, 0x9f, 0x7f, 0xfe, 0xf9, 0xe7, 0x9f, 0xff, 0xdf, 0xf8, 0xbf, 0x00, 0x30, 0xa9, 0xa6, 0x6e, + 0x00, 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1578,8 +1557,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35840, // uncompressed data size (bytes) - 24474, // compressed data size (bytes) + 35584, // uncompressed data size (bytes) + 24132, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1601,8 +1580,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x6e, 0x8b, 0xb6, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1630,1541 +1609,1520 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_dbg_storage_pvt; // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 35840 -// COMPRESSED SIZE (bytes): 24475 +// DATA SIZE (bytes): 35584 +// COMPRESSED SIZE (bytes): 24135 // static BINDATA_CONST NvU8 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0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, + 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, + 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0xf3, 0xcf, 0x3f, 0xff, 0xfc, 0x7f, 0xc6, 0xff, 0x05, 0xd9, + 0x47, 0x1b, 0xdc, 0x00, 0x8b, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3174,8 +3132,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 35840, // uncompressed data size (bytes) - 24475, // compressed data size (bytes) + 35584, // uncompressed data size (bytes) + 24135, // compressed data size (bytes) kgspBinArchiveBooterLoadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -3197,8 +3155,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_image_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x4e, 0x00, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x43, 0x69, - 0x20, 0x00, 0x00, 0x6e, 0x8b, 0xb6, 0xe9, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x8e, 0x07, 0x62, 0x1d, 0x08, 0x13, 0x4c, 0xc4, 0x41, 0x69, + 0x20, 0x00, 0x00, 0x5d, 0x39, 0xf2, 0xda, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3231,7 +3189,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_header_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_data[] = { - 0xfc, 0x18, 0x18, 0x86, 0xe5, 0x7d, 0x71, 0x36, 0xe0, 0x60, 0xde, 0x9c, 0x29, 0x7b, 0x20, 0x82, + 0x8b, 0x1c, 0x78, 0x34, 0xe5, 0x94, 0xac, 0x85, 0x59, 0x61, 0x6e, 0x28, 0x20, 0xca, 0xa6, 0x19, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3264,7 +3222,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_sig_prod_data[] = { - 0x1b, 0x87, 0x49, 0x74, 0xf3, 0xf1, 0xc7, 0xb0, 0xf1, 0x23, 0xb2, 0x1c, 0x47, 0x3f, 0xe2, 0xd3, + 0x95, 0x28, 0x91, 0x0c, 0x23, 0xf7, 0xa5, 0xcc, 0x80, 0x32, 0xd5, 0x1d, 0x15, 0x69, 0x91, 0x78, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -3297,7 +3255,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterLoadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterLoadUcode_TU116_patch_loc_data[] = { - 0x00, 0x62, 0x00, 0x00, + 0x00, 0x61, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c deleted file mode 100644 index c4e1562a8..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA100.c +++ /dev/null @@ -1,1371 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9728 -// COMPRESSED SIZE (bytes): 7415 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_image_dbg_data[] = -{ - 0xed, 0x99, 0x45, 0x50, 0x1d, 0xda, 0xd2, 0x85, 0xcf, 0xc1, 0xdd, 0x35, 0x01, 0x0e, 0xee, 0x0e, - 0xc1, 0xdd, 0xdd, 0x83, 0xbb, 0xbb, 0x04, 0x87, 0xe0, 0xee, 0x4e, 0xf0, 0x83, 0xbb, 0x06, 0x08, - 0xee, 0xc1, 0xdd, 0xdd, 0xdd, 0x5d, 0x83, 0xfc, 0x79, 0xff, 0xf0, 0x8e, 0xde, 0xf8, 0xd5, 0xfd, - 0x26, 0x6b, 0xf5, 0x1e, 0x74, 0x75, 0xd5, 0xaa, 0xda, 0xd5, 0xbb, 0x76, 0x04, 0xc0, 0x1f, 0xf0, - 0x9e, 0x0c, 0xf0, 0x45, 0x05, 0x00, 0x9e, 0x20, 0x9e, 0x00, 0xcf, 0x10, 0x31, 0x00, 0x08, 0x40, - 0xd7, 0xc6, 0xe6, 0xc7, 0xc7, 0x07, 0x6a, 0x04, 0x00, 0x08, 0xf8, 0x00, 0x43, 0xd5, 0xef, 0x01, - 0xd8, 0xd2, 0x96, 0x81, 0xf5, 0xc9, 0x00, 0xfa, 0xb4, 0x65, 0x88, 0xbf, 0x42, 0x91, 0xb6, 0x0c, - 0xf9, 0x57, 0x88, 0x22, 0x00, 0x00, 0x40, 0x1a, 0x18, 0xb2, 0x71, 0x13, 0xb2, 0x0b, 0x9c, 0xbb, - 0x99, 0x06, 0x06, 0xa6, 0xa5, 0x43, 0x34, 0x6e, 0x02, 0x1b, 0x97, 0x21, 0x7c, 0xbb, 0x00, 0x00, - 0x54, 0x16, 0x69, 0x00, 0xda, 0x23, 0x18, 0xd0, 0x91, 0x1c, 0xf7, 0xb7, 0x65, 0xe3, 0x73, 0x40, - 0xe3, 0xb3, 0x7f, 0x04, 0x20, 0x18, 0xf6, 0xef, 0x11, 0x2a, 0x54, 0x73, 0x3a, 0x80, 0x10, 0xe2, - 0x3f, 0x0e, 0xfe, 0xaf, 0x03, 0xfe, 0xbf, 0x03, 0xfe, 0x75, 0x30, 0xff, 0x71, 0x7f, 0xdb, 0x42, - 0xa4, 0xa0, 0xc2, 0x6d, 0xfc, 0x67, 0x84, 0xb7, 0x67, 0xe8, 0x08, 0x00, 0x11, 0xe0, 0x2d, 0x07, - 0xaa, 0x2d, 0x1e, 0xe2, 0x57, 0x32, 0xda, 0xdf, 0xfa, 0xfd, 0x05, 0xe0, 0xfb, 0x77, 0xb0, 0x27, - 0x88, 0x8e, 0xc2, 0x3f, 0xc0, 0xb8, 0xd9, 0x1b, 0xa8, 0x08, 0x34, 0x58, 0x40, 0x2e, 0xf8, 0x09, - 0x10, 0xf7, 0x57, 0xbb, 0x3e, 0xee, 0x98, 0x5f, 0xdf, 0xa5, 0x81, 0xb9, 0x60, 0x81, 0x65, 0xc0, - 0x7f, 0x03, 0x41, 0xf9, 0xf0, 0x16, 0x0b, 0x96, 0x67, 0x70, 0xdf, 0x96, 0xac, 0xb1, 0x68, 0x13, - 0x63, 0xd0, 0xb3, 0x98, 0xe4, 0x13, 0xe1, 0x64, 0x2b, 0xb3, 0x8c, 0xd6, 0x3a, 0xca, 0xd5, 0xb2, - 0xb5, 0x50, 0x41, 0xd4, 0xbd, 0x99, 0x6a, 0x24, 0x7f, 0x57, 0x18, 0xa7, 0x6d, 0xd1, 0xe3, 0x19, - 0x8d, 0x9b, 0x5b, 0x70, 0xe3, 0x37, 0xbc, 0x99, 0x96, 0x21, 0xfe, 0x68, 0x39, 0x32, 0x42, 0x9b, - 0xa8, 0xa0, 0x21, 0x8e, 0x92, 0x80, 0xf2, 0x83, 0x0a, 0x58, 0xb3, 0x10, 0x37, 0xa1, 0x94, 0x6e, - 0xee, 0x13, 0x6c, 0x7c, 0xce, 0x31, 0x1c, 0xb2, 0x52, 0xa2, 0x4f, 0x92, 0x3f, 0x8c, 0xf3, 0x29, - 0x10, 0x26, 0x2c, 0x18, 0xbd, 0x37, 0xbd, 0x9a, 0x28, 0x83, 0xfc, 0x8f, 0x33, 0x2c, 0x11, 0x86, - 0x26, 0x1c, 0xce, 0x65, 0x09, 0x24, 0x87, 0x02, 0xf9, 0x2f, 0x81, 0x20, 0x19, 0x62, 0x94, 0xcb, - 0x17, 0xb2, 0xe3, 0xad, 0xc8, 0xad, 0xa6, 0x17, 0xd1, 0xf5, 0x59, 0xcd, 0xcc, 0xad, 0xb8, 0x1d, - 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-#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 9728, // uncompressed data size (bytes) - 7415, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_image_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("header_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_header_dbg_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x03, 0x62, 0x76, 0x08, 0x13, 0x4c, 0xc8, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x64, 0x80, 0xce, 0x2d, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_header_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_header_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("image_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9728 -// COMPRESSED SIZE (bytes): 7415 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_image_prod_data[] = -{ - 0xed, 0x99, 0x45, 0x50, 0x1d, 0xda, 0xd2, 0x85, 0x0f, 0xee, 0x16, 0xdc, 0xdd, 0xdd, 0xdd, 0xdd, - 0x5d, 0x83, 0x13, 0x08, 0x0e, 0x41, 0x83, 0xbb, 0xbb, 0xbb, 0x3b, 0x27, 0x9c, 0xe0, 0xee, 0xee, - 0xee, 0x01, 0x0e, 0xee, 0x10, 0x34, 0x38, 0xfc, 0x79, 0xff, 0xf0, 0x8e, 0xde, 0xf8, 0xd5, 0xfd, - 0x26, 0x6b, 0xf5, 0x1e, 0x74, 0x75, 0xd5, 0xaa, 0xda, 0xd5, 0xbb, 0x76, 0x14, 0x20, 0x10, 0xf0, - 0x9e, 0x0a, 0xf0, 0x47, 0x03, 0x00, 0x1e, 0x21, 0x1f, 0x01, 0x4f, 0x90, 0x71, 0x00, 0x48, 0x40, - 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9728, // uncompressed data size (bytes) - 7415, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_image_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("header_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_header_prod_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x03, 0x62, 0x76, 0x08, 0x13, 0x4c, 0xc8, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x64, 0x80, 0xce, 0x2d, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_header_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_header_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("sig_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_dbg_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_sig_dbg_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x16, 0xc5, 0x11, 0xb9, 0xdd, 0xe0, 0xf6, 0xae, 0x5a, 0x47, 0x43, - 0xb6, 0x39, 0x2e, 0xdd, 0x01, 0xa7, 0x5d, 0x5f, 0x05, 0x75, 0xc8, 0xa8, 0xc9, 0xa5, 0xad, 0xde, - 0xf5, 0xe5, 0xa7, 0x0e, 0xfd, 0xd7, 0xa8, 0x85, 0xee, 0x53, 0xce, 0x9a, 0x04, 0x78, 0x5f, 0x79, - 0x7b, 0xd6, 0x56, 0xcf, 0xb0, 0x25, 0x23, 0x45, 0xe8, 0x78, 0xa8, 0x9b, 0x72, 0x31, 0xe4, 0x3c, - 0x16, 0x56, 0x5a, 0x01, 0x2c, 0xe9, 0xf6, 0xaa, 0x89, 0xb2, 0xf7, 0xb1, 0x1c, 0xa4, 0xeb, 0xb8, - 0xa1, 0x61, 0x72, 0xc8, 0xf1, 0xa0, 0x18, 0x41, 0x20, 0x26, 0xcf, 0xb7, 0xeb, 0x89, 0x6a, 0x44, - 0xb3, 0x0c, 0xe3, 0xee, 0x30, 0xf1, 0xd1, 0x2d, 0x34, 0xb5, 0x23, 0x69, 0xfc, 0x6c, 0xc6, 0xa2, - 0x27, 0x2f, 0xa5, 0x24, 0x05, 0x7a, 0x21, 0x6a, 0x18, 0xf2, 0x50, 0xd9, 0xfc, 0x0f, 0x92, 0xe1, - 0x96, 0xf9, 0x3d, 0xb4, 0x90, 0x14, 0x95, 0xb0, 0xd7, 0x04, 0xf1, 0xd4, 0xa3, 0xd0, 0x9e, 0x3f, - 0x56, 0x28, 0x6d, 0x9e, 0x87, 0x9d, 0xd7, 0xd0, 0x43, 0x0a, 0x0d, 0xce, 0x9e, 0xfe, 0xe8, 0x4f, - 0x4d, 0x62, 0xaa, 0xcd, 0xbb, 0x23, 0xc6, 0x0a, 0x31, 0xa3, 0x0b, 0x53, 0x68, 0x68, 0xe0, 0xbd, - 0x63, 0x7d, 0xa4, 0x01, 0xda, 0xd0, 0x9b, 0x0b, 0x0e, 0x55, 0x14, 0xfb, 0x16, 0x55, 0x6c, 0x0f, - 0x21, 0x9f, 0xc3, 0xb8, 0x44, 0x89, 0x8a, 0x4e, 0x71, 0x86, 0x3f, 0x83, 0x3b, 0x04, 0x65, 0xe5, - 0x46, 0xd6, 0x26, 0x54, 0x39, 0x4f, 0x51, 0xed, 0x79, 0xf7, 0x55, 0x3a, 0xe2, 0xcb, 0x4d, 0x9c, - 0xdf, 0x52, 0x25, 0xd8, 0x6a, 0x3a, 0xf9, 0x6e, 0x5f, 0x47, 0x8f, 0xb7, 0xa6, 0xac, 0xf8, 0x99, - 0x53, 0x52, 0xc6, 0xc9, 0xd8, 0xda, 0x49, 0x77, 0xcc, 0x76, 0x15, 0x2b, 0xd4, 0x45, 0xc7, 0xfb, - 0x21, 0xa9, 0x0e, 0x4a, 0x82, 0x23, 0x16, 0x22, 0x2d, 0xc0, 0x14, 0x96, 0xa2, 0x60, 0xa0, 0xf5, - 0xa6, 0xa8, 0x87, 0x09, 0xbc, 0xc7, 0x8e, 0x60, 0xb5, 0x3b, 0x65, 0xeb, 0xb4, 0x7b, 0x61, 0xaa, - 0xc0, 0xe0, 0x78, 0xbd, 0x69, 0xb7, 0x31, 0x91, 0xf9, 0x29, 0x31, 0xe6, 0x5b, 0x62, 0x17, 0xb7, - 0xc2, 0x35, 0x12, 0x30, 0x5f, 0xca, 0xf7, 0xac, 0x90, 0x38, 0x31, 0xc8, 0x81, 0x44, 0xbb, 0xce, - 0xd9, 0x82, 0xc4, 0xfb, 0x8c, 0x9d, 0xdc, 0x42, 0x66, 0xeb, 0x1a, 0xa2, 0xa3, 0x87, 0xad, 0x61, - 0x75, 0xc4, 0x44, 0x36, 0x15, 0x48, 0x53, 0x47, 0xbf, 0xfb, 0xa9, 0x32, 0xbb, 0x5c, 0x71, 0xb7, - 0x01, 0xcb, 0x6a, 0xeb, 0x08, 0x4e, 0x50, 0xc6, 0x8a, 0x92, 0x0e, 0xa0, 0xc0, 0x11, 0xea, 0x81, - 0x72, 0x32, 0x74, 0x70, 0x76, 0x2f, 0x3f, 0x04, 0xc6, 0x99, 0x5d, 0xe0, 0xcb, 0x55, 0xf9, 0x14, - 0x52, 0x5b, 0x6f, 0x7f, 0xb6, 0x2c, 0x6c, 0xa1, 0xb9, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_sig_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("sig_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_prod_ga100 -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 384 -// COMPRESSED SIZE (bytes): 397 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_sig_prod_data[] = -{ - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xf8, 0xeb, 0xf9, 0xc0, 0x24, 0x01, 0x91, 0x70, 0x0b, 0x79, 0x99, - 0x44, 0x86, 0x86, 0x99, 0xdf, 0xc1, 0xca, 0x6f, 0xc4, 0x11, 0x3a, 0xb4, 0xed, 0x0c, 0x6f, 0xea, - 0xeb, 0xa3, 0xa5, 0xe9, 0x0a, 0x5a, 0x40, 0xfe, 0x23, 0x29, 0x61, 0x95, 0x00, 0xeb, 0x3a, 0x88, - 0x35, 0xa6, 0xe5, 0x35, 0x73, 0xed, 0x38, 0x32, 0x04, 0x36, 0x9e, 0x3b, 0xd3, 0xa3, 0x04, 0xf8, - 0xc7, 0xf7, 0xb4, 0x58, 0xe2, 0x94, 0x70, 0x00, 0xfa, 0x67, 0x68, 0x5d, 0xab, 0xbc, 0xbd, 0xc5, - 0xa2, 0x33, 0x87, 0x00, 0x2b, 0x54, 0x78, 0xd6, 0x4f, 0xfa, 0xac, 0x36, 0xe0, 0x39, 0xc2, 0xb1, - 0xd5, 0xb4, 0xd1, 0xa3, 0xc8, 0xab, 0x81, 0x74, 0x49, 0xc2, 0x5d, 0xf7, 0xb2, 0x4f, 0x72, 0x64, - 0x03, 0x12, 0xf3, 0xfc, 0xa6, 0x76, 0xf3, 0x86, 0x13, 0xfd, 0x84, 0xb7, 0x64, 0x09, 0xc4, 0x52, - 0x78, 0xfd, 0x26, 0x0c, 0x16, 0x55, 0x3b, 0x1c, 0x1a, 0x86, 0x13, 0xb8, 0xe0, 0xfb, 0x47, 0x19, - 0x45, 0xc8, 0xc7, 0xfe, 0x4b, 0xc4, 0xe1, 0xbc, 0x43, 0xce, 0x97, 0x62, 0xc7, 0xa3, 0x40, 0x9d, - 0xdb, 0xc7, 0xc6, 0x0b, 0x93, 0xdf, 0xaf, 0x63, 0x71, 0x1f, 0x05, 0x38, 0xc3, 0x51, 0x76, 0x1c, - 0x6e, 0x19, 0x86, 0x60, 0xe8, 0xe2, 0xff, 0x9b, 0x72, 0x31, 0xd0, 0x62, 0xde, 0x96, 0x71, 0xf6, - 0x9b, 0xa9, 0x7c, 0xcd, 0x75, 0xac, 0xa3, 0x65, 0x57, 0x43, 0x71, 0x0f, 0xb4, 0x2b, 0x7e, 0xa8, - 0x18, 0x6a, 0x83, 0x04, 0x90, 0xc7, 0xef, 0xe0, 0xdc, 0xf1, 0x02, 0x7f, 0x70, 0x16, 0xe5, 0x4e, - 0xb4, 0xcc, 0x7c, 0x49, 0x30, 0x64, 0x95, 0x72, 0x50, 0x34, 0xe3, 0x9d, 0x11, 0xd9, 0xcc, 0xc9, - 0xb0, 0xd1, 0x78, 0x5a, 0x0f, 0x45, 0x41, 0x8d, 0xb3, 0xa9, 0xeb, 0x4e, 0x3b, 0xdd, 0xe9, 0x3d, - 0x28, 0xd8, 0x46, 0xfa, 0x6c, 0xcf, 0x3f, 0x09, 0xa7, 0x2c, 0xde, 0x44, 0x14, 0xd1, 0x83, 0x54, - 0xe8, 0x6c, 0xa6, 0xf3, 0x48, 0xe2, 0xad, 0xa6, 0xcb, 0x57, 0x46, 0x04, 0xdd, 0xf0, 0xaf, 0x03, - 0x9a, 0x69, 0x7f, 0x64, 0xe1, 0xe2, 0x05, 0x81, 0x1a, 0xb1, 0x79, 0x3b, 0x95, 0x12, 0x42, 0xb4, - 0x44, 0x3d, 0x62, 0x06, 0x4f, 0xc7, 0xe8, 0xdc, 0x58, 0xc2, 0xf2, 0x47, 0x86, 0x53, 0xf6, 0xc8, - 0x74, 0x14, 0xb6, 0x8b, 0x7e, 0x1b, 0x36, 0xfd, 0x70, 0x55, 0x84, 0xd6, 0x38, 0xd3, 0x65, 0x2b, - 0xf0, 0xac, 0x1d, 0x8b, 0x0b, 0x04, 0x8c, 0x06, 0x28, 0x2d, 0x23, 0x67, 0x2f, 0x24, 0x0c, 0x3c, - 0x5e, 0xf6, 0x28, 0x8c, 0x74, 0x19, 0x2b, 0xcd, 0x64, 0xcb, 0x7e, 0x91, 0x91, 0x30, 0x59, 0x55, - 0x6b, 0x22, 0x86, 0xf2, 0x83, 0xe3, 0xf1, 0x6e, 0x1d, 0x36, 0x30, 0x62, 0xd8, 0x8b, 0xe8, 0xe8, - 0xe4, 0xce, 0x6b, 0x2b, 0x9c, 0x32, 0x5e, 0xcc, 0x39, 0x80, 0x01, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_sig_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 384, // uncompressed data size (bytes) - 397, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("patch_loc") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga100_patch_location -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_patch_loc_data[] = -{ - 0x00, 0x20, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_patch_loc_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_patch_loc_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("patch_sig") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga100_patch_signature -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_patch_sig_data[] = -{ - 0x00, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_patch_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_patch_sig_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("patch_meta") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga100_patch_meta_data -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_patch_meta_data[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_patch_meta_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 12, // uncompressed data size (bytes) - 12, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_patch_meta_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA100("num_sigs") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga100/reload/g_booteruc_reload_ga100_ga100_rsa3k_1_sig.h -// FILE TYPE: TEXT -// VAR NAME: num_sigs_per_ucode -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA100_num_sigs_data[] = -{ - 0x01, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA100_num_sigs_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA100_num_sigs_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterReloadUcode_GA100 = -{ - 10, // entryNum - { - // entries[] : { "name", pBinStorage } - { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_image_dbg_storage_pvt }, - { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_header_dbg_storage_pvt }, - { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_image_prod_storage_pvt }, - { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_header_prod_storage_pvt }, - { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_sig_dbg_storage_pvt }, - { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_sig_prod_storage_pvt }, - { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_patch_loc_storage_pvt }, - { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_patch_sig_storage_pvt }, - { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_patch_meta_storage_pvt }, - { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA100_num_sigs_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_GA100(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveBooterReloadUcode_GA100; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c deleted file mode 100644 index 8d62142a8..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_GA102.c +++ /dev/null @@ -1,1443 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9728 -// COMPRESSED SIZE (bytes): 7779 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_image_dbg_data[] = -{ - 0xed, 0xd9, 0x53, 0x77, 0x1d, 0x80, 0xb6, 0x36, 0xe0, 0xa8, 0xb1, 0x6d, 0xb3, 0x61, 0x63, 0xa3, - 0xb1, 0x6d, 0x3b, 0x2b, 0xb6, 0xb9, 0x56, 0x9c, 0xc6, 0xb6, 0x6d, 0x63, 0xc5, 0x46, 0x63, 0xdb, - 0x69, 0x93, 0x34, 0xb6, 0xbf, 0xef, 0x7a, 0xff, 0x81, 0x33, 0xce, 0x38, 0xfb, 0xb9, 0x9b, 0xd7, - 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-#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_image_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 9728, // uncompressed data size (bytes) - 7779, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_image_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("header_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_header_dbg_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x56, 0x00, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xfe, 0x9c, 0x72, 0x04, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_header_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_header_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("image_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9728 -// COMPRESSED SIZE (bytes): 7780 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_image_prod_data[] = -{ - 0xed, 0xd9, 0xd3, 0x5b, 0x25, 0x00, 0xd7, 0x36, 0xf0, 0x6c, 0xdb, 0x98, 0x26, 0xdb, 0xd8, 0x35, - 0xd9, 0xd8, 0xd9, 0xd3, 0xc4, 0x9d, 0x6d, 0xdb, 0xdc, 0x61, 0xc7, 0xc9, 0x4d, 0xb6, 0x6d, 0x4e, - 0x9c, 0x6c, 0xbb, 0x26, 0xbb, 0xa9, 0xf7, 0x3d, 0x7e, 0xfe, 0x81, 0xf7, 0xfa, 0xae, 0xef, 0xf9, - 0x9d, 0xad, 0xe3, 0x75, 0xad, 0x83, 0xfb, 0x5e, 0x50, 0x50, 0xff, 0x7f, 0x4b, 0x8a, 0xa1, 0x47, - 0xce, 0x02, 0x89, 0x59, 0xa7, 0xee, 0x71, 0xa5, 0x8b, 0x47, 0xd2, 0x15, 0xee, 0xfc, 0x61, 0x47, - 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-#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 9728, // uncompressed data size (bytes) - 7780, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_image_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("header_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_header_prod_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x56, 0x00, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x43, 0x69, - 0x20, 0x00, 0x00, 0xfe, 0x9c, 0x72, 0x04, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_header_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_header_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("sig_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_dbg_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 781 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_sig_dbg_data[] = -{ - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x6b, 0xef, 0x6d, 0x57, 0x45, 0x00, 0x70, 0xde, 0x18, 0x97, 0x1f, - 0x61, 0x4f, 0xa5, 0x80, 0xfa, 0x38, 0xcd, 0x7d, 0xd5, 0xf4, 0xab, 0x86, 0x92, 0x13, 0x21, 0x9b, - 0x31, 0x7f, 0x0f, 0xd3, 0x12, 0x70, 0xdc, 0xca, 0x5b, 0xdd, 0x8a, 0xf4, 0x9c, 0xa0, 0x73, 0x43, - 0x52, 0x33, 0x9f, 0xd4, 0x28, 0xd9, 0xad, 0x77, 0xe5, 0xa4, 0xdf, 0x8c, 0xc0, 0x1b, 0x99, 0x1f, - 0x9d, 0x6a, 0xe4, 0x1b, 0x4d, 0x51, 0x42, 0x66, 0x1c, 0x4d, 0xfc, 0x66, 0x72, 0x44, 0x26, 0x69, - 0x73, 0xcc, 0x45, 0xb2, 0xbb, 0xa4, 0xd9, 0x79, 0x82, 0x86, 0xc2, 0x2f, 0x8a, 0x95, 0xf8, 0x38, - 0x68, 0x96, 0x67, 0xfa, 0x8d, 0xbe, 0xa3, 0xd9, 0x25, 0xc9, 0x4d, 0x92, 0xce, 0x88, 0xfb, 0x8f, - 0x02, 0x64, 0x5f, 0x98, 0x52, 0x0f, 0x18, 0x47, 0x6f, 0xc1, 0x5d, 0x99, 0xaa, 0xc7, 0xf9, 0x4f, - 0xba, 0x00, 0x1d, 0x27, 0x5d, 0xb9, 0xf4, 0x04, 0xfe, 0xd1, 0x6a, 0x3c, 0x07, 0xd8, 0xdb, 0xac, - 0xdc, 0xa3, 0x70, 0xe1, 0x98, 0x1d, 0x10, 0xe7, 0x84, 0xd3, 0xfb, 0xb8, 0xd9, 0xf7, 0x09, 0x0b, - 0x74, 0x31, 0xde, 0xb7, 0xf3, 0x43, 0x2e, 0xd6, 0xa7, 0x2c, 0x78, 0x0e, 0xb6, 0x5c, 0xe2, 0xac, - 0x09, 0x3b, 0x79, 0x2b, 0x62, 0xd3, 0x60, 0xf6, 0x70, 0x57, 0x46, 0x5d, 0xbd, 0x3a, 0xcc, 0xc9, - 0x8c, 0xd5, 0x85, 0x83, 0xd5, 0x2d, 0xeb, 0x04, 0x7c, 0xb9, 0xf4, 0x36, 0x5e, 0x43, 0xc5, 0x84, - 0xa2, 0x31, 0x4e, 0x57, 0x89, 0xcd, 0x6e, 0x35, 0xca, 0x9c, 0xa4, 0xe0, 0x46, 0xeb, 0x54, 0x59, - 0xbe, 0x54, 0x48, 0xd3, 0x39, 0xbc, 0x07, 0x95, 0xe3, 0xa9, 0x59, 0x5c, 0xce, 0x2d, 0x0b, 0x34, - 0x6d, 0x87, 0x4c, 0x0e, 0xad, 0x22, 0x64, 0x88, 0x3d, 0xa0, 0x42, 0x7e, 0x9c, 0x90, 0x16, 0xd8, - 0x86, 0x57, 0x03, 0x65, 0x13, 0x78, 0x9a, 0x6b, 0xcf, 0x53, 0x9b, 0x42, 0x55, 0x0b, 0xab, 0x8d, - 0xda, 0x91, 0xd4, 0x99, 0x99, 0x57, 0x1d, 0x5c, 0xe6, 0x22, 0xec, 0x3a, 0x67, 0xe7, 0x85, 0xfe, - 0x5a, 0x4b, 0x26, 0x31, 0x7b, 0x2e, 0xc0, 0xb0, 0xfb, 0xb0, 0xdb, 0x44, 0x50, 0x90, 0x13, 0xa1, - 0x79, 0xca, 0x39, 0x8b, 0x7d, 0xa7, 0x0b, 0xad, 0x13, 0xac, 0x35, 0xdb, 0x83, 0xb1, 0xfc, 0x49, - 0xf8, 0x45, 0xe4, 0x21, 0xbb, 0x2e, 0xba, 0x6d, 0x79, 0xf3, 0xb7, 0x03, 0x70, 0x07, 0x18, 0x0c, - 0x45, 0xb9, 0xd6, 0x53, 0xf7, 0x52, 0x4b, 0x9e, 0xe0, 0x77, 0x49, 0x0a, 0xe9, 0xdc, 0x2b, 0x50, - 0xe1, 0xb6, 0xd9, 0xe3, 0xcd, 0x6b, 0xff, 0xab, 0x6e, 0x3e, 0x03, 0x85, 0x97, 0x7d, 0x50, 0xc2, - 0x74, 0x10, 0xaa, 0x66, 0xee, 0x20, 0x22, 0x50, 0x99, 0xaa, 0x23, 0xee, 0x36, 0x8f, 0x05, 0xab, - 0x61, 0xba, 0xcb, 0xfa, 0x6c, 0x2c, 0x2a, 0xe1, 0xf0, 0x42, 0x6b, 0xe5, 0x97, 0x6b, 0x9b, 0x88, - 0xb0, 0x1f, 0x61, 0x10, 0x8c, 0x93, 0x9b, 0x7b, 0x0a, 0x39, 0xbf, 0xcd, 0xa1, 0xde, 0x2e, 0x9d, - 0xcf, 0x76, 0xa3, 0x7b, 0x2b, 0x80, 0xbf, 0x13, 0x78, 0xd2, 0x09, 0xbf, 0xd5, 0xfa, 0x39, 0x1a, - 0x18, 0x7f, 0x64, 0xfd, 0x63, 0x12, 0x3b, 0x58, 0x6f, 0xff, 0xef, 0xc1, 0xe3, 0xb3, 0xbe, 0x4e, - 0xc1, 0xf8, 0xfd, 0x57, 0x26, 0x51, 0xde, 0x17, 0x42, 0xaa, 0x44, 0x1a, 0x70, 0xa5, 0xb9, 0x62, - 0x48, 0x4a, 0x6d, 0x7c, 0x69, 0x09, 0x41, 0x4a, 0x02, 0x90, 0x7c, 0x83, 0x79, 0xd4, 0xb5, 0x25, - 0x7c, 0xff, 0x8f, 0xfa, 0xfe, 0xa2, 0x99, 0xf3, 0x05, 0xe7, 0xab, 0x6d, 0x0f, 0x8f, 0xb2, 0xbe, - 0xc9, 0x58, 0xa1, 0x73, 0xf7, 0x63, 0x43, 0xef, 0x32, 0xa0, 0x3e, 0xd4, 0x58, 0x79, 0x13, 0x49, - 0x3a, 0x92, 0xb1, 0x76, 0xbf, 0x9b, 0x98, 0xa9, 0x94, 0xf1, 0xb8, 0xcc, 0xf1, 0x44, 0x8e, 0xbd, - 0xd3, 0x32, 0x2b, 0xe0, 0x7e, 0xa2, 0x02, 0xfd, 0x75, 0xdd, 0xcf, 0x47, 0x2e, 0x7f, 0x93, 0x73, - 0xb9, 0xff, 0x75, 0xbf, 0xdd, 0x86, 0x55, 0x6a, 0xe6, 0x64, 0x4d, 0x31, 0x9d, 0x72, 0x77, 0x5c, - 0xfe, 0x2d, 0x7e, 0x73, 0x2a, 0xfa, 0x46, 0xb1, 0x86, 0xdf, 0x76, 0x0d, 0x41, 0xf2, 0x92, 0xfd, - 0x0d, 0x72, 0xaf, 0xd5, 0x2c, 0x8b, 0xcb, 0x08, 0x6a, 0xcf, 0x8d, 0x40, 0xda, 0x95, 0x36, 0xe9, - 0x86, 0xfe, 0xc9, 0x1e, 0x9d, 0xf9, 0xa0, 0x26, 0x45, 0xf4, 0x40, 0xcc, 0xcb, 0x51, 0xcc, 0x52, - 0x71, 0x71, 0x80, 0x26, 0x38, 0x91, 0x40, 0xc6, 0xaf, 0x3e, 0x1b, 0x28, 0x1f, 0x36, 0x09, 0xf2, - 0x10, 0x61, 0xd3, 0x12, 0x4f, 0xd5, 0x6f, 0x37, 0xd5, 0x23, 0xb6, 0x9e, 0x25, 0x12, 0xa8, 0x2e, - 0xb1, 0xf3, 0x13, 0x8f, 0xed, 0x44, 0x90, 0xfe, 0x64, 0xf7, 0x96, 0xc1, 0xaf, 0x24, 0x83, 0xf0, - 0xcd, 0x62, 0xf1, 0xe5, 0xa3, 0xe1, 0x2e, 0x65, 0x47, 0xb8, 0xce, 0x6c, 0xfe, 0x2c, 0x50, 0xbd, - 0x7a, 0x29, 0x3b, 0xd0, 0xce, 0x93, 0x1a, 0x57, 0xb2, 0xbd, 0x19, 0xba, 0x43, 0x4d, 0x62, 0x22, - 0xbc, 0x29, 0xfe, 0xa1, 0x49, 0x1e, 0xd3, 0xc9, 0x91, 0x6a, 0xac, 0x31, 0x33, 0x4b, 0x9b, 0x08, - 0xc5, 0x25, 0xea, 0x42, 0xb2, 0x3b, 0x29, 0xb1, 0xf1, 0x4f, 0xc0, 0x77, 0x98, 0x10, 0x29, 0x2b, - 0xd7, 0x96, 0x64, 0x2c, 0x16, 0x05, 0xa9, 0xa3, 0xdd, 0x7c, 0x12, 0x39, 0x47, 0x94, 0x8b, 0x64, - 0x98, 0xfe, 0x7a, 0x2d, 0x63, 0x07, 0xa0, 0xf8, 0xcd, 0xe0, 0x00, 0x28, 0xcb, 0x94, 0xe1, 0x91, - 0xf6, 0x18, 0xfa, 0x34, 0xb2, 0xaf, 0x8b, 0xef, 0x21, 0x1a, 0x08, 0xcb, 0x05, 0x5e, 0xf0, 0x28, - 0x63, 0x67, 0x06, 0x6a, 0x3c, 0xe4, 0x88, 0x3e, 0x79, 0x00, 0x03, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_sig_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 768, // uncompressed data size (bytes) - 781, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_sig_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("sig_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_prod_ga10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 420 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_sig_prod_data[] = -{ - 0x13, 0x92, 0x50, 0x3e, 0xa9, 0x2d, 0x79, 0x60, 0x61, 0xf2, 0x54, 0x46, 0x11, 0x9f, 0x88, 0x09, - 0x95, 0xbf, 0xb6, 0x29, 0x29, 0xda, 0x57, 0x79, 0x4c, 0x67, 0x99, 0x11, 0x1f, 0xa8, 0x5e, 0x5a, - 0xc2, 0xb7, 0x4c, 0xce, 0x8b, 0xe9, 0x5d, 0x75, 0x6e, 0x90, 0xf8, 0x16, 0x99, 0x68, 0xc1, 0x7e, - 0xce, 0x8f, 0x4f, 0x5f, 0x64, 0xcb, 0xbf, 0xb0, 0xb5, 0xf2, 0x10, 0x38, 0xf4, 0xa7, 0x54, 0xfe, - 0xd2, 0xef, 0x9a, 0x0b, 0x8b, 0x3e, 0xc6, 0x39, 0x1c, 0xc8, 0x77, 0x2e, 0xde, 0xfc, 0x5b, 0x7b, - 0x9b, 0x91, 0xce, 0xf2, 0xc3, 0x3b, 0xcd, 0x56, 0x95, 0xc5, 0xca, 0xf7, 0xba, 0xeb, 0x1e, 0x3d, - 0xa4, 0xb2, 0xd4, 0xe3, 0xcb, 0x1b, 0x59, 0x03, 0x5b, 0x81, 0xe4, 0x3d, 0x56, 0xc1, 0x9f, 0x44, - 0x9e, 0xd5, 0x3c, 0xf7, 0x94, 0x2a, 0x59, 0x9b, 0xf0, 0x70, 0xd3, 0xdd, 0x90, 0x6f, 0xb3, 0xe7, - 0x9f, 0x8a, 0x3d, 0x20, 0xcc, 0x2c, 0x1c, 0xb0, 0x72, 0x6d, 0x48, 0xc2, 0xbb, 0x8f, 0x5f, 0x9d, - 0xc3, 0x1e, 0x84, 0x2f, 0x33, 0x98, 0x7b, 0x48, 0xde, 0x7b, 0x9f, 0xb0, 0xd1, 0x11, 0xf5, 0xe7, - 0xdc, 0x55, 0x1b, 0x73, 0x02, 0x45, 0xb5, 0xd7, 0x78, 0xfb, 0xdc, 0xa9, 0x3d, 0xfe, 0x62, 0xfa, - 0xad, 0x80, 0x0e, 0x71, 0x56, 0xa7, 0xdc, 0x15, 0x77, 0xca, 0x7f, 0x4e, 0xde, 0xe4, 0xf1, 0x68, - 0x63, 0xf7, 0xe2, 0xa7, 0x8f, 0x55, 0x8a, 0x26, 0x1d, 0x16, 0xd1, 0xb4, 0xd1, 0xff, 0xb0, 0x33, - 0xe5, 0xfe, 0xc1, 0x55, 0xa9, 0x5a, 0xe9, 0x93, 0x9e, 0xfd, 0xbd, 0x21, 0xa8, 0x7b, 0x68, 0x45, - 0xce, 0xa7, 0x69, 0x92, 0xe9, 0x6b, 0x37, 0xe6, 0xbc, 0x5e, 0xb9, 0xb5, 0xb8, 0xb1, 0xbe, 0xb7, - 0xf3, 0x50, 0xbc, 0x55, 0xcb, 0x7b, 0x57, 0x11, 0x49, 0xdf, 0xd5, 0x5b, 0xed, 0x2f, 0x9f, 0x52, - 0xf3, 0x76, 0xf0, 0xba, 0x1e, 0xbf, 0x61, 0xed, 0xca, 0x30, 0x07, 0xc5, 0x05, 0xc7, 0x94, 0x17, - 0xe9, 0xfc, 0x5a, 0xb1, 0x6c, 0xd2, 0x54, 0x87, 0x3f, 0x17, 0x0b, 0x35, 0x53, 0x59, 0xae, 0xa4, - 0x1f, 0x5d, 0x6f, 0x26, 0x55, 0x5b, 0x79, 0xe4, 0xeb, 0xee, 0xd9, 0x5f, 0x8a, 0xb2, 0xe4, 0xf6, - 0x3d, 0x59, 0xf0, 0x4d, 0x71, 0xe6, 0x9c, 0x29, 0xfa, 0xbb, 0xa4, 0x9a, 0x7f, 0x70, 0x44, 0x18, - 0xa8, 0x3c, 0xdb, 0x39, 0x9d, 0xb9, 0x90, 0x47, 0x3d, 0x9e, 0xaf, 0x26, 0xf9, 0xb7, 0x93, 0xe8, - 0xaf, 0x2d, 0x4f, 0x37, 0xf9, 0x6f, 0x77, 0x90, 0xf1, 0x3a, 0xbc, 0xbb, 0x7a, 0xcb, 0x11, 0xa3, - 0x7d, 0xdd, 0x17, 0xde, 0x56, 0x56, 0x1f, 0x2a, 0xee, 0xe9, 0xda, 0x72, 0xdd, 0xf7, 0x45, 0xbd, - 0xc9, 0xcc, 0xab, 0xfb, 0x7b, 0xee, 0x9d, 0x9d, 0x19, 0xbb, 0x7a, 0x4d, 0xd1, 0xd3, 0x87, 0x0c, - 0x3b, 0x59, 0x64, 0x5e, 0x5f, 0x8a, 0x32, 0xf8, 0xd4, 0xf1, 0xe7, 0x6d, 0xba, 0x78, 0x40, 0xa6, - 0xc8, 0xb3, 0xb8, 0x77, 0x1f, 0x94, 0x19, 0x46, 0xc1, 0x80, 0x02, 0x00, 0x92, 0xb4, 0x2e, 0x74, - 0x00, 0x03, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_sig_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 768, // uncompressed data size (bytes) - 420, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_sig_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("patch_loc") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga10x_patch_location -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_patch_loc_data[] = -{ - 0x10, 0x20, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_patch_loc_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_patch_loc_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("patch_sig") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga10x_patch_signature -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_patch_sig_data[] = -{ - 0x00, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_patch_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_patch_sig_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("patch_meta") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_ga10x_patch_meta_data -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_patch_meta_data[] = -{ - 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_patch_meta_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 12, // uncompressed data size (bytes) - 12, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_patch_meta_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_GA102("num_sigs") -// FILE NAME: kernel/inc/gsprm/bin/booter/ga10x/reload/g_booteruc_reload_ga10x_ga102_rsa3k_0_sig.h -// FILE TYPE: TEXT -// VAR NAME: num_sigs_per_ucode -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_GA102_num_sigs_data[] = -{ - 0x02, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_GA102_num_sigs_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_GA102_num_sigs_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterReloadUcode_GA102 = -{ - 10, // entryNum - { - // entries[] : { "name", pBinStorage } - { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_image_dbg_storage_pvt }, - { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_header_dbg_storage_pvt }, - { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_image_prod_storage_pvt }, - { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_header_prod_storage_pvt }, - { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_sig_dbg_storage_pvt }, - { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_sig_prod_storage_pvt }, - { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_patch_loc_storage_pvt }, - { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_patch_sig_storage_pvt }, - { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_patch_meta_storage_pvt }, - { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_GA102_num_sigs_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_GA102(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveBooterReloadUcode_GA102; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c deleted file mode 100644 index e06f17f0a..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU102.c +++ /dev/null @@ -1,1317 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_tu10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7375 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_image_dbg_data[] = -{ - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x5a, 0xb0, 0x86, 0x07, 0x77, 0x18, 0xdc, 0xdd, 0xdd, 0x82, 0x04, - 0x82, 0xbb, 0xcb, 0x10, 0x9c, 0xe0, 0x16, 0x82, 0x3b, 0x04, 0x77, 0x27, 0xb8, 0xc3, 0xe0, 0xae, - 0xc1, 0xdd, 0x1d, 0x02, 0x04, 0x19, 0xdc, 0xdd, 0xdd, 0x79, 0xf7, 0x6d, 0xef, 0xee, 0x6d, 0x5f, - 0xdd, 0x6f, 0xf3, 0xf7, 0xd9, 0x9c, 0xee, 0xea, 0x53, 0xf5, 0xf7, 0xa9, 0xea, 0x08, 0x80, 0x3f, - 0xe0, 0x3d, 0x09, 0xe0, 0x8b, 0x01, 0x00, 0x3c, 0x42, 0x3f, 0x02, 0x9e, 0xa0, 0x63, 0x00, 0xd0, - 0x80, 0xee, 0xf5, 0x8d, 0x8f, 0x8f, 0x0f, 0x8c, 0x08, 0x00, 0x14, 0xe0, 0x23, 0x17, 0xb6, 0x61, - 0x17, 0xc0, 0x9d, 0x06, 0x81, 0x6a, 0x48, 0x02, 0xb0, 0xa4, 0x41, 0xa0, 0xff, 0x11, 0xda, 0x34, - 0x08, 0xcc, 0x3f, 0x42, 0x16, 0x01, 0x00, 0x00, 0xd2, 0x72, 0x61, 0x1a, 0x37, 0x60, 0xba, 0x73, - 0xf3, 0x36, 0xd2, 0x72, 0xa1, 0xd2, 0xd2, 0xa1, 0x1b, 0x37, 0xa0, 0x1a, 0x21, 0xd0, 0xbe, 0x4d, - 0x00, 0x00, 0x06, 0xa7, 0x1c, 0x00, 0xf8, 0x90, 0x0b, 0xc0, 0x80, 0x8d, 0x00, 0x58, 0x22, 0xfc, - 0x6f, 0x80, 0xd4, 0x92, 0x0e, 0x80, 0x82, 0xfe, 0x27, 0xba, 0xfd, 0x02, 0x1d, 0x07, 0x00, 0xc0, - 0x47, 0xfc, 0x93, 0xea, 0x2d, 0x17, 0xae, 0xf3, 0xf6, 0xf9, 0x09, 0xfe, 0x11, 0xe6, 0x9f, 0xdb, - 0xa0, 0x93, 0x31, 0x10, 0xd7, 0xff, 0x37, 0xf3, 0xdb, 0x13, 0x5c, 0x04, 0x80, 0x14, 0xf0, 0x96, - 0x03, 0xdb, 0x1e, 0x0f, 0xdd, 0x94, 0x04, 0xfc, 0xe7, 0xfc, 0xfe, 0x0c, 0xf0, 0xfd, 0xa7, 0x9e, - 0x47, 0xe8, 0xce, 0xc2, 0x17, 0xa8, 0x38, 0xc5, 0x04, 0xa4, 0x08, 0x20, 0x1c, 0x20, 0x2f, 0xf7, - 0x11, 0x10, 0xf7, 0x8f, 0x76, 0x7f, 0xdc, 0x72, 0xbc, 0xbe, 0xcb, 0x41, 0xe5, 0xe5, 0x0a, 0xff, - 0x01, 0xfc, 0x9f, 0xf8, 0xc5, 0xfa, 0xca, 0x63, 0xdd, 0xc8, 0x39, 0xe8, 0x3f, 0x29, 0xcf, 0xab, - 0xfe, 0xab, 0x4b, 0xc6, 0x81, 0xe4, 0xf5, 0x86, 0xd4, 0x06, 0x48, 0xf6, 0xd2, 0x4d, 0x74, 0x6e, - 0x47, 0xd5, 0xe4, 0xcd, 0xa9, 0x9d, 0xbb, 0x54, 0x68, 0xeb, 0x79, 0xbd, 0x3e, 0x26, 0x39, 0x2a, - 0xa4, 0x56, 0xb0, 0x26, 0x93, 0x8e, 0xb9, 0x4f, 0x24, 0xc0, 0xfc, 0x41, 0xbf, 0x4e, 0xed, 0x82, - 0xa9, 0xc8, 0xef, 0x95, 0x59, 0xc2, 0xc5, 0x96, 0x60, 0xc0, 0xe7, 0x4c, 0xf8, 0xf1, 0x69, 0x1b, - 0x9e, 0xfa, 0xf8, 0x44, 0xa7, 0xb6, 0x14, 0x57, 0x7e, 0x67, 0xcb, 0xf3, 0x54, 0xba, 0xcb, 0x86, - 0x50, 0x00, 0xdd, 0xba, 0xec, 0xb0, 0x3b, 0x27, 0x14, 0xcd, 0xab, 0xe4, 0x31, 0x2f, 0x1b, 0x7c, - 0x66, 0x2d, 0x41, 0x36, 0x80, 0x7a, 0xa9, 0xfb, 0x5c, 0x98, 0x3e, 0x3f, 0xdd, 0x8a, 0xf2, 0x80, - 0x1f, 0x37, 0x13, 0x01, 0xf8, 0xb2, 0xd2, 0x1b, 0xcc, 0xe5, 0x54, 0x19, 0x7f, 0x71, 0x12, 0xe8, - 0x8b, 0x26, 0x06, 0x2a, 0x01, 0x2d, 0x69, 0xd2, 0x1b, 0xe9, 0xf6, 0xbf, 0x52, 0x6f, 0x49, 0x92, - 0x99, 0x0d, 0x5a, 0x4b, 0x51, 0x67, 0xff, 0x8e, 0x3c, 0xba, 0x10, 0xef, 0x29, 0xd9, 0x4e, 0x72, - 0x27, 0xd7, 0xaa, 0xc5, 0xd4, 0xb4, 0x14, 0x02, 0x1f, 0x98, 0xc8, 0x86, 0x99, 0xb3, 0x81, 0x88, - 0x9f, 0xb8, 0x08, 0x18, 0x04, 0x69, 0x68, 0x7a, 0xbe, 0x12, 0xde, 0xba, 0xc2, 0xcc, 0x81, 0x73, - 0x17, 0x90, 0x77, 0xf8, 0x2b, 0x73, 0xcc, 0xa9, 0x44, 0x31, 0xa5, 0xb5, 0x51, 0x85, 0x5b, 0x9e, - 0x17, 0xff, 0x28, 0x4b, 0xd6, 0xb4, 0xa8, 0x93, 0x49, 0x17, 0x29, 0x32, 0x09, 0x9e, 0xe9, 0xa0, - 0xfd, 0x29, 0xbd, 0xfa, 0x21, 0x1a, 0xa1, 0x42, 0x61, 0x8b, 0xb2, 0xa9, 0x3f, 0x3c, 0x97, 0x99, - 0x7e, 0xe1, 0xb8, 0x03, 0x74, 0xea, 0x19, 0xe8, 0x1d, 0x81, 0x91, 0xd3, 0x98, 0x03, 0x2d, 0xd8, - 0x85, 0x54, 0x7b, 0xd2, 0xaf, 0x05, 0x2e, 0x06, 0xed, 0x05, 0x63, 0x48, 0xcc, 0xd1, 0x35, 0x88, - 0xf8, 0xd4, 0x74, 0xef, 0x4f, 0x53, 0x43, 0xc4, 0x9f, 0x86, 0x38, 0x41, 0x49, 0x38, 0xee, 0x78, - 0xd0, 0x08, 0xab, 0x1e, 0x61, 0x51, 0xcc, 0x73, 0x74, 0xed, 0x5a, 0xdc, 0x30, 0x5a, 0x67, 0xaa, - 0x9b, 0x9c, 0x0e, 0x50, 0xac, 0x76, 0xb6, 0xa1, 0x50, 0x25, 0x4f, 0x62, 0x68, 0x31, 0xe9, 0xf2, - 0x03, 0xb6, 0x47, 0x2b, 0xa5, 0xc4, 0x8b, 0x8c, 0x6d, 0xae, 0x30, 0x33, 0xe2, 0x26, 0xd8, 0xa5, - 0x55, 0xe2, 0x90, 0x50, 0x9b, 0x37, 0xc4, 0x5a, 0x83, 0x26, 0x92, 0xf6, 0xd2, 0x42, 0x5a, 0x7c, - 0xb6, 0x4c, 0xcb, 0xbc, 0xe0, 0xb8, 0xb1, 0x73, 0x2b, 0x18, 0x99, 0x48, 0x99, 0x1d, 0x80, 0x88, - 0x3a, 0xb9, 0x10, 0xeb, 0xe5, 0x78, 0x20, 0x3c, 0xba, 0x13, 0xe9, 0x03, 0xd6, 0xb9, 0xc4, 0xbd, - 0x4e, 0xd7, 0x6a, 0xb4, 0x96, 0x9d, 0x03, 0x6b, 0x41, 0x39, 0xf8, 0xca, 0x7c, 0x93, 0xfd, 0xba, - 0xa8, 0x6f, 0x60, 0xd8, 0x64, 0x66, 0x03, 0xcb, 0x7f, 0x54, 0xd7, 0x07, 0xce, 0x7e, 0xf4, 0x35, - 0xd0, 0x2d, 0xb7, 0x4a, 0x00, 0x29, 0x07, 0xe5, 0xd3, 0x20, 0x9f, 0x08, 0xa7, 0x00, 0xf6, 0x0a, - 0x44, 0x36, 0x24, 0x2f, 0xd2, 0x1a, 0x5b, 0xbc, 0x70, 0x4a, 0x11, 0x25, 0x36, 0xbb, 0x31, 0xd3, - 0x90, 0xc6, 0xa1, 0xad, 0xe0, 0x5a, 0xaa, 0x7d, 0x57, 0x7d, 0x53, 0x81, 0x98, 0x4a, 0x47, 0xd7, - 0x9b, 0xa8, 0x33, 0x25, 0xdd, 0xaf, 0x44, 0xa8, 0xa2, 0x55, 0xcf, 0x44, 0xb6, 0x8c, 0x37, 0xa2, - 0xaa, 0x43, 0x93, 0x35, 0x71, 0x69, 0x03, 0xb6, 0x0e, 0xed, 0x6a, 0xd2, 0xeb, 0x81, 0x56, 0x27, - 0x26, 0x59, 0x2a, 0xf4, 0xd1, 0xbd, 0x2d, 0x9d, 0xe9, 0xce, 0x8d, 0x6b, 0xfc, 0xd6, 0x14, 0xe7, - 0x1b, 0x02, 0x9f, 0x57, 0xf4, 0xcc, 0x8b, 0x72, 0x3e, 0xf3, 0x35, 0xbb, 0xb9, 0xf3, 0x9f, 0x01, - 0x10, 0xef, 0x5d, 0xb2, 0x77, 0x61, 0xbe, 0x32, 0xa5, 0xe0, 0x30, 0x3c, 0xc8, 0x8c, 0x29, 0x5b, - 0xa7, 0xd5, 0xbb, 0x24, 0x6d, 0xfe, 0x13, 0x03, 0xe5, 0xd1, 0x4a, 0xfa, 0xaf, 0x91, 0x19, 0x4f, - 0xd5, 0x75, 0x80, 0xb9, 0xbb, 0xc2, 0x00, 0x02, 0xaa, 0xeb, 0x88, 0xc9, 0xce, 0x93, 0x5f, 0xd1, - 0x6b, 0x04, 0x1e, 0x55, 0x09, 0xb0, 0xda, 0xf6, 0xb4, 0xff, 0x26, 0xe2, 0x3b, 0xd9, 0x64, 0x80, - 0xb5, 0xcd, 0x79, 0x3d, 0x83, 0x49, 0xad, 0x4f, 0xbe, 0x10, 0xdf, 0xf5, 0xc8, 0x04, 0x12, 0xe6, - 0x64, 0x56, 0x35, 0x01, 0x21, 0xcb, 0xc0, 0xdf, 0x43, 0x46, 0xed, 0x50, 0x83, 0x83, 0x57, 0x2f, - 0x4e, 0x72, 0xdf, 0x45, 0xbd, 0x85, 0x12, 0x23, 0x97, 0x97, 0xbb, 0x0c, 0xdf, 0x2d, 0x40, 0x66, - 0xe0, 0x66, 0x98, 0xd8, 0x00, 0x61, 0xe7, 0x02, 0x5b, 0x2f, 0xdc, 0x6e, 0x38, 0xd2, 0xa4, 0x98, - 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0x63, 0x12, 0x38, 0xc5, 0x57, 0x8c, 0x96, 0xf4, 0x2a, 0xcf, 0x6e, 0x3e, 0x12, 0x2c, 0xea, 0x49, - 0xb8, 0x08, 0xec, 0x84, 0x20, 0x52, 0x2d, 0xa0, 0x89, 0xcf, 0x66, 0xa3, 0xb3, 0xfc, 0xb1, 0xed, - 0x8a, 0x3e, 0x36, 0x9c, 0xba, 0xab, 0xfb, 0xf9, 0x77, 0x6e, 0xe1, 0x18, 0x32, 0xa1, 0x1f, 0x62, - 0x1c, 0xed, 0xb0, 0x9f, 0xbf, 0x71, 0x0d, 0xf5, 0xb2, 0x01, 0x26, 0x72, 0xd6, 0xff, 0xc0, 0x89, - 0xad, 0xbb, 0xf2, 0xb5, 0x57, 0x46, 0x1f, 0xd2, 0x1c, 0x26, 0x62, 0xaf, 0x76, 0x32, 0x20, 0x97, - 0x10, 0x21, 0x10, 0x9f, 0xc5, 0x81, 0x7a, 0xff, 0x6f, 0xdb, 0xc2, 0xff, 0xf8, 0x8f, 0xff, 0xf8, - 0x8f, 0xff, 0xf8, 0xff, 0xc2, 0xff, 0x00, 0xf0, 0xd7, 0x5e, 0x38, 0x00, 0x23, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_image_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 8960, // uncompressed data size (bytes) - 7375, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_image_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("header_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_tu10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_header_dbg_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_header_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_header_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("image_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_tu10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7373 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_image_prod_data[] = -{ - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x5a, 0xb0, 0x86, 0x07, 0x87, 0xe0, 0xee, 0xee, 0x3e, 0xe8, 0xe0, - 0x92, 0xe0, 0x1a, 0x5c, 0x82, 0xbb, 0xbb, 0x4b, 0x70, 0x27, 0x10, 0x7c, 0x70, 0x19, 0x24, 0x40, - 0x80, 0xe0, 0xee, 0xee, 0x1e, 0xdc, 0x61, 0x82, 0x7b, 0x70, 0x79, 0xf7, 0x6d, 0xef, 0xee, 0x6d, - 0x5f, 0xdd, 0x6f, 0xf3, 0xf7, 0xd9, 0x74, 0x77, 0xf5, 0xa9, 0xee, 0x73, 0xaa, 0x3a, 0x06, 0x10, - 0x0c, 0x78, 0x4b, 0x05, 0x7c, 0xc5, 0x04, 0x00, 0x1e, 0x60, 0x1f, 0x00, 0x8f, 0xb0, 0xdf, 0x00, - 0xb0, 0x80, 0xee, 0xcd, 0xad, 0xf7, 0xf7, 0x77, 0xcc, 0x18, 0x00, 0x0c, 0xe0, 0x3d, 0x1f, 0xbe, - 0x7e, 0x1f, 0xc0, 0x03, 0x5e, 0x81, 0xa9, 0x4f, 0x05, 0xb0, 0x81, 0x57, 0x60, 0xff, 0x11, 0x7a, - 0xf0, 0x0a, 0xdc, 0x3f, 0x42, 0x11, 0x03, 0x00, 0x00, 0xc0, 0xf9, 0x70, 0x8d, 0x5b, 0x70, 0xdd, - 0xf9, 0x05, 0x5b, 0xe0, 0x7c, 0x18, 0x70, 0x26, 0x6c, 0xe3, 0x16, 0x4c, 0xe3, 0x0a, 0xec, 0xd7, - 0x26, 0x00, 0x00, 0x93, 0x4b, 0x1e, 0x80, 0x75, 0x9f, 0x0f, 0xc0, 0x84, 0x8f, 0x01, 0x58, 0x23, - 0xfd, 0xaf, 0x81, 0xd2, 0x92, 0x09, 0x80, 0x81, 0xfd, 0xc7, 0xba, 0x15, 0x81, 0x4d, 0x04, 0x00, - 0x10, 0x63, 0xfe, 0x09, 0xf5, 0x9a, 0x8f, 0xd0, 0x79, 0xfb, 0xf4, 0x88, 0xf8, 0x00, 0xf7, 0x8f, - 0x37, 0xd8, 0x34, 0x4c, 0xe4, 0xcd, 0xff, 0x8d, 0xfc, 0xfa, 0x88, 0x10, 0x03, 0x20, 0x07, 0xbc, - 0xe6, 0xc1, 0xb7, 0x7f, 0x87, 0x6d, 0x4a, 0xc5, 0xfa, 0xe7, 0xfc, 0xf6, 0x04, 0xf8, 0xfa, 0x4f, - 0x3e, 0x0f, 0xb0, 0x9d, 0xc5, 0xcf, 0x30, 0x89, 0x4a, 0xc9, 0x28, 0x31, 0x58, 0x08, 0x80, 0x82, - 0xfc, 0x07, 0x40, 0xe2, 0x3f, 0xda, 0xfd, 0x7e, 0x0b, 0x7c, 0x79, 0x93, 0x87, 0x29, 0xc8, 0x17, - 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NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("header_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_tu10x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_header_prod_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_header_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_header_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("sig_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_dbg_tu10x -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 16 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_sig_dbg_data[] = -{ - 0x0f, 0xa5, 0x47, 0x59, 0x9d, 0xc1, 0xb5, 0x03, 0x7b, 0x20, 0x5f, 0xab, 0xc1, 0x83, 0x57, 0xe7, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_sig_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 16, // uncompressed data size (bytes) - 16, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_sig_dbg_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("sig_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_prod_tu10x -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 16 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_sig_prod_data[] = -{ - 0x41, 0x2d, 0x5e, 0x94, 0xd5, 0x69, 0xef, 0xfc, 0x89, 0xc1, 0x6d, 0x07, 0xb7, 0xdd, 0xbb, 0x96, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_sig_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 16, // uncompressed data size (bytes) - 16, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_sig_prod_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("patch_loc") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu10x_patch_location -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_patch_loc_data[] = -{ - 0x00, 0x1f, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_patch_loc_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_patch_loc_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("patch_sig") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu10x_patch_signature -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_patch_sig_data[] = -{ - 0x00, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_patch_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_patch_sig_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("patch_meta") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu10x_patch_meta_data -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_patch_meta_data[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_patch_meta_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 12, // uncompressed data size (bytes) - 12, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_patch_meta_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU102("num_sigs") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu10x/reload/g_booteruc_reload_tu10x_tu102_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: num_sigs_per_ucode -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU102_num_sigs_data[] = -{ - 0x01, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU102_num_sigs_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU102_num_sigs_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterReloadUcode_TU102 = -{ - 10, // entryNum - { - // entries[] : { "name", pBinStorage } - { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_image_dbg_storage_pvt }, - { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_header_dbg_storage_pvt }, - { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_image_prod_storage_pvt }, - { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_header_prod_storage_pvt }, - { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_sig_dbg_storage_pvt }, - { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_sig_prod_storage_pvt }, - { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_patch_loc_storage_pvt }, - { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_patch_sig_storage_pvt }, - { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_patch_meta_storage_pvt }, - { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU102_num_sigs_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_TU102(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveBooterReloadUcode_TU102; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c deleted file mode 100644 index 63fd8cd6b..000000000 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterReloadUcode_TU116.c +++ /dev/null @@ -1,1317 +0,0 @@ -/* - * SPDX-FileCopyrightText: Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. - * SPDX-License-Identifier: MIT - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - - -/* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT! */ - - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("image_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_tu11x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7364 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_image_dbg_data[] = -{ - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x0a, 0x90, 0x86, 0x87, 0x61, 0xb0, 0xe0, 0x0c, 0xee, 0x4e, 0xf0, - 0x00, 0xc1, 0x9d, 0xe0, 0x0e, 0x43, 0x90, 0x00, 0xc1, 0x83, 0x05, 0x82, 0x04, 0x1b, 0xdc, 0xdd, - 0xdd, 0xdd, 0x5d, 0x83, 0xbb, 0x6b, 0x70, 0x97, 0x20, 0x09, 0x10, 0x9c, 0x01, 0x06, 0xdf, 0xb7, - 0xd7, 0x77, 0xdb, 0xeb, 0xd6, 0xfb, 0x2e, 0x7f, 0xf7, 0xa5, 0xbb, 0xab, 0xba, 0xaa, 0x0f, 0x7f, - 0x87, 0x03, 0xfc, 0x00, 0x2f, 0x49, 0x00, 0x1f, 0x6c, 0x00, 0x00, 0x0e, 0x84, 0x03, 0xee, 0x81, - 0xd1, 0x00, 0x20, 0xa0, 0x67, 0x6b, 0xfb, 0xf5, 0xf5, 0x15, 0x3b, 0x1c, 0x80, 0x00, 0x78, 0xcd, - 0x05, 0x35, 0xee, 0x03, 0x78, 0xd2, 0x56, 0x11, 0x1a, 0x93, 0x00, 0x6c, 0x69, 0xab, 0xc0, 0x7f, - 0x84, 0x21, 0x6d, 0x15, 0xf1, 0x1f, 0xa1, 0x0c, 0x07, 0x00, 0x00, 0x69, 0xb9, 0x88, 0xcd, 0xdb, - 0x88, 0x3d, 0xb9, 0x79, 0xdb, 0x69, 0xb9, 0x08, 0x69, 0xe9, 0xc0, 0xe6, 0x6d, 0x84, 0xe6, 0x55, - 0xa0, 0x4f, 0x0b, 0x00, 0x80, 0xcd, 0xa5, 0x00, 0xc0, 0xb9, 0xcb, 0x05, 0x60, 0x83, 0xc2, 0x01, - 0x96, 0x28, 0xff, 0x1b, 0xa0, 0xb5, 0xa6, 0x03, 0x10, 0x80, 0xff, 0x44, 0x30, 0x11, 0x60, 0x2c, - 0x00, 0x80, 0x1c, 0xfe, 0x4f, 0xab, 0xe7, 0x5c, 0xa4, 0x2e, 0xd8, 0xc3, 0x3d, 0x32, 0x1c, 0xf1, - 0x9f, 0x6a, 0xc0, 0x64, 0x6c, 0xd4, 0xad, 0xff, 0xed, 0xfc, 0x7c, 0x8f, 0x14, 0x0e, 0xa0, 0x00, - 0x3c, 0xe7, 0x80, 0x3a, 0xe2, 0x80, 0x2d, 0x49, 0x38, 0xff, 0xe4, 0x2f, 0x0f, 0x00, 0x9f, 0x7f, - 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NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("header_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_dbg.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_tu11x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_header_dbg_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_header_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_header_dbg_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("image_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_data_tu11x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 7364 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_image_prod_data[] = -{ - 0xed, 0x99, 0x45, 0x54, 0x1c, 0x5a, 0x90, 0x86, 0x9b, 0xc6, 0xdd, 0xdd, 0x09, 0x0e, 0xc1, 0x09, - 0x0e, 0xc1, 0xdd, 0x82, 0x3b, 0xc1, 0xdd, 0x42, 0xd0, 0x40, 0xd0, 0x40, 0xe3, 0x0e, 0x8d, 0x35, - 0xee, 0xee, 0xd0, 0xb8, 0x04, 0xf7, 0xe0, 0x0e, 0x8d, 0x04, 0x27, 0x38, 0x41, 0xe6, 0xcd, 0xf6, - 0xed, 0x66, 0x3b, 0xe7, 0x7d, 0x9b, 0xbf, 0xee, 0xa6, 0xaa, 0xce, 0xa9, 0x73, 0x6b, 0xf1, 0x17, - 0x08, 0x10, 0x04, 0x78, 0x4d, 0x01, 0x04, 0x62, 0x03, 0x00, 0x0f, 0xc0, 0x07, 0xc0, 0x23, 0x30, - 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0x6e, 0xc6, 0xbb, 0x7b, 0x3d, 0x4f, 0x9d, 0xd2, 0x36, 0x2a, 0x62, 0xfa, 0x32, 0x85, 0x9f, 0x69, - 0x31, 0xcb, 0xc2, 0x3d, 0x7a, 0xc3, 0xbf, 0x71, 0x01, 0x53, 0xb6, 0xe4, 0x3a, 0x49, 0xe1, 0xae, - 0xdb, 0xe3, 0x51, 0x9e, 0xde, 0x34, 0xc3, 0xb5, 0xce, 0x0d, 0xd7, 0xa0, 0xfc, 0xff, 0xdb, 0xb5, - 0xf0, 0x3f, 0xfe, 0xe3, 0x3f, 0xfe, 0xe3, 0x3f, 0xfe, 0xbf, 0xf0, 0x3f, 0xa9, 0x90, 0xad, 0xcd, - 0x00, 0x23, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_image_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 8960, // uncompressed data size (bytes) - 7364, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_image_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("header_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_prod.h -// FILE TYPE: TEXT -// VAR NAME: booter_ucode_header_tu11x -// COMPRESSION: YES -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 36 -// COMPRESSED SIZE (bytes): 27 -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_header_prod_data[] = -{ - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, - 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_header_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 36, // uncompressed data size (bytes) - 27, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_header_prod_data, // compressed data pointer - NV_TRUE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("sig_dbg") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_dbg_tu11x -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 16 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_sig_dbg_data[] = -{ - 0x1a, 0x34, 0xb6, 0x32, 0x75, 0x24, 0x15, 0x41, 0x5d, 0x9f, 0xa8, 0xaf, 0xca, 0xe0, 0x2c, 0x73, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_sig_dbg_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 16, // uncompressed data size (bytes) - 16, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_sig_dbg_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("sig_prod") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_prod_tu11x -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 16 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_sig_prod_data[] = -{ - 0xab, 0xbb, 0x13, 0xff, 0x34, 0x6c, 0xc6, 0x0b, 0x42, 0x7b, 0xdf, 0x2b, 0x79, 0x59, 0x10, 0x26, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_sig_prod_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 16, // uncompressed data size (bytes) - 16, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_sig_prod_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("patch_loc") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu11x_patch_location -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_patch_loc_data[] = -{ - 0x00, 0x1f, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_patch_loc_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_patch_loc_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("patch_sig") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu11x_patch_signature -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_patch_sig_data[] = -{ - 0x00, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_patch_sig_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_patch_sig_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("patch_meta") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: booter_reload_sig_tu11x_patch_meta_data -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 12 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_patch_meta_data[] = -{ - 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_patch_meta_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 12, // uncompressed data size (bytes) - 12, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_patch_meta_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_DATA) -// -// FUNCTION: kgspGetBinArchiveBooterReloadUcode_TU116("num_sigs") -// FILE NAME: kernel/inc/gsprm/bin/booter/tu11x/reload/g_booteruc_reload_tu11x_tu116_aes_sig.h -// FILE TYPE: TEXT -// VAR NAME: num_sigs_per_ucode -// COMPRESSION: NO -// COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 4 -// COMPRESSED SIZE (bytes): N/A -// -static BINDATA_CONST NvU8 kgspBinArchiveBooterReloadUcode_TU116_num_sigs_data[] = -{ - 0x01, 0x00, 0x00, 0x00, -}; -#endif // defined(BINDATA_INCLUDE_DATA) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) -BINDATA_STORAGE_PVT kgspBinArchiveBooterReloadUcode_TU116_num_sigs_storage_pvt; -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DECL) - -#if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) -{ - 4, // uncompressed data size (bytes) - 4, // compressed data size (bytes) - kgspBinArchiveBooterReloadUcode_TU116_num_sigs_data, // compressed data pointer - NV_FALSE, // is pData compressed? - NV_TRUE, // contain information for file overriding? - NV_FALSE, // is the data referenced during load? (Only valid when BINDATA_IS_MUTABLE is true) -}, -#endif // defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) - - -#if defined(BINDATA_INCLUDE_ARCHIVE) -// -// Bindata Archive structure -// -static const BINDATA_ARCHIVE __kgspGetBinArchiveBooterReloadUcode_TU116 = -{ - 10, // entryNum - { - // entries[] : { "name", pBinStorage } - { "image_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_image_dbg_storage_pvt }, - { "header_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_header_dbg_storage_pvt }, - { "image_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_image_prod_storage_pvt }, - { "header_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_header_prod_storage_pvt }, - { "sig_dbg" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_sig_dbg_storage_pvt }, - { "sig_prod" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_sig_prod_storage_pvt }, - { "patch_loc" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_patch_loc_storage_pvt }, - { "patch_sig" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_patch_sig_storage_pvt }, - { "patch_meta" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_patch_meta_storage_pvt }, - { "num_sigs" , (const PBINDATA_STORAGE) &g_bindata_pvt.kgspBinArchiveBooterReloadUcode_TU116_num_sigs_storage_pvt }, - } -}; - -#endif // defined(BINDATA_INCLUDE_ARCHIVE) - - - -#if defined(BINDATA_INCLUDE_FUNCTION) -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_TU116(struct KernelGsp *pKernelGsp) -{ - return &__kgspGetBinArchiveBooterReloadUcode_TU116; -} -#endif // defined(BINDATA_INCLUDE_FUNCTION) - - - - - diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c index 96f695ace..18b6d6a81 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA100.c @@ -34,438 +34,427 @@ // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 6817 +// DATA SIZE (bytes): 8704 +// COMPRESSED SIZE (bytes): 6655 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x50, 0x1c, 0x0a, 0xb3, 0xb6, 0x87, 0x21, 0x38, 0x41, 0x83, 0xbb, 0xbb, 0x0e, - 0xee, 0xee, 0xee, 0x04, 0x09, 0x1e, 0x34, 0x68, 0x70, 0x77, 0x77, 0x19, 0x64, 0x70, 0x77, 0x87, - 0x41, 0x83, 0x6b, 0x90, 0x40, 0xd0, 0xe0, 0xee, 0x10, 0xdc, 0xef, 0xf9, 0x16, 0xff, 0xe6, 0x5b, - 0xdd, 0xbb, 0xfd, 0xeb, 0x3c, 0x9b, 0xf7, 0xed, 0x5e, 0x74, 0xf5, 0xa6, 0xab, 0xba, 0xba, 0xa3, - 0x00, 0x00, 0x98, 0xb7, 0x54, 0x80, 0x3f, 0x3a, 0x00, 0xf0, 0x00, 0x7c, 0x00, 0x3c, 0x02, 0xe3, - 0x00, 0x40, 0x40, 0xef, 0xfa, 0xc6, 0xfb, 0xfb, 0x3b, 0x7a, 0x14, 0x00, 0x06, 0xf0, 0x9e, 0xf7, - 0xa1, 0x69, 0x17, 0x00, 0x02, 0x2f, 0xc3, 0x34, 0xa5, 0x02, 0x98, 0xc1, 0xcb, 0xc0, 0x7f, 0x84, - 0x06, 0xbc, 0x0c, 0xfb, 0x8f, 0x90, 0x46, 0x01, 0x00, 0x00, 0x70, 0x1e, 0x6c, 0xcb, 0x06, 0x6c, - 0x6f, 0x5e, 0xfe, 0x06, 0x38, 0x0f, 0x06, 0x9c, 0x09, 0x6c, 0xd9, 0x80, 0x69, 0x59, 0x06, 0xfa, - 0xf7, 0x02, 0x00, 0xe8, 0x1c, 0xf2, 0x00, 0x8c, 0xfb, 0x3c, 0x40, 0x77, 0x6a, 0xc2, 0x3f, 0x25, - 0x5b, 0x1e, 0x83, 0x5a, 0x1e, 0x03, 0xa3, 0x00, 0xa1, 0x1f, 0xfe, 0x49, 0xa1, 0xc3, 0xb4, 0x67, - 0x02, 0x48, 0x80, 0xff, 0x71, 0xb0, 0xff, 0x38, 0x18, 0xe0, 0xff, 0xcb, 0xc1, 0xff, 0xc7, 0xfd, - 0x53, 0x16, 0x98, 0x86, 0x8e, 0xb8, 0xfe, 0x9f, 0x16, 0x5e, 0x1f, 0xe1, 0xa2, 0x00, 0x44, 0x80, - 0xd7, 0xdc, 0x0f, 0x9d, 0x89, 0xc0, 0xd6, 0x54, 0x8c, 0x7f, 0xe2, 0xb7, 0x27, 0x80, 0xff, 0x3f, - 0x8d, 0x3d, 0x00, 0xbb, 0x8b, 0x9f, 0x61, 0x12, 0x5e, 0x33, 0xd0, 0xa3, 0xc8, 0x11, 0x00, 0xf9, - 0x79, 0x0f, 0x80, 0x84, 0x7f, 0xb4, 0xf7, 0xfd, 0x86, 0xfd, 0xe5, 0x4d, 0x1e, 0x26, 0x3f, 0x4f, - 0x64, 0x19, 0xf0, 0xbf, 0x01, 0xef, 0xc3, 0xc9, 0x05, 0xd1, 0x0b, 0x4a, 0xe2, 0xdb, 0x84, 0xdc, - 0x0e, 0x6e, 0x2e, 0x48, 0x23, 0xb0, 0xe8, 0xc6, 0x89, 0xb4, 0xd3, 0x9f, 0xe9, 0xd4, 0xac, 0x5f, - 0xf6, 0x21, 0xfb, 0xb1, 0x73, 0xbf, 0x33, 0x6d, 0x24, 0x8e, 0x29, 0x0c, 0x8a, 0x54, 0xed, 0x9b, - 0x6e, 0x7f, 0x46, 0xbf, 0xd2, 0xb6, 0x22, 0x69, 0x43, 0x94, 0xc2, 0x15, 0x84, 0x54, 0x1f, 0x2e, - 0xd2, 0x50, 0x43, 0xe4, 0xbd, 0x5c, 0x56, 0xa8, 0x7e, 0x3c, 0x58, 0xbd, 0xbf, 0x73, 0x6a, 0x28, - 0x29, 0x98, 0x8c, 0xf7, 0xc5, 0x6e, 0xa8, 0x73, 0x1f, 0x49, 0xff, 0x52, 0x1c, 0x9e, 0x5f, 0xa9, - 0x3f, 0x7a, 0x7a, 0xce, 0x5f, 0x65, 0x9b, 0x1a, 0x5d, 0xda, 0x1d, 0x99, 0x1e, 0xd5, 0x74, 0x8a, - 0x4f, 0x1f, 0xbf, 0x3e, 0xa0, 0xc9, 0x70, 0x59, 0xc7, 0x85, 0xc2, 0x8d, 0x10, 0xa8, 0x8e, 0x98, - 0x46, 0xd0, 0x81, 0x2a, 0xb2, 0xdd, 0x52, 0xfa, 0xf7, 0x06, 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0x39, 0x9e, 0xe0, 0x0e, 0xbd, 0x42, 0x25, 0xd5, + 0x36, 0x6c, 0x8d, 0xf0, 0xfb, 0x3f, 0x7d, 0x92, 0xfc, 0xcb, 0xbf, 0xfc, 0xcb, 0xbf, 0xfc, 0xcb, + 0xbf, 0xfc, 0xcb, 0xff, 0x2b, 0xfe, 0x07, 0xfe, 0x0f, 0x41, 0x61, 0x00, 0x22, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -475,8 +464,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8960, // uncompressed data size (bytes) - 6817, // compressed data size (bytes) + 8704, // uncompressed data size (bytes) + 6655, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -498,8 +487,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6b, 0x3e, 0x38, 0x7d, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -527,438 +516,427 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga100 // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8960 -// COMPRESSED SIZE (bytes): 6823 +// DATA SIZE (bytes): 8704 +// COMPRESSED SIZE (bytes): 6649 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1b, 0x0c, 0xd3, 0xb6, 0x43, 0xb0, 0x04, 0x0f, 0x52, 0x5c, 0x8a, 0xbb, - 0x53, 0xac, 0xb8, 0x3b, 0x45, 0x0a, 0x45, 0x8b, 0x7b, 0x71, 0x28, 0xee, 0xee, 0x45, 0x83, 0x5b, - 0xd1, 0xd0, 0x42, 0x83, 0x15, 0x8a, 0x6b, 0x81, 0xe2, 0xee, 0xa5, 0xc5, 0x82, 0x4b, 0x43, 0x91, - 0xc0, 0xf7, 0xbc, 0x8b, 0x7f, 0xf3, 0xae, 0xbe, 0x6f, 0xfb, 0x9f, 0xe7, 0xda, 0xdc, 0xf7, 0xcc, - 0x62, 0xce, 0x6c, 0xe6, 0x9c, 0x39, 0x33, 0x09, 0x00, 0x00, 0xda, 0x63, 0x16, 0x20, 0x94, 0x10, - 0x00, 0xf8, 0x0b, 0xfc, 0x0b, 0xb8, 0x05, 0xa6, 0x00, 0x80, 0x80, 0x9e, 0xcd, 0xad, 0xa7, 0xa7, - 0x27, 0xc2, 0x04, 0x00, 0x1a, 0xe0, 0xa9, 0x04, 0x03, 0xfe, 0x1b, 0x20, 0x94, 0xb7, 0x82, 0x06, - 0xcf, 0x02, 0x70, 0xe7, 0xad, 0x00, 0xff, 0x11, 0x96, 0xbc, 0x15, 0xf4, 0x7f, 0x84, 0x2e, 0x01, - 0x00, 0x00, 0xe4, 0x95, 0xa0, 0xb7, 0x6c, 0xa1, 0xf7, 0x94, 0x94, 0x6e, 0xe5, 0x95, 0xa0, 0xe5, - 0x41, 0x81, 0x2d, 0x5b, 0x68, 0x2d, 0x2b, 0xc0, 0xd0, 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uncompressed data size (bytes) + 6649, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA100_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -991,8 +969,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x6b, 0x3e, 0x38, 0x7d, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x0e, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x2b, 0x43, 0x56, 0x8a, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1025,31 +1003,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x3f, 0x1c, 0x05, 0x53, 0xf9, 0x05, 0x6c, 0x56, 0x8b, 0x5d, 0xaf, - 0xb8, 0x82, 0x7d, 0xc7, 0x76, 0xcc, 0x6e, 0x87, 0x43, 0x65, 0xfe, 0x0e, 0x2e, 0x01, 0x85, 0x48, - 0x1c, 0xb9, 0xa6, 0xdf, 0xae, 0x1c, 0x81, 0x50, 0x39, 0x2f, 0x35, 0xca, 0x6f, 0x7b, 0x54, 0xef, - 0x04, 0x3d, 0x1a, 0x3c, 0xd9, 0x5e, 0x1f, 0xa6, 0x39, 0xd2, 0x1e, 0x2e, 0xdd, 0xd6, 0x73, 0x49, - 0xc2, 0x44, 0xaf, 0x0b, 0x4b, 0x1c, 0xab, 0xea, 0xef, 0x8d, 0x25, 0xc4, 0xc3, 0x5e, 0xd7, 0x81, - 0x09, 0x5c, 0x9f, 0x83, 0x3b, 0x9b, 0xda, 0xe3, 0xcb, 0x98, 0x1a, 0x05, 0x6f, 0x87, 0x07, 0x41, - 0x24, 0xf6, 0x0c, 0x22, 0x3e, 0x37, 0xfa, 0x3c, 0xa7, 0xda, 0x02, 0xaf, 0x24, 0xac, 0xc1, 0xe0, - 0x94, 0xb3, 0x68, 0x0f, 0x77, 0x35, 0x76, 0xa5, 0x68, 0x21, 0xc9, 0x22, 0x21, 0xff, 0xd3, 0x77, - 0xfa, 0xdb, 0x55, 0x42, 0x7d, 0x1e, 0x59, 0xf5, 0x23, 0x62, 0xab, 0xcf, 0xe2, 0x7b, 0xf9, 0x8b, - 0xec, 0xc4, 0xcb, 0x0d, 0xe0, 0x62, 0xb0, 0x9f, 0xd8, 0x42, 0xaf, 0x69, 0xe2, 0x29, 0xdd, 0xcd, - 0x68, 0xc6, 0x7c, 0x20, 0xd9, 0x41, 0x6a, 0xf4, 0x2d, 0x1e, 0xe9, 0xb4, 0x5a, 0x27, 0x87, 0x3b, - 0xfb, 0x87, 0xdb, 0x42, 0x30, 0xf5, 0xb6, 0xd4, 0xbf, 0x22, 0x33, 0x75, 0x65, 0x0f, 0xfc, 0xfd, - 0xd9, 0x6a, 0x1e, 0x39, 0x82, 0xe7, 0x75, 0xac, 0xb2, 0x53, 0x0c, 0x4e, 0xcb, 0x37, 0x5f, 0x32, - 0xf2, 0xc2, 0x0f, 0xf6, 0x79, 0x2c, 0xa9, 0x28, 0x1d, 0x84, 0xb5, 0xf3, 0xbc, 0xf9, 0x8c, 0xf4, - 0x1f, 0x9b, 0x58, 0xe4, 0x69, 0x4c, 0x56, 0x74, 0xa3, 0xb1, 0x17, 0xae, 0xbc, 0x64, 0x64, 0xdc, - 0x00, 0x2d, 0xd3, 0xa1, 0x69, 0xeb, 0xbe, 0x9b, 0x12, 0x08, 0x04, 0x92, 0xba, 0x9c, 0x23, 0x56, - 0xd8, 0x95, 0xae, 0xea, 0xf2, 0x4b, 0x32, 0x6c, 0x55, 0xb5, 0x56, 0x2c, 0x86, 0xb0, 0x7b, 0x04, - 0x8d, 0xb4, 0xb8, 0x38, 0xdd, 0x27, 0xd0, 0x83, 0x77, 0xe8, 0x5b, 0x7d, 0x6d, 0x26, 0x89, 0xc0, - 0x11, 0x72, 0xb1, 0xbe, 0xc6, 0x45, 0xff, 0xa8, 0x71, 0xb4, 0xba, 0x96, 0x78, 0xf2, 0x9d, 0xbb, - 0x96, 0x9c, 0xcf, 0xe8, 0xb6, 0x12, 0x25, 0xe2, 0x6c, 0x2a, 0x1f, 0x3a, 0xc6, 0x48, 0x09, 0x82, - 0x79, 0x9e, 0x7c, 0x2c, 0x62, 0xf2, 0xae, 0xc0, 0xb7, 0x7a, 0x97, 0x74, 0xec, 0x26, 0x10, 0x42, - 0xa1, 0x76, 0x79, 0x67, 0xee, 0x9e, 0x39, 0x3f, 0x32, 0x17, 0x0b, 0x0f, 0xee, 0xd4, 0xa2, 0xe4, - 0xea, 0xa8, 0xe0, 0x73, 0x8d, 0x81, 0x25, 0xf8, 0x9e, 0xff, 0x30, 0xd1, 0xe8, 0x2a, 0x11, 0x68, - 0x06, 0x8e, 0xcd, 0x26, 0xd3, 0x56, 0x31, 0xce, 0xb8, 0x00, 0xab, 0x52, 0xca, 0xbd, 0x7b, 0xb5, - 0x4f, 0xc2, 0x3e, 0xa1, 0xbf, 0x88, 0x0c, 0xa6, 0xd0, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x27, 0x14, 0x82, 0xed, 0x50, 0xb4, 0xad, 0x04, 0xb4, 0x65, 0xe6, + 0xa2, 0x91, 0x3f, 0x4a, 0xc1, 0x55, 0x7a, 0xb0, 0x08, 0x78, 0x5f, 0x32, 0xe9, 0x8f, 0x54, 0xf1, + 0xcd, 0xa2, 0x05, 0x16, 0xaf, 0xbf, 0xfc, 0xc0, 0xa4, 0x96, 0x83, 0xd7, 0xfe, 0xaa, 0x9d, 0x7a, + 0x82, 0x5a, 0x78, 0x44, 0x26, 0xa6, 0xc4, 0x6c, 0xdc, 0x17, 0x98, 0x90, 0x55, 0xe2, 0x39, 0x8d, + 0xb4, 0xfa, 0xb2, 0x0b, 0x45, 0x0b, 0x2d, 0xd5, 0x2b, 0xb5, 0x63, 0x8d, 0x31, 0x20, 0xde, 0x12, + 0x8f, 0xe8, 0x7c, 0x24, 0xe4, 0xfe, 0xe7, 0x29, 0x37, 0xc3, 0xcf, 0x3f, 0x2d, 0xff, 0x50, 0x69, + 0x62, 0xf3, 0xd2, 0xc2, 0x77, 0x1c, 0x85, 0x3a, 0xbb, 0x5b, 0x93, 0x61, 0x8b, 0x46, 0xd4, 0xca, + 0x55, 0xc1, 0x1b, 0x58, 0x95, 0x38, 0x70, 0xb0, 0x02, 0x85, 0x6c, 0x21, 0x1d, 0x4b, 0x5b, 0xd6, + 0x94, 0xa8, 0xf0, 0xb5, 0xba, 0x5e, 0xfa, 0x75, 0x16, 0x7a, 0xec, 0x27, 0xfd, 0x9f, 0x0d, 0x42, + 0xc0, 0xcd, 0x50, 0x38, 0x8e, 0x56, 0x09, 0xbf, 0x3f, 0x31, 0x19, 0xa8, 0xd5, 0xe9, 0x5c, 0x84, + 0x66, 0xcc, 0xf6, 0x79, 0x2c, 0x5e, 0x02, 0x6a, 0xb1, 0x51, 0x94, 0xaa, 0x16, 0xe7, 0xed, 0xd0, + 0xca, 0x69, 0x13, 0xab, 0x50, 0xac, 0x82, 0xcb, 0x8e, 0x92, 0x35, 0xcd, 0xb1, 0x77, 0x4d, 0xe4, + 0xe4, 0x1d, 0x58, 0xea, 0x59, 0x2d, 0x34, 0x09, 0x9b, 0xe9, 0x2a, 0x6c, 0xf5, 0x84, 0xe8, 0x9d, + 0x9a, 0x99, 0xea, 0x6c, 0xab, 0x90, 0xb7, 0xa8, 0xa8, 0x01, 0x9b, 0x46, 0xd9, 0x86, 0x5d, 0xc5, + 0x1b, 0x9b, 0x5e, 0x11, 0x9e, 0x1a, 0x6f, 0x4d, 0x45, 0x5c, 0x87, 0x26, 0x92, 0x7e, 0xaf, 0x04, + 0x56, 0x3e, 0xe6, 0x09, 0x8e, 0x13, 0xac, 0x13, 0x77, 0x0a, 0xb2, 0xcd, 0x4f, 0xa1, 0x61, 0xba, + 0x43, 0x92, 0x8d, 0x60, 0x5e, 0x23, 0x40, 0x57, 0x29, 0x43, 0x26, 0x6e, 0xb8, 0x5d, 0xfe, 0x9e, + 0x93, 0x7f, 0x62, 0x04, 0x76, 0xa9, 0xb5, 0xd3, 0x8d, 0xa9, 0x6f, 0xe9, 0x60, 0x67, 0xe9, 0xd9, + 0xf6, 0x80, 0x1b, 0x89, 0x9f, 0xa9, 0x26, 0x00, 0x1f, 0x63, 0x99, 0x68, 0xf1, 0xe9, 0x64, 0x5c, + 0x7e, 0xd0, 0x47, 0xe2, 0xcc, 0x03, 0x1a, 0xaf, 0xb6, 0xb8, 0xa4, 0xc1, 0x31, 0xf5, 0x27, 0xe5, + 0x21, 0x45, 0x56, 0xfb, 0xc4, 0xfd, 0xec, 0x65, 0x79, 0x0b, 0x86, 0x76, 0xcc, 0x21, 0x8c, 0x62, + 0xce, 0xd3, 0x6a, 0x09, 0xfe, 0x34, 0xec, 0x4d, 0xba, 0xe3, 0x6e, 0x11, 0x0b, 0x4e, 0x70, 0x6d, + 0xe7, 0xc4, 0x47, 0xa0, 0xee, 0xc3, 0x66, 0x1d, 0xfc, 0xec, 0x1c, 0xf7, 0x2f, 0x3b, 0xbc, 0xda, + 0xc2, 0x63, 0x68, 0x0d, 0xfc, 0xe1, 0x92, 0xbb, 0x56, 0xae, 0x8c, 0x14, 0xf9, 0x98, 0x30, 0x4f, + 0x03, 0x56, 0x61, 0xd5, 0x8b, 0x30, 0x5c, 0xb1, 0xb3, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1082,31 +1060,31 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_data[] = { - 0x01, 0x80, 0x01, 0x7f, 0xfe, 0xf1, 0x3b, 0x42, 0xb1, 0xf2, 0xda, 0xaa, 0x9e, 0x07, 0x8c, 0x0f, - 0x9f, 0x8d, 0xb8, 0xb7, 0x2d, 0x59, 0xd0, 0x9e, 0xd3, 0xd2, 0x4a, 0xec, 0x0f, 0x8c, 0x84, 0xe0, - 0xd0, 0x81, 0xba, 0x92, 0xc9, 0xf5, 0x4c, 0xa7, 0x9b, 0x3c, 0x7e, 0xa7, 0xb9, 0x61, 0x6c, 0x55, - 0xcc, 0xef, 0xcf, 0xfb, 0x2d, 0x46, 0x1d, 0x08, 0xf7, 0x56, 0xa6, 0x8f, 0x28, 0xd9, 0xc4, 0x69, - 0x92, 0x48, 0x11, 0xb0, 0xad, 0x01, 0xe9, 0x95, 0x0f, 0x62, 0x95, 0xdd, 0x0c, 0xbb, 0xac, 0x02, - 0x65, 0x2d, 0x29, 0x7a, 0x98, 0xcd, 0x36, 0xdd, 0x01, 0xb1, 0x22, 0xba, 0x20, 0xad, 0x90, 0x01, - 0xe1, 0x57, 0x5a, 0x07, 0x6f, 0x8d, 0xaa, 0xa1, 0x8f, 0x00, 0xaa, 0xa9, 0x95, 0xae, 0xbe, 0xa6, - 0xa9, 0x37, 0xeb, 0x29, 0x8f, 0x52, 0x33, 0x31, 0x4b, 0xef, 0x97, 0x98, 0x20, 0x62, 0x38, 0x81, - 0x6d, 0x34, 0xb8, 0x0f, 0x12, 0x72, 0x1f, 0x50, 0xbc, 0xdc, 0x29, 0x16, 0xe9, 0x01, 0xb1, 0xbf, - 0xad, 0x96, 0x25, 0x7c, 0xa1, 0xc6, 0x63, 0x5e, 0xe6, 0x45, 0x9a, 0x99, 0xf6, 0x5e, 0x2d, 0x95, - 0xcb, 0xd6, 0x49, 0x4c, 0x8a, 0x97, 0xea, 0x51, 0x07, 0xe2, 0x67, 0xf6, 0xca, 0x20, 0xda, 0x59, - 0x17, 0x71, 0x26, 0x0b, 0xdc, 0xd6, 0x1a, 0x84, 0x01, 0xca, 0xed, 0xea, 0x5c, 0x82, 0x1d, 0xb4, - 0x91, 0x9f, 0xf1, 0x25, 0xf4, 0x96, 0x9c, 0xee, 0xe7, 0xc9, 0x8e, 0xe5, 0xfe, 0x0e, 0x4d, 0x3d, - 0xdd, 0x05, 0xb8, 0xac, 0x15, 0x1f, 0x7a, 0x8e, 0xc0, 0x16, 0xfd, 0x39, 0xbc, 0xc6, 0x1b, 0x10, - 0x63, 0x06, 0xa9, 0xe9, 0x1f, 0x55, 0xd8, 0x94, 0xb8, 0xd8, 0x17, 0x19, 0xfb, 0x0b, 0x8c, 0xa2, - 0x77, 0xf5, 0xf6, 0x43, 0x6b, 0xa1, 0x64, 0x43, 0xe5, 0xee, 0x91, 0x12, 0x23, 0x2a, 0x2d, 0x7a, - 0x06, 0x07, 0x38, 0x55, 0xa9, 0x6e, 0x54, 0x6a, 0x05, 0xfe, 0x0a, 0x8f, 0x86, 0x8b, 0x82, 0xbb, - 0xd4, 0x3a, 0x4b, 0x08, 0xbc, 0x8d, 0x25, 0x2d, 0x63, 0x09, 0x26, 0x40, 0x58, 0x46, 0x15, 0x35, - 0x5a, 0xbe, 0x86, 0x57, 0x76, 0xf5, 0x3d, 0xd7, 0x96, 0x47, 0x44, 0xa1, 0x8f, 0x06, 0xb4, 0x5c, - 0x6a, 0x74, 0x67, 0xbc, 0xfa, 0x9d, 0x7a, 0xe1, 0xac, 0xa1, 0x17, 0x97, 0xb5, 0xf7, 0x46, 0x7f, - 0x15, 0xc8, 0x12, 0x7c, 0xeb, 0x58, 0x8e, 0xcc, 0xe9, 0x7a, 0x3e, 0x9b, 0x20, 0xcf, 0xad, 0x37, - 0xd0, 0x74, 0x3c, 0xc9, 0x70, 0xe3, 0x81, 0x85, 0x93, 0xe0, 0x5a, 0x7b, 0x0f, 0x41, 0xbb, 0xd4, - 0xe6, 0x37, 0xe3, 0xf7, 0xf8, 0xa5, 0xdb, 0x87, 0xed, 0xd4, 0x92, 0x2b, 0xba, 0x6f, 0x53, 0xb4, - 0x03, 0x81, 0xda, 0x26, 0x7d, 0xa4, 0x4a, 0x14, 0xc0, 0x96, 0x25, 0x2c, 0x41, 0xd9, 0x8a, 0x7d, - 0xd9, 0x53, 0x5b, 0x7f, 0x18, 0x1f, 0x15, 0x0e, 0x63, 0x80, 0x01, 0x00, 0x00, + 0x01, 0x80, 0x01, 0x7f, 0xfe, 0x99, 0x28, 0x07, 0xb5, 0xce, 0x8e, 0x09, 0x5c, 0x30, 0x2a, 0x9c, + 0xdc, 0x66, 0x84, 0xa4, 0x0d, 0x33, 0x44, 0x87, 0xa2, 0xd7, 0x17, 0xb5, 0x14, 0x15, 0x12, 0x82, + 0x3e, 0xd3, 0x74, 0xc9, 0xac, 0xb1, 0x92, 0xcc, 0x85, 0x88, 0xcb, 0x87, 0x9f, 0xdc, 0x1e, 0x72, + 0xf8, 0x0a, 0x44, 0xec, 0x86, 0x0d, 0x4b, 0xbf, 0x04, 0x19, 0x73, 0x45, 0x5e, 0x1b, 0x90, 0x90, + 0xb8, 0xad, 0x94, 0x67, 0x14, 0x60, 0xee, 0xc2, 0x86, 0x37, 0xd1, 0x02, 0x54, 0xbe, 0x7c, 0x01, + 0x7f, 0xae, 0x40, 0x03, 0x88, 0x0e, 0x45, 0x84, 0x5e, 0x52, 0x33, 0x2b, 0x2c, 0x5b, 0x00, 0x85, + 0xfe, 0x78, 0xb8, 0xf2, 0x5d, 0x43, 0xa1, 0xa0, 0xbb, 0xc0, 0x6b, 0xa7, 0x83, 0xa8, 0xbc, 0xf9, + 0xa3, 0x83, 0xd4, 0x0f, 0x9f, 0xc9, 0x88, 0x4f, 0x4c, 0x6a, 0xfa, 0x90, 0x39, 0x86, 0xc5, 0xe4, + 0x79, 0x20, 0xf3, 0x1e, 0x76, 0x6d, 0x59, 0x1d, 0x27, 0x1b, 0x47, 0x55, 0x3c, 0x49, 0xe6, 0xdf, + 0xa8, 0x63, 0xb4, 0xbd, 0x8c, 0x66, 0xc8, 0x9c, 0x43, 0x9d, 0x49, 0xc5, 0x20, 0xdc, 0x71, 0x0b, + 0xf6, 0xac, 0x49, 0x9a, 0xe0, 0x4f, 0xa9, 0x3a, 0x00, 0x0c, 0x01, 0x5e, 0xfd, 0xbc, 0xdc, 0xbc, + 0x3f, 0x4b, 0xd6, 0xf6, 0x59, 0x48, 0x57, 0xdd, 0xbe, 0xa3, 0xbf, 0x6e, 0x9c, 0x52, 0x3c, 0xa8, + 0xde, 0x49, 0x56, 0x9a, 0x69, 0x01, 0x86, 0xf5, 0x48, 0x2f, 0xe8, 0xe6, 0xf2, 0x16, 0xf0, 0xee, + 0xe3, 0xf9, 0xce, 0x42, 0x13, 0x7d, 0x8e, 0xa5, 0xb2, 0xb4, 0x04, 0xc2, 0x82, 0xe2, 0x1e, 0xaf, + 0xc9, 0xa0, 0x2c, 0x68, 0x01, 0xde, 0xbf, 0x4f, 0x56, 0x55, 0x3d, 0x8f, 0xf4, 0x6b, 0x77, 0x32, + 0x0c, 0xaf, 0x9b, 0x5c, 0x5e, 0x8f, 0x52, 0x6a, 0xcb, 0x91, 0xa2, 0xa3, 0x63, 0x36, 0x9f, 0xea, + 0x35, 0x75, 0x6f, 0x17, 0xcc, 0xd2, 0x24, 0x21, 0x74, 0xcc, 0x32, 0x72, 0x2e, 0x99, 0x8d, 0x01, + 0xcf, 0x96, 0xf7, 0xaa, 0xaa, 0xb7, 0x13, 0xd1, 0x2e, 0xf0, 0x7d, 0x8f, 0x7c, 0xa8, 0xfe, 0x42, + 0x18, 0x7a, 0x46, 0xec, 0x46, 0x2a, 0x1f, 0xf3, 0xef, 0x2e, 0xc7, 0x74, 0x7f, 0x60, 0x46, 0xf1, + 0x9b, 0xb8, 0x45, 0x6e, 0x88, 0x3f, 0x71, 0xd8, 0xea, 0x43, 0x9e, 0x4b, 0xd9, 0x7b, 0xa9, 0xac, + 0x86, 0xf8, 0x20, 0x71, 0xf4, 0x81, 0xfa, 0xed, 0x4a, 0x46, 0xb7, 0xe6, 0xdd, 0x62, 0x2c, 0xcf, + 0x92, 0xcc, 0xb4, 0x4f, 0x5e, 0x33, 0xa0, 0xfe, 0xea, 0xcd, 0x41, 0x68, 0x1f, 0x7e, 0xc4, 0xc3, + 0x38, 0x67, 0x65, 0x37, 0xad, 0xc5, 0x88, 0xac, 0x51, 0x71, 0xfa, 0xec, 0x5a, 0x6d, 0x6b, 0x20, + 0x64, 0x81, 0xbc, 0x75, 0x7c, 0x2e, 0xf4, 0xb3, 0xfb, 0x5e, 0x0c, 0xbf, 0x14, 0x0f, 0x7d, 0x94, + 0x1a, 0x20, 0x11, 0xd4, 0x25, 0x4f, 0x24, 0x10, 0xe0, 0x80, 0x01, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1139,7 +1117,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA100_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA100_patch_loc_data[] = { - 0x00, 0x1d, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c index c2bfa9681..f311434ef 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_GA102.c @@ -34,472 +34,459 @@ // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9216 -// COMPRESSED SIZE (bytes): 7365 +// DATA SIZE (bytes): 8960 +// COMPRESSED SIZE (bytes): 7153 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data[] = { - 0xed, 0xd9, 0x45, 0x50, 0x1c, 0x80, 0xb2, 0xa8, 0x61, 0xdc, 0x35, 0xb8, 0xbb, 0x3b, 0x04, 0x4d, - 0x70, 0x77, 0x06, 0xf7, 0xe0, 0x16, 0x1c, 0x32, 0x10, 0x82, 0x13, 0x7c, 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0xa5, + 0x6c, 0xf4, 0xaa, 0x3b, 0xc9, 0xec, 0x6c, 0x06, 0xd1, 0x1b, 0xf7, 0x60, 0xaa, 0x32, 0x32, 0x7e, + 0xb6, 0x4c, 0x4e, 0x2d, 0x2a, 0x0e, 0x3e, 0xe7, 0x0e, 0xeb, 0x84, 0x71, 0x16, 0xe7, 0xcf, 0x94, + 0x98, 0xfd, 0xf1, 0xc5, 0x1d, 0x5f, 0xc3, 0x7c, 0x02, 0x83, 0xf2, 0xc1, 0xb2, 0x7d, 0xcd, 0xba, + 0x36, 0x6b, 0xfd, 0x30, 0x5d, 0x5f, 0xde, 0xb9, 0x74, 0xdf, 0xc0, 0x71, 0x04, 0x46, 0xef, 0xfd, + 0x2b, 0xba, 0x4a, 0x2d, 0x15, 0x51, 0x02, 0x6e, 0x4e, 0x29, 0x22, 0xef, 0xaa, 0x4b, 0x96, 0x31, + 0x37, 0xd5, 0x80, 0xbf, 0x86, 0xa5, 0x72, 0x98, 0x4c, 0xae, 0x60, 0x3f, 0xf0, 0xa0, 0x7c, 0xf0, + 0xb6, 0xf8, 0xc1, 0xad, 0xc2, 0x89, 0xc0, 0x2d, 0x10, 0x2f, 0xfd, 0x6c, 0x9c, 0x2b, 0xf8, 0x16, + 0x81, 0x58, 0x53, 0xbf, 0x39, 0xdc, 0xe7, 0x7f, 0x9b, 0xff, 0xaf, 0xff, 0x8f, 0xff, 0xf5, 0x5f, + 0xff, 0xf5, 0x5f, 0xff, 0xf5, 0x7f, 0xe3, 0x7f, 0x00, 0x1d, 0x39, 0xbc, 0x61, 0x00, 0x23, 0x00, + 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -509,8 +496,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 9216, // uncompressed data size (bytes) - 7365, // compressed data size (bytes) + 8960, // uncompressed data size (bytes) + 7153, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -532,8 +519,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x03, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x8d, 0x53, 0x58, 0xc0, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -561,472 +548,458 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_ga10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 9216 -// COMPRESSED SIZE (bytes): 7363 +// DATA SIZE (bytes): 8960 +// COMPRESSED SIZE (bytes): 7151 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data[] = { - 0xed, 0xd9, 0x43, 0x74, 0x1d, 0x00, 0xb7, 0xb0, 0xe1, 0xd8, 0x8d, 0x6d, 0x9e, 0x18, 0x0d, 0x1b, - 0xe3, 0xc4, 0xb6, 0x9d, 0x34, 0x3e, 0xf1, 0x09, 0x1a, 0xdb, 0xb6, 0xcd, 0x13, 0xdb, 0x36, 0x1a, - 0x9b, 0x4d, 0x83, 0xc6, 0x6a, 0xdc, 0x24, 0xff, 0x3f, 0xfe, 0xc6, 0x77, 0xad, 0x3b, 0xb8, 0xdf, - 0x33, 0xdb, 0xe3, 0xbd, 0xd6, 0x3b, 0xd8, 0x1b, 0x0a, 0xea, 0xff, 0xb6, 0xee, 0x7b, 0x53, 0x48, - 0x2a, 0xd5, 0x21, 0x2f, 0xce, 0x82, 0x19, 0xe8, 0x43, 0x9f, 0x6a, 0x74, 0x7f, 0x91, 0x1d, 0x39, - 0x04, 0x66, 0xd8, 0xcd, 0x50, 0x7d, 0x69, 0xa9, 0x91, 0xaf, 0x2f, 0xff, 0xd7, 0x41, 0x59, 0x1c, - 0xcd, 0xf9, 0x2b, 0x57, 0x6e, 0xc9, 0x32, 0xe5, 0x9f, 0x92, 0x96, 0xbf, 0xed, 0x47, 0xb2, 0xce, - 0x38, 0x07, 0x81, 0x54, 0x95, 0x68, 0x24, 0x79, 0xfd, 0xbb, 0x4b, 0x81, 0x05, 0x62, 0x6c, 0x6d, - 0x95, 0x2c, 0x29, 0x4f, 0x89, 0xf6, 0xf3, 0x38, 0x9f, 0x32, 0xfd, 0x3f, 0x70, 0x91, 0x00, 0xda, - 0x0f, 0xc9, 0x0a, 0x49, 0xeb, 0x5d, 0xa4, 0xb7, 0x9a, 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0xf5, 0x5f, + 0xff, 0xf5, 0x5f, 0xff, 0x37, 0xfe, 0x07, 0x12, 0x7f, 0x27, 0x64, 0x00, 0x23, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1036,8 +1009,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 9216, // uncompressed data size (bytes) - 7363, // compressed data size (bytes) + 8960, // uncompressed data size (bytes) + 7151, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1059,8 +1032,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x03, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x42, 0x69, - 0x20, 0x00, 0x00, 0x8d, 0x53, 0x58, 0xc0, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x05, 0x62, 0x56, 0x08, 0x13, 0x4c, 0xc8, 0x40, 0x69, + 0x20, 0x00, 0x00, 0x8e, 0xa1, 0x42, 0xb2, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1093,55 +1066,55 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_data[] = { - 0x01, 0x00, 0x03, 0xff, 0xfc, 0x0c, 0x62, 0x10, 0xd7, 0x88, 0x37, 0x32, 0x49, 0x2b, 0x50, 0xe2, - 0xcb, 0xcf, 0x76, 0x35, 0xce, 0xea, 0x5b, 0xbb, 0x5c, 0xc3, 0x43, 0x6c, 0x42, 0xf0, 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0xe1, 0x45, 0x4e, 0x71, + 0x52, 0x92, 0xd1, 0x7c, 0x2f, 0xbf, 0x83, 0xfa, 0x03, 0xcf, 0xeb, 0x49, 0xf9, 0xc0, 0xa0, 0x96, + 0xc6, 0x2d, 0x8e, 0x6d, 0x99, 0x64, 0x9a, 0x4f, 0x23, 0x6d, 0x2a, 0x0b, 0x24, 0x7c, 0xb5, 0x42, + 0x1b, 0x25, 0x28, 0xe6, 0x03, 0x78, 0x19, 0x83, 0xd0, 0x0f, 0x17, 0xfc, 0xed, 0x45, 0xca, 0xb4, + 0x6c, 0xf1, 0xea, 0x23, 0x07, 0xa4, 0x3a, 0x54, 0x5e, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1170,37 +1143,37 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_dbg_storage_pvt; // COMPRESSION: YES // COMPLEX_STRUCT: NO // DATA SIZE (bytes): 768 -// COMPRESSED SIZE (bytes): 418 +// COMPRESSED SIZE (bytes): 421 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data[] = { - 0x4b, 0x3b, 0x68, 0xf7, 0x2e, 0x61, 0xcb, 0x73, 0xf1, 0x99, 0x52, 0xc1, 0xb6, 0xcf, 0x56, 0x7c, - 0xaf, 0x38, 0x79, 0x7a, 0xc1, 0x85, 0xff, 0x12, 0x52, 0xf6, 0x2b, 0x34, 0xc2, 0x56, 0x05, 0x87, - 0xf4, 0x2b, 0xf0, 0xd8, 0xad, 0x2b, 0xed, 0x8f, 0x0d, 0xf4, 0x75, 0x76, 0xae, 0xdc, 0x2b, 0xbc, - 0x22, 0xbd, 0x6d, 0xbd, 0x86, 0xcd, 0xc2, 0x00, 0x17, 0xaf, 0x48, 0xb6, 0x46, 0xc3, 0x2d, 0x7f, - 0x4c, 0xf2, 0xff, 0xbd, 0x3c, 0x91, 0x51, 0x23, 0xf1, 0xa5, 0xae, 0x7e, 0xe6, 0x7f, 0x33, 0x1e, - 0x6f, 0xd1, 0x87, 0xb6, 0xd7, 0x34, 0x52, 0xcf, 0x6b, 0xeb, 0xf7, 0x4a, 0x04, 0x9b, 0xad, 0x98, - 0x16, 0xc1, 0xed, 0xc2, 0xc4, 0xf6, 0x2e, 0xff, 0x88, 0x81, 0xd0, 0xda, 0x1b, 0x07, 0x9f, 0x09, - 0x9b, 0xd4, 0x49, 0x2a, 0x2a, 0x5c, 0x6e, 0xdd, 0x1a, 0x6f, 0xf2, 0x48, 0x40, 0x5a, 0x67, 0xe3, - 0x0f, 0x96, 0xea, 0x24, 0xc1, 0xbf, 0x6d, 0x7d, 0x8b, 0x6f, 0x29, 0x3a, 0x7d, 0xd6, 0xd9, 0xb1, - 0xe8, 0x92, 0xb9, 0xa9, 0xe4, 0xdc, 0x2b, 0x13, 0x77, 0xf3, 0xbf, 0x49, 0xd5, 0x4a, 0x3f, 0xe3, - 0xe2, 0xd2, 0xd6, 0x13, 0xf0, 0xec, 0x7f, 0xd2, 0xf5, 0x9a, 0xbf, 0x97, 0x64, 0x16, 0xee, 0x3b, - 0xa9, 0x10, 0xe7, 0x6c, 0x56, 0xbe, 0x37, 0xd1, 0xff, 0xb8, 0xdc, 0x6a, 0xcd, 0x3c, 0xbd, 0xfd, - 0x7b, 0x7e, 0x7d, 0xde, 0x94, 0xbe, 0xaf, 0xb3, 0x69, 0x09, 0x6b, 0xfc, 0xae, 0x3b, 0xab, 0x16, - 0x38, 0x96, 0x27, 0x94, 0x4d, 0xba, 0x52, 0xf6, 0xd1, 0x76, 0xe5, 0x26, 0xd7, 0xa6, 0x3d, 0x7a, - 0xc2, 0x5e, 0x3e, 0xa5, 0xe9, 0x6d, 0xbd, 0x8f, 0x3c, 0x5d, 0xad, 0x58, 0x32, 0xdb, 0x5b, 0xcd, - 0x3e, 0x3f, 0x3c, 0x13, 0x7f, 0xc6, 0xb7, 0x62, 0x3e, 0xbf, 0xb9, 0xd7, 0xab, 0xc2, 0x7a, 0xc5, - 0x3d, 0x26, 0x12, 0xe6, 0x9f, 0x4a, 0xc4, 0xe2, 0x77, 0xbb, 0x85, 0x33, 0xb8, 0xcf, 0xeb, 0xed, - 0xf9, 0x33, 0x37, 0xe5, 0x09, 0x53, 0xd3, 0x9d, 0xda, 0xa0, 0xa8, 0x2b, 0x49, 0x47, 0x55, 0xe7, - 0x2d, 0x3d, 0x2e, 0x63, 0xc9, 0xc7, 0xe5, 0x64, 0x70, 0xf0, 0xdb, 0x93, 0x5f, 0x2f, 0xd8, 0x6f, - 0xde, 0x3d, 0xdd, 0x9b, 0x3c, 0xaf, 0xe1, 0xd7, 0x43, 0xd5, 0xec, 0x97, 0xd1, 0xd6, 0xe9, 0x3f, - 0x37, 0x1e, 0xfb, 0xb7, 0x59, 0x73, 0xa2, 0xd6, 0x26, 0x09, 0x77, 0xc6, 0x1d, 0xbf, 0x83, 0x65, - 0x6a, 0xfa, 0x97, 0xd4, 0xad, 0xf6, 0xef, 0x38, 0x6b, 0x12, 0xdc, 0x72, 0x48, 0x33, 0xf7, 0x88, - 0xdc, 0x9d, 0x1b, 0x01, 0x2b, 0x04, 0x37, 0xe5, 0x15, 0x1f, 0x71, 0x58, 0x7a, 0xcc, 0xc9, 0x72, - 0x76, 0xfa, 0xca, 0x6b, 0xd7, 0x97, 0x3e, 0x7f, 0xc1, 0x7b, 0x29, 0xf1, 0xdf, 0xbc, 0xcf, 0x29, - 0xce, 0x33, 0xa5, 0x0c, 0xfb, 0xf5, 0x1e, 0x0a, 0x27, 0x49, 0x15, 0xfa, 0x45, 0xbc, 0x38, 0xaf, - 0x52, 0xe5, 0x1d, 0xce, 0x30, 0x0a, 0x06, 0x14, 0x00, 0x00, 0xa0, 0x3f, 0xc7, 0x35, 0x00, 0x03, - 0x00, 0x00, + 0xf3, 0x7a, 0x16, 0x2f, 0x7b, 0x64, 0xf9, 0xec, 0x6f, 0x41, 0xdb, 0x45, 0x3a, 0x1e, 0x37, 0x6d, + 0xbf, 0xbb, 0xf4, 0x9e, 0x44, 0x03, 0xab, 0xf2, 0x5d, 0xfd, 0x89, 0xec, 0x52, 0x97, 0xde, 0x5d, + 0x58, 0xc7, 0xd6, 0xb0, 0x7d, 0xd2, 0x97, 0x53, 0x49, 0xb9, 0x12, 0x76, 0x0f, 0x19, 0x7e, 0x7f, + 0xdb, 0xd6, 0x1b, 0xb2, 0x5a, 0xf4, 0xec, 0xc2, 0xf0, 0x27, 0x9e, 0xad, 0x82, 0xfb, 0x37, 0xcd, + 0x64, 0x50, 0x3e, 0xeb, 0xbd, 0x99, 0x93, 0x71, 0x7e, 0xd9, 0x19, 0xd7, 0xaf, 0xea, 0xcb, 0xac, + 0xf8, 0x1c, 0xfb, 0x36, 0x05, 0xcc, 0x92, 0x90, 0xb9, 0x9e, 0x55, 0x19, 0x3e, 0x73, 0xc2, 0x77, + 0xf7, 0xb3, 0xfb, 0xb2, 0x94, 0x3c, 0x55, 0xa7, 0xee, 0xc8, 0x64, 0x9b, 0x23, 0xac, 0x94, 0xba, + 0x4d, 0x5e, 0x63, 0xf7, 0xc4, 0x52, 0x87, 0xcb, 0xb7, 0xaf, 0x5b, 0x7e, 0x79, 0x70, 0xe5, 0xba, + 0xaf, 0xff, 0xdf, 0x9e, 0x47, 0x17, 0x45, 0x8f, 0x19, 0xfd, 0x5c, 0x98, 0x7d, 0xb5, 0x68, 0x8e, + 0xe3, 0x36, 0x35, 0x91, 0x50, 0x67, 0xdb, 0xcb, 0x36, 0x97, 0x19, 0x03, 0xb6, 0x6d, 0x4d, 0x16, + 0xb8, 0xa1, 0xea, 0x39, 0x4b, 0xe4, 0x46, 0x97, 0xa4, 0xc8, 0xe3, 0x37, 0x39, 0x61, 0x52, 0x9b, + 0x5d, 0xcf, 0xee, 0xd9, 0x11, 0xc9, 0xb4, 0x46, 0x42, 0x69, 0xd2, 0xfe, 0x04, 0x21, 0xd3, 0xdd, + 0xd9, 0xea, 0x1c, 0x67, 0xae, 0xe8, 0x38, 0xc4, 0x9d, 0x99, 0x7c, 0xa0, 0x6e, 0x4d, 0xa5, 0xd9, + 0x81, 0x7b, 0x9f, 0x3d, 0xf6, 0x44, 0x1b, 0x16, 0x65, 0xac, 0x7c, 0x96, 0x37, 0x4b, 0xf9, 0x52, + 0xc6, 0x2a, 0xeb, 0x05, 0x7e, 0xcf, 0x4f, 0xaf, 0x3f, 0xff, 0xc2, 0x98, 0x69, 0xf6, 0x4f, 0x1b, + 0xc6, 0x37, 0x25, 0xff, 0x04, 0x6a, 0xd8, 0x1b, 0x19, 0xb7, 0xdd, 0x3b, 0xdd, 0x32, 0x9f, 0x63, + 0xc7, 0xa3, 0x19, 0x9d, 0xd7, 0xbd, 0xd7, 0x1f, 0xba, 0xd4, 0x7a, 0x30, 0xbb, 0x6e, 0xd1, 0x45, + 0xe9, 0xda, 0xde, 0x94, 0x57, 0x27, 0x12, 0xad, 0xfe, 0x6b, 0x86, 0x7f, 0x0b, 0xb8, 0xb2, 0xe4, + 0x8c, 0x47, 0x4c, 0xe7, 0xc3, 0x1d, 0x96, 0xfa, 0x9e, 0x87, 0xaf, 0x4a, 0x97, 0xad, 0x4d, 0xf4, + 0xca, 0x3d, 0x79, 0xac, 0x55, 0x4e, 0xb1, 0xc7, 0x82, 0xd7, 0x2f, 0x8b, 0xf7, 0xcd, 0x97, 0xeb, + 0x3b, 0x66, 0x2b, 0x68, 0x65, 0x57, 0xfd, 0xef, 0x8d, 0x53, 0x78, 0xd3, 0xfd, 0xed, 0x49, 0xe6, + 0xa5, 0xb9, 0x86, 0xaf, 0x15, 0xae, 0x7f, 0x5b, 0x90, 0x3a, 0xdb, 0x52, 0xb5, 0x73, 0x57, 0x41, + 0xb9, 0xc7, 0xb3, 0xa2, 0x29, 0xf7, 0x2f, 0x27, 0x35, 0xa8, 0x15, 0x1c, 0x95, 0x5a, 0xeb, 0xf8, + 0xc4, 0x83, 0x4b, 0xfc, 0xc5, 0xf9, 0x75, 0xb9, 0x95, 0xe6, 0x9f, 0x14, 0x39, 0xf7, 0x6c, 0x5a, + 0xf5, 0xc9, 0xe8, 0x42, 0x8c, 0x97, 0xe8, 0x1a, 0xe6, 0x73, 0x05, 0xbb, 0xd2, 0x9a, 0xff, 0xdf, + 0xf4, 0x8c, 0xfa, 0xf8, 0x62, 0xa2, 0x33, 0xc3, 0x28, 0x18, 0x50, 0x00, 0x00, 0x6f, 0x81, 0x84, + 0xf3, 0x00, 0x03, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1211,7 +1184,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { 768, // uncompressed data size (bytes) - 418, // compressed data size (bytes) + 421, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -1233,7 +1206,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_GA102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_GA102_patch_loc_data[] = { - 0x10, 0x1e, 0x00, 0x00, + 0x10, 0x1d, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c index 0ff75f7ce..723f63e70 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU102.c @@ -34,436 +34,424 @@ // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8448 -// COMPRESSED SIZE (bytes): 6785 +// DATA SIZE (bytes): 8192 +// COMPRESSED SIZE (bytes): 6600 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0x5a, 0xb0, 0xb5, 0x1b, 0x77, 0x0d, 0x4e, 0x70, 0x77, 0xd7, 0x60, - 0x41, 0x83, 0x5b, 0x08, 0x4e, 0xe3, 0x04, 0x08, 0x4e, 0xd0, 0xd0, 0xd0, 0xb8, 0x04, 0x77, 0x6d, - 0x5c, 0x82, 0xbb, 0xbb, 0x4b, 0x1a, 0x77, 0x77, 0x82, 0x5b, 0xa0, 0xf1, 0x77, 0xdf, 0xf4, 0xce, - 0xde, 0xe0, 0x9f, 0xfc, 0xeb, 0x7e, 0x93, 0x5d, 0x7b, 0x72, 0xea, 0x0c, 0xaa, 0xd6, 0xda, 0x67, - 0x9d, 0x08, 0x00, 0x00, 0xee, 0x35, 0x09, 0x00, 0xc2, 0x01, 0x00, 0x60, 0xf0, 0x30, 0xc0, 0x03, - 0x7c, 0x34, 0x00, 0x1e, 0xd0, 0xbd, 0xb1, 0xf9, 0xf6, 0xf6, 0x86, 0x13, 0x01, 0x80, 0x03, 0xbc, - 0x41, 0x10, 0xeb, 0xf7, 0x00, 0x7c, 0x69, 0xcb, 0x70, 0xf5, 0x49, 0x00, 0xf6, 0xb4, 0x65, 0xf8, - 0x7f, 0x84, 0x21, 0x6d, 0x19, 0xe1, 0x1f, 0xa1, 0x8c, 0x00, 0x00, 0x00, 0x69, 0x10, 0x84, 0xc6, - 0x4d, 0x84, 0x6e, 0x48, 0xee, 0x66, 0x1a, 0x04, 0x2e, 0x2d, 0x1d, 0xbe, 0x71, 0x13, 0xae, 0x71, - 0x19, 0x1e, 0xd4, 0x04, 0x00, 0xe0, 0xf0, 0x28, 0x02, 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0x46, 0xf7, 0x7f, 0x9b, 0xff, + 0x77, 0xdf, 0x92, 0xff, 0xf1, 0x3f, 0xfe, 0xc7, 0xff, 0xf8, 0x1f, 0xff, 0xbf, 0xf0, 0xff, 0x00, + 0x2e, 0x7a, 0xf5, 0x3c, 0x00, 0x20, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -473,8 +461,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8448, // uncompressed data size (bytes) - 6785, // compressed data size (bytes) + 8192, // uncompressed data size (bytes) + 6600, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -496,8 +484,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x37, 0x0f, 0x4b, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -525,436 +513,424 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu10x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8448 -// COMPRESSED SIZE (bytes): 6785 +// DATA SIZE (bytes): 8192 +// COMPRESSED SIZE (bytes): 6599 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1c, 0x0a, 0xac, 0xf7, 0x07, 0x77, 0xf7, 0xe2, 0xee, 0xee, 0x1d, 0xac, - 0xb8, 0xfb, 0x40, 0x71, 0x28, 0xee, 0x5a, 0x1c, 0x5a, 0x1c, 0x06, 0x2d, 0x3a, 0x14, 0xb7, 0xe2, - 0x30, 0x0c, 0xee, 0x5e, 0x4a, 0xa1, 0xb8, 0xbb, 0xb6, 0x78, 0xd1, 0xc1, 0xe1, 0xdd, 0xb7, 0xbd, - 0xbb, 0xb7, 0xf8, 0x36, 0xdf, 0xb9, 0xbf, 0xcd, 0x3f, 0xd9, 0x24, 0x59, 0x24, 0xe7, 0x24, 0x27, - 0x71, 0x00, 0x00, 0xc2, 0x4b, 0x3a, 0x20, 0x14, 0x0f, 0x00, 0xb8, 0x43, 0xbc, 0x03, 0xdc, 0x23, - 0x26, 0x02, 0x10, 0x01, 0xbd, 0x1b, 0x9b, 0xaf, 0xaf, 0xaf, 0x78, 0x71, 0x00, 0x04, 0xc0, 0x6b, - 0x01, 0x72, 0xe3, 0x1e, 0x40, 0x10, 0xb2, 0x8c, 0xd0, 0x98, 0x0e, 0xe0, 0x82, 0x2c, 0x23, 0xfe, - 0x23, 0xcc, 0x90, 0x65, 0xa4, 0x7f, 0x84, 0x26, 0x0e, 0x00, 0x00, 0x40, 0x0a, 0x90, 0x9a, 0x37, - 0x91, 0x7a, 0x0b, 0x0a, 0x37, 0x21, 0x05, 0x08, 0x90, 0x6c, 0xc4, 0xe6, 0x4d, 0x84, 0xe6, 0x65, - 0xc4, 0xd0, 0x16, 0x00, 0x00, 0x8f, 0x5f, 0x05, 0x80, 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0x62, 0xbb, 0xcc, 0xfc, 0x96, 0x93, 0x9d, 0xe8, + 0x1a, 0xd6, 0xa8, 0x6a, 0x4d, 0x22, 0x63, 0x14, 0x70, 0x53, 0xaf, 0x70, 0xcd, 0x5c, 0x28, 0xb6, + 0x64, 0x98, 0xd3, 0x40, 0xf5, 0x36, 0x0b, 0x4b, 0x40, 0x55, 0x98, 0xa5, 0x94, 0x30, 0x03, 0xb1, + 0xd2, 0x14, 0x6b, 0xe1, 0x7d, 0xa2, 0xd0, 0xf8, 0x80, 0xe5, 0xb0, 0xd3, 0x45, 0x4c, 0x0c, 0x04, + 0xba, 0x0d, 0xe9, 0x16, 0x2b, 0x33, 0xd0, 0x6a, 0x86, 0x62, 0x7e, 0x97, 0xb8, 0x44, 0xde, 0x81, + 0x90, 0xe9, 0xb6, 0x98, 0x36, 0xaa, 0x23, 0xfb, 0x8b, 0xf8, 0x16, 0xfc, 0x4a, 0x64, 0x84, 0xce, + 0xfb, 0x61, 0x03, 0x58, 0xd5, 0xa7, 0x6a, 0x1f, 0x1d, 0x30, 0xa4, 0xcc, 0xc1, 0x4f, 0x07, 0x62, + 0xb6, 0x6d, 0x1a, 0xef, 0x21, 0x01, 0xd8, 0x6e, 0x7f, 0xf4, 0x8a, 0x25, 0xb0, 0x95, 0x28, 0x02, + 0xf0, 0x57, 0x9f, 0xca, 0xc1, 0x5f, 0xfd, 0x29, 0xd1, 0xb9, 0x2c, 0xda, 0xf5, 0x18, 0xaa, 0x69, + 0x7f, 0x10, 0xb7, 0xc6, 0x7b, 0x6e, 0x24, 0xca, 0xb7, 0x8c, 0x15, 0xdc, 0x24, 0x37, 0x97, 0xb3, + 0x48, 0x58, 0x1f, 0xa8, 0x6f, 0x63, 0x12, 0x38, 0x2d, 0xc1, 0xd5, 0x5d, 0x71, 0xfe, 0x57, 0xff, + 0x7f, 0xfb, 0x96, 0xfc, 0xcb, 0xbf, 0xfc, 0xcb, 0xbf, 0xfc, 0xcb, 0xff, 0x17, 0xfe, 0x0f, 0xec, + 0x88, 0x8e, 0x95, 0x00, 0x20, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -964,8 +940,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8448, // uncompressed data size (bytes) - 6785, // compressed data size (bytes) + 8192, // uncompressed data size (bytes) + 6599, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU102_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -987,8 +963,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x37, 0x0f, 0x4b, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1021,7 +997,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_data[] = { - 0x1d, 0x5d, 0xcc, 0x87, 0xb8, 0x39, 0xaf, 0xfe, 0x80, 0xb7, 0x76, 0x7e, 0x93, 0x93, 0x30, 0xd1, + 0x8d, 0xf3, 0xbb, 0x29, 0x1d, 0x0d, 0xac, 0xa0, 0xce, 0x43, 0xd8, 0xc5, 0x51, 0xb0, 0xd0, 0x9d, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1054,7 +1030,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_data[] = { - 0xe4, 0x53, 0xfd, 0x5f, 0x0f, 0xf8, 0x70, 0x57, 0x0e, 0xfb, 0x23, 0x4f, 0xbe, 0xe7, 0xc2, 0x95, + 0x5b, 0xe8, 0xcf, 0xaa, 0x40, 0x4a, 0x12, 0xff, 0xf0, 0xe8, 0x39, 0x5b, 0x2e, 0x44, 0x7a, 0x64, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1087,7 +1063,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU102_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU102_patch_loc_data[] = { - 0x00, 0x1d, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c index 1b2e6ffd7..9501f9f42 100644 --- a/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c +++ b/src/nvidia/generated/g_bindata_kgspGetBinArchiveBooterUnloadUcode_TU116.c @@ -34,436 +34,424 @@ // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8448 -// COMPRESSED SIZE (bytes): 6800 +// DATA SIZE (bytes): 8192 +// COMPRESSED SIZE (bytes): 6602 // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data[] = { - 0xed, 0x99, 0x45, 0x54, 0x1b, 0x00, 0xb3, 0xb6, 0x13, 0xdc, 0x09, 0x92, 0xe2, 0x50, 0x9c, 0xe0, - 0xee, 0x56, 0xb4, 0x78, 0x29, 0xc5, 0x4b, 0x71, 0x28, 0xa5, 0x48, 0x71, 0x29, 0xee, 0x50, 0xa4, - 0xb8, 0x14, 0x12, 0x5c, 0x82, 0xbb, 0x7b, 0x21, 0x14, 0x08, 0x5e, 0xdc, 0xdd, 0x8b, 0x14, 0x97, - 0xdb, 0xbb, 0xfd, 0x76, 0x77, 0xf1, 0x6f, 0xfe, 0xf3, 0x3d, 0x9b, 0x77, 0x66, 0x33, 0x33, 0x8b, - 0x99, 0x73, 0xde, 0x73, 0x26, 0x0a, 0x00, 0x00, 0x3e, 0x25, 0x03, 0xfc, 0x09, 0x01, 0x80, 0x1b, - 0x94, 0x1b, 0xc0, 0x2d, 0x4a, 0x2c, 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(bytes) + 6602, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -496,8 +484,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x37, 0x0f, 0x4b, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -525,436 +513,424 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_dbg_storage_pvt // VAR NAME: booter_ucode_data_tu11x // COMPRESSION: YES // COMPLEX_STRUCT: NO -// DATA SIZE (bytes): 8448 -// COMPRESSED SIZE (bytes): 6797 +// DATA SIZE (bytes): 8192 +// COMPRESSED SIZE (bytes): 6594 // static BINDATA_CONST NvU8 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0x71, + 0x27, 0x19, 0xaa, 0xb5, 0xad, 0xbf, 0x89, 0x28, 0xf8, 0x5f, 0xfd, 0xff, 0xed, 0x5b, 0xf2, 0x2f, + 0xff, 0xf2, 0x2f, 0xff, 0xf2, 0x2f, 0xff, 0x5f, 0xf8, 0x3f, 0x25, 0xd9, 0x85, 0x43, 0x00, 0x20, + 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -964,8 +940,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt #if defined(BINDATA_INCLUDE_STORAGE_PVT_DEFN) { - 8448, // uncompressed data size (bytes) - 6797, // compressed data size (bytes) + 8192, // uncompressed data size (bytes) + 6594, // compressed data size (bytes) kgspBinArchiveBooterUnloadUcode_TU116_image_prod_data, // compressed data pointer NV_TRUE, // is pData compressed? NV_TRUE, // contain information for file overriding? @@ -987,8 +963,8 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_image_prod_storage_pvt // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_header_prod_data[] = { - 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x06, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x41, 0x69, - 0x20, 0x00, 0x00, 0x37, 0x0f, 0x4b, 0x90, 0x24, 0x00, 0x00, 0x00, + 0x63, 0x60, 0x00, 0x02, 0x46, 0x20, 0x96, 0x02, 0x62, 0x36, 0x08, 0x13, 0x4c, 0x48, 0x42, 0x69, + 0x20, 0x00, 0x00, 0x77, 0x72, 0x25, 0x67, 0x24, 0x00, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1021,7 +997,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_header_prod_storage_pv // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_data[] = { - 0x6a, 0x5e, 0x0c, 0x35, 0x0d, 0x7e, 0x26, 0x93, 0xd3, 0x96, 0x82, 0x5e, 0xcc, 0x37, 0xe3, 0xc6, + 0xd2, 0xd7, 0x61, 0x5d, 0x7e, 0x54, 0x57, 0xef, 0xa8, 0xba, 0xb0, 0x6c, 0x4b, 0xf1, 0x2b, 0xbc, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1054,7 +1030,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_dbg_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_data[] = { - 0x37, 0x5b, 0xb4, 0x8f, 0x0f, 0x86, 0x44, 0xb7, 0xba, 0xdf, 0xb7, 0xbb, 0x72, 0xe4, 0xec, 0x9a, + 0x6b, 0x77, 0x25, 0x37, 0xf0, 0xfe, 0x01, 0x30, 0x26, 0xef, 0xb5, 0x87, 0x87, 0xff, 0x2c, 0x57, }; #endif // defined(BINDATA_INCLUDE_DATA) @@ -1087,7 +1063,7 @@ BINDATA_STORAGE_PVT kgspBinArchiveBooterUnloadUcode_TU116_sig_prod_storage_pvt; // static BINDATA_CONST NvU8 kgspBinArchiveBooterUnloadUcode_TU116_patch_loc_data[] = { - 0x00, 0x1d, 0x00, 0x00, + 0x00, 0x1c, 0x00, 0x00, }; #endif // defined(BINDATA_INCLUDE_DATA) diff --git a/src/nvidia/generated/g_gpu_mgr_nvoc.h b/src/nvidia/generated/g_gpu_mgr_nvoc.h index 51589d7ea..ed97fc351 100644 --- a/src/nvidia/generated/g_gpu_mgr_nvoc.h +++ b/src/nvidia/generated/g_gpu_mgr_nvoc.h @@ -233,6 +233,18 @@ typedef struct GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY GPUMGR_SAVE_GPU_INSTANCE saveGI[GPUMGR_MAX_GPU_INSTANCES]; } GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY; + +#include "containers/list.h" +typedef struct PCIEP2PCAPSINFO +{ + NvU32 gpuId[GPUMGR_MAX_GPU_INSTANCES]; // Group of GPUs + NvU32 gpuCount; // GPU count in gpuId[] + NvU8 p2pWriteCapsStatus; // PCIE P2P CAPS status for this group of GPUs + NvU8 p2pReadCapsStatus; + ListNode node; // For intrusive lists +} PCIEP2PCAPSINFO; +MAKE_INTRUSIVE_LIST(pcieP2PCapsInfoList, PCIEP2PCAPSINFO, node); + #ifdef NVOC_GPU_MGR_H_PRIVATE_ACCESS_ALLOWED #define PRIVATE_FIELD(x) x #else @@ -260,6 +272,8 @@ struct OBJGPUMGR { GPUMGR_SAVE_MIG_INSTANCE_TOPOLOGY MIGTopologyInfo[32]; GPU_HANDLE_ID gpuHandleIDList[32]; NvU32 numGpuHandles; + pcieP2PCapsInfoList pcieP2PCapsInfoCache; + void *pcieP2PCapsInfoLock; }; #ifndef __NVOC_CLASS_OBJGPUMGR_TYPEDEF__ @@ -290,6 +304,31 @@ NV_STATUS __nvoc_objCreate_OBJGPUMGR(OBJGPUMGR**, Dynamic*, NvU32); #define __objCreate_OBJGPUMGR(ppNewObj, pParent, createFlags) \ __nvoc_objCreate_OBJGPUMGR((ppNewObj), staticCast((pParent), Dynamic), (createFlags)) +NV_STATUS gpumgrInitPcieP2PCapsCache_IMPL(struct OBJGPUMGR *pGpuMgr); + +#define gpumgrInitPcieP2PCapsCache(pGpuMgr) gpumgrInitPcieP2PCapsCache_IMPL(pGpuMgr) +#define gpumgrInitPcieP2PCapsCache_HAL(pGpuMgr) gpumgrInitPcieP2PCapsCache(pGpuMgr) + +void gpumgrDestroyPcieP2PCapsCache_IMPL(struct OBJGPUMGR *pGpuMgr); + +#define gpumgrDestroyPcieP2PCapsCache(pGpuMgr) gpumgrDestroyPcieP2PCapsCache_IMPL(pGpuMgr) +#define gpumgrDestroyPcieP2PCapsCache_HAL(pGpuMgr) gpumgrDestroyPcieP2PCapsCache(pGpuMgr) + +NV_STATUS gpumgrStorePcieP2PCapsCache_IMPL(NvU32 gpuMask, NvU8 p2pWriteCapStatus, NvU8 p2pReadCapStatus); + +#define gpumgrStorePcieP2PCapsCache(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) gpumgrStorePcieP2PCapsCache_IMPL(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) +#define gpumgrStorePcieP2PCapsCache_HAL(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) gpumgrStorePcieP2PCapsCache(gpuMask, p2pWriteCapStatus, p2pReadCapStatus) + +void gpumgrRemovePcieP2PCapsFromCache_IMPL(NvU32 gpuId); + +#define gpumgrRemovePcieP2PCapsFromCache(gpuId) gpumgrRemovePcieP2PCapsFromCache_IMPL(gpuId) +#define gpumgrRemovePcieP2PCapsFromCache_HAL(gpuId) gpumgrRemovePcieP2PCapsFromCache(gpuId) + +NvBool gpumgrGetPcieP2PCapsFromCache_IMPL(NvU32 gpuMask, NvU8 *pP2PWriteCapStatus, NvU8 *pP2PReadCapStatus); + +#define gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) gpumgrGetPcieP2PCapsFromCache_IMPL(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) +#define gpumgrGetPcieP2PCapsFromCache_HAL(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus) + NV_STATUS gpumgrConstruct_IMPL(struct OBJGPUMGR *arg_); #define __nvoc_gpumgrConstruct(arg_) gpumgrConstruct_IMPL(arg_) void gpumgrDestruct_IMPL(struct OBJGPUMGR *arg0); diff --git a/src/nvidia/generated/g_gpu_nvoc.c b/src/nvidia/generated/g_gpu_nvoc.c index 09c6f32e6..c54acebbb 100644 --- a/src/nvidia/generated/g_gpu_nvoc.c +++ b/src/nvidia/generated/g_gpu_nvoc.c @@ -508,6 +508,22 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) { { } + // Hal function -- gpuFuseSupportsDisplay + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000003e0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 */ + { + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GM107; + } + else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__gpuFuseSupportsDisplay__ = &gpuFuseSupportsDisplay_GA100; + } + else if (0) + { + } + else if (0) + { + } + // Hal function -- gpuClearFbhubPoisonIntrForBug2924523 if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { diff --git a/src/nvidia/generated/g_gpu_nvoc.h b/src/nvidia/generated/g_gpu_nvoc.h index d3649f9a7..40ecf92fd 100644 --- a/src/nvidia/generated/g_gpu_nvoc.h +++ b/src/nvidia/generated/g_gpu_nvoc.h @@ -829,6 +829,7 @@ struct OBJGPU { struct OBJGPU *__nvoc_pbase_OBJGPU; const GPUCHILDPRESENT *(*__gpuGetChildrenPresent__)(struct OBJGPU *, NvU32 *); const CLASSDESCRIPTOR *(*__gpuGetClassDescriptorList__)(struct OBJGPU *, NvU32 *); + NvBool (*__gpuFuseSupportsDisplay__)(struct OBJGPU *); NV_STATUS (*__gpuClearFbhubPoisonIntrForBug2924523__)(struct OBJGPU *); NV_STATUS (*__gpuConstructDeviceInfoTable__)(struct OBJGPU *); NvU64 (*__gpuGetFlaVasSize__)(struct OBJGPU *, NvBool); @@ -1019,6 +1020,9 @@ struct OBJGPU { struct Subdevice *pCachedSubdevice; struct RsClient *pCachedRsClient; RM_API physicalRmApi; + struct Subdevice **pSubdeviceBackReferences; + NvU32 numSubdeviceBackReferences; + NvU32 maxSubdeviceBackReferences; NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS *pChipInfo; NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS *boardInfo; NvBool bBar2MovedByVtd; @@ -1049,6 +1053,7 @@ struct OBJGPU { NvU32 instLocOverrides4; NvBool bInstLoc47bitPaWar; NvU32 instVprOverrides; + NvBool bdisableTconOd; NvU32 optimizeUseCaseOverride; NvS16 fecsCtxswLogConsumerCount; NvS16 videoCtxswLogConsumerCount; @@ -1245,6 +1250,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32, NvU32, NvU32, NvU32 #define gpuGetChildrenPresent_HAL(pGpu, pNumEntries) gpuGetChildrenPresent_DISPATCH(pGpu, pNumEntries) #define gpuGetClassDescriptorList(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) #define gpuGetClassDescriptorList_HAL(pGpu, arg0) gpuGetClassDescriptorList_DISPATCH(pGpu, arg0) +#define gpuFuseSupportsDisplay(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) +#define gpuFuseSupportsDisplay_HAL(pGpu) gpuFuseSupportsDisplay_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuClearFbhubPoisonIntrForBug2924523_HAL(pGpu) gpuClearFbhubPoisonIntrForBug2924523_DISPATCH(pGpu) #define gpuConstructDeviceInfoTable(pGpu) gpuConstructDeviceInfoTable_DISPATCH(pGpu) @@ -2255,6 +2262,18 @@ static inline const CLASSDESCRIPTOR *gpuGetClassDescriptorList_DISPATCH(struct O return pGpu->__gpuGetClassDescriptorList__(pGpu, arg0); } +NvBool gpuFuseSupportsDisplay_GM107(struct OBJGPU *pGpu); + +NvBool gpuFuseSupportsDisplay_GA100(struct OBJGPU *pGpu); + +static inline NvBool gpuFuseSupportsDisplay_491d52(struct OBJGPU *pGpu) { + return ((NvBool)(0 != 0)); +} + +static inline NvBool gpuFuseSupportsDisplay_DISPATCH(struct OBJGPU *pGpu) { + return pGpu->__gpuFuseSupportsDisplay__(pGpu); +} + NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_GA100_KERNEL(struct OBJGPU *pGpu); static inline NV_STATUS gpuClearFbhubPoisonIntrForBug2924523_56cd7a(struct OBJGPU *pGpu) { @@ -3198,6 +3217,25 @@ static inline void gpuNotifySubDeviceEvent(struct OBJGPU *pGpu, NvU32 notifyInde #define gpuNotifySubDeviceEvent(pGpu, notifyIndex, pNotifyParams, notifyParamsSize, info32, info16) gpuNotifySubDeviceEvent_IMPL(pGpu, notifyIndex, pNotifyParams, notifyParamsSize, info32, info16) #endif //__nvoc_gpu_h_disabled +NV_STATUS gpuRegisterSubdevice_IMPL(struct OBJGPU *pGpu, struct Subdevice *pSubdevice); +#ifdef __nvoc_gpu_h_disabled +static inline NV_STATUS gpuRegisterSubdevice(struct OBJGPU *pGpu, struct Subdevice *pSubdevice) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_gpu_h_disabled +#define gpuRegisterSubdevice(pGpu, pSubdevice) gpuRegisterSubdevice_IMPL(pGpu, pSubdevice) +#endif //__nvoc_gpu_h_disabled + +void gpuUnregisterSubdevice_IMPL(struct OBJGPU *pGpu, struct Subdevice *pSubdevice); +#ifdef __nvoc_gpu_h_disabled +static inline void gpuUnregisterSubdevice(struct OBJGPU *pGpu, struct Subdevice *pSubdevice) { + NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!"); +} +#else //__nvoc_gpu_h_disabled +#define gpuUnregisterSubdevice(pGpu, pSubdevice) gpuUnregisterSubdevice_IMPL(pGpu, pSubdevice) +#endif //__nvoc_gpu_h_disabled + NV_STATUS gpuGetProcWithObject_IMPL(struct OBJGPU *pGpu, NvU32 elementID, NvU32 internalClassId, NvU32 *pPidArray, NvU32 *pPidArrayCount, MIG_INSTANCE_REF *pRef); #ifdef __nvoc_gpu_h_disabled static inline NV_STATUS gpuGetProcWithObject(struct OBJGPU *pGpu, NvU32 elementID, NvU32 internalClassId, NvU32 *pPidArray, NvU32 *pPidArrayCount, MIG_INSTANCE_REF *pRef) { diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.c b/src/nvidia/generated/g_kernel_bif_nvoc.c index 28927d5b2..e4f926e9d 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.c +++ b/src/nvidia/generated/g_kernel_bif_nvoc.c @@ -78,6 +78,10 @@ static NV_STATUS __nvoc_thunk_KernelBif_engstateStateLoad(struct OBJGPU *pGpu, s return kbifStateLoad(pGpu, (struct KernelBif *)(((unsigned char *)pKernelBif) - __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } +static NV_STATUS __nvoc_thunk_KernelBif_engstateStatePostLoad(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBif, NvU32 arg0) { + return kbifStatePostLoad(pGpu, (struct KernelBif *)(((unsigned char *)pKernelBif) - __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); +} + static NV_STATUS __nvoc_thunk_KernelBif_engstateStateUnload(struct OBJGPU *pGpu, struct OBJENGSTATE *pKernelBif, NvU32 arg0) { return kbifStateUnload(pGpu, (struct KernelBif *)(((unsigned char *)pKernelBif) - __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); } @@ -130,10 +134,6 @@ static void __nvoc_thunk_OBJENGSTATE_kbifFreeTunableState(POBJGPU pGpu, struct K engstateFreeTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), pTunableState); } -static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifStatePostLoad(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { - return engstateStatePostLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), arg0); -} - static NV_STATUS __nvoc_thunk_OBJENGSTATE_kbifAllocTunableState(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { return engstateAllocTunableState(pGpu, (struct OBJENGSTATE *)(((unsigned char *)pEngstate) + __nvoc_rtti_KernelBif_OBJENGSTATE.offset), ppTunableState); } @@ -274,6 +274,15 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifStateLoad__ = &kbifStateLoad_IMPL; } + // Hal function -- kbifStatePostLoad + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + pThis->__kbifStatePostLoad__ = &kbifStatePostLoad_IMPL; + } + // Hal function -- kbifStateUnload if (0) { @@ -296,6 +305,23 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifIsPciIoAccessEnabled__ = &kbifIsPciIoAccessEnabled_491d52; } + // Hal function -- kbifInitRelaxedOrderingFromEmulatedConfigSpace + if (0) + { + } + else if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ + { + if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100; + } + // default + else + { + pThis->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__ = &kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a; + } + } + // Hal function -- kbifApplyWARBug3208922 if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 */ { @@ -312,6 +338,8 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__nvoc_base_OBJENGSTATE.__engstateStateLoad__ = &__nvoc_thunk_KernelBif_engstateStateLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__ = &__nvoc_thunk_KernelBif_engstateStatePostLoad; + pThis->__nvoc_base_OBJENGSTATE.__engstateStateUnload__ = &__nvoc_thunk_KernelBif_engstateStateUnload; pThis->__kbifReconcileTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifReconcileTunableState; @@ -338,8 +366,6 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner * pThis->__kbifFreeTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifFreeTunableState; - pThis->__kbifStatePostLoad__ = &__nvoc_thunk_OBJENGSTATE_kbifStatePostLoad; - pThis->__kbifAllocTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifAllocTunableState; pThis->__kbifSetTunableState__ = &__nvoc_thunk_OBJENGSTATE_kbifSetTunableState; diff --git a/src/nvidia/generated/g_kernel_bif_nvoc.h b/src/nvidia/generated/g_kernel_bif_nvoc.h index f51345929..a1a88dd29 100644 --- a/src/nvidia/generated/g_kernel_bif_nvoc.h +++ b/src/nvidia/generated/g_kernel_bif_nvoc.h @@ -91,8 +91,10 @@ struct KernelBif { NV_STATUS (*__kbifConstructEngine__)(struct OBJGPU *, struct KernelBif *, ENGDESCRIPTOR); NV_STATUS (*__kbifStateInitLocked__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifStateLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); + NV_STATUS (*__kbifStatePostLoad__)(struct OBJGPU *, struct KernelBif *, NvU32); NV_STATUS (*__kbifStateUnload__)(struct OBJGPU *, struct KernelBif *, NvU32); NvBool (*__kbifIsPciIoAccessEnabled__)(struct OBJGPU *, struct KernelBif *); + void (*__kbifInitRelaxedOrderingFromEmulatedConfigSpace__)(struct OBJGPU *, struct KernelBif *); void (*__kbifApplyWARBug3208922__)(struct OBJGPU *, struct KernelBif *); NV_STATUS (*__kbifReconcileTunableState__)(POBJGPU, struct KernelBif *, void *); NV_STATUS (*__kbifStatePreLoad__)(POBJGPU, struct KernelBif *, NvU32); @@ -106,7 +108,6 @@ struct KernelBif { NV_STATUS (*__kbifGetTunableState__)(POBJGPU, struct KernelBif *, void *); NV_STATUS (*__kbifCompareTunableState__)(POBJGPU, struct KernelBif *, void *, void *); void (*__kbifFreeTunableState__)(POBJGPU, struct KernelBif *, void *); - NV_STATUS (*__kbifStatePostLoad__)(POBJGPU, struct KernelBif *, NvU32); NV_STATUS (*__kbifAllocTunableState__)(POBJGPU, struct KernelBif *, void **); NV_STATUS (*__kbifSetTunableState__)(POBJGPU, struct KernelBif *, void *); NvBool (*__kbifIsPresent__)(POBJGPU, struct KernelBif *); @@ -123,6 +124,7 @@ struct KernelBif { NvBool PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944; NvBool PDB_PROP_KBIF_SUPPORT_NONCOHERENT; NvBool PDB_PROP_KBIF_PCIE_GEN4_CAPABLE; + NvBool PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE; NvU32 dmaCaps; RmPhysAddr dmaWindowStartAddress; NvU32 p2pOverride; @@ -164,6 +166,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_KernelBif; #define PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI_BASE_NAME PDB_PROP_KBIF_USE_CONFIG_SPACE_TO_REARM_MSI #define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_CAST #define PDB_PROP_KBIF_IS_MSI_ENABLED_BASE_NAME PDB_PROP_KBIF_IS_MSI_ENABLED +#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_CAST +#define PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE_BASE_NAME PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_CAST #define PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944_BASE_NAME PDB_PROP_KBIF_UPSTREAM_LTR_SUPPORT_WAR_BUG_200634944 #define PDB_PROP_KBIF_IS_MSIX_CACHED_BASE_CAST @@ -191,10 +195,14 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifStateInitLocked(pGpu, pKernelBif) kbifStateInitLocked_DISPATCH(pGpu, pKernelBif) #define kbifStateLoad(pGpu, pKernelBif, arg0) kbifStateLoad_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateLoad_HAL(pGpu, pKernelBif, arg0) kbifStateLoad_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifStatePostLoad(pGpu, pKernelBif, arg0) kbifStatePostLoad_DISPATCH(pGpu, pKernelBif, arg0) +#define kbifStatePostLoad_HAL(pGpu, pKernelBif, arg0) kbifStatePostLoad_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) #define kbifStateUnload_HAL(pGpu, pKernelBif, arg0) kbifStateUnload_DISPATCH(pGpu, pKernelBif, arg0) #define kbifIsPciIoAccessEnabled(pGpu, pKernelBif) kbifIsPciIoAccessEnabled_DISPATCH(pGpu, pKernelBif) #define kbifIsPciIoAccessEnabled_HAL(pGpu, pKernelBif) kbifIsPciIoAccessEnabled_DISPATCH(pGpu, pKernelBif) +#define kbifInitRelaxedOrderingFromEmulatedConfigSpace(pGpu, pBif) kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(pGpu, pBif) +#define kbifInitRelaxedOrderingFromEmulatedConfigSpace_HAL(pGpu, pBif) kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(pGpu, pBif) #define kbifApplyWARBug3208922(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) #define kbifApplyWARBug3208922_HAL(pGpu, pKernelBif) kbifApplyWARBug3208922_DISPATCH(pGpu, pKernelBif) #define kbifReconcileTunableState(pGpu, pEngstate, pTunableState) kbifReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState) @@ -209,7 +217,6 @@ NV_STATUS __nvoc_objCreate_KernelBif(KernelBif**, Dynamic*, NvU32); #define kbifGetTunableState(pGpu, pEngstate, pTunableState) kbifGetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbifCompareTunableState(pGpu, pEngstate, pTunables1, pTunables2) kbifCompareTunableState_DISPATCH(pGpu, pEngstate, pTunables1, pTunables2) #define kbifFreeTunableState(pGpu, pEngstate, pTunableState) kbifFreeTunableState_DISPATCH(pGpu, pEngstate, pTunableState) -#define kbifStatePostLoad(pGpu, pEngstate, arg0) kbifStatePostLoad_DISPATCH(pGpu, pEngstate, arg0) #define kbifAllocTunableState(pGpu, pEngstate, ppTunableState) kbifAllocTunableState_DISPATCH(pGpu, pEngstate, ppTunableState) #define kbifSetTunableState(pGpu, pEngstate, pTunableState) kbifSetTunableState_DISPATCH(pGpu, pEngstate, pTunableState) #define kbifIsPresent(pGpu, pEngstate) kbifIsPresent_DISPATCH(pGpu, pEngstate) @@ -503,6 +510,16 @@ static inline NV_STATUS kbifStateLoad_DISPATCH(struct OBJGPU *pGpu, struct Kerne return pKernelBif->__kbifStateLoad__(pGpu, pKernelBif, arg0); } +static inline NV_STATUS kbifStatePostLoad_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return NV_OK; +} + +NV_STATUS kbifStatePostLoad_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0); + +static inline NV_STATUS kbifStatePostLoad_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { + return pKernelBif->__kbifStatePostLoad__(pGpu, pKernelBif, arg0); +} + static inline NV_STATUS kbifStateUnload_56cd7a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU32 arg0) { return NV_OK; } @@ -523,6 +540,16 @@ static inline NvBool kbifIsPciIoAccessEnabled_DISPATCH(struct OBJGPU *pGpu, stru return pKernelBif->__kbifIsPciIoAccessEnabled__(pGpu, pKernelBif); } +static inline void kbifInitRelaxedOrderingFromEmulatedConfigSpace_b3696a(struct OBJGPU *pGpu, struct KernelBif *pBif) { + return; +} + +void kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100(struct OBJGPU *pGpu, struct KernelBif *pBif); + +static inline void kbifInitRelaxedOrderingFromEmulatedConfigSpace_DISPATCH(struct OBJGPU *pGpu, struct KernelBif *pBif) { + pBif->__kbifInitRelaxedOrderingFromEmulatedConfigSpace__(pGpu, pBif); +} + void kbifApplyWARBug3208922_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif); static inline void kbifApplyWARBug3208922_b3696a(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) { @@ -581,10 +608,6 @@ static inline void kbifFreeTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif pEngstate->__kbifFreeTunableState__(pGpu, pEngstate, pTunableState); } -static inline NV_STATUS kbifStatePostLoad_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, NvU32 arg0) { - return pEngstate->__kbifStatePostLoad__(pGpu, pEngstate, arg0); -} - static inline NV_STATUS kbifAllocTunableState_DISPATCH(POBJGPU pGpu, struct KernelBif *pEngstate, void **ppTunableState) { return pEngstate->__kbifAllocTunableState__(pGpu, pEngstate, ppTunableState); } diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.c b/src/nvidia/generated/g_kernel_gsp_nvoc.c index a2cee0149..35bf576d0 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.c +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.c @@ -511,33 +511,6 @@ static void __nvoc_init_funcTable_KernelGsp_1(KernelGsp *pThis, RmHalspecOwner * { } - // Hal function -- kgspGetBinArchiveBooterReloadUcode - if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ - { - if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x000000e0UL) )) /* ChipHal: TU102 | TU104 | TU106 */ - { - pThis->__kgspGetBinArchiveBooterReloadUcode__ = &kgspGetBinArchiveBooterReloadUcode_TU102; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000300UL) )) /* ChipHal: TU116 | TU117 */ - { - pThis->__kgspGetBinArchiveBooterReloadUcode__ = &kgspGetBinArchiveBooterReloadUcode_TU116; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */ - { - pThis->__kgspGetBinArchiveBooterReloadUcode__ = &kgspGetBinArchiveBooterReloadUcode_GA100; - } - else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x0000f800UL) )) /* ChipHal: GA102 | GA103 | GA104 | GA106 | GA107 */ - { - pThis->__kgspGetBinArchiveBooterReloadUcode__ = &kgspGetBinArchiveBooterReloadUcode_GA102; - } - else if (0) - { - } - } - else if (0) - { - } - // Hal function -- kgspGetBinArchiveBooterUnloadUcode if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */ { diff --git a/src/nvidia/generated/g_kernel_gsp_nvoc.h b/src/nvidia/generated/g_kernel_gsp_nvoc.h index 8d1f09fc0..0b5d0758a 100644 --- a/src/nvidia/generated/g_kernel_gsp_nvoc.h +++ b/src/nvidia/generated/g_kernel_gsp_nvoc.h @@ -255,7 +255,6 @@ struct KernelGsp { NV_STATUS (*__kgspExecuteFwsecFrts__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, const NvU64); NV_STATUS (*__kgspExecuteHsFalcon__)(struct OBJGPU *, struct KernelGsp *, KernelGspFlcnUcode *, struct KernelFalcon *, NvU32 *, NvU32 *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterLoadUcode__)(struct KernelGsp *); - const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterReloadUcode__)(struct KernelGsp *); const BINDATA_ARCHIVE *(*__kgspGetBinArchiveBooterUnloadUcode__)(struct KernelGsp *); const char *(*__kgspGetSignatureSectionName__)(struct OBJGPU *, struct KernelGsp *); void (*__kgspStateDestroy__)(POBJGPU, struct KernelGsp *); @@ -282,7 +281,6 @@ struct KernelGsp { struct OBJRPC *pRpc; KernelGspFlcnUcode *pFwsecUcode; KernelGspFlcnUcode *pBooterLoadUcode; - KernelGspFlcnUcode *pBooterReloadUcode; KernelGspFlcnUcode *pBooterUnloadUcode; MEMORY_DESCRIPTOR *pWprMetaDescriptor; GspFwWprMeta *pWprMeta; @@ -368,8 +366,6 @@ NV_STATUS __nvoc_objCreate_KernelGsp(KernelGsp**, Dynamic*, NvU32); #define kgspExecuteHsFalcon_HAL(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) kgspExecuteHsFalcon_DISPATCH(pGpu, pKernelGsp, pFlcnUcode, pKernelFlcn, pMailbox0, pMailbox1) #define kgspGetBinArchiveBooterLoadUcode(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterLoadUcode_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveBooterReloadUcode(pKernelGsp) kgspGetBinArchiveBooterReloadUcode_DISPATCH(pKernelGsp) -#define kgspGetBinArchiveBooterReloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterReloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp) kgspGetBinArchiveBooterUnloadUcode_DISPATCH(pKernelGsp) #define kgspGetSignatureSectionName(pGpu, pKernelGsp) kgspGetSignatureSectionName_DISPATCH(pGpu, pKernelGsp) @@ -511,6 +507,19 @@ static inline NV_STATUS kgspExtractVbiosFromRom(struct OBJGPU *pGpu, struct Kern #define kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, ppVbiosImg) kgspExtractVbiosFromRom(pGpu, pKernelGsp, ppVbiosImg) +NV_STATUS kgspExecuteFwsecSb_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspExecuteFwsecSb(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb_TU102(pGpu, pKernelGsp, pFwsecUcode) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pFwsecUcode) kgspExecuteFwsecSb(pGpu, pKernelGsp, pFwsecUcode) + NV_STATUS kgspExecuteBooterLoad_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, const NvU64 gspFwWprMetaOffset); #ifdef __nvoc_kernel_gsp_h_disabled @@ -524,19 +533,6 @@ static inline NV_STATUS kgspExecuteBooterLoad(struct OBJGPU *pGpu, struct Kernel #define kgspExecuteBooterLoad_HAL(pGpu, pKernelGsp, gspFwWprMetaOffset) kgspExecuteBooterLoad(pGpu, pKernelGsp, gspFwWprMetaOffset) -NV_STATUS kgspExecuteBooterReload_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); - -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspExecuteBooterReload(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspExecuteBooterReload(pGpu, pKernelGsp) kgspExecuteBooterReload_TU102(pGpu, pKernelGsp) -#endif //__nvoc_kernel_gsp_h_disabled - -#define kgspExecuteBooterReload_HAL(pGpu, pKernelGsp) kgspExecuteBooterReload(pGpu, pKernelGsp) - NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); #ifdef __nvoc_kernel_gsp_h_disabled @@ -563,6 +559,19 @@ static inline NV_STATUS kgspWaitForGfwBootOk(struct OBJGPU *pGpu, struct KernelG #define kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp) kgspWaitForGfwBootOk(pGpu, pKernelGsp) +NV_STATUS kgspWaitForProcessorSuspend_TU102(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp); + +#ifdef __nvoc_kernel_gsp_h_disabled +static inline NV_STATUS kgspWaitForProcessorSuspend(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp) { + NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); + return NV_ERR_NOT_SUPPORTED; +} +#else //__nvoc_kernel_gsp_h_disabled +#define kgspWaitForProcessorSuspend(pGpu, pKernelGsp) kgspWaitForProcessorSuspend_TU102(pGpu, pKernelGsp) +#endif //__nvoc_kernel_gsp_h_disabled + +#define kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp) kgspWaitForProcessorSuspend(pGpu, pKernelGsp) + NV_STATUS kgspConstructEngine_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0); static inline NV_STATUS kgspConstructEngine_DISPATCH(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, ENGDESCRIPTOR arg0) { @@ -741,22 +750,6 @@ static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterLoadUcode_DISPATCH(s return pKernelGsp->__kgspGetBinArchiveBooterLoadUcode__(pKernelGsp); } -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_TU102(struct KernelGsp *pKernelGsp); - -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_TU116(struct KernelGsp *pKernelGsp); - -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_GA100(struct KernelGsp *pKernelGsp); - -const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_GA102(struct KernelGsp *pKernelGsp); - -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_80f438(struct KernelGsp *pKernelGsp) { - NV_ASSERT_OR_RETURN_PRECOMP(0, ((void *)0)); -} - -static inline const BINDATA_ARCHIVE *kgspGetBinArchiveBooterReloadUcode_DISPATCH(struct KernelGsp *pKernelGsp) { - return pKernelGsp->__kgspGetBinArchiveBooterReloadUcode__(pKernelGsp); -} - const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU102(struct KernelGsp *pKernelGsp); const BINDATA_ARCHIVE *kgspGetBinArchiveBooterUnloadUcode_TU116(struct KernelGsp *pKernelGsp); @@ -1013,16 +1006,6 @@ static inline NV_STATUS kgspAllocateBooterLoadUcodeImage(struct OBJGPU *pGpu, st #define kgspAllocateBooterLoadUcodeImage(pGpu, pKernelGsp, ppBooterLoadUcode) kgspAllocateBooterLoadUcodeImage_IMPL(pGpu, pKernelGsp, ppBooterLoadUcode) #endif //__nvoc_kernel_gsp_h_disabled -NV_STATUS kgspAllocateBooterReloadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterReloadUcode); -#ifdef __nvoc_kernel_gsp_h_disabled -static inline NV_STATUS kgspAllocateBooterReloadUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterReloadUcode) { - NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!"); - return NV_ERR_NOT_SUPPORTED; -} -#else //__nvoc_kernel_gsp_h_disabled -#define kgspAllocateBooterReloadUcodeImage(pGpu, pKernelGsp, ppBooterReloadUcode) kgspAllocateBooterReloadUcodeImage_IMPL(pGpu, pKernelGsp, ppBooterReloadUcode) -#endif //__nvoc_kernel_gsp_h_disabled - NV_STATUS kgspAllocateBooterUnloadUcodeImage_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterUnloadUcode); #ifdef __nvoc_kernel_gsp_h_disabled static inline NV_STATUS kgspAllocateBooterUnloadUcodeImage(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, KernelGspFlcnUcode **ppBooterUnloadUcode) { diff --git a/src/nvidia/generated/g_nv_name_released.h b/src/nvidia/generated/g_nv_name_released.h index 2b9bb3079..e66c436e3 100644 --- a/src/nvidia/generated/g_nv_name_released.h +++ b/src/nvidia/generated/g_nv_name_released.h @@ -808,6 +808,7 @@ static const CHIPS_RELEASED sChipsReleased[] = { { 0x20B3, 0x14a7, 0x10de, "NVIDIA PG506-242" }, { 0x20B3, 0x14a8, 0x10de, "NVIDIA PG506-243" }, { 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" }, + { 0x20B5, 0x1642, 0x10de, "NVIDIA A100 80GB PCIe" }, { 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" }, { 0x20B7, 0x1532, 0x10de, "NVIDIA A30" }, { 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" }, diff --git a/src/nvidia/generated/g_subdevice_nvoc.c b/src/nvidia/generated/g_subdevice_nvoc.c index 05437f490..75ba22b1f 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.c +++ b/src/nvidia/generated/g_subdevice_nvoc.c @@ -2866,6 +2866,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic #endif }, { /* [176] */ +#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*pFunc=*/ (void (*)(void)) NULL, +#else + /*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdBifSetPcieRo_IMPL, +#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + /*flags=*/ 0x600u, + /*accessRight=*/0x0u, + /*methodId=*/ 0x20800ab9u, + /*paramSize=*/ sizeof(NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS), + /*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo), +#if NV_PRINTF_STRINGS_ALLOWED + /*func=*/ "subdeviceCtrlCmdBifSetPcieRo" +#endif + }, + { /* [177] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2880,7 +2895,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetGpfifo" #endif }, - { /* [177] */ + { /* [178] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2895,7 +2910,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoBindEngines" #endif }, - { /* [178] */ + { /* [179] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2910,7 +2925,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetOperationalProperties" #endif }, - { /* [179] */ + { /* [180] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2925,7 +2940,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetPhysicalChannelCount" #endif }, - { /* [180] */ + { /* [181] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2940,7 +2955,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetInfo" #endif }, - { /* [181] */ + { /* [182] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2955,7 +2970,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableChannels" #endif }, - { /* [182] */ + { /* [183] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2970,7 +2985,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetChannelMemInfo" #endif }, - { /* [183] */ + { /* [184] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -2985,7 +3000,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetUserdLocation" #endif }, - { /* [184] */ + { /* [185] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3000,7 +3015,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoGetDeviceInfoTable" #endif }, - { /* [185] */ + { /* [186] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3015,7 +3030,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoClearFaultedBit" #endif }, - { /* [186] */ + { /* [187] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2310u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3030,7 +3045,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoRunlistSetSchedPolicy" #endif }, - { /* [187] */ + { /* [188] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3045,7 +3060,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoUpdateChannelInfo" #endif }, - { /* [188] */ + { /* [189] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3060,7 +3075,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFifoDisableUsermodeChannels" #endif }, - { /* [189] */ + { /* [190] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3075,7 +3090,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfo" #endif }, - { /* [190] */ + { /* [191] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3090,7 +3105,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullMode" #endif }, - { /* [191] */ + { /* [192] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3105,7 +3120,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullInfo" #endif }, - { /* [192] */ + { /* [193] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3120,7 +3135,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmMode" #endif }, - { /* [193] */ + { /* [194] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3135,7 +3150,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswZcullBind" #endif }, - { /* [194] */ + { /* [195] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3150,7 +3165,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPmBind" #endif }, - { /* [195] */ + { /* [196] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3165,7 +3180,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetGpcTileMap" #endif }, - { /* [196] */ + { /* [197] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3180,7 +3195,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswSmpcMode" #endif }, - { /* [197] */ + { /* [198] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3195,7 +3210,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmToGpcTpcMappings" #endif }, - { /* [198] */ + { /* [199] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3210,7 +3225,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetCtxswPreemptionMode" #endif }, - { /* [199] */ + { /* [200] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3225,7 +3240,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrCtxswPreemptionBind" #endif }, - { /* [200] */ + { /* [201] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3240,7 +3255,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrPcSamplingMode" #endif }, - { /* [201] */ + { /* [202] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3255,7 +3270,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetROPInfo" #endif }, - { /* [202] */ + { /* [203] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3270,7 +3285,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswStats" #endif }, - { /* [203] */ + { /* [204] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3285,7 +3300,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferSize" #endif }, - { /* [204] */ + { /* [205] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3300,7 +3315,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxBufferInfo" #endif }, - { /* [205] */ + { /* [206] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3315,7 +3330,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGlobalSmOrder" #endif }, - { /* [206] */ + { /* [207] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3330,7 +3345,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCurrentResidentChannel" #endif }, - { /* [207] */ + { /* [208] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3345,7 +3360,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetVatAlarmData" #endif }, - { /* [208] */ + { /* [209] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3360,7 +3375,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetAttributeBufferSize" #endif }, - { /* [209] */ + { /* [210] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3375,7 +3390,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolQuerySize" #endif }, - { /* [210] */ + { /* [211] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3390,7 +3405,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolInitialize" #endif }, - { /* [211] */ + { /* [212] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3405,7 +3420,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolAddSlots" #endif }, - { /* [212] */ + { /* [213] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3420,7 +3435,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGfxPoolRemoveSlots" #endif }, - { /* [213] */ + { /* [214] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3435,7 +3450,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCapsV2" #endif }, - { /* [214] */ + { /* [215] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3450,7 +3465,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetInfoV2" #endif }, - { /* [215] */ + { /* [216] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3465,7 +3480,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcMask" #endif }, - { /* [216] */ + { /* [217] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3480,7 +3495,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetTpcMask" #endif }, - { /* [217] */ + { /* [218] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3495,7 +3510,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrSetTpcPartitionMode" #endif }, - { /* [218] */ + { /* [219] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3510,7 +3525,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetEngineContextProperties" #endif }, - { /* [219] */ + { /* [220] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3525,7 +3540,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetSmIssueRateModifier" #endif }, - { /* [220] */ + { /* [221] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3540,7 +3555,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUid" #endif }, - { /* [221] */ + { /* [222] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3555,7 +3570,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPhysGpcMask" #endif }, - { /* [222] */ + { /* [223] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3570,7 +3585,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetPpcMask" #endif }, - { /* [223] */ + { /* [224] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3585,7 +3600,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetNumTpcsForGpc" #endif }, - { /* [224] */ + { /* [225] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3600,7 +3615,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetCtxswModes" #endif }, - { /* [225] */ + { /* [226] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3615,7 +3630,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetGpcTileMap" #endif }, - { /* [226] */ + { /* [227] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3630,7 +3645,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrGetZcullMask" #endif }, - { /* [227] */ + { /* [228] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8010u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3645,7 +3660,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKGrFecsBindEvtbufForUidV2" #endif }, - { /* [228] */ + { /* [229] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3660,7 +3675,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfo" #endif }, - { /* [229] */ + { /* [230] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3675,7 +3690,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetInfoV2" #endif }, - { /* [230] */ + { /* [231] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3690,7 +3705,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCarveoutAddressInfo" #endif }, - { /* [231] */ + { /* [232] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3705,7 +3720,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCalibrationLockFailed" #endif }, - { /* [232] */ + { /* [233] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3720,7 +3735,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbFlushGpuCache" #endif }, - { /* [233] */ + { /* [234] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3735,7 +3750,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicy" #endif }, - { /* [234] */ + { /* [235] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3750,7 +3765,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetBar1Offset" #endif }, - { /* [235] */ + { /* [236] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3765,7 +3780,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicy" #endif }, - { /* [236] */ + { /* [237] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3780,7 +3795,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbIsKind" #endif }, - { /* [237] */ + { /* [238] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3795,7 +3810,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheInfo" #endif }, - { /* [238] */ + { /* [239] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3810,7 +3825,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetGpuCacheAllocPolicyV2" #endif }, - { /* [239] */ + { /* [240] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3825,7 +3840,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetGpuCacheAllocPolicyV2" #endif }, - { /* [240] */ + { /* [241] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3840,7 +3855,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFBRegionInfo" #endif }, - { /* [241] */ + { /* [242] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3855,7 +3870,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetOfflinedPages" #endif }, - { /* [242] */ + { /* [243] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3870,7 +3885,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetLTCInfoForFBP" #endif }, - { /* [243] */ + { /* [244] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3885,7 +3900,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbCBCOp" #endif }, - { /* [244] */ + { /* [245] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3900,7 +3915,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCtagsForCbcEviction" #endif }, - { /* [245] */ + { /* [246] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3915,7 +3930,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetupVprRegion" #endif }, - { /* [246] */ + { /* [247] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3930,7 +3945,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCliManagedOfflinedPages" #endif }, - { /* [247] */ + { /* [248] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3945,7 +3960,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetCompBitCopyConstructInfo" #endif }, - { /* [248] */ + { /* [249] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3960,7 +3975,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetRrd" #endif }, - { /* [249] */ + { /* [250] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3975,7 +3990,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetReadLimit" #endif }, - { /* [250] */ + { /* [251] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -3990,7 +4005,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbSetWriteLimit" #endif }, - { /* [251] */ + { /* [252] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4005,7 +4020,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbPatchPbrForMining" #endif }, - { /* [252] */ + { /* [253] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4020,7 +4035,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetMemAlignment" #endif }, - { /* [253] */ + { /* [254] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4035,7 +4050,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRemappedRows" #endif }, - { /* [254] */ + { /* [255] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4050,7 +4065,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetFsInfo" #endif }, - { /* [255] */ + { /* [256] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4065,7 +4080,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetRowRemapperHistogram" #endif }, - { /* [256] */ + { /* [257] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4080,7 +4095,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetDynamicOfflinedPages" #endif }, - { /* [257] */ + { /* [258] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4095,7 +4110,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbUpdateNumaStatus" #endif }, - { /* [258] */ + { /* [259] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4110,7 +4125,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFbGetNumaInfo" #endif }, - { /* [259] */ + { /* [260] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x812u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4125,7 +4140,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetArchInfo" #endif }, - { /* [260] */ + { /* [261] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4140,7 +4155,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcServiceInterrupts" #endif }, - { /* [261] */ + { /* [262] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4155,7 +4170,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcGetManufacturer" #endif }, - { /* [262] */ + { /* [263] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4170,7 +4185,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcQueryHostclkSlowdownStatus" #endif }, - { /* [263] */ + { /* [264] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4185,7 +4200,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcSetHostclkSlowdownStatus" #endif }, - { /* [264] */ + { /* [265] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4200,7 +4215,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdMcChangeReplayableFaultOwnership" #endif }, - { /* [265] */ + { /* [266] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4215,7 +4230,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciInfo" #endif }, - { /* [266] */ + { /* [267] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4230,7 +4245,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfo" #endif }, - { /* [267] */ + { /* [268] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4245,7 +4260,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPciBarInfo" #endif }, - { /* [268] */ + { /* [269] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4260,7 +4275,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLinkWidth" #endif }, - { /* [269] */ + { /* [270] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4275,7 +4290,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieSpeed" #endif }, - { /* [270] */ + { /* [271] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4290,7 +4305,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetHwbcUpstreamPcieSpeed" #endif }, - { /* [271] */ + { /* [272] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4305,7 +4320,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetHwbcUpstreamPcieSpeed" #endif }, - { /* [272] */ + { /* [273] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4320,7 +4335,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusHWBCGetUpstreamBAR0" #endif }, - { /* [273] */ + { /* [274] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4335,7 +4350,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusServiceGpuMultifunctionState" #endif }, - { /* [274] */ + { /* [275] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4350,7 +4365,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexCounters" #endif }, - { /* [275] */ + { /* [276] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4365,7 +4380,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexCounters" #endif }, - { /* [276] */ + { /* [277] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4380,7 +4395,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusFreezePexCounters" #endif }, - { /* [277] */ + { /* [278] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4395,7 +4410,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexLaneCounters" #endif }, - { /* [278] */ + { /* [279] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4410,7 +4425,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPcieLtrLatency" #endif }, - { /* [279] */ + { /* [280] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4425,7 +4440,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetPcieLtrLatency" #endif }, - { /* [280] */ + { /* [281] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4440,7 +4455,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetPexUtilCounters" #endif }, - { /* [281] */ + { /* [282] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4455,7 +4470,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusClearPexUtilCounters" #endif }, - { /* [282] */ + { /* [283] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4470,7 +4485,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetBFD" #endif }, - { /* [283] */ + { /* [284] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4485,7 +4500,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetAspmDisableFlags" #endif }, - { /* [284] */ + { /* [285] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4500,7 +4515,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetInfoV2" #endif }, - { /* [285] */ + { /* [286] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4515,7 +4530,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusControlPublicAspmBits" #endif }, - { /* [286] */ + { /* [287] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4530,7 +4545,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkPeerIdMask" #endif }, - { /* [287] */ + { /* [288] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4545,7 +4560,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSetEomParameters" #endif }, - { /* [288] */ + { /* [289] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4560,7 +4575,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetUphyDlnCfgSpace" #endif }, - { /* [289] */ + { /* [290] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4575,7 +4590,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetEomStatus" #endif }, - { /* [290] */ + { /* [291] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4590,7 +4605,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusSysmemAccess" #endif }, - { /* [291] */ + { /* [292] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4605,7 +4620,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdKPerfBoost" #endif }, - { /* [292] */ + { /* [293] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4620,7 +4635,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpGetControl" #endif }, - { /* [293] */ + { /* [294] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4635,7 +4650,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfRatedTdpSetControl" #endif }, - { /* [294] */ + { /* [295] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4650,7 +4665,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfReservePerfmonHw" #endif }, - { /* [295] */ + { /* [296] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4665,7 +4680,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdPerfGetGpumonPerfmonUtilSamplesV2" #endif }, - { /* [296] */ + { /* [297] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4680,7 +4695,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReadVirtualMem" #endif }, - { /* [297] */ + { /* [298] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4695,7 +4710,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorCount" #endif }, - { /* [298] */ + { /* [299] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4710,7 +4725,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSetCleanErrorHistory" #endif }, - { /* [299] */ + { /* [300] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4725,7 +4740,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetWatchdogInfo" #endif }, - { /* [300] */ + { /* [301] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4740,7 +4755,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcDisableWatchdog" #endif }, - { /* [301] */ + { /* [302] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4755,7 +4770,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcEnableWatchdog" #endif }, - { /* [302] */ + { /* [303] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4770,7 +4785,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcReleaseWatchdogRequests" #endif }, - { /* [303] */ + { /* [304] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4785,7 +4800,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcRecovery" #endif }, - { /* [304] */ + { /* [305] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4800,7 +4815,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcRecovery" #endif }, - { /* [305] */ + { /* [306] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4815,7 +4830,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcSoftDisableWatchdog" #endif }, - { /* [306] */ + { /* [307] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4830,7 +4845,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdSetRcInfo" #endif }, - { /* [307] */ + { /* [308] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4845,7 +4860,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetRcInfo" #endif }, - { /* [308] */ + { /* [309] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4860,7 +4875,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdRcGetErrorV2" #endif }, - { /* [309] */ + { /* [310] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4875,7 +4890,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDumpSize" #endif }, - { /* [310] */ + { /* [311] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4890,7 +4905,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetDump" #endif }, - { /* [311] */ + { /* [312] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4905,7 +4920,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdGetNocatJournalRpt" #endif }, - { /* [312] */ + { /* [313] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4920,7 +4935,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvdSetNocatJournalData" #endif }, - { /* [313] */ + { /* [314] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4935,7 +4950,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaInvalidateTLB" #endif }, - { /* [314] */ + { /* [315] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4950,7 +4965,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdDmaGetInfo" #endif }, - { /* [315] */ + { /* [316] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4965,7 +4980,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCaps" #endif }, - { /* [316] */ + { /* [317] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4980,7 +4995,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCePceMask" #endif }, - { /* [317] */ + { /* [318] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -4995,7 +5010,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetCapsV2" #endif }, - { /* [318] */ + { /* [319] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5010,7 +5025,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdatePceLceMappings" #endif }, - { /* [319] */ + { /* [320] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5025,7 +5040,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeUpdateClassDB" #endif }, - { /* [320] */ + { /* [321] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5040,7 +5055,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetPhysicalCaps" #endif }, - { /* [321] */ + { /* [322] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5055,7 +5070,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetFaultMethodBufferSize" #endif }, - { /* [322] */ + { /* [323] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4600u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5070,7 +5085,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetHubPceMask" #endif }, - { /* [323] */ + { /* [324] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5085,7 +5100,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllCaps" #endif }, - { /* [324] */ + { /* [325] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5100,7 +5115,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdCeGetAllPhysicalCaps" #endif }, - { /* [325] */ + { /* [326] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x850u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5115,7 +5130,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkCaps" #endif }, - { /* [326] */ + { /* [327] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5130,7 +5145,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdBusGetNvlinkStatus" #endif }, - { /* [327] */ + { /* [328] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5145,7 +5160,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetNvlinkCounters" #endif }, - { /* [328] */ + { /* [329] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5160,7 +5175,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdClearNvlinkCounters" #endif }, - { /* [329] */ + { /* [330] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5175,7 +5190,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkFatalErrorCounts" #endif }, - { /* [330] */ + { /* [331] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5190,7 +5205,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupEom" #endif }, - { /* [331] */ + { /* [332] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5205,7 +5220,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetPowerState" #endif }, - { /* [332] */ + { /* [333] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5220,7 +5235,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkReadTpCounters" #endif }, - { /* [333] */ + { /* [334] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5235,7 +5250,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableNvlinkPeer" #endif }, - { /* [334] */ + { /* [335] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5250,7 +5265,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLpCounters" #endif }, - { /* [335] */ + { /* [336] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5265,7 +5280,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkCoreCallback" #endif }, - { /* [336] */ + { /* [337] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5280,7 +5295,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateRemoteLocalSid" #endif }, - { /* [337] */ + { /* [338] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5295,7 +5310,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateHshubMux" #endif }, - { /* [338] */ + { /* [339] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5310,7 +5325,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPreSetupNvlinkPeer" #endif }, - { /* [339] */ + { /* [340] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5325,7 +5340,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkPostSetupNvlinkPeer" #endif }, - { /* [340] */ + { /* [341] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5340,7 +5355,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkRemoveNvlinkMapping" #endif }, - { /* [341] */ + { /* [342] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5355,7 +5370,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSaveRestoreHshubState" #endif }, - { /* [342] */ + { /* [343] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5370,7 +5385,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramBufferready" #endif }, - { /* [343] */ + { /* [344] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5385,7 +5400,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateCurrentConfig" #endif }, - { /* [344] */ + { /* [345] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5400,7 +5415,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetLoopbackMode" #endif }, - { /* [345] */ + { /* [346] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5415,7 +5430,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdatePeerLinkMask" #endif }, - { /* [346] */ + { /* [347] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5430,7 +5445,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkUpdateLinkConnection" #endif }, - { /* [347] */ + { /* [348] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5445,7 +5460,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinksPostTopology" #endif }, - { /* [348] */ + { /* [349] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5460,7 +5475,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetRefreshCounters" #endif }, - { /* [349] */ + { /* [350] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5475,7 +5490,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkClearRefreshCounters" #endif }, - { /* [350] */ + { /* [351] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5490,7 +5505,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkMaskPostRxDet" #endif }, - { /* [351] */ + { /* [352] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5505,7 +5520,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetNvlinkDeviceInfo" #endif }, - { /* [352] */ + { /* [353] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5520,7 +5535,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetIoctrlDeviceInfo" #endif }, - { /* [353] */ + { /* [354] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5535,7 +5550,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProgramLinkSpeed" #endif }, - { /* [354] */ + { /* [355] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5550,7 +5565,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkAreLinksTrained" #endif }, - { /* [355] */ + { /* [356] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5565,7 +5580,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkResetLinks" #endif }, - { /* [356] */ + { /* [357] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5580,7 +5595,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkDisableDlInterrupts" #endif }, - { /* [357] */ + { /* [358] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5595,7 +5610,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetLinkAndClockInfo" #endif }, - { /* [358] */ + { /* [359] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5610,7 +5625,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSetupNvlinkSysmem" #endif }, - { /* [359] */ + { /* [360] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5625,7 +5640,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessForcedConfigs" #endif }, - { /* [360] */ + { /* [361] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5640,7 +5655,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLaneShutdownProps" #endif }, - { /* [361] */ + { /* [362] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5655,7 +5670,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableSysmemNvlinkAts" #endif }, - { /* [362] */ + { /* [363] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5670,7 +5685,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkHshubGetSysmemNvlinkMask" #endif }, - { /* [363] */ + { /* [364] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5685,7 +5700,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkGetSetNvswitchFlaAddr" #endif }, - { /* [364] */ + { /* [365] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x201u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5700,7 +5715,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkSyncLinkMasksAndVbiosInfo" #endif }, - { /* [365] */ + { /* [366] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5715,7 +5730,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkEnableLinks" #endif }, - { /* [366] */ + { /* [367] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5730,7 +5745,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdNvlinkProcessInitDisabledLinks" #endif }, - { /* [367] */ + { /* [368] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5745,7 +5760,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage" #endif }, - { /* [368] */ + { /* [369] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5760,7 +5775,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationMap" #endif }, - { /* [369] */ + { /* [370] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5775,7 +5790,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationUnmap" #endif }, - { /* [370] */ + { /* [371] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5790,7 +5805,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationGetInfo" #endif }, - { /* [371] */ + { /* [372] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5805,7 +5820,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationGetControl" #endif }, - { /* [372] */ + { /* [373] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5820,7 +5835,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationSetControl" #endif }, - { /* [373] */ + { /* [374] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5835,7 +5850,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnInstrumentationRecalibrate" #endif }, - { /* [374] */ + { /* [375] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5850,7 +5865,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch" #endif }, - { /* [375] */ + { /* [376] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5865,7 +5880,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo" #endif }, - { /* [376] */ + { /* [377] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5880,7 +5895,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet" #endif }, - { /* [377] */ + { /* [378] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5895,7 +5910,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet" #endif }, - { /* [378] */ + { /* [379] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x200u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5910,7 +5925,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo" #endif }, - { /* [379] */ + { /* [380] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5925,7 +5940,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize" #endif }, - { /* [380] */ + { /* [381] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5940,7 +5955,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters" #endif }, - { /* [381] */ + { /* [382] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5955,7 +5970,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaRange" #endif }, - { /* [382] */ + { /* [383] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2204u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5970,7 +5985,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock" #endif }, - { /* [383] */ + { /* [384] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -5985,7 +6000,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetRange" #endif }, - { /* [384] */ + { /* [385] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1810u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6000,7 +6015,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats" #endif }, - { /* [385] */ + { /* [386] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x211u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6015,7 +6030,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGspGetFeatures" #endif }, - { /* [386] */ + { /* [387] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x2210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6030,7 +6045,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo" #endif }, - { /* [387] */ + { /* [388] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6045,7 +6060,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt" #endif }, - { /* [388] */ + { /* [389] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6060,7 +6075,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff" #endif }, - { /* [389] */ + { /* [390] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6075,7 +6090,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower" #endif }, - { /* [390] */ + { /* [391] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x13u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6090,7 +6105,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus" #endif }, - { /* [391] */ + { /* [392] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6105,7 +6120,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus" #endif }, - { /* [392] */ + { /* [393] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xa50u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6120,7 +6135,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic /*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask" #endif }, - { /* [393] */ + { /* [394] */ #if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u) /*pFunc=*/ (void (*)(void)) NULL, #else @@ -6140,7 +6155,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice = { - /*numEntries=*/ 394, + /*numEntries=*/ 395, /*pExportEntries=*/ __nvoc_exported_method_def_Subdevice }; @@ -7749,6 +7764,10 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner * pThis->__subdeviceCtrlCmdBifGetAspmL1Flags__ = &subdeviceCtrlCmdBifGetAspmL1Flags_IMPL; #endif +#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) + pThis->__subdeviceCtrlCmdBifSetPcieRo__ = &subdeviceCtrlCmdBifSetPcieRo_IMPL; +#endif + #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x600u) pThis->__subdeviceCtrlCmdHshubPeerConnConfig__ = &subdeviceCtrlCmdHshubPeerConnConfig_IMPL; #endif diff --git a/src/nvidia/generated/g_subdevice_nvoc.h b/src/nvidia/generated/g_subdevice_nvoc.h index 53d978a0c..f1179424c 100644 --- a/src/nvidia/generated/g_subdevice_nvoc.h +++ b/src/nvidia/generated/g_subdevice_nvoc.h @@ -519,6 +519,7 @@ struct Subdevice { NV_STATUS (*__subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount__)(struct Subdevice *, NV2080_CTRL_INTERNAL_PERF_CF_CONTROLLERS_SET_MAX_VGPU_VM_COUNT_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetStaticInfo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdBifGetAspmL1Flags__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_GET_ASPM_L1_FLAGS_PARAMS *); + NV_STATUS (*__subdeviceCtrlCmdBifSetPcieRo__)(struct Subdevice *, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubPeerConnConfig__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubFirstLinkPeerId__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS *); NV_STATUS (*__subdeviceCtrlCmdHshubGetHshubIdForLinks__)(struct Subdevice *, NV2080_CTRL_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS_PARAMS *); @@ -998,6 +999,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C #define subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount(pSubdevice, pParams) subdeviceCtrlCmdInternalPerfCfControllerSetMaxVGpuVMCount_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetStaticInfo(pSubdevice, pParams) subdeviceCtrlCmdBifGetStaticInfo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdBifGetAspmL1Flags(pSubdevice, pParams) subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(pSubdevice, pParams) +#define subdeviceCtrlCmdBifSetPcieRo(pSubdevice, pParams) subdeviceCtrlCmdBifSetPcieRo_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubPeerConnConfig(pSubdevice, pParams) subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubFirstLinkPeerId(pSubdevice, pParams) subdeviceCtrlCmdHshubFirstLinkPeerId_DISPATCH(pSubdevice, pParams) #define subdeviceCtrlCmdHshubGetHshubIdForLinks(pSubdevice, pParams) subdeviceCtrlCmdHshubGetHshubIdForLinks_DISPATCH(pSubdevice, pParams) @@ -3391,6 +3393,12 @@ static inline NV_STATUS subdeviceCtrlCmdBifGetAspmL1Flags_DISPATCH(struct Subdev return pSubdevice->__subdeviceCtrlCmdBifGetAspmL1Flags__(pSubdevice, pParams); } +NV_STATUS subdeviceCtrlCmdBifSetPcieRo_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *pParams); + +static inline NV_STATUS subdeviceCtrlCmdBifSetPcieRo_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS *pParams) { + return pSubdevice->__subdeviceCtrlCmdBifSetPcieRo__(pSubdevice, pParams); +} + NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams); static inline NV_STATUS subdeviceCtrlCmdHshubPeerConnConfig_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS *pParams) { diff --git a/src/nvidia/inc/libraries/containers/list.h b/src/nvidia/inc/libraries/containers/list.h index 1dc0ab7bf..799c7e1a5 100644 --- a/src/nvidia/inc/libraries/containers/list.h +++ b/src/nvidia/inc/libraries/containers/list.h @@ -41,7 +41,7 @@ extern "C" { * * @details Order of values is not necessarily increasing or sorted, but order is * preserved across mutation. Please see - * http://en.wikipedia.org/wiki/Sequence for a formal definition. + * https://en.wikipedia.org/wiki/Sequence for a formal definition. * * The provided interface is abstract, decoupling the user from the underlying * list implementation. Two options are available with regard to memory diff --git a/src/nvidia/inc/libraries/nvport/crypto.h b/src/nvidia/inc/libraries/nvport/crypto.h index ab320ce70..28c4bc079 100644 --- a/src/nvidia/inc/libraries/nvport/crypto.h +++ b/src/nvidia/inc/libraries/nvport/crypto.h @@ -70,9 +70,9 @@ * - No HW random support (older CPUs) * * For additional information, see these links: - * - http://www.2uo.de/myths-about-urandom/ + * - https://www.2uo.de/myths-about-urandom/ * - https://bugs.ruby-lang.org/issues/9569 - * - http://security.stackexchange.com/questions/3936/is-a-rand-from-dev-urandom-secure-for-a-login-key + * - https://security.stackexchange.com/questions/3936/is-a-rand-from-dev-urandom-secure-for-a-login-key * * @{ */ diff --git a/src/nvidia/inc/libraries/nvport/debug.h b/src/nvidia/inc/libraries/nvport/debug.h index 2240a263b..fe7a94d7a 100644 --- a/src/nvidia/inc/libraries/nvport/debug.h +++ b/src/nvidia/inc/libraries/nvport/debug.h @@ -198,7 +198,7 @@ NvBool nvDbgBreakpointEnabled(void); * coverage. * * - See @ref PORT_ASSERT for usage example. - * - See http://www.bullseye.com/help/build-exclude.html for more details. + * - See https://www.bullseye.com/help/build-exclude.html for more details. */ /** * @def PORT_COVERAGE_PUSH_ON() diff --git a/src/nvidia/inc/libraries/nvport/sync.h b/src/nvidia/inc/libraries/nvport/sync.h index 2db3b7e41..29e472ded 100644 --- a/src/nvidia/inc/libraries/nvport/sync.h +++ b/src/nvidia/inc/libraries/nvport/sync.h @@ -110,7 +110,7 @@ void portSyncShutdown(void); * @brief A spinlock data type. * * For documentation on what a spinlock is and how it behaves see - * http://en.wikipedia.org/wiki/Spinlock + * https://en.wikipedia.org/wiki/Spinlock * * - A valid spinlock is any which is non-NULL * - Spinlocks are not recursive. diff --git a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c index 74c989a99..7888a6c6a 100644 --- a/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c +++ b/src/nvidia/src/kernel/gpu/arch/ampere/kern_gpu_ga100.c @@ -26,6 +26,20 @@ #include "gpu/mem_mgr/mem_mgr.h" #include "published/ampere/ga100/dev_fb.h" #include "published/ampere/ga100/dev_vm.h" +#include "published/ampere/ga100/dev_fuse.h" + +/*! + * @brief Read fuse for display supported status. + * Some chips not marked displayless do not support display + */ +NvBool +gpuFuseSupportsDisplay_GA100 +( + OBJGPU *pGpu +) +{ + return GPU_FLD_TEST_DRF_DEF(pGpu, _FUSE, _STATUS_OPT_DISPLAY, _DATA, _ENABLE); +} /*! * @brief Clear FBHUB POISON Interrupt state for Bug 2924523. diff --git a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c index f12fdd2cd..af1147c15 100644 --- a/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c +++ b/src/nvidia/src/kernel/gpu/arch/maxwell/kern_gpu_gm107.c @@ -27,7 +27,20 @@ #include "published/maxwell/gm107/dev_bus.h" #include "published/maxwell/gm107/dev_nv_xve.h" #include "published/maxwell/gm107/dev_nv_xve1.h" +#include "published/maxwell/gm107/dev_fuse.h" +/*! + * @brief Read fuse for display supported status. + * Some chips not marked displayless do not support display + */ +NvBool +gpuFuseSupportsDisplay_GM107 +( + OBJGPU *pGpu +) +{ + return GPU_FLD_TEST_DRF_DEF(pGpu, _FUSE, _STATUS_OPT_DISPLAY, _DATA, _ENABLE); +} /*! * @brief gpuReadBusConfigRegEx_GM107 diff --git a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c index d522e3384..a0ac5cdc8 100644 --- a/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c +++ b/src/nvidia/src/kernel/gpu/bif/arch/ampere/kernel_bif_ga100.c @@ -24,6 +24,7 @@ /* ------------------------ Includes ---------------------------------------- */ #include "gpu/bif/kernel_bif.h" +#include "ampere/ga100/dev_nv_xve_addendum.h" /* ------------------------ Public Functions -------------------------------- */ @@ -47,3 +48,26 @@ kbifApplyWARBug3208922_GA100 pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_P2P_WRITES_DISABLED, NV_TRUE); } } + +/*! + * @brief Check for RO enablement request in emulated config space. + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif BIF object pointer + */ +void +kbifInitRelaxedOrderingFromEmulatedConfigSpace_GA100 +( + OBJGPU *pGpu, + KernelBif *pKernelBif +) +{ + NvU32 passthroughEmulatedConfig = osPciReadDword(osPciInitHandle(gpuGetDomain(pGpu), + gpuGetBus(pGpu), + gpuGetDevice(pGpu), + 0, NULL, NULL), + NV_XVE_PASSTHROUGH_EMULATED_CONFIG); + NvBool roEnabled = DRF_VAL(_XVE, _PASSTHROUGH_EMULATED_CONFIG, _RELAXED_ORDERING_ENABLE, passthroughEmulatedConfig); + + pKernelBif->setProperty(pKernelBif, PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE, roEnabled); +} \ No newline at end of file diff --git a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c index 6ff7a6c44..b7818369c 100644 --- a/src/nvidia/src/kernel/gpu/bif/kernel_bif.c +++ b/src/nvidia/src/kernel/gpu/bif/kernel_bif.c @@ -45,7 +45,7 @@ /* ------------------------ Static Function Prototypes ---------------------- */ static void _kbifInitRegistryOverrides(OBJGPU *, KernelBif *); static void _kbifCheckIfGpuExists(OBJGPU *, void*); - +static NV_STATUS _kbifSetPcieRelaxedOrdering(OBJGPU *, KernelBif *, NvBool); /* ------------------------ Public Functions -------------------------------- */ @@ -160,6 +160,70 @@ kbifStateLoad_IMPL return NV_OK; } +/*! + * @brief Configure PCIe Relaxed Ordering in BIF + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KBIF object pointer + * @param[in] enableRo Enable/disable RO + */ +static NV_STATUS +_kbifSetPcieRelaxedOrdering +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvBool enableRo +) +{ + NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS pcieRo; + RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu); + NV_STATUS status; + + pcieRo.enableRo = enableRo; + + status = pRmApi->Control(pRmApi, pGpu->hInternalClient, pGpu->hInternalSubdevice, + NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO, + &pcieRo, sizeof(pcieRo)); + if (status != NV_OK) { + NV_PRINTF(LEVEL_ERROR, "NV2080_CTRL_CMD_INTERNAL_BIF_SET_PCIE_RO failed %s (0x%x)\n", + nvstatusToString(status), status); + return status; + } + + return NV_OK; +} + +/*! + * @brief KernelBif state post-load + * + * @param[in] pGpu GPU object pointer + * @param[in] pKernelBif KBIF object pointer + * @param[in] flags GPU state flag + */ +NV_STATUS +kbifStatePostLoad_IMPL +( + OBJGPU *pGpu, + KernelBif *pKernelBif, + NvU32 flags +) +{ + NV_STATUS status; + + kbifInitRelaxedOrderingFromEmulatedConfigSpace(pGpu, pKernelBif); + if (pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_PCIE_RELAXED_ORDERING_SET_IN_EMULATED_CONFIG_SPACE)) { + // + // This is done from StatePostLoad() to guarantee that BIF's StateLoad() + // is already completed for both monolithic RM and GSP RM. + // + status = _kbifSetPcieRelaxedOrdering(pGpu, pKernelBif, NV_TRUE); + if (status != NV_OK) + return NV_OK; + } + + return NV_OK; +} + /*! * @brief KernelBif state unload * diff --git a/src/nvidia/src/kernel/gpu/disp/kern_disp.c b/src/nvidia/src/kernel/gpu/disp/kern_disp.c index b68a084df..166499604 100644 --- a/src/nvidia/src/kernel/gpu/disp/kern_disp.c +++ b/src/nvidia/src/kernel/gpu/disp/kern_disp.c @@ -218,6 +218,9 @@ kdispStatePreInitLocked_IMPL(OBJGPU *pGpu, NvU32 hSubdevice = pGpu->hInternalSubdevice; NV2080_CTRL_INTERNAL_DISPLAY_GET_IP_VERSION_PARAMS ctrlParams; + if (!gpuFuseSupportsDisplay_HAL(pGpu)) + return NV_ERR_NOT_SUPPORTED; + status = pRmApi->Control(pRmApi, hClient, hSubdevice, NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_IP_VERSION, &ctrlParams, sizeof(ctrlParams)); diff --git a/src/nvidia/src/kernel/gpu/gpu.c b/src/nvidia/src/kernel/gpu/gpu.c index 2ef054dfa..a8aee3676 100644 --- a/src/nvidia/src/kernel/gpu/gpu.c +++ b/src/nvidia/src/kernel/gpu/gpu.c @@ -1339,6 +1339,12 @@ gpuDestruct_IMPL pGpu->regopScratchBufferMaxOffsets = 0; + NV_ASSERT(pGpu->numSubdeviceBackReferences == 0); + portMemFree(pGpu->pSubdeviceBackReferences); + pGpu->pSubdeviceBackReferences = NULL; + pGpu->numSubdeviceBackReferences = 0; + pGpu->maxSubdeviceBackReferences = 0; + gpuDestructPhysical(pGpu); } diff --git a/src/nvidia/src/kernel/gpu/gpu_rmapi.c b/src/nvidia/src/kernel/gpu/gpu_rmapi.c index fb4a6b10a..6a848c642 100644 --- a/src/nvidia/src/kernel/gpu/gpu_rmapi.c +++ b/src/nvidia/src/kernel/gpu/gpu_rmapi.c @@ -226,6 +226,53 @@ gpuGetByHandle return gpuGetByRef(pResourceRef, pbBroadcast, ppGpu); } +NV_STATUS gpuRegisterSubdevice_IMPL(OBJGPU *pGpu, Subdevice *pSubdevice) +{ + const NvU32 initialSize = 32; + const NvU32 expansionFactor = 2; + + if (pGpu->numSubdeviceBackReferences == pGpu->maxSubdeviceBackReferences) + { + if (pGpu->pSubdeviceBackReferences == NULL) + { + pGpu->pSubdeviceBackReferences = portMemAllocNonPaged(initialSize * sizeof(Subdevice*)); + if (pGpu->pSubdeviceBackReferences == NULL) + return NV_ERR_NO_MEMORY; + pGpu->maxSubdeviceBackReferences = initialSize; + } + else + { + const NvU32 newSize = expansionFactor * pGpu->maxSubdeviceBackReferences * sizeof(Subdevice*); + Subdevice **newArray = portMemAllocNonPaged(newSize); + if (newArray == NULL) + return NV_ERR_NO_MEMORY; + + portMemCopy(newArray, newSize, pGpu->pSubdeviceBackReferences, pGpu->maxSubdeviceBackReferences * sizeof(Subdevice*)); + portMemFree(pGpu->pSubdeviceBackReferences); + pGpu->pSubdeviceBackReferences = newArray; + pGpu->maxSubdeviceBackReferences *= expansionFactor; + } + } + pGpu->pSubdeviceBackReferences[pGpu->numSubdeviceBackReferences++] = pSubdevice; + return NV_OK; +} + +void gpuUnregisterSubdevice_IMPL(OBJGPU *pGpu, Subdevice *pSubdevice) +{ + NvU32 i; + for (i = 0; i < pGpu->numSubdeviceBackReferences; i++) + { + if (pGpu->pSubdeviceBackReferences[i] == pSubdevice) + { + pGpu->numSubdeviceBackReferences--; + pGpu->pSubdeviceBackReferences[i] = pGpu->pSubdeviceBackReferences[pGpu->numSubdeviceBackReferences]; + pGpu->pSubdeviceBackReferences[pGpu->numSubdeviceBackReferences] = NULL; + return; + } + } + NV_ASSERT_FAILED("Subdevice not found!"); +} + /*! * @brief Determine whether the given event should be triggered on the given * subdevice based upon MIG attribution, and translate encoded global IDs into @@ -437,9 +484,9 @@ gpuNotifySubDeviceEvent_IMPL { PEVENTNOTIFICATION pEventNotification; THREAD_STATE_NODE *pCurThread; - RS_SHARE_ITERATOR it = serverutilShareIter(classId(NotifShare)); NvU32 localNotifyType; NvU32 localInfo32; + NvU32 i; if (NV_OK == threadStateGetCurrent(&pCurThread, pGpu)) { @@ -451,22 +498,11 @@ gpuNotifySubDeviceEvent_IMPL NV_ASSERT(notifyIndex < NV2080_NOTIFIERS_MAXCOUNT); // search notifiers with events hooked up for this gpu - while (serverutilShareIterNext(&it)) + for (i = 0; i < pGpu->numSubdeviceBackReferences; i++) { - RsShared *pShared = it.pShared; - Subdevice *pSubdevice; - INotifier *pNotifier; - NotifShare *pNotifierShare = dynamicCast(pShared, NotifShare); + Subdevice *pSubdevice = pGpu->pSubdeviceBackReferences[i]; + INotifier *pNotifier = staticCast(pSubdevice, INotifier); - if ((pNotifierShare == NULL) || (pNotifierShare->pNotifier == NULL)) - continue; - - pNotifier = pNotifierShare->pNotifier; - pSubdevice = dynamicCast(pNotifier, Subdevice); - - // Only notify matching GPUs - if ((pSubdevice == NULL) || (GPU_RES_GET_GPU(pSubdevice) != pGpu)) - continue; GPU_RES_SET_THREAD_BC_STATE(pSubdevice); // diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c index 7327415c6..ac899b0db 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/ampere/kernel_gsp_ga102.c @@ -36,7 +36,9 @@ #include "published/ampere/ga102/dev_falcon_second_pri.h" #include "published/ampere/ga102/dev_gsp.h" #include "published/ampere/ga102/dev_gsp_addendum.h" - +#include "published/ampere/ga102/dev_gc6_island.h" +#include "published/ampere/ga102/dev_gc6_island_addendum.h" +#include "gpu/sec2/kernel_sec2.h" #define RISCV_BR_ADDR_ALIGNMENT (8) @@ -87,6 +89,23 @@ _kgspResetIntoRiscv return NV_OK; } +/*! + * Determine if GSP reload via SEC2 is completed. + */ +static NvBool +_kgspIsReloadCompleted +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 reg; + + reg = GPU_REG_RD32(pGpu, NV_PGC6_BSI_SECURE_SCRATCH_14); + + return FLD_TEST_DRF(_PGC6, _BSI_SECURE_SCRATCH_14, _BOOT_STAGE_3_HANDOFF, _VALUE_DONE, reg); +} + /*! * Boot GSP-RM. * @@ -265,6 +284,7 @@ kgspExecuteSequencerCommand_GA102 { NV_STATUS status = NV_OK; KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + NvU32 secMailbox0 = 0; switch (opCode) { @@ -301,14 +321,26 @@ kgspExecuteSequencerCommand_GA102 NV_ASSERT_OR_RETURN(payloadSize == 0, NV_ERR_INVALID_ARGUMENT); { + KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + NV_ASSERT_OK_OR_RETURN(_kgspResetIntoRiscv(pGpu, pKernelGsp)); kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); - status = kgspExecuteBooterReload_HAL(pGpu, pKernelGsp); - if (status != NV_OK) + NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); + // Start SEC2 in order to resume GSP-RM + kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); + + // Wait for reload to be completed. + status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); + + // Check SEC mailbox. + secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); + + if ((status != NV_OK) || (secMailbox0 != NV_OK)) { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Reload (ucode for resume from sequencer): 0x%x\n", status); - break; + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; } } diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c index 65e1df370..d41f6e615 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_booter_tu102.c @@ -25,7 +25,6 @@ #include "gpu/gpu.h" #include "gpu/falcon/kernel_falcon.h" -#include "gpu/nvdec/kernel_nvdec.h" #include "gpu/sec2/kernel_sec2.h" #include "published/turing/tu102/dev_fb.h" // for NV_PFB_PRI_MMU_WPR2_ADDR_HI @@ -117,34 +116,6 @@ kgspExecuteBooterLoad_TU102 return status; } -NV_STATUS -kgspExecuteBooterReload_TU102 -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp -) -{ - NV_STATUS status; - - KernelNvdec *pKernelNvdec = GPU_GET_KERNEL_NVDEC(pGpu); - - NV_PRINTF(LEVEL_INFO, "executing Booter Reload\n"); - NV_ASSERT_OR_RETURN(pKernelGsp->pBooterReloadUcode != NULL, NV_ERR_INVALID_STATE); - - kflcnReset_HAL(pGpu, staticCast(pKernelNvdec, KernelFalcon)); - status = s_executeBooterUcode_TU102(pGpu, pKernelGsp, - pKernelGsp->pBooterReloadUcode, - staticCast(pKernelNvdec, KernelFalcon), - 0xFF, 0xFF); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Reload: 0x%x\n", status); - return status; - } - - return status; -} - NV_STATUS kgspExecuteBooterUnloadIfNeeded_TU102 ( diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c index fb76d5bb8..2850bb125 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_frts_tu102.c @@ -36,7 +36,8 @@ #include "published/turing/tu102/dev_bus.h" // for NV_PBUS_VBIOS_SCRATCH #include "published/turing/tu102/dev_fb.h" // for NV_PFB_PRI_MMU_WPR2_ADDR_HI -#include "published/turing/tu102/dev_gc6_island_addendum.h" // for NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K +#include "published/turing/tu102/dev_gc6_island.h" +#include "published/turing/tu102/dev_gc6_island_addendum.h" /*! * Get size of FRTS data. @@ -98,6 +99,7 @@ typedef struct } FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3; #define FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS (0x15) +#define FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB (0x19) typedef struct { @@ -132,25 +134,33 @@ typedef struct #define NV_VBIOS_FWSECLIC_FRTS_ERR_CODE 31:16 #define NV_VBIOS_FWSECLIC_FRTS_ERR_CODE_NONE 0x00000000 +#define NV_VBIOS_FWSECLIC_SCRATCH_INDEX_15 0x15 +#define NV_VBIOS_FWSECLIC_SB_ERR_CODE 15:0 +#define NV_VBIOS_FWSECLIC_SB_ERR_CODE_NONE 0x00000000 + // --------------------------------------------------------------------------- // Functions for preparing and executing FWSEC commands // --------------------------------------------------------------------------- /*! - * Patch DMEM of FWSEC for FRTS command + * Patch DMEM of FWSEC for a given command * * @param[inout] pMappedData Pointer to mapped DMEM of FWSEC * @param[in] mappedDataSize Number of bytes valid under pMappedData - * @param[in] pFrtsCmd FRTS command to patch in + * @param[in] cmd FWSEC command to invoke + * @param[in] pCmdBuffer Buffer containing command arguments to patch in + * @param[in] cmdBufferSize Size of buffer pointed by pCmdBuffer * @param[in] interfaceOffset Interface offset given by VBIOS for FWSEC */ -NV_STATUS -s_vbiosPatchFrtsInterfaceData +static NV_STATUS +s_vbiosPatchInterfaceData ( NvU8 *pMappedData, // inout const NvU32 mappedDataSize, - const FWSECLIC_FRTS_CMD *pFrtsCmd, + const NvU32 cmd, + const void *pCmdBuffer, + const NvU32 cmdBufferSize, const NvU32 interfaceOffset ) { @@ -178,7 +188,7 @@ s_vbiosPatchFrtsInterfaceData pIntFaceHdr = (FALCON_APPLICATION_INTERFACE_HEADER_V1 *) (pMappedData + interfaceOffset); if (pIntFaceHdr->entryCount < 2) { - NV_PRINTF(LEVEL_ERROR, "too few interface entires found for FRTS\n"); + NV_PRINTF(LEVEL_ERROR, "too few interface entires found for FWSEC cmd 0x%x\n", cmd); return NV_ERR_INVALID_DATA; } @@ -222,15 +232,15 @@ s_vbiosPatchFrtsInterfaceData if (!pDmemMapper) { - NV_PRINTF(LEVEL_ERROR, "failed to find required interface entry for FRTS\n"); + NV_PRINTF(LEVEL_ERROR, "failed to find required interface entry for FWSEC cmd 0x%x\n", cmd); return NV_ERR_INVALID_DATA; } - pDmemMapper->init_cmd = FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS; + pDmemMapper->init_cmd = cmd; - if (pDmemMapper->cmd_in_buffer_size < sizeof(FWSECLIC_FRTS_CMD)) + if (pDmemMapper->cmd_in_buffer_size < cmdBufferSize) { - NV_PRINTF(LEVEL_ERROR, "insufficient cmd buffer for FRTS interface\n"); + NV_PRINTF(LEVEL_ERROR, "insufficient cmd buffer for FWSEC interface cmd 0x%x\n", cmd); } if (pDmemMapper->cmd_in_buffer_offset >= mappedDataSize) @@ -238,60 +248,88 @@ s_vbiosPatchFrtsInterfaceData return NV_ERR_INVALID_OFFSET; } - bSafe = portSafeAddU32(pIntFaceEntry->dmemOffset, sizeof(*pFrtsCmd), &nextOffset); + bSafe = portSafeAddU32(pIntFaceEntry->dmemOffset, cmdBufferSize, &nextOffset); if (!bSafe || nextOffset > mappedDataSize) { return NV_ERR_INVALID_OFFSET; } - portMemCopy(pMappedData + pDmemMapper->cmd_in_buffer_offset, sizeof(*pFrtsCmd), - pFrtsCmd, sizeof(*pFrtsCmd)); + portMemCopy(pMappedData + pDmemMapper->cmd_in_buffer_offset, cmdBufferSize, + pCmdBuffer, cmdBufferSize); return NV_OK; } /*! - * Excecute FWSEC for FRTS and wait for completion. + * Excecute a given FWSEC cmd and wait for completion. * * @param[in] pGpu OBJGPU pointer * @param[in] pKernelGsp KernelGsp pointer * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode - * @param[in] frtsOffset Desired offset in FB of FRTS data and WPR2 + * @param[in] cmd FWSEC cmd (FRTS or SB) + * @param[in] frtsOffset (if cmd is FRTS) desired FB offset of FRTS data */ -NV_STATUS -kgspExecuteFwsecFrts_TU102 +static NV_STATUS +s_executeFwsec_TU102 ( OBJGPU *pGpu, KernelGsp *pKernelGsp, KernelGspFlcnUcode *pFwsecUcode, + const NvU32 cmd, const NvU64 frtsOffset ) { NV_STATUS status; - NvU32 blockSizeIn4K; + FWSECLIC_READ_VBIOS_DESC readVbiosDesc; FWSECLIC_FRTS_CMD frtsCmd; + void *pCmdBuffer; + NvU32 cmdBufferSize; + NV_ASSERT_OR_RETURN(!IS_VIRTUAL(pGpu), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(pGpu), NV_ERR_NOT_SUPPORTED); NV_ASSERT_OR_RETURN(pFwsecUcode != NULL, NV_ERR_INVALID_ARGUMENT); - NV_ASSERT_OR_RETURN(frtsOffset > 0, NV_ERR_INVALID_ARGUMENT); + NV_ASSERT_OR_RETURN((cmd != FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) || + (frtsOffset > 0), NV_ERR_INVALID_ARGUMENT); - // Build up FRTS args - blockSizeIn4K = NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K; + if ((cmd != FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) && + (cmd != FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB)) + { + NV_ASSERT(0); + return NV_ERR_INVALID_ARGUMENT; + } - frtsCmd.frtsRegionDesc.version = 1; - frtsCmd.frtsRegionDesc.size = sizeof(frtsCmd.frtsRegionDesc); - frtsCmd.frtsRegionDesc.frtsRegionOffset4K = (NvU32) (frtsOffset >> 12); - frtsCmd.frtsRegionDesc.frtsRegionSize = blockSizeIn4K; - frtsCmd.frtsRegionDesc.frtsRegionMediaType = FWSECLIC_FRTS_REGION_MEDIA_FB; + readVbiosDesc.version = 1; + readVbiosDesc.size = sizeof(readVbiosDesc); + readVbiosDesc.gfwImageOffset = 0; + readVbiosDesc.gfwImageSize = 0; + readVbiosDesc.flags = FWSECLIC_READ_VBIOS_STRUCT_FLAGS; - frtsCmd.readVbiosDesc.version = 1; - frtsCmd.readVbiosDesc.size = sizeof(frtsCmd.readVbiosDesc); - frtsCmd.readVbiosDesc.gfwImageOffset = 0; - frtsCmd.readVbiosDesc.gfwImageSize = 0; - frtsCmd.readVbiosDesc.flags = FWSECLIC_READ_VBIOS_STRUCT_FLAGS; + if (cmd == FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) + { + // FRTS takes an FRTS_CMD, here we build that up + NvU32 blockSizeIn4K = NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K; + + frtsCmd.frtsRegionDesc.version = 1; + frtsCmd.frtsRegionDesc.size = sizeof(frtsCmd.frtsRegionDesc); + frtsCmd.frtsRegionDesc.frtsRegionOffset4K = (NvU32) (frtsOffset >> 12); + frtsCmd.frtsRegionDesc.frtsRegionSize = blockSizeIn4K; + frtsCmd.frtsRegionDesc.frtsRegionMediaType = FWSECLIC_FRTS_REGION_MEDIA_FB; + + frtsCmd.readVbiosDesc = readVbiosDesc; + + pCmdBuffer = &frtsCmd; + cmdBufferSize = sizeof(frtsCmd); + + } + else // i.e. FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB + { + // SB takes READ_VBIOS_DESC directly + pCmdBuffer = &readVbiosDesc; + cmdBufferSize = sizeof(readVbiosDesc); + } if (pFwsecUcode->bootType == KGSP_FLCN_UCODE_BOOT_FROM_HS) { @@ -345,8 +383,8 @@ kgspExecuteFwsecFrts_TU102 } pMappedData = pMappedImage + pUcode->dataOffset; - status = s_vbiosPatchFrtsInterfaceData(pMappedData, pUcode->dmemSize, - &frtsCmd, pUcode->interfaceOffset); + status = s_vbiosPatchInterfaceData(pMappedData, pUcode->dmemSize, cmd, + pCmdBuffer, cmdBufferSize, pUcode->interfaceOffset); portMemCopy(pMappedData + pUcode->hsSigDmemAddr, pUcode->sigSize, ((NvU8 *) pUcode->pSignatures) + sigOffset, pUcode->sigSize); @@ -358,7 +396,8 @@ kgspExecuteFwsecFrts_TU102 if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FRTS: 0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FWSEC cmd 0x%x: 0x%x\n", + cmd, status); return status; } } @@ -376,8 +415,8 @@ kgspExecuteFwsecFrts_TU102 return NV_ERR_INSUFFICIENT_RESOURCES; } - status = s_vbiosPatchFrtsInterfaceData(pMappedData, pUcode->dmemSize, - &frtsCmd, pUcode->interfaceOffset); + status = s_vbiosPatchInterfaceData(pMappedData, pUcode->dmemSize, cmd, + pCmdBuffer, cmdBufferSize, pUcode->interfaceOffset); memdescUnmapInternal(pGpu, pUcode->pDataMemDesc, TRANSFER_FLAGS_DESTROY_MAPPING); @@ -385,7 +424,8 @@ kgspExecuteFwsecFrts_TU102 if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FRTS: 0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, "failed to prepare interface data for FWSEC cmd 0x%x: 0x%x\n", + cmd, status); return status; } } @@ -399,10 +439,11 @@ kgspExecuteFwsecFrts_TU102 if (status != NV_OK) { - NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for FRTS: status 0x%x\n", status); + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC cmd 0x%x: status 0x%x\n", cmd, status); return status; } + if (cmd == FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS) { NvU32 data; NvU32 frtsErrCode; @@ -437,6 +478,73 @@ kgspExecuteFwsecFrts_TU102 return NV_ERR_GENERIC; } } + else // i.e. FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB + { + NvU32 data; + NvU32 sbErrCode; + + if (!GPU_FLD_TEST_DRF_DEF(pGpu, _PGC6, _AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK, + _READ_PROTECTION_LEVEL0, _ENABLE)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: GFW PLM not lowered\n"); + return NV_ERR_GENERIC; + } + + if (!GPU_FLD_TEST_DRF_DEF(pGpu, _PGC6, _AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT, + _PROGRESS, _COMPLETED)) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: GFW progress not completed\n"); + return NV_ERR_GENERIC; + } + + data = GPU_REG_RD32(pGpu, NV_PBUS_VBIOS_SCRATCH(NV_VBIOS_FWSECLIC_SCRATCH_INDEX_15)); + sbErrCode = DRF_VAL(_VBIOS, _FWSECLIC, _SB_ERR_CODE, data); + if (sbErrCode != NV_VBIOS_FWSECLIC_SB_ERR_CODE_NONE) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC for SB: SB error code 0x%x\n", sbErrCode); + return NV_ERR_GENERIC; + } + } return status; } + +/*! + * Excecute FWSEC for FRTS and wait for completion. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGsp KernelGsp pointer + * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode + * @param[in] frtsOffset Desired offset in FB of FRTS data and WPR2 + */ +NV_STATUS +kgspExecuteFwsecFrts_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + KernelGspFlcnUcode *pFwsecUcode, + const NvU64 frtsOffset +) +{ + return s_executeFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, + FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_FRTS, frtsOffset); +} + +/*! + * Excecute FWSEC's SB command and wait for completion. + * + * @param[in] pGpu OBJGPU pointer + * @param[in] pKernelGsp KernelGsp pointer + * @param[in] pFwsecUcode KernelGspFlcnUcode structure of FWSEC ucode + */ +NV_STATUS +kgspExecuteFwsecSb_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp, + KernelGspFlcnUcode *pFwsecUcode +) +{ + return s_executeFwsec_TU102(pGpu, pKernelGsp, pFwsecUcode, + FALCON_APPLICATION_INTERFACE_DMEM_MAPPER_V3_CMD_SB, 0); +} diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c index fff6e1b15..5fe47ca01 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c @@ -48,6 +48,8 @@ #include "published/turing/tu102/dev_gc6_island.h" #include "published/turing/tu102/dev_gc6_island_addendum.h" +#include "gpu/sec2/kernel_sec2.h" + #define RPC_STRUCTURES #define RPC_GENERIC_UNION #include "g_rpc-structures.h" @@ -261,6 +263,23 @@ kgspFreeBootArgs_TU102 } } +/*! + * Determine if GSP reload via SEC2 is completed. + */ +static NvBool +_kgspIsReloadCompleted +( + OBJGPU *pGpu, + void *pVoid +) +{ + NvU32 reg; + + reg = GPU_REG_RD32(pGpu, NV_PGC6_BSI_SECURE_SCRATCH_14); + + return FLD_TEST_DRF(_PGC6, _BSI_SECURE_SCRATCH_14, _BOOT_STAGE_3_HANDOFF, _VALUE_DONE, reg); +} + /*! * Set command queue head for CPU to GSP message queue * @@ -464,6 +483,7 @@ kgspCalculateFbLayout_TU102 ) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); + KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu); GspFwWprMeta *pWprMeta = pKernelGsp->pWprMeta; RM_RISCV_UCODE_DESC *pRiscvDesc = pKernelGsp->pGspRmBootUcodeDesc; @@ -488,9 +508,8 @@ kgspCalculateFbLayout_TU102 // Figure out where VGA workspace is located. We do not have to adjust // it ourselves (see vgaRelocateWorkspaceBase_HAL()). // - KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu); - - if (kdispGetVgaWorkspaceBase(pGpu, pKernelDisplay, &pWprMeta->vgaWorkspaceOffset)) + if (gpuFuseSupportsDisplay_HAL(pGpu) && + kdispGetVgaWorkspaceBase(pGpu, pKernelDisplay, &pWprMeta->vgaWorkspaceOffset)) { if (pWprMeta->vgaWorkspaceOffset < (pWprMeta->fbSize - DRF_SIZE(NV_PRAMIN))) { @@ -629,22 +648,46 @@ kgspExecuteSequencerCommand_TU102 { NV_STATUS status = NV_OK; KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon); + NvU32 secMailbox0 = 0; + switch (opCode) { case GSP_SEQ_BUF_OPCODE_CORE_RESUME: { { + KernelFalcon *pKernelSec2Falcon = staticCast(GPU_GET_KERNEL_SEC2(pGpu), KernelFalcon); + kflcnSecureReset_HAL(pGpu, pKernelFalcon); kgspProgramLibosBootArgsAddr_HAL(pGpu, pKernelGsp); - status = kgspExecuteBooterReload_HAL(pGpu, pKernelGsp); - if (status != NV_OK) + NV_PRINTF(LEVEL_INFO, "---------------Starting SEC2 to resume GSP-RM------------\n"); + // Start SEC2 in order to resume GSP-RM + kflcnStartCpu_HAL(pGpu, pKernelSec2Falcon); + + // Wait for reload to be completed. + status = gpuTimeoutCondWait(pGpu, _kgspIsReloadCompleted, NULL, NULL); + + // Check SEC mailbox. + secMailbox0 = kflcnRegRead_HAL(pGpu, pKernelSec2Falcon, NV_PFALCON_FALCON_MAILBOX0); + + if ((status != NV_OK) || (secMailbox0 != NV_OK)) { - NV_PRINTF(LEVEL_ERROR, "failed to execute Booter Reload (ucode for resume from sequencer): 0x%x\n", status); - break; + NV_PRINTF(LEVEL_ERROR, "Timeout waiting for SEC2-RTOS to resume GSP-RM. SEC2 Mailbox0 is : 0x%x\n", secMailbox0); + DBG_BREAKPOINT(); + return NV_ERR_TIMEOUT; } } + // Ensure the CPU is started + if (kflcnIsRiscvActive_HAL(pGpu, pKernelFalcon)) + { + NV_PRINTF(LEVEL_INFO, "GSP ucode loaded and RISCV started.\n"); + } + else + { + NV_ASSERT_FAILED("Failed to boot GSP"); + status = NV_ERR_NOT_READY; + } break; } @@ -790,6 +833,33 @@ kgspService_TU102 return intrStatus; } +static NvBool +_kgspIsProcessorSuspended +( + OBJGPU *pGpu, + void *pVoid +) +{ + KernelGsp *pKernelGsp = reinterpretCast(pVoid, KernelGsp *); + NvU32 mailbox; + + // Check for LIBOS_INTERRUPT_PROCESSOR_SUSPENDED in mailbox + mailbox = kflcnRegRead_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon), + NV_PFALCON_FALCON_MAILBOX0); + return (mailbox & 0x80000000) == 0x80000000; +} + +NV_STATUS +kgspWaitForProcessorSuspend_TU102 +( + OBJGPU *pGpu, + KernelGsp *pKernelGsp +) +{ + return gpuTimeoutCondWait(pGpu, _kgspIsProcessorSuspended, pKernelGsp, NULL); +} + + #define FWSECLIC_PROG_START_TIMEOUT 50000 // 50ms #define FWSECLIC_PROG_COMPLETE_TIMEOUT 2000000 // 2s diff --git a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c index 9f05423e2..14a4a1473 100644 --- a/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c +++ b/src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_vbios_tu102.c @@ -233,7 +233,7 @@ s_romImgFindPciHeader_TU102 default: NV_PRINTF(LEVEL_ERROR, "Error: IFR version not supported = 0x%08x.\n", ifrVersion); - return NV_ERR_NOT_SUPPORTED; + return NV_ERR_INVALID_DATA; } } diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c index e823882be..5d62491e1 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c @@ -1256,43 +1256,52 @@ kgspInitRm_IMPL * * Here, we extract a VBIOS image from ROM, and parse it for FWSEC. */ - if (kgspGetFrtsSize_HAL(pGpu, pKernelGsp) > 0) + if (pKernelGsp->pFwsecUcode == NULL) { - if (pKernelGsp->pFwsecUcode == NULL) + KernelGspVbiosImg *pVbiosImg = NULL; + + // Try and extract a VBIOS image. + status = kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, &pVbiosImg); + + if (status == NV_OK) { - KernelGspVbiosImg *pVbiosImg = NULL; - - status = kgspExtractVbiosFromRom_HAL(pGpu, pKernelGsp, &pVbiosImg); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to extract VBIOS image from ROM: 0x%x\n", - status); - goto done; - } - + // Got a VBIOS image, now parse it for FWSEC. status = kgspParseFwsecUcodeFromVbiosImg(pGpu, pKernelGsp, pVbiosImg, - &pKernelGsp->pFwsecUcode); + &pKernelGsp->pFwsecUcode); kgspFreeVbiosImg(pVbiosImg); if (status != NV_OK) { NV_PRINTF(LEVEL_ERROR, "failed to parse FWSEC ucode from VBIOS image: 0x%x\n", - status); + status); goto done; } } + else if (status == NV_ERR_NOT_SUPPORTED) + { + // + // Extracting VBIOS image from ROM is not supported. + // Sanity check we don't depend on it for FRTS, and proceed without FWSEC. + // + NV_ASSERT_OR_GOTO(kgspGetFrtsSize(pGpu, pKernelGsp) == 0, done); + status = NV_OK; + } + else + { + NV_PRINTF(LEVEL_ERROR, "failed to extract VBIOS image from ROM: 0x%x\n", + status); + goto done; + } + } /* * We use a set of Booter ucodes to boot GSP-RM as well as manage its lifecycle. * * Booter Load loads, verifies, and boots GSP-RM in WPR2. - * Booter Reload resumes GSP-RM after it has suspended for running GSP sequencer. * Booter Unload tears down WPR2 for driver unload. * * Here we prepare the Booter ucode images in SYSMEM so they may be loaded onto * SEC2 (Load / Unload) and NVDEC0 (Unload). - * - * GSPRM-TODO: remove Reload (and Reload comment) once reload is handled by SEC2-RTOS */ { if (pKernelGsp->pBooterLoadUcode == NULL) @@ -1306,25 +1315,6 @@ kgspInitRm_IMPL } } - if (pKernelGsp->pBooterReloadUcode == NULL) - { - KernelNvdec *pKernelNvdec = GPU_GET_KERNEL_NVDEC(pGpu); - if (pKernelNvdec == NULL) - { - NV_PRINTF(LEVEL_ERROR, "missing NVDEC0 engine, cannot initialize GSP-RM\n"); - status = NV_ERR_NOT_SUPPORTED; - goto done; - } - - status = kgspAllocateBooterReloadUcodeImage(pGpu, pKernelGsp, - &pKernelGsp->pBooterReloadUcode); - if (status != NV_OK) - { - NV_PRINTF(LEVEL_ERROR, "failed to allocate Booter Reload ucode: 0x%x\n", status); - goto done; - } - } - if (pKernelGsp->pBooterUnloadUcode == NULL) { status = kgspAllocateBooterUnloadUcodeImage(pGpu, pKernelGsp, @@ -1438,6 +1428,21 @@ kgspUnloadRm_IMPL NV_PRINTF(LEVEL_INFO, "unloading GSP-RM\n"); NV_RM_RPC_UNLOADING_GUEST_DRIVER(pGpu, rpcStatus, NV_FALSE, NV_FALSE, 0); + // Wait for GSP-RM processor to suspend + kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp); + + // Dump GSP-RM logs and reset before invoking FWSEC-SB + kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE); + kflcnReset_HAL(pGpu, staticCast(pKernelGsp, KernelFalcon)); + + // Invoke FWSEC-SB to put back PreOsApps during driver unload + status = kgspExecuteFwsecSb_HAL(pGpu, pKernelGsp, pKernelGsp->pFwsecUcode); + if (status != NV_OK) + { + NV_PRINTF(LEVEL_ERROR, "failed to execute FWSEC-SB for PreOsApps during driver unload: 0x%x\n", status); + NV_ASSERT(0); + } + { // After instructing GSP-RM to unload itself, run Booter Unload to teardown WPR2 status = kgspExecuteBooterUnloadIfNeeded_HAL(pGpu, pKernelGsp); @@ -1471,9 +1476,6 @@ kgspDestruct_IMPL kgspFreeFlcnUcode(pKernelGsp->pBooterLoadUcode); pKernelGsp->pBooterLoadUcode = NULL; - kgspFreeFlcnUcode(pKernelGsp->pBooterReloadUcode); - pKernelGsp->pBooterReloadUcode = NULL; - kgspFreeFlcnUcode(pKernelGsp->pBooterUnloadUcode); pKernelGsp->pBooterUnloadUcode = NULL; diff --git a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c index 85eadc924..8ea5b9706 100644 --- a/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c +++ b/src/nvidia/src/kernel/gpu/gsp/kernel_gsp_booter.c @@ -24,7 +24,6 @@ #include "gpu/gsp/kernel_gsp.h" #include "gpu/mem_mgr/mem_mgr.h" -#include "gpu/nvdec/kernel_nvdec.h" #include "gpu/sec2/kernel_sec2.h" #include "core/bin_data.h" @@ -133,7 +132,6 @@ static NV_STATUS s_patchBooterUcodeSignature ( OBJGPU *pGpu, - NvBool bIsForNvdec, NvU32 ucodeId, NvU8 *pImage, NvU32 sigDestOffset, @@ -153,19 +151,9 @@ s_patchBooterUcodeSignature NV_ASSERT_OR_RETURN(pSignatures != NULL, NV_ERR_INVALID_STATE); NV_ASSERT_OR_RETURN(numSigs > 0, NV_ERR_INVALID_DATA); - // Booter Reload is on NVDEC0, all other Booters are on SEC2 - if (bIsForNvdec) - { - KernelNvdec *pKernelNvdec = GPU_GET_KERNEL_NVDEC(pGpu); - NV_ASSERT_OR_RETURN(pKernelNvdec != NULL, NV_ERR_INVALID_STATE); - fuseVer = knvdecReadUcodeFuseVersion_HAL(pGpu, pKernelNvdec, ucodeId); - } - else - { - KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); - NV_ASSERT_OR_RETURN(pKernelSec2 != NULL, NV_ERR_INVALID_STATE); - fuseVer = ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId); - } + KernelSec2 *pKernelSec2 = GPU_GET_KERNEL_SEC2(pGpu); + NV_ASSERT_OR_RETURN(pKernelSec2 != NULL, NV_ERR_INVALID_STATE); + fuseVer = ksec2ReadUcodeFuseVersion_HAL(pGpu, pKernelSec2, ucodeId); if (numSigs > 1) { @@ -187,7 +175,6 @@ s_allocateUcodeFromBinArchive OBJGPU *pGpu, KernelGsp *pKernelGsp, const BINDATA_ARCHIVE *pBinArchive, - const NvBool bIsForNvdec, KernelGspFlcnUcode **ppFlcnUcode // out ) { @@ -375,7 +362,7 @@ s_allocateUcodeFromBinArchive if (status == NV_OK) { status = s_patchBooterUcodeSignature(pGpu, - bIsForNvdec, patchMeta.ucodeId, + patchMeta.ucodeId, pMappedUcodeMem, patchLoc, pUcode->size, pSignatures, signaturesTotalSize, numSigs); NV_ASSERT(status == NV_OK); @@ -421,7 +408,7 @@ s_allocateUcodeFromBinArchive // Patch signatures NV_ASSERT_OK_OR_GOTO(status, s_patchBooterUcodeSignature(pGpu, - bIsForNvdec, patchMeta.ucodeId, + patchMeta.ucodeId, pUcode->pImage, patchLoc, pUcode->size, pSignatures, signaturesTotalSize, numSigs), out); @@ -459,27 +446,7 @@ kgspAllocateBooterLoadUcodeImage_IMPL pBinArchive = kgspGetBinArchiveBooterLoadUcode_HAL(pKernelGsp); NV_ASSERT_OR_RETURN(pBinArchive != NULL, NV_ERR_NOT_SUPPORTED); - return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, - NV_FALSE /* i.e. not NVDEC */, ppBooterLoadUcode); -} - -NV_STATUS -kgspAllocateBooterReloadUcodeImage_IMPL -( - OBJGPU *pGpu, - KernelGsp *pKernelGsp, - KernelGspFlcnUcode **ppBooterReloadUcode // out -) -{ - const BINDATA_ARCHIVE *pBinArchive; - - NV_ASSERT_OR_RETURN(ppBooterReloadUcode != NULL, NV_ERR_INVALID_ARGUMENT); - - pBinArchive = kgspGetBinArchiveBooterReloadUcode_HAL(pKernelGsp); - NV_ASSERT_OR_RETURN(pBinArchive != NULL, NV_ERR_NOT_SUPPORTED); - - return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, - NV_TRUE /* i.e. NVDEC */, ppBooterReloadUcode); + return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, ppBooterLoadUcode); } NV_STATUS @@ -497,6 +464,5 @@ kgspAllocateBooterUnloadUcodeImage_IMPL pBinArchive = kgspGetBinArchiveBooterUnloadUcode_HAL(pKernelGsp); NV_ASSERT_OR_RETURN(pBinArchive != NULL, NV_ERR_NOT_SUPPORTED); - return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, - NV_FALSE /* i.e. not NVDEC */, ppBooterUnloadUcode); + return s_allocateUcodeFromBinArchive(pGpu, pKernelGsp, pBinArchive, ppBooterUnloadUcode); } diff --git a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c index 1a3b74a77..18e8764e1 100644 --- a/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c +++ b/src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c @@ -514,11 +514,13 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI) int nRet; int i; int nRetries; + int nMaxRetries = 3; int nElements = 1; // Assume record fits in one 256-byte queue element for now. NvU32 uElementSize = 0; + NvU32 seqMismatchDiff = NV_U32_MAX; NV_STATUS nvStatus = NV_OK; - for (nRetries = 0; nRetries < 3; nRetries++) + for (nRetries = 0; nRetries < nMaxRetries; nRetries++) { pTgt = (NvU8 *)pMQI->pCmdQueueElement; nvStatus = NV_OK; @@ -587,10 +589,29 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI) // Retry if sequence number is wrong. if (pMQI->pCmdQueueElement->seqNum != pMQI->rxSeqNum) - { - NV_PRINTF(LEVEL_ERROR, "Bad sequence number. Expected %u got %u.\n", + NV_PRINTF(LEVEL_ERROR, "Bad sequence number. Expected %u got %u. Possible memory corruption.\n", pMQI->rxSeqNum, pMQI->pCmdQueueElement->seqNum); + + // If we read an old piece of data, try to ignore it and move on.. + if (pMQI->pCmdQueueElement->seqNum < pMQI->rxSeqNum) + { + // Make sure we're converging to the desired pMQI->rxSeqNum + if ((pMQI->rxSeqNum - pMQI->pCmdQueueElement->seqNum) < seqMismatchDiff) + { + NV_PRINTF(LEVEL_ERROR, "Attempting recovery: ignoring old package with seqNum=%u of %u elements.\n", + pMQI->pCmdQueueElement->seqNum, nElements); + + seqMismatchDiff = pMQI->rxSeqNum - pMQI->pCmdQueueElement->seqNum; + nRet = msgqRxMarkConsumed(pMQI->hQueue, nElements); + if (nRet < 0) + { + NV_PRINTF(LEVEL_ERROR, "msgqRxMarkConsumed failed: %d\n", nRet); + } + nMaxRetries++; + } + } + nvStatus = NV_ERR_INVALID_DATA; continue; } diff --git a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c index 694112de9..d20038188 100644 --- a/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c +++ b/src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c @@ -1285,21 +1285,14 @@ _memdescFreeInternal // we're plenty off the rails already, but avoid using the pGpu // and carry on as best we can // - if (gpumgrGetGpuGrpFromGpu(pGpu) != NULL) + if (gpumgrIsGpuPointerValid(pGpu)) { SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY) { KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu); - if (pKernelMemorySystem == NULL) - { - NV_ASSERT_FAILED("Sysmemdesc outlived its attached Gpu Memory System"); - } - else - { - NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, + NV_ASSERT_OK(kmemsysCacheOp_HAL(pGpu, pKernelMemorySystem, pMemDesc, FB_CACHE_SYSTEM_MEMORY, FB_CACHE_INVALIDATE)); - } } SLI_LOOP_END } diff --git a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c index 5bcad0407..4c15f45c6 100644 --- a/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c +++ b/src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c @@ -451,6 +451,30 @@ knvlinkTrainP2pLinksToActive_IMPL return NV_OK; } + // + // Bug# 3601144: On Ampere+ systems, return if links are already initialized, + // since that implies links are already trained. + // + if (IsAMPEREorBetter(pGpu0)) + { + NvU32 linkMask = 0; + + FOR_EACH_INDEX_IN_MASK(32, i, pKernelNvlink0->enabledLinks) + { + if (KNVLINK_IS_LINK_CONNECTED_TO_GPU(pKernelNvlink0, i, pGpu1)) + { + linkMask |= BIT(i); + } + } + FOR_EACH_INDEX_IN_MASK_END; + + if ((linkMask & pKernelNvlink0->initializedLinks) == linkMask) + { + NV_PRINTF(LEVEL_INFO, "P2P links are all trained already, return\n"); + return NV_OK; + } + } + // Get the link train status for the enabled link masks NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS linkTrainedParams; diff --git a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c index 7ba1c8b94..609297449 100644 --- a/src/nvidia/src/kernel/gpu/subdevice/subdevice.c +++ b/src/nvidia/src/kernel/gpu/subdevice/subdevice.c @@ -116,6 +116,8 @@ subdeviceConstruct_IMPL } } + NV_ASSERT_OK_OR_RETURN(gpuRegisterSubdevice(pGpu, pSubdevice)); + if (IS_VIRTUAL(pGpu) || IS_GSP_CLIENT(pGpu)) { NV_RM_RPC_ALLOC_SUBDEVICE(pPrimaryGpu, pRsClient->hClient, pParentRef->hResource, @@ -206,6 +208,8 @@ subdeviceDestruct_IMPL pSubdevice->bSchedPolicySet = NV_FALSE; } } + + gpuUnregisterSubdevice(pGpu, pSubdevice); } NV_STATUS diff --git a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c index 780b800fc..5c342d9ce 100644 --- a/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c +++ b/src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c @@ -44,8 +44,9 @@ #include "gpu/mem_sys/kern_mem_sys.h" // local static funcs -static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); -static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); +static void gpumgrSetAttachInfo(OBJGPU *, GPUATTACHARG *); +static void gpumgrGetGpuHalFactor(NvU32 *pChipId0, NvU32 *pChipId1, RM_RUNTIME_VARIANT *pRmVariant, GPUATTACHARG *pAttachArg); +static NvBool _gpumgrGetPcieP2PCapsFromCache(NvU32 gpuMask, NvU8* pP2PWriteCapsStatus, NvU8* pP2PReadCapsStatus); static void _gpumgrUnregisterRmCapsForGpuUnderLock(NvU64 gpuDomainBusDevice) @@ -157,6 +158,8 @@ gpumgrConstruct_IMPL(OBJGPUMGR *pGpuMgr) pGpuMgr->powerDisconnectedGpuCount = 0; + NV_ASSERT_OK_OR_RETURN(gpumgrInitPcieP2PCapsCache(pGpuMgr)); + return NV_OK; } @@ -167,6 +170,9 @@ gpumgrDestruct_IMPL(OBJGPUMGR *pGpuMgr) NV_PRINTF(LEVEL_INFO, "gpumgrDestruct\n"); portSyncMutexDestroy(pGpuMgr->probedGpusLock); + + gpumgrDestroyPcieP2PCapsCache(pGpuMgr); + } // @@ -538,6 +544,7 @@ gpumgrUnregisterGpuId(NvU32 gpuId) if (pProbedGpu->gpuId == gpuId) { + gpumgrRemovePcieP2PCapsFromCache(pProbedGpu->gpuId); _gpumgrUnregisterRmCapsForGpuUnderLock(pProbedGpu->gpuDomainBusDevice); pProbedGpu->gpuId = NV0000_CTRL_GPU_INVALID_ID; pProbedGpu->bDrainState = NV_FALSE; @@ -3136,3 +3143,251 @@ gpumgrGetGpuBridgeType(void) return pGpuMgr->gpuBridgeType; } + +/** +* @brief Init the PCIE P2P info cache +*/ +NV_STATUS +gpumgrInitPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) +{ + listInitIntrusive(&pGpuMgr->pcieP2PCapsInfoCache); + pGpuMgr->pcieP2PCapsInfoLock = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged()); + if (pGpuMgr->pcieP2PCapsInfoLock == NULL) + { + return NV_ERR_INSUFFICIENT_RESOURCES; + } + return NV_OK; +} + +/** +* @brief Destroy the PCIE P2P info cache +*/ +void +gpumgrDestroyPcieP2PCapsCache_IMPL(OBJGPUMGR* pGpuMgr) +{ + PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext; + + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); + + // Remove and free all entries that have this GPU + for (pPcieCapsInfo = listHead(&(pGpuMgr->pcieP2PCapsInfoCache)); + pPcieCapsInfo != NULL; + pPcieCapsInfo = pPcieCapsInfoNext) + { + pPcieCapsInfoNext = listNext(&(pGpuMgr->pcieP2PCapsInfoCache), pPcieCapsInfo); + portMemFree(pPcieCapsInfo); + } + + listDestroy(&pGpuMgr->pcieP2PCapsInfoCache); + portSyncMutexRelease(pGpuMgr->pcieP2PCapsInfoLock); + + portSyncMutexDestroy(pGpuMgr->pcieP2PCapsInfoLock); +} + +/** +* @brief Add an entry in the PCIE P2P info cache + * @param[in] gpuMask NvU32 value + * @param[in] p2pWriteCapsStatus NvU8 value + * @param[in] pP2PReadCapsStatus NvU8 value + * + * @return NV_OK or NV_ERR_NO_MEMORY + */ +NV_STATUS +gpumgrStorePcieP2PCapsCache_IMPL +( + NvU32 gpuMask, + NvU8 p2pWriteCapsStatus, + NvU8 p2pReadCapsStatus +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + PCIEP2PCAPSINFO *pPcieCapsInfo; + NvU32 gpuInstance; + OBJGPU *pGpu; + NvU32 gpuCount = 0; + NvU32 status = NV_OK; + + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); + if (_gpumgrGetPcieP2PCapsFromCache(gpuMask, NULL, NULL)) + { + // Entry already present in cache + goto exit; + } + + pPcieCapsInfo = portMemAllocNonPaged(sizeof(PCIEP2PCAPSINFO)); + if (pPcieCapsInfo == NULL) + { + status = NV_ERR_NO_MEMORY; + goto exit; + } + listAppendExisting(&(pGpuMgr->pcieP2PCapsInfoCache), pPcieCapsInfo); + + gpuInstance = 0; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + pPcieCapsInfo->gpuId[gpuCount] = pGpu->gpuId; + gpuCount++; + } + + pPcieCapsInfo->gpuCount = gpuCount; + pPcieCapsInfo->p2pWriteCapsStatus = p2pWriteCapsStatus; + pPcieCapsInfo->p2pReadCapsStatus = p2pReadCapsStatus; + +exit: + portSyncMutexRelease(pGpuMgr->pcieP2PCapsInfoLock); + return status; +} + +/** + * @brief Get the PCIE P2P info from cache if present + * - Helper function + * + * @param[in] gpuMask NvU32 value + * @param[out] pP2PWriteCapsStatus NvU8* pointer + * Can be NULL + * @param[out] pP2PReadCapsStatus NvU8* pointer + * Can be NULL + * Return bFound NvBool + */ +static NvBool +_gpumgrGetPcieP2PCapsFromCache +( + NvU32 gpuMask, + NvU8 *pP2PWriteCapsStatus, + NvU8 *pP2PReadCapsStatus) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + PCIEP2PCAPSINFO *pPcieCapsInfo; + pcieP2PCapsInfoListIter it; + NvU32 gpuInstance; + NvU32 gpuCount; + NvU32 remainingGpuCount; + OBJGPU *pGpu; + NvU32 gpuIdLoop; + NvBool bFound = NV_FALSE; + + gpuCount = gpumgrGetSubDeviceCount(gpuMask); + + it = listIterAll(&pGpuMgr->pcieP2PCapsInfoCache); + while (listIterNext(&it)) + { + pPcieCapsInfo = it.pValue; + if (gpuCount != pPcieCapsInfo->gpuCount) + { + continue; + } + + // + // Same count of GPUs in gpuId array and GPU mask. + // All GPU in the gpuMask must have a match in gpuId[] + // + gpuInstance = 0; + remainingGpuCount = gpuCount; + while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) + { + gpuIdLoop = 0; + while (gpuIdLoop < gpuCount) + { + if (pPcieCapsInfo->gpuId[gpuIdLoop] == pGpu->gpuId) + { + remainingGpuCount--; + break; + } + gpuIdLoop++; + } + if (remainingGpuCount == 0) + { + break; + } + } + + if (remainingGpuCount == 0) + { + if (pP2PWriteCapsStatus != NULL) + *pP2PWriteCapsStatus = pPcieCapsInfo->p2pWriteCapsStatus; + if (pP2PReadCapsStatus != NULL) + *pP2PReadCapsStatus = pPcieCapsInfo->p2pReadCapsStatus; + bFound = NV_TRUE; + break; + } + } + return bFound; +} + +/** + * @brief Get the PCIE P2P info from cache if present + * - Take cache locks + * + * @param[in] gpuMask NvU32 value + * @param[out] pP2PWriteCapsStatus NvU8* pointer + * Can be NULL + * @param[out] pP2PReadCapsStatus NvU8* pointer + * Can be NULL + * + * return bFound NvBool + */ +NvBool +gpumgrGetPcieP2PCapsFromCache_IMPL +( + NvU32 gpuMask, + NvU8 *pP2PWriteCapsStatus, + NvU8 *pP2PReadCapsStatus +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + NvBool bFound; + + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); + + bFound = _gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapsStatus, pP2PReadCapsStatus); + + portSyncMutexRelease(pGpuMgr->pcieP2PCapsInfoLock); + + return bFound; +} + + +/** + * @brief Remove the PCIE P2P info from cache if present + * + * @param[in] gpuId NvU32 value + */ +void +gpumgrRemovePcieP2PCapsFromCache_IMPL +( + NvU32 gpuId +) +{ + OBJSYS *pSys = SYS_GET_INSTANCE(); + OBJGPUMGR *pGpuMgr = SYS_GET_GPUMGR(pSys); + PCIEP2PCAPSINFO *pPcieCapsInfo, *pPcieCapsInfoNext; + NvU32 gpuIdLoop; + + portSyncMutexAcquire(pGpuMgr->pcieP2PCapsInfoLock); + + // Remove and free all entries that have this GPU + for (pPcieCapsInfo = listHead(&(pGpuMgr->pcieP2PCapsInfoCache)); + pPcieCapsInfo != NULL; + pPcieCapsInfo = pPcieCapsInfoNext) + { + // As we potentially remove an entry we need to save off the next one. + pPcieCapsInfoNext = listNext(&(pGpuMgr->pcieP2PCapsInfoCache), pPcieCapsInfo); + gpuIdLoop = 0; + while (gpuIdLoop < pPcieCapsInfo->gpuCount) + { + if (pPcieCapsInfo->gpuId[gpuIdLoop] == gpuId) + { + listRemove(&pGpuMgr->pcieP2PCapsInfoCache, pPcieCapsInfo); + portMemFree(pPcieCapsInfo); + // Go to next entry (for loop) + break; + } + gpuIdLoop++; + } + } + portSyncMutexRelease(pGpuMgr->pcieP2PCapsInfoLock); +} + diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_info.c b/src/nvidia/src/kernel/platform/chipset/chipset_info.c index 8fcdccb0d..e03d541ce 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_info.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_info.c @@ -487,7 +487,7 @@ Intel_Core_Nehalem_Processor_setupFunc // config space BAR in a Core i7 CPU. // // Current link for i7: - // http://download.intel.com/design/processor/datashts/320835.pdf + // https://download.intel.com/design/processor/datashts/320835.pdf // Link for i5 not found. It has been reverse engineered. // We need to find the pci functions, "Intel QuickPath diff --git a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c index bfa501e9a..014a2a9ed 100644 --- a/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c +++ b/src/nvidia/src/kernel/platform/chipset/chipset_pcie.c @@ -3308,7 +3308,7 @@ gpuIsMultiGpuBoard * RSDT or XSDT ACPI table. * * We will use these tables to find the addresses of other tables. - * http://www.acpi.info/DOWNLOADS/ACPIspec40.pdf sections 5.2.5.1 and 5.2.5.3. + * https://www.acpi.info/DOWNLOADS/ACPIspec40.pdf sections 5.2.5.1 and 5.2.5.3. * * @param[in] pOS OBJOS pointer * @param[in] start RmPhysAddr starting point from where to look for the RDSP table @@ -3423,7 +3423,7 @@ clGetRsdtXsdtTablesAddr_IMPL } // - // Sections from http://www.acpi.info/DOWNLOADS/ACPIspec40.pdf referenced below. + // Sections from https://www.acpi.info/DOWNLOADS/ACPIspec40.pdf referenced below. // 1. Section 5.2.5.1 and 5.2.5.2 - get the Root System Description Pointer (RSDP) // Search physical memory ranges on 16-byte boundaries for a valid // Root System Description Pointer structure signature and checksum @@ -3560,7 +3560,7 @@ clGetMcfgTableFromOS_IMPL * @brief Scans the RSDT and/or XSDT tables to get the address of the table matching the * signature. * - * http://www.acpi.info/DOWNLOADS/ACPIspec40.pdf sections 5.2.7 and 5.2.8 + * https://www.acpi.info/DOWNLOADS/ACPIspec40.pdf sections 5.2.7 and 5.2.8 * The description header addresses start at offset 36. * * @param[in] POS OBJOS pointer diff --git a/src/nvidia/src/kernel/platform/cpu.c b/src/nvidia/src/kernel/platform/cpu.c index 53534b2a9..779a33648 100644 --- a/src/nvidia/src/kernel/platform/cpu.c +++ b/src/nvidia/src/kernel/platform/cpu.c @@ -246,7 +246,7 @@ void RmInitCpuInfo(void) /* * Documentation: * - * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388f/CIHHDACH.html + * https://developer.arm.com/documentation/ddi0388/f/CIHHDACH */ static void DecodeCortexA9Cache(OBJSYS *pSys) { diff --git a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c index 144eee6d8..987d14577 100644 --- a/src/nvidia/src/kernel/platform/p2p/p2p_caps.c +++ b/src/nvidia/src/kernel/platform/p2p/p2p_caps.c @@ -336,7 +336,17 @@ _kp2pCapsGetStatusOverPcie return NV_OK; } + pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance); + if (IS_GSP_CLIENT(pGpu)) + { + if (gpumgrGetPcieP2PCapsFromCache(gpuMask, pP2PWriteCapStatus, pP2PReadCapStatus)) + { + return NV_OK; + } + } + // PCI-E topology checks + gpuInstance = 0; while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL) { // @@ -374,7 +384,7 @@ _kp2pCapsGetStatusOverPcie { *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED; *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED; - return NV_OK; + goto done; } } } @@ -390,7 +400,7 @@ _kp2pCapsGetStatusOverPcie { *pP2PReadCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; *pP2PWriteCapStatus = NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED; - return NV_OK; + goto done; } // This call returns the most upper bridge @@ -496,6 +506,16 @@ done: } } + // + // Not fatal if failing, effect would be perf degradation as we would not hit the cache. + // So just assert. + // + gpuInstance = 0; + pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance); + if (IS_GSP_CLIENT(pGpu)) + { + NV_ASSERT_OK(gpumgrStorePcieP2PCapsCache(gpuMask, *pP2PWriteCapStatus, *pP2PReadCapStatus)); + } return status; } diff --git a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c index 5515a1d75..13a31a3d3 100644 --- a/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c +++ b/src/nvidia/src/kernel/rmapi/nv_gpu_ops.c @@ -203,6 +203,7 @@ struct gpuSession PORT_RWLOCK *btreeLock; }; + MAKE_MAP(MemdescMap, PMEMORY_DESCRIPTOR); struct gpuDevice @@ -249,7 +250,6 @@ struct gpuAddressSpace PORT_RWLOCK *physAllocationsLock; NvU64 vaBase; NvU64 vaSize; - // Dummy BAR1 allocation required on PCIe systems when GPPut resides in // sysmem. struct @@ -1550,7 +1550,7 @@ out: // megabytes per seconds.. static NV_STATUS getPCIELinkRateMBps(struct gpuDevice *device, NvU32 *pcieLinkRate) { - // PCI Express Base Specification: http://www.pcisig.com/specifications/pciexpress + // PCI Express Base Specification: https://www.pcisig.com/specifications/pciexpress const NvU32 PCIE_1_ENCODING_RATIO_TOTAL = 10; const NvU32 PCIE_1_ENCODING_RATIO_EFFECTIVE = 8; const NvU32 PCIE_2_ENCODING_RATIO_TOTAL = 10; @@ -3690,6 +3690,7 @@ static NV_STATUS nvGpuOpsAllocVirtual(struct gpuAddressSpace *vaSpace, portSyncRwLockAcquireWrite(vaSpace->allocationsLock); status = trackDescriptor(&vaSpace->allocations, memDesc->address, memDesc); portSyncRwLockReleaseWrite(vaSpace->allocationsLock); + if (status != NV_OK) goto done; @@ -4654,7 +4655,7 @@ static NV_STATUS engineAllocate(struct gpuChannel *channel, gpuChannelInfo *chan return NV_ERR_NO_MEMORY; object->handle = NV01_NULL_OBJECT; - + if (engineType == UVM_GPU_CHANNEL_ENGINE_TYPE_CE) { ceAllocParams.version = NVB0B5_ALLOCATION_PARAMETERS_VERSION_1; @@ -7214,7 +7215,7 @@ static NV_STATUS nvGpuOpsGetChannelInstanceMemInfo(gpuRetainedChannel *retainedC CHID_MGR *pChidMgr = kfifoGetChidMgr(retainedChannel->pGpu, pKernelFifo, retainedChannel->runlistId); - + pKernelChannel = kfifoChidMgrGetKernelChannel(retainedChannel->pGpu, pKernelFifo, pChidMgr, @@ -8702,6 +8703,7 @@ void nvGpuOpsPagingChannelsUnmap(struct gpuAddressSpace *srcVaSpace, return; } + status = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU_OPS); NV_ASSERT(status == NV_OK); if (status != NV_OK) diff --git a/src/nvidia/src/lib/protobuf/prbenc.c b/src/nvidia/src/lib/protobuf/prbenc.c index 0eaa67601..3f9802b90 100644 --- a/src/nvidia/src/lib/protobuf/prbenc.c +++ b/src/nvidia/src/lib/protobuf/prbenc.c @@ -104,7 +104,7 @@ prbBufLeft(PRB_BUF *buf) /*! * @brief Encodes a variable integer in base-128 format. - * See http://code.google.com/apis/protocolbuffers/docs/encoding.html for more + * See https://code.google.com/apis/protocolbuffers/docs/encoding.html for more * information. * @param [in] buf Memory buffer * @param [in] varint Value to encode @@ -136,7 +136,7 @@ encode_varint(PRB_BUF *buf, NvU64 varint, NvBool countOnly) /** * Decodes a variable integer in base-128 format. - * See http://code.google.com/apis/protocolbuffers/docs/encoding.html for more + * See https://code.google.com/apis/protocolbuffers/docs/encoding.html for more * information. * @param [in] pBuff Buffer to decode * @param [in] len Length of input buffer diff --git a/src/nvidia/src/libraries/containers/btree/btree.c b/src/nvidia/src/libraries/containers/btree/btree.c index 155dee131..6dd9de814 100644 --- a/src/nvidia/src/libraries/containers/btree/btree.c +++ b/src/nvidia/src/libraries/containers/btree/btree.c @@ -25,7 +25,7 @@ /***************************** Balanced Tree *******************************\ * * * A generic library to red black tree -- every operation is O(log(n)) * -* check http://en.wikipedia.org/wiki/Red-black_tree or similar www pages * +* check https://en.wikipedia.org/wiki/Red-black_tree or similar www pages * * * \***************************************************************************/ diff --git a/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c b/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c index d8be920e4..93e4fa726 100644 --- a/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c +++ b/src/nvidia/src/libraries/nvport/crypto/crypto_random_xorshift.c @@ -31,7 +31,7 @@ * @note Xorshift algorithms take either 128bit or 1024bit seeds. The algorithm * author suggests seeding a splitmix64.c with a 64bit value, and using its * output to seed xorshift. - * See http://xorshift.di.unimi.it/ for details. + * See https://prng.di.unimi.it/ for details. * * @warning Xorshift algorithms are NOT CRYPTOGRAPHICALLY SECURE. They generally * perform really well on various randomness tests, but are not suitable for @@ -84,7 +84,7 @@ void portCryptoShutdown() * @brief Initializes a xorshift state from a 64bit seed. Performed using a * splitmix64 PRNG. * - * Adapted from: http://xorshift.di.unimi.it/splitmix64.c + * Adapted from: https://xorshift.di.unimi.it/splitmix64.c */ static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) { @@ -101,7 +101,7 @@ static void _initState(NvU64 seed64, NvU64 state[XORSHIFT_STATE_QWORDS]) /** * @brief Get the next 64bit value using the xorshift128+ algorithm * - * Adapted from: http://xorshift.di.unimi.it/xorshift128plus.c + * Adapted from: https://xorshift.di.unimi.it/xorshift128plus.c */ static NvU64 _xorshift128plus_GetU64(NvU64 state[2]) { diff --git a/utils.mk b/utils.mk index d09807eb2..ec2b51f64 100644 --- a/utils.mk +++ b/utils.mk @@ -107,7 +107,11 @@ CHMOD ?= chmod OBJCOPY ?= objcopy XZ ?= xz WHOAMI ?= whoami -HOSTNAME ?= hostname + +ifndef HOSTNAME + HOSTNAME = $(shell hostname) +endif + NV_AUTO_DEPEND ?= 1 NV_VERBOSE ?= 0 @@ -195,7 +199,7 @@ PCIACCESS_LDFLAGS ?= ############################################################################## # This makefile uses the $(eval) builtin function, which was added in # GNU make 3.80. Check that the current make version recognizes it. -# Idea suggested by: http://www.jgc.org/blog/cookbook-sample.pdf +# Idea suggested by "The GNU Make Book" by John Graham-Cumming. ############################################################################## _eval_available := @@ -524,7 +528,7 @@ define GENERATE_NVIDSTRING # g_nvid_string.c depends on all objects except g_nvid_string.o, and version.mk $(NVIDSTRING): $$(filter-out $$(call BUILD_OBJECT_LIST,$$(NVIDSTRING)), $(3)) $$(VERSION_MK) $(at_if_quiet)$$(MKDIR) $$(dir $$@) - $(at_if_quiet)$$(ECHO) "const char $(1)[] = \"nvidia id: NVIDIA $$(strip $(2)) for $$(TARGET_ARCH) $$(NVIDIA_VERSION) $$(NVIDSTRING_BUILD_TYPE_STRING) (`$$(WHOAMI)`@`$$(HOSTNAME)`) `$$(DATE)`\";" > $$@ + $(at_if_quiet)$$(ECHO) "const char $(1)[] = \"nvidia id: NVIDIA $$(strip $(2)) for $$(TARGET_ARCH) $$(NVIDIA_VERSION) $$(NVIDSTRING_BUILD_TYPE_STRING) (`$$(WHOAMI)`@$$(HOSTNAME)) `$$(DATE)`\";" > $$@ $(at_if_quiet)$$(ECHO) "const char *const p$$(strip $(1)) = $(1) + 11;" >> $$@; endef diff --git a/version.mk b/version.mk index c6189e5ca..fbf7ab0f4 100644 --- a/version.mk +++ b/version.mk @@ -1,4 +1,4 @@ -NVIDIA_VERSION = 515.43.04 +NVIDIA_VERSION = 515.48.07 # This file. VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))