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515.57

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Andy Ritger 2022-06-28 08:00:06 -07:00
parent 965db98552
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34
CHANGELOG.md
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@ -2,6 +2,12 @@
## Release 515 Entries
### [515.57] 2022-06-28
#### Fixed
- Backtick is deprecated, [#273](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/273) by @arch-user-france1
### [515.48.07] 2022-05-31
#### Added
@ -10,20 +16,20 @@
#### Fixed
- Fix various README capitalizations, [#8 by @lx-is](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/8)
- Automatically tag bug report issues, [#15 by @thebeanogamer](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/15)
- Improve conftest.sh Script, [#37 by @Nitepone](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/37)
- Update HTTP link to HTTPS, [#101 by @alcaparra](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/101)
- moved array sanity check to before the array access, [#117 by @RealAstolfo](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/117)
- Fixed some typos, [#122 by @FEDOyt](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/122)
- Fixed capitalization, [#123 by @keroeslux](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/123)
- Fix typos in NVDEC Engine Descriptor, [#126 from @TrickyDmitriy](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/126)
- Extranous apostrohpes in a makefile script [sic], [#14 by @kiroma](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/14)
- HDMI no audio @4K above 60Hz, [#75 by @adolfotregosa](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/75)
- dp_configcaps.cpp:405: array index sanity check in wrong place?, [#110 by @dcb314](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/110)
- NVRM kgspInitRm_IMPL: missing NVDEC0 engine, cannot initialize GSP-RM, [#116 by @kfazz](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/116)
- ERROR: modpost: "backlight_device_register" [...nvidia-modeset.ko] undefined, [#135 by @sndirsch](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/135)
- aarch64 build fails, [#151 by @frezbo](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/151)
- Fix various README capitalizations, [#8](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/8) by @27lx
- Automatically tag bug report issues, [#15](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/15) by @thebeanogamer
- Improve conftest.sh Script, [#37](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/37) by @Nitepone
- Update HTTP link to HTTPS, [#101](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/101) by @alcaparra
- moved array sanity check to before the array access, [#117](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/117) by @RealAstolfo
- Fixed some typos, [#122](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/122) by @FEDOyt
- Fixed capitalization, [#123](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/123) by @keroeslux
- Fix typos in NVDEC Engine Descriptor, [#126](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/126) from @TrickyDmitriy
- Extranous apostrohpes in a makefile script [sic], [#14](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/14) by @kiroma
- HDMI no audio @ 4K above 60Hz, [#75](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/75) by @adolfotregosa
- dp_configcaps.cpp:405: array index sanity check in wrong place?, [#110](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/110) by @dcb314
- NVRM kgspInitRm_IMPL: missing NVDEC0 engine, cannot initialize GSP-RM, [#116](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/116) by @kfazz
- ERROR: modpost: "backlight_device_register" [...nvidia-modeset.ko] undefined, [#135](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/135) by @sndirsch
- aarch64 build fails, [#151](https://github.com/NVIDIA/open-gpu-kernel-modules/issues/151) by @frezbo
### [515.43.04] 2022-05-11

19
README.md
View File

@ -1,23 +1,23 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 515.48.07.
version 515.57.
## How to Build
To build:
make modules -j`nproc`
make modules -j$(nproc)
To install, first uninstall any existing NVIDIA kernel modules. Then,
as root:
make modules_install -j`nproc`
make modules_install -j$(nproc)
Note that the kernel modules built here must be used with gsp.bin
firmware and user-space NVIDIA GPU driver components from a corresponding
515.48.07 driver release. This can be achieved by installing
515.57 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@ -39,7 +39,7 @@ If cross-compiling, set these variables on the make command line:
E.g.,
# compile on x86_64 for aarch64
make modules -j`nproc` \
make modules -j$(nproc) \
TARGET_ARCH=aarch64 \
CC=aarch64-linux-gnu-gcc \
LD=aarch64-linux-gnu-ld \
@ -59,7 +59,7 @@ DEBUG - Set this to "1" to build the kernel modules as debug. By default, the
These variables can be set on the make command line. E.g.,
make modules -j`nproc` NV_VERBOSE=1
make modules -j$(nproc) NV_VERBOSE=1
## Supported Toolchains
@ -167,7 +167,7 @@ for the target kernel.
## Compatible GPUs
The open-gpu-kernel-modules can be used on any Turing or later GPU
(see the table below). However, in the 515.48.07 release,
(see the table below). However, in the 515.57 release,
GeForce and Workstation support is still considered alpha-quality.
To enable use of the open kernel modules on GeForce and Workstation GPUs,
@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
parameter to 1. For more details, see the NVIDIA GPU driver end user
README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/515.48.07/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/515.57/README/kernel_open.html
In the below table, if three IDs are listed, the first is the PCI Device
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@ -501,6 +501,7 @@ Subsystem Device ID.
| Matrox D-Series D2450 | 1F76 102B 2800 |
| Matrox D-Series D2480 | 1F76 102B 2900 |
| NVIDIA GeForce GTX 1650 | 1F82 |
| NVIDIA GeForce GTX 1630 | 1F83 |
| NVIDIA GeForce GTX 1650 | 1F91 |
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 863E |
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 86E7 |
@ -703,8 +704,6 @@ Subsystem Device ID.
| NVIDIA RTX A5500 | 2233 10DE 165A |
| NVIDIA RTX A5500 | 2233 17AA 165A |
| NVIDIA A40 | 2235 10DE 145A |
| NVIDIA A10 | 2236 10DE 1482 |
| NVIDIA A10G | 2237 10DE 152F |
| NVIDIA A10M | 2238 10DE 1677 |
| NVIDIA GeForce RTX 3060 Ti | 2414 |
| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 |

2
kernel-open/Kbuild
View File

@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"515.48.07\"
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"515.57\"
EXTRA_CFLAGS += -Wno-unused-function

39
kernel-open/nvidia-uvm/uvm_gpu_replayable_faults.c
View File

@ -1942,45 +1942,32 @@ static NV_STATUS cancel_faults_precise_va(uvm_gpu_t *gpu,
// Function called when the system has found a global error and needs to
// trigger RC in RM.
// We cancel one entry per uTLB
static void cancel_fault_batch_tlb(uvm_gpu_t *gpu,
uvm_fault_service_batch_context_t *batch_context,
UvmEventFatalReason reason)
{
NvU32 i;
// Fault filtering is not allowed in the TLB-based fault cancel path
UVM_ASSERT(batch_context->num_cached_faults == batch_context->num_coalesced_faults);
for (i = 0; i < batch_context->num_cached_faults; ++i) {
NV_STATUS status;
for (i = 0; i < batch_context->num_coalesced_faults; ++i) {
NV_STATUS status = NV_OK;
uvm_fault_buffer_entry_t *current_entry;
uvm_fault_utlb_info_t *utlb;
uvm_fault_buffer_entry_t *coalesced_entry;
current_entry = &batch_context->fault_cache[i];
utlb = &batch_context->utlbs[current_entry->fault_source.utlb_id];
current_entry = batch_context->ordered_fault_cache[i];
// If this uTLB has been already cancelled, skip it
if (utlb->cancelled)
continue;
// The list iteration below skips the entry used as 'head'.
// Report the 'head' entry explicitly.
uvm_va_space_down_read(current_entry->va_space);
uvm_tools_record_gpu_fatal_fault(gpu->parent->id, current_entry->va_space, current_entry, reason);
record_fatal_fault_helper(gpu, current_entry, reason);
list_for_each_entry(coalesced_entry, &current_entry->merged_instances_list, merged_instances_list)
uvm_tools_record_gpu_fatal_fault(gpu->parent->id, current_entry->va_space, coalesced_entry, reason);
uvm_va_space_up_read(current_entry->va_space);
// Although the global cancellation method can be used here instead of
// targeted, we still use the targeted method since this function is
// only invoked in GPUs without support for VA fault cancellation, for
// which the targeted version is already required in
// cancel_faults_precise_tlb(). To maintain consistency, we use the
// targeted variant in both cases.
status = push_cancel_on_gpu_targeted(gpu,
current_entry->instance_ptr,
current_entry->fault_source.gpc_id,
current_entry->fault_source.client_id,
&batch_context->tracker);
// We need to cancel each instance pointer to correctly handle faults from multiple contexts.
status = push_cancel_on_gpu_global(gpu, current_entry->instance_ptr, &batch_context->tracker);
if (status != NV_OK)
break;
utlb->cancelled = true;
}
}

9
kernel-open/nvidia-uvm/uvm_migrate_pageable.c
View File

@ -899,9 +899,14 @@ static NV_STATUS migrate_pageable(migrate_vma_state_t *state)
// VMAs are validated and migrated one at a time, since migrate_vma works
// on one vma at a time
for (; vma->vm_start <= prev_outer; vma = vma->vm_next) {
for (; vma->vm_start <= prev_outer; vma = find_vma_intersection(mm, prev_outer, outer)) {
unsigned long next_addr = 0;
NV_STATUS status = migrate_pageable_vma(vma, start, outer, state, &next_addr);
NV_STATUS status;
// Callers have already validated the range so the vma should be valid.
UVM_ASSERT(vma);
status = migrate_pageable_vma(vma, start, outer, state, &next_addr);
if (status == NV_WARN_NOTHING_TO_DO) {
NV_STATUS populate_status = NV_OK;
bool touch = uvm_migrate_args->touch;

2
kernel-open/nvidia-uvm/uvm_policy.c
View File

@ -44,7 +44,7 @@ bool uvm_is_valid_vma_range(struct mm_struct *mm, NvU64 start, NvU64 length)
if (vma->vm_end >= end)
return true;
start = vma->vm_end;
vma = vma->vm_next;
vma = find_vma_intersection(mm, start, end);
}
return false;

2
kernel-open/nvidia-uvm/uvm_populate_pageable.c
View File

@ -158,7 +158,7 @@ NV_STATUS uvm_populate_pageable(struct mm_struct *mm,
// VMAs are validated and populated one at a time, since they may have
// different protection flags
// Validation of VM_SPECIAL flags is delegated to get_user_pages
for (; vma->vm_start <= prev_end; vma = vma->vm_next) {
for (; vma && vma->vm_start <= prev_end; vma = find_vma_intersection(mm, prev_end, end)) {
NV_STATUS status = uvm_populate_pageable_vma(vma, start, end - start, min_prot, touch, populate_permissions);
if (status != NV_OK)

3
src/common/displayport/inc/dp_messages.h
View File

@ -116,7 +116,9 @@ namespace DisplayPort
bool isBeingDestroyed;
bool isPaused;
// Properties from regkey
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
List messageReceivers;
List notYetSentDownRequest; // Down Messages yet to be processed
@ -160,6 +162,7 @@ namespace DisplayPort
DP_ASSERT(dpRegkeyDatabase.bInitialized &&
"All regkeys are invalid because dpRegkeyDatabase is not initialized!");
bNoReplyTimerForBusyWaiting = dpRegkeyDatabase.bNoReplyTimerForBusyWaiting;
bDpcdProbingForBusyWaiting = dpRegkeyDatabase.bDpcdProbingForBusyWaiting;
}
MessageManager(DPCDHAL * hal, Timer * timer)

4
src/common/displayport/inc/dp_regkeydatabase.h
View File

@ -72,6 +72,9 @@
#define NV_DP_DSC_OPTIMIZE_LT_BUG_3534707 "DP_DSC_OPTIMIZE_LT_BUG_3534707"
#define NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING "NO_REPLY_TIMER_FOR_BUSY_WAITING"
#define NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING "DP_DPCD_PROBING_FOR_BUSY_WAITING"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@ -106,6 +109,7 @@ struct DP_REGKEY_DATABASE
bool bDscMstEnablePassThrough;
bool bDscOptimizeLTBug3534707;
bool bNoReplyTimerForBusyWaiting;
bool bDpcdProbingForBusyWaiting;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@ -96,7 +96,8 @@ const struct
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_ENABLE_PASS_THROUGH, &dpRegkeyDatabase.bDscMstEnablePassThrough, DP_REG_VAL_BOOL},
{NV_DP_DSC_OPTIMIZE_LT_BUG_3534707, &dpRegkeyDatabase.bDscOptimizeLTBug3534707, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_NO_REPLY_TIMER_FOR_BUSY_WAITING, &dpRegkeyDatabase.bNoReplyTimerForBusyWaiting, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DPCD_PROBING_FOR_BUSY_WAITING, &dpRegkeyDatabase.bDpcdProbingForBusyWaiting, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

15
src/common/displayport/src/dp_messages.cpp
View File

@ -72,6 +72,20 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
startTime = timer->getTimeUs();
do
{
if (bDpcdProbingForBusyWaiting)
{
hal->updateDPCDOffline();
if (hal->isDpcdOffline())
{
DP_LOG(("DP-MM> Device went offline while waiting for reply and so ignoring message %p (ID = %02X, target = %s)",
(Message*)this, ((Message*)this)->requestIdentifier, (((Message*)this)->state.target).toString(sb)));
nakData = completion.nakData;
completion.failed = true;
break;
}
}
hal->notifyIRQ();
if (hal->interruptDownReplyReady())
IRQDownReply();
@ -81,6 +95,7 @@ bool MessageManager::send(MessageManager::Message * message, NakData & nakData)
nakData = completion.nakData;
break;
}
elapsedTime = timer->getTimeUs() - startTime;
if (elapsedTime > (DPCD_MESSAGE_REPLY_TIMEOUT * 1000))

10
src/common/displayport/src/dp_wardatabase.cpp
View File

@ -581,6 +581,16 @@ void Edid::applyEdidWorkArounds(NvU32 warFlag, const DpMonitorDenylistData *pDen
}
break;
// Asus
case 0x6D1E:
if(ProductID == 0x7707)
{
this->WARFlags.bIgnoreDscCap = true;
DP_LOG(("DP-WAR> Panel incorrectly exposing DSC capability. Ignoring it."));
DP_LOG(("DP-WAR> Bug 3543158"));
}
break;
default:
break;
}

20
src/common/inc/nvBldVer.h
View File

@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r516_10
#define NV_BUILD_BRANCH r515_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r516_10
#define NV_PUBLIC_BRANCH r515_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r516_10-205"
#define NV_BUILD_CHANGELIST_NUM (31396299)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r515/r515_00-269"
#define NV_BUILD_CHANGELIST_NUM (31485447)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r515/r516_10-205"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31396299)
#define NV_BUILD_NAME "rel/gpu_drv/r515/r515_00-269"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31485447)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r516_10-10"
#define NV_BUILD_CHANGELIST_NUM (31385161)
#define NV_BUILD_BRANCH_VERSION "r515_00-210"
#define NV_BUILD_CHANGELIST_NUM (31485447)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "516.26"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31385161)
#define NV_BUILD_NAME "516.56"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31485447)
#define NV_BUILD_BRANCH_BASE_VERSION R515
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "515.48.07"
#define NV_VERSION_STRING "515.57"
#else

15
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@ -2223,4 +2223,19 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
NvBool enableRo;
} NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
*
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xbaU)
typedef struct NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS {
// Get Coherent Fb Aperture Size
NV_DECLARE_ALIGNED(NvU64 coherentFbApertureSize, 8);
} NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS;
/* ctrl2080internal_h */

1
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@ -181,6 +181,7 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_NVIDIA, 0x0FAE, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},
{PCI_VENDOR_ID_NVIDIA, 0x0FAF, CS_NVIDIA_T210, "T210", Nvidia_T210_setupFunc},

1
src/nvidia/arch/nvalloc/common/inc/nvdevid.h
View File

@ -641,6 +641,7 @@ enum {
, CS_HYGON_C86
, CS_PHYTIUM_S2500
, CS_MELLANOX_BLUEFIELD2
, CS_INTEL_1B81
, CS_MAX_PCIE
};

7
src/nvidia/generated/g_kernel_rc_nvoc.h
View File

@ -88,6 +88,7 @@ struct KernelRc {
NvBool bRobustChannelsEnabled;
NvBool bBreakOnRc;
NvBool bLogEvents;
struct KernelChannel *pPreviousChannelInError;
NvBool bGpuUuidLoggedOnce;
KernelWatchdog watchdog;
KernelWatchdogPersistent watchdogPersistent;
@ -195,9 +196,7 @@ static inline void krcGetMigAttributionForError(struct KernelRc *pKernelRc, NvU3
#define krcGetMigAttributionForError_HAL(pKernelRc, exceptType, pGpuPartitionId, pComputeInstanceId) krcGetMigAttributionForError(pKernelRc, exceptType, pGpuPartitionId, pComputeInstanceId)
static inline struct KernelChannel *krcGetChannelInError_9e2234(struct KernelRc *pKernelRc) {
return ((void *)0);
}
struct KernelChannel *krcGetChannelInError_FWCLIENT(struct KernelRc *pKernelRc);
#ifdef __nvoc_kernel_rc_h_disabled
static inline struct KernelChannel *krcGetChannelInError(struct KernelRc *pKernelRc) {
@ -205,7 +204,7 @@ static inline struct KernelChannel *krcGetChannelInError(struct KernelRc *pKerne
return NULL;
}
#else //__nvoc_kernel_rc_h_disabled
#define krcGetChannelInError(pKernelRc) krcGetChannelInError_9e2234(pKernelRc)
#define krcGetChannelInError(pKernelRc) krcGetChannelInError_FWCLIENT(pKernelRc)
#endif //__nvoc_kernel_rc_h_disabled
#define krcGetChannelInError_HAL(pKernelRc) krcGetChannelInError(pKernelRc)

7
src/nvidia/generated/g_nv_name_released.h
View File

@ -664,6 +664,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1F76, 0x2800, 0x102b, "Matrox D-Series D2450" },
{ 0x1F76, 0x2900, 0x102b, "Matrox D-Series D2480" },
{ 0x1F82, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650" },
{ 0x1F83, 0x0000, 0x0000, "NVIDIA GeForce GTX 1630" },
{ 0x1F91, 0x0000, 0x0000, "NVIDIA GeForce GTX 1650" },
{ 0x1F91, 0x863e, 0x103c, "NVIDIA GeForce GTX 1650 with Max-Q Design" },
{ 0x1F91, 0x86e7, 0x103c, "NVIDIA GeForce GTX 1650 with Max-Q Design" },
@ -867,8 +868,6 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2233, 0x165a, 0x10de, "NVIDIA RTX A5500" },
{ 0x2233, 0x165a, 0x17aa, "NVIDIA RTX A5500" },
{ 0x2235, 0x145a, 0x10de, "NVIDIA A40" },
{ 0x2236, 0x1482, 0x10de, "NVIDIA A10" },
{ 0x2237, 0x152f, 0x10de, "NVIDIA A10G" },
{ 0x2238, 0x1677, 0x10de, "NVIDIA A10M" },
{ 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
{ 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },
@ -1410,6 +1409,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2235, 0x1686, 0x10DE, "NVIDIA A40-4" },
{ 0x2235, 0x1687, 0x10DE, "NVIDIA A40-6" },
{ 0x2235, 0x1688, 0x10DE, "NVIDIA A40-8" },
{ 0x2235, 0x16e7, 0x10DE, "NVIDIA A40-1" },
{ 0x2236, 0x14b6, 0x10DE, "NVIDIA A10-1B" },
{ 0x2236, 0x14b7, 0x10DE, "NVIDIA A10-2B" },
{ 0x2236, 0x14b8, 0x10DE, "NVIDIA A10-1Q" },
@ -1432,6 +1432,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2236, 0x167e, 0x10DE, "NVIDIA A10-2" },
{ 0x2236, 0x167f, 0x10DE, "NVIDIA A10-3" },
{ 0x2236, 0x1680, 0x10DE, "NVIDIA A10-4" },
{ 0x2236, 0x16e8, 0x10DE, "NVIDIA A10-1" },
{ 0x2237, 0x155a, 0x10DE, "NVIDIA A10G-1" },
{ 0x2237, 0x155b, 0x10DE, "NVIDIA A10G-2" },
{ 0x2237, 0x155c, 0x10DE, "NVIDIA A10G-3" },
{ 0x2237, 0x155d, 0x10DE, "NVIDIA A10G-4" },
@ -1466,6 +1468,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2238, 0x16b7, 0x10DE, "NVIDIA A10M-5C" },
{ 0x2238, 0x16b8, 0x10DE, "NVIDIA A10M-10C" },
{ 0x2238, 0x16b9, 0x10DE, "NVIDIA A10M-20C" },
{ 0x2238, 0x16e6, 0x10DE, "NVIDIA A10M-1" },
{ 0x25B6, 0x159d, 0x10DE, "NVIDIA A16-1B" },
{ 0x25B6, 0x159e, 0x10DE, "NVIDIA A16-2B" },
{ 0x25B6, 0x159f, 0x10DE, "NVIDIA A16-1Q" },

12
src/nvidia/generated/g_rpc-structures.h
View File

@ -278,6 +278,8 @@ typedef rpc_rc_triggered_v17_02 rpc_rc_triggered_v;
typedef struct rpc_os_error_log_v17_00
{
NvU32 exceptType;
NvU32 runlistId;
NvU32 chid;
char errString[0x100];
} rpc_os_error_log_v17_00;
@ -1314,6 +1316,16 @@ static vmiopd_fdesc_t vmiopd_fdesc_t_rpc_os_error_log_v17_00[] = {
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, exceptType),
.name = "exceptType"
},
{
.vtype = vtype_NvU32,
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, runlistId),
.name = "runlistId"
},
{
.vtype = vtype_NvU32,
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, chid),
.name = "chid"
},
{
.vtype = vtype_char_array,
.offset = NV_OFFSETOF(rpc_os_error_log_v17_00, errString),

455
src/nvidia/generated/g_subdevice_nvoc.c
View File

File diff suppressed because it is too large Load Diff

8
src/nvidia/generated/g_subdevice_nvoc.h
View File

@ -528,6 +528,7 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr__)(struct Subdevice *);
NV_STATUS (*__subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr__)(struct Subdevice *, NV2080_CTRL_INTERNAL_NVLINK_GET_SET_NVSWITCH_FABRIC_ADDR_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdInternalGetPcieP2pCaps__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_PCIE_P2P_CAPS_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__)(struct Subdevice *, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *);
NV_STATUS (*__subdeviceCtrlCmdGetAvailableHshubMask__)(struct Subdevice *, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *);
NvBool (*__subdeviceShareCallback__)(struct Subdevice *, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *);
NV_STATUS (*__subdeviceMapTo__)(struct Subdevice *, RS_RES_MAP_TO_PARAMS *);
@ -1008,6 +1009,7 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr(pSubdevice) subdeviceCtrlCmdInternalNvlinkEnableComputePeerAddr_DISPATCH(pSubdevice)
#define subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr(pSubdevice, pParams) subdeviceCtrlCmdInternalNvlinkGetSetNvswitchFabricAddr_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdInternalGetPcieP2pCaps(pSubdevice, pParams) subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdInternalGetCoherentFbApertureSize(pSubdevice, pParams) subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(pSubdevice, pParams)
#define subdeviceCtrlCmdGetAvailableHshubMask(pSubdevice, pParams) subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(pSubdevice, pParams)
#define subdeviceShareCallback(pGpuResource, pInvokingClient, pParentRef, pSharePolicy) subdeviceShareCallback_DISPATCH(pGpuResource, pInvokingClient, pParentRef, pSharePolicy)
#define subdeviceMapTo(pResource, pParams) subdeviceMapTo_DISPATCH(pResource, pParams)
@ -3447,6 +3449,12 @@ static inline NV_STATUS subdeviceCtrlCmdInternalGetPcieP2pCaps_DISPATCH(struct S
return pSubdevice->__subdeviceCtrlCmdInternalGetPcieP2pCaps__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdInternalGetCoherentFbApertureSize_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *pParams);
static inline NV_STATUS subdeviceCtrlCmdInternalGetCoherentFbApertureSize_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS *pParams) {
return pSubdevice->__subdeviceCtrlCmdInternalGetCoherentFbApertureSize__(pSubdevice, pParams);
}
NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_IMPL(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams);
static inline NV_STATUS subdeviceCtrlCmdGetAvailableHshubMask_DISPATCH(struct Subdevice *pSubdevice, NV2080_CTRL_CMD_HSHUB_GET_AVAILABLE_MASK_PARAMS *pParams) {

27
src/nvidia/inc/libraries/containers/list.h
View File

@ -33,6 +33,7 @@ extern "C" {
#include "nvtypes.h"
#include "nvmisc.h"
#include "nvport/nvport.h"
#include "utils/nvassert.h"
/**
* @defgroup NV_CONTAINERS_LIST List
@ -190,29 +191,29 @@ struct IntrusiveList
#define listInsertNew(pList, pNext) \
CONT_CAST_ELEM(pList, \
listInsertNew_IMPL(&(pList)->real, \
CONT_CHECK_ARG(pList, pNext)))
CONT_CHECK_ARG(pList, pNext)), listIsValid_IMPL)
#define listAppendNew(pList) \
CONT_CAST_ELEM(pList, listAppendNew_IMPL(&(pList)->real))
CONT_CAST_ELEM(pList, listAppendNew_IMPL(&(pList)->real), listIsValid_IMPL)
#define listPrependNew(pList) \
CONT_CAST_ELEM(pList, listPrependNew_IMPL(&(pList)->real))
CONT_CAST_ELEM(pList, listPrependNew_IMPL(&(pList)->real), listIsValid_IMPL)
#define listInsertValue(pList, pNext, pValue) \
CONT_CAST_ELEM(pList, \
listInsertValue_IMPL(&(pList)->real, \
CONT_CHECK_ARG(pList, pNext), \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listAppendValue(pList, pValue) \
CONT_CAST_ELEM(pList, \
listAppendValue_IMPL(&(pList)->real, \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listPrependValue(pList, pValue) \
CONT_CAST_ELEM(pList, \
listPrependValue_IMPL(&(pList)->real, \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listInsertExisting(pList, pNext, pValue) \
listInsertExisting_IMPL(&(pList)->real, \
@ -249,30 +250,30 @@ struct IntrusiveList
#define listFindByValue(pList, pValue) \
CONT_CAST_ELEM(pList, \
listFindByValue_IMPL(&(pList)->real, \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listHead(pList) \
CONT_CAST_ELEM(pList, listHead_IMPL(&((pList)->real).base))
CONT_CAST_ELEM(pList, listHead_IMPL(&((pList)->real).base), listIsValid_IMPL)
#define listTail(pList) \
CONT_CAST_ELEM(pList, listTail_IMPL(&((pList)->real).base))
CONT_CAST_ELEM(pList, listTail_IMPL(&((pList)->real).base), listIsValid_IMPL)
#define listNext(pList, pValue) \
CONT_CAST_ELEM(pList, \
listNext_IMPL(&((pList)->real).base, \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listPrev(pList, pValue) \
CONT_CAST_ELEM(pList, \
listPrev_IMPL(&((pList)->real).base, \
CONT_CHECK_ARG(pList, pValue)))
CONT_CHECK_ARG(pList, pValue)), listIsValid_IMPL)
#define listIterAll(pList) \
listIterRange(pList, listHead(pList), listTail(pList))
#define listIterRange(pList, pFirst, pLast) \
CONT_ITER_RANGE(pList, &listIterRange_IMPL, \
CONT_CHECK_ARG(pList, pFirst), CONT_CHECK_ARG(pList, pLast))
CONT_CHECK_ARG(pList, pFirst), CONT_CHECK_ARG(pList, pLast), listIsValid_IMPL)
#define listIterNext(pIt) \
listIterNext_IMPL(&((pIt)->iter))
@ -324,6 +325,8 @@ listNodeToValue(ListBase *pList, ListNode *pNode)
return (NvU8*)pNode - pList->nodeOffset;
}
NvBool listIsValid_IMPL(void *pMap);
#ifdef __cplusplus
}
#endif

18
src/nvidia/inc/libraries/containers/map.h
View File

@ -192,12 +192,12 @@ struct IntrusiveMap
mapKey_IMPL(&((pMap)->real).base, pValue)
#define mapInsertNew(pMap, key) \
CONT_CAST_ELEM(pMap, mapInsertNew_IMPL(&(pMap)->real, key))
CONT_CAST_ELEM(pMap, mapInsertNew_IMPL(&(pMap)->real, key), mapIsValid_IMPL)
#define mapInsertValue(pMap, key, pValue) \
CONT_CAST_ELEM(pMap, \
mapInsertValue_IMPL(&(pMap)->real, key, \
CONT_CHECK_ARG(pMap, pValue)))
CONT_CHECK_ARG(pMap, pValue)), mapIsValid_IMPL)
#define mapInsertExisting(pMap, key, pValue) \
mapInsertExisting_IMPL(&(pMap)->real, key, \
@ -221,32 +221,32 @@ struct IntrusiveMap
contDispatchVoid_STUB())
#define mapFind(pMap, key) \
CONT_CAST_ELEM(pMap, mapFind_IMPL(&((pMap)->real).base, key))
CONT_CAST_ELEM(pMap, mapFind_IMPL(&((pMap)->real).base, key), mapIsValid_IMPL)
#define mapFindGEQ(pMap, keyMin) \
CONT_CAST_ELEM(pMap, \
mapFindGEQ_IMPL(&((pMap)->real).base, keyMin))
mapFindGEQ_IMPL(&((pMap)->real).base, keyMin), mapIsValid_IMPL)
#define mapFindLEQ(pMap, keyMax) \
CONT_CAST_ELEM(pMap, \
mapFindLEQ_IMPL(&((pMap)->real).base, keyMax))
mapFindLEQ_IMPL(&((pMap)->real).base, keyMax), mapIsValid_IMPL)
#define mapNext(pMap, pValue) \
CONT_CAST_ELEM(pMap, \
mapNext_IMPL(&((pMap)->real).base, \
CONT_CHECK_ARG(pMap, pValue)))
CONT_CHECK_ARG(pMap, pValue)), mapIsValid_IMPL)
#define mapPrev(pMap, pValue) \
CONT_CAST_ELEM(pMap, \
mapPrev_IMPL(&((pMap)->real).base, \
CONT_CHECK_ARG(pMap, pValue)))
CONT_CHECK_ARG(pMap, pValue)), mapIsValid_IMPL)
#define mapIterAll(pMap) \
mapIterRange(pMap, mapFindGEQ(pMap, 0), mapFindLEQ(pMap, NV_U64_MAX))
#define mapIterRange(pMap, pFirst, pLast) \
CONT_ITER_RANGE(pMap, &mapIterRange_IMPL, \
CONT_CHECK_ARG(pMap, pFirst), CONT_CHECK_ARG(pMap, pLast))
CONT_CHECK_ARG(pMap, pFirst), CONT_CHECK_ARG(pMap, pLast), mapIsValid_IMPL)
#define mapIterNext(pIt) \
mapIterNext_IMPL(&((pIt)->iter))
@ -293,6 +293,8 @@ mapNodeToValue(MapBase *pMap, MapNode *pNode)
return (NvU8*)pNode - pMap->nodeOffset;
}
NvBool mapIsValid_IMPL(void *pMap);
#ifdef __cplusplus
}
#endif

27
src/nvidia/inc/libraries/containers/multimap.h
View File

@ -157,35 +157,35 @@ struct MultimapBase
#define multimapFindSubmap(pMultimap, submapKey) \
CONT_CAST_ELEM(&(pMultimap)->type.map, \
multimapFindSubmap_IMPL(&(pMultimap)->real.base, submapKey))
multimapFindSubmap_IMPL(&(pMultimap)->real.base, submapKey), multimapIsValid_IMPL)
#define multimapFindSubmapLEQ(pMultimap, submapKey) \
CONT_CAST_ELEM(&(pMultimap)->type.map, \
multimapFindSubmapLEQ_IMPL(&(pMultimap)->real.base, submapKey))
multimapFindSubmapLEQ_IMPL(&(pMultimap)->real.base, submapKey), multimapIsValid_IMPL)
#define multimapFindSubmapGEQ(pMultimap, submapKey) \
CONT_CAST_ELEM(&(pMultimap)->type.map, \
multimapFindSubmapGEQ_IMPL(&(pMultimap)->real.base, submapKey))
multimapFindSubmapGEQ_IMPL(&(pMultimap)->real.base, submapKey), multimapIsValid_IMPL)
#define multimapCountSubmapItems(pMultimap, pSubmap) \
mapCount(pSubmap)
#define multimapInsertItemNew(pMultimap, submapKey, itemKey) \
CONT_CAST_ELEM(pMultimap, \
multimapInsertItemNew_IMPL(&(pMultimap)->real.base, submapKey, itemKey))
multimapInsertItemNew_IMPL(&(pMultimap)->real.base, submapKey, itemKey), multimapIsValid_IMPL)
#define multimapInsertItemValue(pMultimap, submapKey, itemKey, pValue) \
CONT_CAST_ELEM(pMultimap, \
multimapInsertItemValue_IMPL(&(pMultimap)->real.base, \
submapKey, itemKey, pValue))
submapKey, itemKey, pValue), multimapIsValid_IMPL)
#define multimapInsertSubmap(pMultimap, submapKey) \
CONT_CAST_ELEM(&(pMultimap)->type.map, \
multimapInsertSubmap_IMPL(&(pMultimap)->real.base, submapKey))
multimapInsertSubmap_IMPL(&(pMultimap)->real.base, submapKey), multimapIsValid_IMPL)
#define multimapFindItem(pMultimap, submapKey, itemKey) \
CONT_CAST_ELEM(pMultimap, \
multimapFindItem_IMPL(&(pMultimap)->real.base, submapKey, itemKey))
multimapFindItem_IMPL(&(pMultimap)->real.base, submapKey, itemKey), multimapIsValid_IMPL)
#define multimapRemoveItem(pMultimap, pValue) \
multimapRemoveItem_IMPL(&(pMultimap)->real.base, pValue)
@ -198,17 +198,17 @@ struct MultimapBase
#define multimapNextItem(pMultimap, pValue) \
CONT_CAST_ELEM(pMultimap, \
multimapNextItem_IMPL(&(pMultimap)->real.base, pValue))
multimapNextItem_IMPL(&(pMultimap)->real.base, pValue), multimapIsValid_IMPL)
#define multimapPrevItem(pMultimap, pValue) \
CONT_CAST_ELEM(pMultimap, \
multimapPrevItem_IMPL(&(pMultimap)->real.base, pValue))
multimapPrevItem_IMPL(&(pMultimap)->real.base, pValue), multimapIsValid_IMPL)
#define multimapFirstItem(pMultimap) \
CONT_CAST_ELEM(pMultimap, multimapFirstItem_IMPL(&(pMultimap)->real.base))
CONT_CAST_ELEM(pMultimap, multimapFirstItem_IMPL(&(pMultimap)->real.base), multimapIsValid_IMPL)
#define multimapLastItem(pMultimap) \
CONT_CAST_ELEM(pMultimap, multimapLastItem_IMPL(&(pMultimap)->real.base))
CONT_CAST_ELEM(pMultimap, multimapLastItem_IMPL(&(pMultimap)->real.base), multimapIsValid_IMPL)
#define multimapItemIterAll(pMultimap) \
multimapItemIterRange(pMultimap, \
@ -216,7 +216,7 @@ struct MultimapBase
#define multimapItemIterRange(pMultimap, pFirst, pLast) \
CONT_ITER_RANGE(pMultimap, multimapItemIterRange_IMPL, \
CONT_CHECK_ARG(pMultimap, pFirst), CONT_CHECK_ARG(pMultimap, pLast))
CONT_CHECK_ARG(pMultimap, pFirst), CONT_CHECK_ARG(pMultimap, pLast), multimapIsValid_IMPL)
#define multimapSubmapIterItems(pMultimap, pSubmap) \
multimapItemIterRange(pMultimap, \
@ -289,6 +289,9 @@ multimapNodeToValue(MultimapBase *pBase, MultimapNode *pNode)
return (NvU8*)pNode - pBase->multimapNodeOffset;
}
NvBool multimapIsValid_IMPL(void *pMap);
#ifdef __cplusplus
}
#endif

5
src/nvidia/inc/libraries/containers/queue.h
View File

@ -107,7 +107,7 @@ typedef enum
CONT_CHECK_ARG(pQueue, pElements), numElements)
#define queuePeek(pQueue) \
CONT_CAST_ELEM(pQueue, circularQueuePeek_IMPL(&((pQueue)->real)))
CONT_CAST_ELEM(pQueue, circularQueuePeek_IMPL(&((pQueue)->real)), circularQueueIsValid_IMPL)
#define queuePop(pQueue) \
circularQueuePop_IMPL(&((pQueue)->real))
@ -136,6 +136,9 @@ void circularQueuePop_IMPL(Queue *pQueue);
NvBool circularQueuePopAndCopy_IMPL(Queue *pQueue, void *pCopyTo);
NvBool circularQueuePopAndCopyNonManaged_IMPL(Queue *pQueue, QueueContext *pCtx,
void *pCopyTo);
NvBool circularQueueIsValid_IMPL(void *pQueue);
#ifdef __cplusplus
}
#endif

35
src/nvidia/inc/libraries/containers/type_safety.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -103,7 +103,7 @@ typename T::ElemType *CONT_CHECK_ARG(T *pCont, typename T::ElemType *pValue)
}
template <class T>
typename T::ElemType *CONT_CAST_ELEM(T *pCont, void *pValue)
typename T::ElemType *CONT_CAST_ELEM(T *pCont, void *pValue, ...)
{
return (typename T::ElemType *)pValue;
}
@ -114,7 +114,8 @@ typename T::IterType CONT_ITER_RANGE
T *pCont,
It (*pFunc)(typename T::ContType *, void *, void *),
void *pFirst,
void *pLast
void *pLast,
...
)
{
typename T::IterType temp;
@ -128,7 +129,8 @@ typename T::IterType CONT_ITER_RANGE_INDEX
T *pCont,
It (*pFunc)(typename T::ContType *, NvU64, NvU64),
NvU64 first,
NvU64 last
NvU64 last,
...
)
{
typename T::IterType temp;
@ -155,31 +157,42 @@ typename T::IterType CONT_ITER_RANGE_INDEX
//
#if NV_TYPEOF_SUPPORTED
#define CONT_CAST_ELEM(pCont, ret) ((typeof((pCont)->elem))(ret))
#define CONT_CAST_ELEM(pCont, ret, validfunc) ((typeof((pCont)->elem))(ret))
//
// The dummy contId prevents compilers from warning about incompatible
// function casts. This is safe since we know the two return structures
// are identical (modulo alpha-conversion).
//
#define CONT_ITER_RANGE(pCont, pFunc, pFirst, pLast) \
#define CONT_ITER_RANGE(pCont, pFunc, pFirst, pLast, validfunc) \
(((typeof(*(pCont)->iter)(*)(void *, void *, void *))contId(pFunc))( \
pCont, pFirst, pLast))
#define CONT_ITER_RANGE_INDEX(pCont, pFunc, first, last) \
#define CONT_ITER_RANGE_INDEX(pCont, pFunc, first, last, validfunc) \
(((typeof(*(pCont)->iter)(*)(void *, NvU64, NvU64))contId(pFunc))( \
pCont, first, last))
#else
#define CONT_CAST_ELEM(pCont, ret) ((pCont)->vtable->checkRet(ret))
// Actual implementations
#define CONT_CAST_ELEM2(pCont, ret) ((pCont)->vtable->checkRet(ret))
#define CONT_ITER_RANGE(pCont, pFunc, pFirst, pLast) \
#define CONT_ITER_RANGE2(pCont, pFunc, pFirst, pLast) \
((pCont)->vtable->iterRange(&(pCont)->real.base, pFirst, pLast))
#define CONT_ITER_RANGE_RANGE(pCont, pFunc, first, last) \
#define CONT_ITER_RANGE_RANGE2(pCont, pFunc, first, last) \
((pCont)->vtable->iterRangeIndex(&(pCont)->real.base, first, last))
// Calls validfunc() first to initialize vtable
#define CONT_CAST_ELEM(pCont, ret, validfunc) \
(validfunc((pCont)) ? CONT_CAST_ELEM2(pCont, ret) : CONT_CAST_ELEM2(pCont, NULL))
#define CONT_ITER_RANGE(pCont, pFunc, pFirst, pLast, validfunc) \
(validfunc((pCont)) ? CONT_ITER_RANGE2(pCont, pFunc, pFirst, pLast) : CONT_ITER_RANGE2(pCont, NULL, NULL, NULL))
#define CONT_ITER_RANGE_INDEX(pCont, pFunc, first, last, validfunc) \
(validfunc((pCont)) ? CONT_ITER_RANGE_INDEX2(pCont, pFunc, first, last) : CONT_ITER_RANGE_INDEX2(pCont, NULL, 0, 0))
#endif
#endif
@ -223,6 +236,8 @@ typename T::IterType CONT_ITER_RANGE_INDEX
#define CONT_VTABLE_INIT(contType, pCont) \
((pCont)->vtable = &g_##contType##_VTABLE)
#define CONT_VTABLE_VALID(pCont) ((pCont)->vtable != NULL)
#endif
enum CONT_KIND

18
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@ -298,7 +298,25 @@ _kgspRpcOsErrorLog
{
RPC_PARAMS(os_error_log, _v17_00);
KernelRc *pKernelRc = GPU_GET_KERNEL_RC(pGpu);
KernelChannel *pKernelChannel = NULL;
KernelFifo *pKernelFifo = GPU_GET_KERNEL_FIFO(pGpu);
CHID_MGR *pChidMgr;
if (rpc_params->chid != INVALID_CHID)
{
pChidMgr = kfifoGetChidMgr(pGpu, pKernelFifo, rpc_params->runlistId);
if (pChidMgr != NULL)
{
pKernelChannel = kfifoChidMgrGetKernelChannel(pGpu, pKernelFifo,
pChidMgr,
rpc_params->chid);
}
}
pKernelRc->pPreviousChannelInError = pKernelChannel;
nvErrorLog_va(pGpu, rpc_params->exceptType, "%s", rpc_params->errString);
pKernelRc->pPreviousChannelInError = NULL;
}
/*!

11
src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c
View File

@ -592,8 +592,17 @@ kmemsysSetupCoherentCpuLink_IMPL
&pGpu->numaNodeId));
if (pKernelMemorySystem->coherentCpuFbBase != 0)
{
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS params = {0};
NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi,
pGpu->hInternalClient,
pGpu->hInternalSubdevice,
NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE,
&params,
sizeof(NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS)));
pKernelMemorySystem->coherentCpuFbEnd = pKernelMemorySystem->coherentCpuFbBase +
pMemoryManager->Ram.fbUsableMemSize;
params.coherentFbApertureSize;
}
}

10
src/nvidia/src/kernel/gpu/rc/kernel_rc.c
View File

@ -500,3 +500,13 @@ krcCheckBusError_KERNEL
return NV_OK;
}
KernelChannel *
krcGetChannelInError_FWCLIENT
(
KernelRc *pKernelRc
)
{
NV_ASSERT_OR_RETURN(IS_GSP_CLIENT(ENG_GET_GPU(pKernelRc)), NULL);
return pKernelRc->pPreviousChannelInError;
}

15
src/nvidia/src/libraries/containers/list.c
View File

@ -407,3 +407,18 @@ static void _listInsertBase
NV_CHECKED_ONLY(pList->versionNumber++);
NV_CHECKED_ONLY(pNode->pList = pList);
}
NvBool listIsValid_IMPL(void *pList)
{
#if NV_TYPEOF_SUPPORTED
return NV_TRUE;
#else
if (CONT_VTABLE_VALID((ListBase*)pList))
return NV_TRUE;
NV_ASSERT_FAILED("vtable not valid!");
CONT_VTABLE_INIT(ListBase, (ListBase*)pList);
return NV_FALSE;
#endif
}

16
src/nvidia/src/libraries/containers/map.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -896,3 +896,17 @@ static NvBool _mapInsertBase
pMap->count++;
return NV_TRUE;
}
NvBool mapIsValid_IMPL(void *pMap)
{
#if NV_TYPEOF_SUPPORTED
return NV_TRUE;
#else
if (CONT_VTABLE_VALID((MapBase*)pMap))
return NV_TRUE;
NV_ASSERT_FAILED("vtable not valid!");
CONT_VTABLE_INIT(MapBase, (MapBase*)pMap);
return NV_FALSE;
#endif
}

14
src/nvidia/src/libraries/containers/multimap.c
View File

@ -378,3 +378,17 @@ NvBool multimapItemIterNext_IMPL(MultimapIterBase *pIt)
return NV_TRUE;
}
NvBool multimapIsValid_IMPL(void *pMap)
{
#if NV_TYPEOF_SUPPORTED
return NV_TRUE;
#else
if (CONT_VTABLE_VALID((MultimapBase*)pMap))
return NV_TRUE;
NV_ASSERT_FAILED("vtable not valid!");
CONT_VTABLE_INIT(MultimapBase, (MultimapBase*)pMap);
return NV_FALSE;
#endif
}

7
src/nvidia/src/libraries/containers/queue.c
View File

@ -297,3 +297,10 @@ NvBool circularQueuePopAndCopy_IMPL(Queue *pQueue, void *pCopyTo)
return circularQueuePopAndCopyNonManaged_IMPL(pQueue, &ctx, pCopyTo);
}
NvBool circularQueueIsValid_IMPL(void *pQueue)
{
// No vtable for circularQueue
return NV_TRUE;
}

3
src/nvidia/src/libraries/mmu/mmu_walk.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -28,6 +28,7 @@
/*--------------------------------Includes------------------------------------*/
#if defined(SRT_BUILD)
#include "shrdebug.h"
#else
#include "os/os.h"

3
src/nvidia/src/libraries/mmu/mmu_walk_reserve.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -25,6 +25,7 @@
#if defined(SRT_BUILD)
#include "shrdebug.h"
#endif
#include "mmu_walk_private.h"
/* ------------------------ Static Function Prototypes ---------------------- */

2
version.mk
View File

@ -1,4 +1,4 @@
NVIDIA_VERSION = 515.48.07
NVIDIA_VERSION = 515.57
# This file.
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))