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530.41.03

This commit is contained in:
Andy Ritger 2023-03-23 11:00:12 -07:00
parent 4397463e73
commit 6dd092ddb7
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GPG Key ID: 6D466BB75E006CFC
63 changed files with 848 additions and 149 deletions
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6
CHANGELOG.md
View File

@ -2,12 +2,18 @@
## Release 530 Entries
### [530.41.03] 2023-03-23
### [530.30.02] 2023-02-28
#### Fixed
- Add support for resizable BAR on Linux when NVreg_EnableResizableBar=1 module param is set. [#3](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/3) by @sjkelly
#### Added
- Support for power management features like Suspend, Hibernate and Resume.
## Release 525 Entries
### [525.89.02] 2023-02-08

19
README.md
View File

@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 530.30.02.
version 530.41.03.
## How to Build
@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
530.30.02 driver release. This can be achieved by installing
530.41.03 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@ -167,7 +167,7 @@ for the target kernel.
## Compatible GPUs
The open-gpu-kernel-modules can be used on any Turing or later GPU
(see the table below). However, in the 530.30.02 release,
(see the table below). However, in the 530.41.03 release,
GeForce and Workstation support is still considered alpha-quality.
To enable use of the open kernel modules on GeForce and Workstation GPUs,
@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
parameter to 1. For more details, see the NVIDIA GPU driver end user
README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/530.30.02/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/530.41.03/README/kernel_open.html
In the below table, if three IDs are listed, the first is the PCI Device
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@ -720,9 +720,13 @@ Subsystem Device ID.
| NVIDIA A10 | 2236 10DE 1482 |
| NVIDIA A10G | 2237 10DE 152F |
| NVIDIA A10M | 2238 10DE 1677 |
| NVIDIA H800 PCIe | 2322 10DE 17A4 |
| NVIDIA H800 | 2324 10DE 17A6 |
| NVIDIA H800 | 2324 10DE 17A8 |
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C0 |
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C1 |
| NVIDIA H100 PCIe | 2331 10DE 1626 |
| NVIDIA H100 | 2339 10DE 17FC |
| NVIDIA GeForce RTX 3060 Ti | 2414 |
| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 |
| NVIDIA RTX A5500 Laptop GPU | 2438 |
@ -809,11 +813,18 @@ Subsystem Device ID.
| NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 |
| NVIDIA RTX 6000 Ada Generation | 26B1 17AA 16A1 |
| NVIDIA L40 | 26B5 10DE 169D |
| NVIDIA L40 | 26B5 10DE 17DA |
| NVIDIA GeForce RTX 4080 | 2704 |
| NVIDIA GeForce RTX 4090 Laptop GPU | 2717 |
| NVIDIA GeForce RTX 4090 Laptop GPU | 2757 |
| NVIDIA GeForce RTX 4070 Ti | 2782 |
| NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 |
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 1028 16FA |
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA |
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 10DE 16FA |
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA |
| NVIDIA L4 | 27B8 10DE 16CA |
| NVIDIA L4 | 27B8 10DE 16EE |
| NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 |
| NVIDIA GeForce RTX 4070 Laptop GPU | 2820 |
| NVIDIA GeForce RTX 4070 Laptop GPU | 2860 |

2
kernel-open/Kbuild
View File

@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"530.30.02\"
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"530.41.03\"
ifneq ($(SYSSRCHOST1X),)
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

18
kernel-open/common/inc/nv-mm.h
View File

@ -261,4 +261,22 @@ static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
#endif
}
static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
{
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
vm_flags_set(vma, flags);
#else
vma->vm_flags |= flags;
#endif
}
static inline void nv_vm_flags_clear(struct vm_area_struct *vma, vm_flags_t flags)
{
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
vm_flags_clear(vma, flags);
#else
vma->vm_flags &= ~flags;
#endif
}
#endif // __NV_MM_H__

19
kernel-open/conftest.sh
View File

@ -5680,6 +5680,25 @@ compile_test() {
compile_check_conftest "$CODE" "NV_IOMMU_SVA_BIND_DEVICE_HAS_DRVDATA_ARG" "" "types"
;;
vm_area_struct_has_const_vm_flags)
#
# Determine if the 'vm_area_struct' structure has
# const 'vm_flags'.
#
# A union of '__vm_flags' and 'const vm_flags' was added
# by commit bc292ab00f6c ("mm: introduce vma->vm_flags
# wrapper functions") in mm-stable branch (2023-02-09)
# of the akpm/mm maintainer tree.
#
CODE="
#include <linux/mm_types.h>
int conftest_vm_area_struct_has_const_vm_flags(void) {
return offsetof(struct vm_area_struct, __vm_flags);
}"
compile_check_conftest "$CODE" "NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS" "" "types"
;;
# When adding a new conftest entry, please use the correct format for
# specifying the relevant upstream Linux kernel commit.
#

2
kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
View File

@ -201,7 +201,7 @@ static struct sg_table *__nv_drm_gem_nvkms_memory_prime_get_sg_table(
nv_dev,
"Cannot create sg_table for NvKmsKapiMemory 0x%p",
nv_gem->pMemory);
return NULL;
return ERR_PTR(-ENOMEM);
}
sg_table = nv_drm_prime_pages_to_sg(nv_dev->dev,

6
kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
View File

@ -92,9 +92,9 @@ static int __nv_drm_gem_user_memory_mmap(struct nv_drm_gem_object *nv_gem,
return -EINVAL;
}
vma->vm_flags &= ~VM_PFNMAP;
vma->vm_flags &= ~VM_IO;
vma->vm_flags |= VM_MIXEDMAP;
nv_vm_flags_clear(vma, VM_PFNMAP);
nv_vm_flags_clear(vma, VM_IO);
nv_vm_flags_set(vma, VM_MIXEDMAP);
return 0;
}

2
kernel-open/nvidia-drm/nvidia-drm-gem.c
View File

@ -299,7 +299,7 @@ int nv_drm_mmap(struct file *file, struct vm_area_struct *vma)
ret = -EINVAL;
goto done;
}
vma->vm_flags &= ~VM_MAYWRITE;
nv_vm_flags_clear(vma, VM_MAYWRITE);
}
#endif

1
kernel-open/nvidia-drm/nvidia-drm.Kbuild
View File

@ -129,3 +129,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_file_get_master
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_modeset_lock_all_end
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_lookup
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_put
NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags

9
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
View File

@ -86,6 +86,15 @@ module_param_named(config_file, nvkms_conf, charp, 0400);
static atomic_t nvkms_alloc_called_count;
static bool force_api_to_hw_head_identity_mapping = false;
module_param_named(force_api_to_hw_head_identity_mapping,
force_api_to_hw_head_identity_mapping, bool, 0400);
NvBool nvkms_force_api_to_hw_head_identity_mappings(void)
{
return force_api_to_hw_head_identity_mapping;
}
NvBool nvkms_output_rounding_fix(void)
{
return output_rounding_fix;

1
kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
View File

@ -77,6 +77,7 @@ typedef struct {
} read_minval;
} NvKmsSyncPtOpParams;
NvBool nvkms_force_api_to_hw_head_identity_mappings(void);
NvBool nvkms_output_rounding_fix(void);
void nvkms_call_rm (void *ops);

1
kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
View File

@ -103,5 +103,6 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += timespec64
NV_CONFTEST_TYPE_COMPILE_TESTS += mm_has_mmap_lock
NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_vma_added_flags
NV_CONFTEST_TYPE_COMPILE_TESTS += migrate_device_range
NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg

2
kernel-open/nvidia-uvm/uvm.c
View File

@ -696,7 +696,7 @@ static int uvm_mmap(struct file *filp, struct vm_area_struct *vma)
// of removing CPU mappings in the parent on fork()+exec(). Users can call
// madvise(MDV_DOFORK) if the child process requires access to the
// allocation.
vma->vm_flags |= VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTCOPY;
nv_vm_flags_set(vma, VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTCOPY);
vma->vm_ops = &uvm_vm_ops_managed;

12
kernel-open/nvidia/nv-mmap.c
View File

@ -458,7 +458,7 @@ static int nvidia_mmap_numa(
}
// Needed for the linux kernel for mapping compound pages
vma->vm_flags |= VM_MIXEDMAP;
nv_vm_flags_set(vma, VM_MIXEDMAP);
for (i = 0, addr = mmap_context->page_array[0]; i < pages;
addr = mmap_context->page_array[++i], start += PAGE_SIZE)
@ -603,7 +603,7 @@ int nvidia_mmap_helper(
}
up(&nvl->mmap_lock);
vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND;
nv_vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND);
}
else
{
@ -670,15 +670,15 @@ int nvidia_mmap_helper(
NV_PRINT_AT(NV_DBG_MEMINFO, at);
vma->vm_flags |= (VM_IO | VM_LOCKED | VM_RESERVED);
vma->vm_flags |= (VM_DONTEXPAND | VM_DONTDUMP);
nv_vm_flags_set(vma, VM_IO | VM_LOCKED | VM_RESERVED);
nv_vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP);
}
if ((prot & NV_PROTECT_WRITEABLE) == 0)
{
vma->vm_page_prot = NV_PGPROT_READ_ONLY(vma->vm_page_prot);
vma->vm_flags &= ~VM_WRITE;
vma->vm_flags &= ~VM_MAYWRITE;
nv_vm_flags_clear(vma, VM_WRITE);
nv_vm_flags_clear(vma, VM_MAYWRITE);
}
vma->vm_ops = &nv_vm_ops;

24
kernel-open/nvidia/nv.c
View File

@ -165,7 +165,7 @@ NvBool nv_ats_supported = NVCPU_IS_PPC64LE
/* nvos_ functions.. do not take a state device parameter */
static int nvos_count_devices(void);
static nv_alloc_t *nvos_create_alloc(struct device *, int);
static nv_alloc_t *nvos_create_alloc(struct device *, NvU64);
static int nvos_free_alloc(nv_alloc_t *);
/***
@ -280,11 +280,11 @@ void nv_sev_init(
static
nv_alloc_t *nvos_create_alloc(
struct device *dev,
int num_pages
NvU64 num_pages
)
{
nv_alloc_t *at;
unsigned int pt_size;
NvU64 pt_size;
unsigned int i;
NV_KZALLOC(at, sizeof(nv_alloc_t));
@ -296,6 +296,23 @@ nv_alloc_t *nvos_create_alloc(
at->dev = dev;
pt_size = num_pages * sizeof(nvidia_pte_t *);
//
// Check for multiplication overflow and check whether num_pages value can fit in at->num_pages.
//
if ((num_pages != 0) && ((pt_size / num_pages) != sizeof(nvidia_pte_t*)))
{
nv_printf(NV_DBG_ERRORS, "NVRM: Invalid page table allocation - Number of pages exceeds max value.\n");
NV_KFREE(at, sizeof(nv_alloc_t));
return NULL;
}
at->num_pages = num_pages;
if (at->num_pages != num_pages)
{
nv_printf(NV_DBG_ERRORS, "NVRM: Invalid page table allocation - requested size overflows.\n");
NV_KFREE(at, sizeof(nv_alloc_t));
return NULL;
}
if (os_alloc_mem((void **)&at->page_table, pt_size) != NV_OK)
{
@ -305,7 +322,6 @@ nv_alloc_t *nvos_create_alloc(
}
memset(at->page_table, 0, pt_size);
at->num_pages = num_pages;
NV_ATOMIC_SET(at->usage_count, 0);
for (i = 0; i < at->num_pages; i++)

1
kernel-open/nvidia/nvidia.Kbuild
View File

@ -236,6 +236,7 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += remove_memory_has_nid_arg
NV_CONFTEST_TYPE_COMPILE_TESTS += add_memory_driver_managed_has_mhp_flags_arg
NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb
NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma
NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build

4
src/common/displayport/inc/dp_connector.h
View File

@ -215,6 +215,10 @@ namespace DisplayPort
virtual NvBool isDSCSupported() = 0;
virtual NvBool isDSCDecompressionSupported() = 0;
virtual NvBool isDSCPassThroughSupported() = 0;
virtual DscCaps getDscCaps() = 0;
//

1
src/common/displayport/inc/dp_deviceimpl.h
View File

@ -449,6 +449,7 @@ namespace DisplayPort
bool getFECSupport();
NvBool isDSCPassThroughSupported();
NvBool isDSCSupported();
NvBool isDSCDecompressionSupported();
NvBool isDSCPossible();
bool isFECSupported();
bool readAndParseDSCCaps();

4
src/common/displayport/src/dp_connectorimpl.cpp
View File

@ -5546,7 +5546,8 @@ void ConnectorImpl::notifyLongPulse(bool statusConnected)
if (existingDev && existingDev->isFakedMuxDevice() && !bIsMuxOnDgpu)
{
DP_LOG((" NotifyLongPulse ignored as mux is not pointing to dGPU and there is a faked device"));
DP_LOG((" NotifyLongPulse ignored as mux is not pointing to dGPU and there is a faked device. Marking detect complete"));
sink->notifyDetectComplete();
return;
}
@ -6520,6 +6521,7 @@ void ConnectorImpl::createFakeMuxDevice(const NvU8 *buffer, NvU32 bufferSize)
// Initialize DSC state
newDev->dscCaps.bDSCSupported = true;
newDev->dscCaps.bDSCDecompressionSupported = true;
newDev->parseDscCaps(buffer, bufferSize);
dpMemCopy(newDev->rawDscCaps, buffer, DP_MIN(bufferSize, 16));
newDev->bDSCPossible = true;

27
src/common/displayport/src/dp_deviceimpl.cpp
View File

@ -1560,7 +1560,11 @@ NvBool DeviceImpl::getDSCSupport()
{
if (FLD_TEST_DRF(_DPCD14, _DSC_SUPPORT, _DSC_SUPPORT, _YES, byte))
{
dscCaps.bDSCSupported = true;
dscCaps.bDSCDecompressionSupported = true;
}
if (FLD_TEST_DRF(_DPCD20, _DSC_SUPPORT, _PASS_THROUGH_SUPPORT, _YES, byte))
{
dscCaps.bDSCPassThroughSupported = true;
}
}
@ -1569,6 +1573,11 @@ NvBool DeviceImpl::getDSCSupport()
DP_LOG(("DP-DEV> DSC Support AUX READ failed for %s!", address.toString(sb)));
}
if (dscCaps.bDSCDecompressionSupported || dscCaps.bDSCPassThroughSupported)
{
dscCaps.bDSCSupported = true;
}
return dscCaps.bDSCSupported;
}
@ -1687,6 +1696,11 @@ NvBool DeviceImpl::isDSCSupported()
return dscCaps.bDSCSupported;
}
NvBool DeviceImpl::isDSCDecompressionSupported()
{
return dscCaps.bDSCDecompressionSupported;
}
NvBool DeviceImpl::isDSCPassThroughSupported()
{
return dscCaps.bDSCPassThroughSupported;
@ -2027,7 +2041,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
this->devDoingDscDecompression = this;
this->bDSCPossible = true;
}
else if (this->parent->isDSCSupported())
else if (this->parent->isDSCDecompressionSupported())
{
//
// This condition takes care of DSC capable sink devices
@ -2040,12 +2054,15 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
}
else
{
// This condition takes care of branch device capable of DSC.
if (this->isDSCDecompressionSupported())
{
// This condition takes care of branch device capable of DSC decoding.
this->devDoingDscDecompression = this;
this->bDSCPossible = true;
}
}
else if (this->parent && this->parent->isDSCSupported())
}
else if (this->parent && this->parent->isDSCDecompressionSupported())
{
//
// This condition takes care of sink devices not capable of DSC
@ -2058,7 +2075,7 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
}
else
{
if (this->isDSCSupported())
if (this->isDSCDecompressionSupported())
{
this->bDSCPossible = true;
this->devDoingDscDecompression = this;

1
src/common/inc/displayport/displayport.h
View File

@ -240,6 +240,7 @@ typedef enum
typedef struct DscCaps
{
NvBool bDSCSupported;
NvBool bDSCDecompressionSupported;
NvBool bDSCPassThroughSupported;
unsigned versionMajor, versionMinor;
unsigned rcBufferBlockSize;

20
src/common/inc/nvBldVer.h
View File

@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r530_99
#define NV_BUILD_BRANCH r531_37
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r530_99
#define NV_PUBLIC_BRANCH r531_37
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r530/r530_99-89"
#define NV_BUILD_CHANGELIST_NUM (32484765)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r530/r531_37-121"
#define NV_BUILD_CHANGELIST_NUM (32603126)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r530/r530_99-89"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32484765)
#define NV_BUILD_NAME "rel/gpu_drv/r530/r531_37-121"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32603126)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r530_99-8"
#define NV_BUILD_CHANGELIST_NUM (32470325)
#define NV_BUILD_BRANCH_VERSION "r531_37-1"
#define NV_BUILD_CHANGELIST_NUM (32601466)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "531.08"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32470325)
#define NV_BUILD_NAME "531.40"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32601466)
#define NV_BUILD_BRANCH_BASE_VERSION R530
#endif
// End buildmeister python edited section

1
src/common/inc/nvPNPVendorIds.h
View File

@ -448,6 +448,7 @@ static const PNPVendorId PNPVendorIds[] =
{ "SEA", _VENDOR_NAME_ENTRY("Segate") },
{ "SEC", _VENDOR_NAME_ENTRY("Seiko/Epson") },
{ "SEN", _VENDOR_NAME_ENTRY("Sencore") },
{ "SFL", _VENDOR_NAME_ENTRY("Shiftall Inc") },
{ "SGT", _VENDOR_NAME_ENTRY("Stargate Technology/AT&T") },
{ "SGX", _VENDOR_NAME_ENTRY("SGI") },
{ "SHP", _VENDOR_NAME_ENTRY("Sharp") },

2
src/common/inc/nvUnixVersion.h
View File

@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "530.30.02"
#define NV_VERSION_STRING "530.41.03"
#else

8
src/common/modeset/timing/nvt_edid.c
View File

@ -2103,8 +2103,8 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while (pDTD->wDTPixelClock != 0 &&
(NvU8 *)pDTD - pExt < (int)sizeof(EIA861EXTENSION))
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) - 1)))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
{
@ -2351,8 +2351,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// validate DTD blocks
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pExt[((EIA861EXTENSION *)pExt)->offset];
while (pDTD->wDTPixelClock != 0 &&
(NvU8 *)pDTD - pExt < (int)sizeof(EIA861EXTENSION))
while ((pDTD->wDTPixelClock != 0) &&
(((NvU8 *)pDTD - pExt + sizeof(DETAILEDTIMINGDESCRIPTOR)) < ((NvU8)sizeof(EIA861EXTENSION) -1)))
{
if (parseEdidDetailedTimingDescriptor((NvU8 *)pDTD, NULL) != NVT_STATUS_SUCCESS)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD);

13
src/common/modeset/timing/nvt_edidext_861.c
View File

@ -397,7 +397,7 @@ void parse861ExtDetailedTiming(NvU8 *pEdidExt,
// Get all detailed timings in CEA ext block
pDTD = (DETAILEDTIMINGDESCRIPTOR *)&pEdidExt[pEIA861->offset];
while((NvU8 *)pDTD < (pEdidExt + sizeof(EDIDV1STRUC)) && // Check that we're not going beyond this extension block.
while((NvU8 *)pDTD + sizeof(DETAILEDTIMINGDESCRIPTOR) < (pEdidExt + sizeof(EDIDV1STRUC) - 1) &&
pDTD->wDTPixelClock != 0)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
@ -1237,6 +1237,12 @@ NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info)
return NVT_STATUS_ERR;
}
// DTD offset sanity check
if (p[2] >= 1 && p[2] <= 3)
{
return NVT_STATUS_ERR;
}
// don't do anything further if p861info is NULL
if (p861info == NULL)
{
@ -1300,6 +1306,11 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
tag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(p[i]);
payload = NVT_CEA861_GET_SHORT_DESCRIPTOR_SIZE(p[i]);
/*don't allow data colleciton totally size larger than [127 - 5 (tag, revision, offset, describing native video format, checksum)]*/
if ((i + payload > size) || (i + payload > 122))
{
return NVT_STATUS_ERR;
}
// move the pointer to the payload section or extended Tag Code
i++;

13
src/common/nvswitch/kernel/nvswitch.c
View File

@ -3253,6 +3253,18 @@ _nvswitch_ctrl_get_board_part_number
NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p
)
{
if (IS_RTLSIM(device) || IS_EMULATION(device) || IS_FMODEL(device))
{
NVSWITCH_PRINT(device, INFO,
"%s: Skipping retrieval of board part number on FSF\n",
__FUNCTION__);
nvswitch_os_memset(p, 0, sizeof(NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR));
return NVL_SUCCESS;
}
else
{
if (!nvswitch_is_inforom_supported(device))
{
NVSWITCH_PRINT(device, ERROR, "InfoROM is not supported\n");
@ -3260,6 +3272,7 @@ _nvswitch_ctrl_get_board_part_number
}
return device->hal.nvswitch_ctrl_get_board_part_number(device, p);
}
}
static NvlStatus

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@ -136,6 +136,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS {
/*! Ampere PLC bug */
NvBool bDisablePlcForCertainOffsetsBug3046774;
/*! FB override Start KB */
NV_DECLARE_ALIGNED(NvU64 fbOverrideStartKb, 8);
} NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS;
/*!

3
src/nvidia-modeset/include/nvkms-headsurface-priv.h
View File

@ -481,6 +481,7 @@ static inline void HsIncrementNextIndex(
}
static inline void HsChangeSurfaceFlipRefCount(
NVDevEvoPtr pDevEvo,
NVSurfaceEvoPtr pSurfaceEvo,
NvBool increase)
{
@ -488,7 +489,7 @@ static inline void HsChangeSurfaceFlipRefCount(
if (increase) {
nvEvoIncrementSurfaceRefCnts(pSurfaceEvo);
} else {
nvEvoDecrementSurfaceRefCnts(pSurfaceEvo);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo);
}
}
}

2
src/nvidia-modeset/include/nvkms-private.h
View File

@ -68,8 +68,6 @@ NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDev(
struct NvKmsPerOpenDev *pOpenDev);
const NVEvoApiHandlesRec *nvGetSurfaceHandlesFromOpenDevConst(
const struct NvKmsPerOpenDev *pOpenDev);
NVDevEvoPtr nvGetDevEvoFromOpenDev(
const struct NvKmsPerOpenDev *pOpenDev);
void nvKmsServiceNonStallInterrupt(void *dataPtr, NvU32 dataU32);

3
src/nvidia-modeset/include/nvkms-surface.h
View File

@ -47,7 +47,8 @@ void nvEvoIncrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo);
void nvEvoDecrementSurfaceStructRefCnt(NVSurfaceEvoPtr pSurfaceEvo);
void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo);
void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo);
void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo,
NVSurfaceEvoPtr pSurfaceEvo);
NvBool nvEvoSurfaceRefCntsTooLarge(const NVSurfaceEvoRec *pSurfaceEvo);

12
src/nvidia-modeset/include/nvkms-types.h
View File

@ -1880,7 +1880,11 @@ static inline NvU32 nvHardwareHeadToApiHead(const NVDevEvoRec *pDevEvo,
*/
if (head < pDevEvo->numHeads) {
if (!nvkms_force_api_to_hw_head_identity_mappings()) {
return (pDevEvo->numHeads - 1) - head;
} else {
return head;
}
} else {
nvAssert(head == NV_INVALID_HEAD);
return head;
@ -2360,11 +2364,19 @@ typedef struct _NVFrameLockEvo {
NvBool videoModeReadOnly; /* If video mode is read-only */
NvU32 maxMulDivValue; /* Max sync multiply/divide value */
NvBool mulDivSupported; /* Whether this board supports setting a sync
* multiplier/divider; maxMulDivValue is only
* valid if this is true */
/* Current device state */
enum NvKmsFrameLockAttributePolarityValue polarity;
NvU32 syncDelay;
NvU32 syncInterval;
enum NvKmsFrameLockAttributeVideoModeValue videoMode;
NvU8 mulDivValue;
enum NvKmsFrameLockAttributeMulDivModeValue mulDivMode;
NvBool testMode;
} NVFrameLockEvoRec;

8
src/nvidia-modeset/interface/nvkms-api.h
View File

@ -2820,6 +2820,8 @@ enum NvKmsFrameLockAttribute {
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE,
NV_KMS_FRAMELOCK_ATTRIBUTE_SYNC_RATE_4,
NV_KMS_FRAMELOCK_ATTRIBUTE_INCOMING_HOUSE_SYNC_RATE,
NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_VALUE,
NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_POLARITY attribute. */
@ -2857,6 +2859,12 @@ enum NvKmsFrameLockAttributePortStatusValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_PORT_STATUS_OUTPUT = 1,
};
/*! Values for the NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE attribute. */
enum NvKmsFrameLockAttributeMulDivModeValue {
NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY = 0,
NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_DIVIDE = 1,
};
struct NvKmsSetFrameLockAttributeRequest {
NvKmsFrameLockHandle frameLockHandle;
enum NvKmsFrameLockAttribute attribute;

1
src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
View File

@ -77,6 +77,7 @@ typedef struct {
} read_minval;
} NvKmsSyncPtOpParams;
NvBool nvkms_force_api_to_hw_head_identity_mappings(void);
NvBool nvkms_output_rounding_fix(void);
void nvkms_call_rm (void *ops);

2
src/nvidia-modeset/src/nvkms-cursor.c
View File

@ -118,7 +118,7 @@ SetCursorImageOneHead(NVDispEvoPtr pDispEvo,
}
if (pSurfaceEvoOld) {
nvEvoDecrementSurfaceRefCnts(pSurfaceEvoOld);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvoOld);
}
pDevEvo->gpus[sd].headState[head].cursor.pSurfaceEvo = pSurfaceEvoNew;

146
src/nvidia-modeset/src/nvkms-framelock.c
View File

@ -440,6 +440,8 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo,
pFrameLockEvo->testMode = FALSE;
pFrameLockEvo->houseSyncMode =
NV_KMS_FRAMELOCK_ATTRIBUTE_HOUSE_SYNC_MODE_DISABLED;
pFrameLockEvo->mulDivValue = 1;
pFrameLockEvo->mulDivMode = NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY;
/* Query the framelock revision information */
if (nvRmApiControl(nvEvoGlobal.clientHandle,
@ -482,6 +484,9 @@ static NVFrameLockEvoPtr AllocFrameLockEvo(NVDevEvoPtr pDevEvo,
pFrameLockEvo->maxSyncInterval = gsyncGetCapsParams.maxSyncInterval;
pFrameLockEvo->videoModeReadOnly = !!(gsyncGetCapsParams.capFlags &
NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE);
pFrameLockEvo->mulDivSupported = !!(gsyncGetCapsParams.capFlags &
NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC);
pFrameLockEvo->maxMulDivValue = gsyncGetCapsParams.maxMulDivValue;
/* Determine if house sync is selectable on this frame lock device */
if (!FrameLockUseHouseSyncGetSupport(pFrameLockEvo,
@ -865,6 +870,74 @@ static NvBool FrameLockSetSyncDelay(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val)
return TRUE;
}
/*!
* Set the sync multiply/divide value given in val. Returns FALSE if the
* assignment failed. Assigns pFrameLockEvo->mulDivValue upon success.
*/
static NvBool SetFrameLockMulDivVal(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val)
{
NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS
gsyncSetControlParamsParams = { 0 };
NvU32 ret;
if (!pFrameLockEvo->mulDivSupported ||
(val > pFrameLockEvo->maxMulDivValue)) {
return FALSE;
}
gsyncSetControlParamsParams.which =
NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE;
gsyncSetControlParamsParams.syncMulDiv.multiplyDivideValue = val;
gsyncSetControlParamsParams.syncMulDiv.multiplyDivideMode = pFrameLockEvo->mulDivMode;
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
pFrameLockEvo->device,
NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS,
&gsyncSetControlParamsParams,
sizeof(gsyncSetControlParamsParams));
if (ret != NVOS_STATUS_SUCCESS) return FALSE;
pFrameLockEvo->mulDivValue = val;
return TRUE;
}
/*!
* Set the sync multiply/divide mode given in val. Returns FALSE if the
* assignment failed. Assigns pFrameLockEvo->mulDivMode upon success.
*/
static NvBool SetFrameLockMulDivMode(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val)
{
NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS
gsyncSetControlParamsParams = { 0 };
NvU32 ret;
if (!pFrameLockEvo->mulDivSupported ||
((val != NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_MULTIPLY) &&
(val != NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE_DIVIDE))) {
return FALSE;
}
gsyncSetControlParamsParams.which =
NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE;
gsyncSetControlParamsParams.syncMulDiv.multiplyDivideValue = pFrameLockEvo->mulDivValue;
gsyncSetControlParamsParams.syncMulDiv.multiplyDivideMode = val;
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
pFrameLockEvo->device,
NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS,
&gsyncSetControlParamsParams,
sizeof(gsyncSetControlParamsParams));
if (ret != NVOS_STATUS_SUCCESS) return FALSE;
pFrameLockEvo->mulDivMode = val;
return TRUE;
}
/*!
* Set the sync interval to the value given in val. Returns FALSE if
* the assignment failed. Assigns pFrameLockEvo->syncInterval upon
@ -1342,6 +1415,12 @@ static NvBool ResetHardwareOneDisp(NVDispEvoPtr pDispEvo, NvS64 value)
if (!FrameLockSetTestMode(pFrameLockEvo, pFrameLockEvo->testMode)) {
ret = FALSE;
}
if (!SetFrameLockMulDivVal(pFrameLockEvo, pFrameLockEvo->mulDivValue)) {
ret = FALSE;
}
if (!SetFrameLockMulDivMode(pFrameLockEvo, pFrameLockEvo->mulDivMode)) {
ret = FALSE;
}
/* Since (we think) sync is disabled, these should always be disabled */
if (!FrameLockSetWatchdog(pFrameLockEvo, FALSE)) {
@ -1452,6 +1531,61 @@ static NvBool GetFrameLockSyncDelayValidValues(
return TRUE;
}
static NvBool GetFrameLockMulDivVal(const NVFrameLockEvoRec *pFrameLockEvo,
enum NvKmsFrameLockAttribute attribute,
NvS64 *val)
{
if (!pFrameLockEvo->mulDivSupported) {
return FALSE;
}
*val = pFrameLockEvo->mulDivValue;
return TRUE;
}
static NvBool GetFrameLockMulDivValValidValues(
const NVFrameLockEvoRec *pFrameLockEvo,
struct NvKmsAttributeValidValuesCommonReply *pValidValues)
{
nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_RANGE);
if (!pFrameLockEvo->mulDivSupported) {
return FALSE;
}
pValidValues->u.range.min = 1;
pValidValues->u.range.max = pFrameLockEvo->maxMulDivValue;
return TRUE;
}
static NvBool GetFrameLockMulDivModeValidValues(
const NVFrameLockEvoRec *pFrameLockEvo,
struct NvKmsAttributeValidValuesCommonReply *pValidValues)
{
if (!pFrameLockEvo->mulDivSupported) {
return FALSE;
}
nvAssert(pValidValues->type == NV_KMS_ATTRIBUTE_TYPE_INTEGER);
return TRUE;
}
static NvBool GetFrameLockMulDivMode(const NVFrameLockEvoRec *pFrameLockEvo,
enum NvKmsFrameLockAttribute attribute,
NvS64 *val)
{
if (!pFrameLockEvo->mulDivSupported) {
return FALSE;
}
*val = pFrameLockEvo->mulDivMode;
return TRUE;
}
static NvBool SetHouseSyncMode(NVFrameLockEvoPtr pFrameLockEvo, NvS64 val)
{
if ((val < 0) || (val > 31)) {
@ -2085,6 +2219,18 @@ static const struct {
.getValidValues = NULL,
.type = NV_KMS_ATTRIBUTE_TYPE_INTEGER,
},
[NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_VALUE] = {
.set = SetFrameLockMulDivVal,
.get = GetFrameLockMulDivVal,
.getValidValues = GetFrameLockMulDivValValidValues,
.type = NV_KMS_ATTRIBUTE_TYPE_RANGE,
},
[NV_KMS_FRAMELOCK_ATTRIBUTE_MULTIPLY_DIVIDE_MODE] = {
.set = SetFrameLockMulDivMode,
.get = GetFrameLockMulDivMode,
.getValidValues = GetFrameLockMulDivModeValidValues,
.type = NV_KMS_ATTRIBUTE_TYPE_INTEGER,
},
};
NvBool nvSetFrameLockAttributeEvo(

15
src/nvidia-modeset/src/nvkms-headsurface-config.c
View File

@ -1837,16 +1837,21 @@ static void HsConfigInitFlipQueue(
}
static void HsConfigUpdateSurfaceRefCount(
NVDevEvoPtr pDevEvo,
const NVHsChannelConfig *pChannelConfig,
NvBool increase)
{
HsChangeSurfaceFlipRefCount(pChannelConfig->warpMesh.pSurface, increase);
HsChangeSurfaceFlipRefCount(
pDevEvo, pChannelConfig->warpMesh.pSurface, increase);
HsChangeSurfaceFlipRefCount(pChannelConfig->pBlendTexSurface, increase);
HsChangeSurfaceFlipRefCount(
pDevEvo, pChannelConfig->pBlendTexSurface, increase);
HsChangeSurfaceFlipRefCount(pChannelConfig->pOffsetTexSurface, increase);
HsChangeSurfaceFlipRefCount(
pDevEvo, pChannelConfig->pOffsetTexSurface, increase);
HsChangeSurfaceFlipRefCount(pChannelConfig->cursor.pSurfaceEvo, increase);
HsChangeSurfaceFlipRefCount(
pDevEvo, pChannelConfig->cursor.pSurfaceEvo, increase);
}
/*!
@ -2258,6 +2263,7 @@ void nvHsConfigStart(
*/
if (pHsConfigOneHead->pHsChannel != NULL) {
HsConfigUpdateSurfaceRefCount(
pDevEvo,
&pHsConfigOneHead->channelConfig,
TRUE /* increase */);
}
@ -2268,6 +2274,7 @@ void nvHsConfigStart(
*/
if (pDispEvo->pHsChannel[apiHead] != NULL) {
HsConfigUpdateSurfaceRefCount(
pDevEvo,
&pDispEvo->pHsChannel[apiHead]->config,
FALSE /* increase */);
}

6
src/nvidia-modeset/src/nvkms-headsurface-ioctl.c
View File

@ -169,6 +169,8 @@ static void HsIoctlSetCursorImage(
NVHsChannelEvoRec *pHsChannel,
NVSurfaceEvoRec *pSurfaceEvo)
{
NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo;
/*
* Increment the refcnt of the new surface, and
* decrement the refcnt of the old surface.
@ -178,10 +180,10 @@ static void HsIoctlSetCursorImage(
*/
HsChangeSurfaceFlipRefCount(
pSurfaceEvo, TRUE /* increase */);
pDevEvo, pSurfaceEvo, TRUE /* increase */);
HsChangeSurfaceFlipRefCount(
pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */);
pDevEvo, pHsChannel->config.cursor.pSurfaceEvo, FALSE /* increase */);
pHsChannel->config.cursor.pSurfaceEvo = pSurfaceEvo;

31
src/nvidia-modeset/src/nvkms-headsurface.c
View File

@ -549,21 +549,22 @@ static NvBool HsFlipQueueEntryIsReady(
* Update the reference count of all the surfaces described in the pFlipState.
*/
static void HsUpdateFlipQueueEntrySurfaceRefCount(
NVDevEvoPtr pDevEvo,
const NVHsLayerRequestedFlipState *pFlipState,
NvBool increase)
{
HsChangeSurfaceFlipRefCount(
pFlipState->pSurfaceEvo[NVKMS_LEFT], increase);
pDevEvo, pFlipState->pSurfaceEvo[NVKMS_LEFT], increase);
HsChangeSurfaceFlipRefCount(
pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase);
pDevEvo, pFlipState->pSurfaceEvo[NVKMS_RIGHT], increase);
if (!pFlipState->syncObject.usingSyncpt) {
HsChangeSurfaceFlipRefCount(
pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase);
pDevEvo, pFlipState->syncObject.u.semaphores.acquireSurface.pSurfaceEvo, increase);
HsChangeSurfaceFlipRefCount(
pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase);
pDevEvo, pFlipState->syncObject.u.semaphores.releaseSurface.pSurfaceEvo, increase);
}
}
@ -602,7 +603,7 @@ static void HsReleaseFlipQueueEntry(
* HeadSurface no longer needs to read from the surfaces in pFlipState;
* decrement their reference counts.
*/
HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE);
HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE);
}
/*!
@ -684,6 +685,7 @@ void nvHsPushFlipQueueEntry(
const NvU8 layer,
const NVHsLayerRequestedFlipState *pFlipState)
{
NVDevEvoPtr pDevEvo = pHsChannel->pDispEvo->pDevEvo;
NVListRec *pFlipQueue = &pHsChannel->flipQueue[layer].queue;
NVHsChannelFlipQueueEntry *pEntry = nvCalloc(1, sizeof(*pEntry));
@ -700,7 +702,7 @@ void nvHsPushFlipQueueEntry(
/* Increment the ref counts on the surfaces in the flip queue entry. */
HsUpdateFlipQueueEntrySurfaceRefCount(&pEntry->hwState, TRUE);
HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, &pEntry->hwState, TRUE);
/* "Fast forward" through existing flip queue entries that are ready. */
@ -722,7 +724,7 @@ void nvHsPushFlipQueueEntry(
* If this function returns TRUE, it is the caller's responsibility to
* eventually call
*
* HsUpdateFlipQueueEntrySurfaceRefCount(pFlipState, FALSE)
* HsUpdateFlipQueueEntrySurfaceRefCount(pDevEvo, pFlipState, FALSE)
*
* for the returned pFlipState.
*
@ -2097,9 +2099,15 @@ static NvBool HsCanOmitNonSgHsUpdate(NVHsChannelEvoPtr pHsChannel)
* config) still require rendering an updated frame to the backbuffer.
* Thus, we will simply limit this optimization for frames that come
* within one frame time after the last recorded flip.
*
* This doesn't apply with full screen swap group flipping clients, which
* must have one fliplocked hardware flip for each flip IOCTL request,
* and would break if RG interrupt fake flips interfered with the flip
* queue.
*/
if (pHeadSwapGroup &&
pHeadSwapGroup->swapGroupIsFullscreen) {
pHeadSwapGroup->swapGroupIsFullscreen &&
!pHsChannel->swapGroupFlipping) {
NvU64 nowUs = nvkms_get_usec();
NvU64 frameTimeUs = nvEvoFrametimeUsFromTimings(
@ -2243,8 +2251,11 @@ static void HsVBlankCallback(NVDispEvoRec *pDispEvo,
*/
/*
* When fullscreen swapgroup flipping, we don't need to update
* non-swapgroup content at vblank.
* When fullscreen swapgroup flipping, updating
* non-swapgroup content at vblank is unnecessary and
* dangerous, since it results in releasing client
* semaphores before their contents have actually been
* displayed.
*/
if (!pHsChannel->swapGroupFlipping) {
nvHsNextFrame(pHsDevice, pHsChannel,

2
src/nvidia-modeset/src/nvkms-hw-flip.c
View File

@ -1790,7 +1790,7 @@ static void ChangeSurfaceFlipRefCount(
if (increase) {
nvEvoIncrementSurfaceRefCnts(pSurfaceEvo);
} else {
nvEvoDecrementSurfaceRefCnts(pSurfaceEvo);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo);
}
}
}

12
src/nvidia-modeset/src/nvkms-surface.c
View File

@ -958,7 +958,7 @@ void nvEvoFreeClientSurfaces(NVDevEvoPtr pDevEvo,
nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle);
if (isOwner) {
nvEvoDecrementSurfaceRefCnts(pSurfaceEvo);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo);
} else {
nvEvoDecrementSurfaceStructRefCnt(pSurfaceEvo);
}
@ -1003,7 +1003,7 @@ void nvEvoUnregisterSurface(NVDevEvoPtr pDevEvo,
/* Remove the handle from the calling client's namespace. */
nvEvoDestroyApiHandle(pOpenDevSurfaceHandles, surfaceHandle);
nvEvoDecrementSurfaceRefCnts(pSurfaceEvo);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pSurfaceEvo);
}
void nvEvoReleaseSurface(NVDevEvoPtr pDevEvo,
@ -1041,15 +1041,13 @@ void nvEvoIncrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo)
pSurfaceEvo->structRefCnt++;
}
void nvEvoDecrementSurfaceRefCnts(NVSurfaceEvoPtr pSurfaceEvo)
void nvEvoDecrementSurfaceRefCnts(NVDevEvoPtr pDevEvo,
NVSurfaceEvoPtr pSurfaceEvo)
{
nvAssert(pSurfaceEvo->rmRefCnt >= 1);
pSurfaceEvo->rmRefCnt--;
if (pSurfaceEvo->rmRefCnt == 0) {
NVDevEvoPtr pDevEvo =
nvGetDevEvoFromOpenDev(pSurfaceEvo->owner.pOpenDev);
/*
* Don't sync if this surface was registered as not requiring display
* hardware access, to WAR timeouts that result from OGL unregistering
@ -1224,7 +1222,7 @@ void nvEvoUnregisterDeferredRequestFifo(
pDeferredRequestFifo->fifo,
0);
nvEvoDecrementSurfaceRefCnts(pDeferredRequestFifo->pSurfaceEvo);
nvEvoDecrementSurfaceRefCnts(pDevEvo, pDeferredRequestFifo->pSurfaceEvo);
nvFree(pDeferredRequestFifo);
}

7
src/nvidia-modeset/src/nvkms.c
View File

@ -5795,13 +5795,6 @@ NvBool nvSurfaceEvoInAnyOpens(const NVSurfaceEvoRec *pSurfaceEvo)
}
#endif
NVDevEvoPtr nvGetDevEvoFromOpenDev(
const struct NvKmsPerOpenDev *pOpenDev)
{
nvAssert(pOpenDev != NULL);
return pOpenDev->pDevEvo;
}
const struct NvKmsFlipPermissions *nvGetFlipPermissionsFromOpenDev(
const struct NvKmsPerOpenDev *pOpenDev)
{

5
src/nvidia/arch/nvalloc/unix/src/os.c
View File

@ -931,6 +931,11 @@ NV_STATUS osAllocPagesInternal(
if (nv && (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE)))
nv->force_dma32_alloc = NV_TRUE;
if (NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount) > NV_U32_MAX)
{
status = NV_ERR_INVALID_LIMIT;
}
else
{
status = nv_alloc_pages(
NV_GET_NV_STATE(pGpu),

63
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@ -167,12 +167,25 @@ const NvU8 * RmGetGpuUuidRaw(
)
{
NV_STATUS rmStatus;
OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
OBJGPU *pGpu = NULL;
NvU32 gidFlags;
NvBool isApiLockTaken = NV_FALSE;
if (pNv->nv_uuid_cache.valid)
goto done;
return pNv->nv_uuid_cache.uuid;
if (!rmapiLockIsOwner())
{
rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU);
if (rmStatus != NV_OK)
{
return NULL;
}
isApiLockTaken = NV_TRUE;
}
pGpu = NV_GET_NV_PRIV_PGPU(pNv);
//
// PBI is not present in simulation and the loop inside
@ -193,7 +206,7 @@ const NvU8 * RmGetGpuUuidRaw(
rmStatus = gpumgrSetUuid(pNv->gpu_id, pNv->nv_uuid_cache.uuid);
if (rmStatus != NV_OK)
{
return NULL;
goto err;
}
pNv->nv_uuid_cache.valid = NV_TRUE;
@ -209,45 +222,35 @@ const NvU8 * RmGetGpuUuidRaw(
gidFlags = DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_TYPE,_SHA1)
| DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_FORMAT,_BINARY);
if (!rmapiLockIsOwner())
{
rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU);
if (rmStatus != NV_OK)
{
return NULL;
}
isApiLockTaken = NV_TRUE;
}
if (pGpu == NULL)
{
if (isApiLockTaken == NV_TRUE)
{
rmapiLockRelease();
}
return NULL;
}
if (!pGpu)
goto err;
rmStatus = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags);
if (isApiLockTaken == NV_TRUE)
{
rmapiLockRelease();
}
if (rmStatus != NV_OK)
return NULL;
goto err;
if (!pGpu->gpuUuid.isInitialized)
return NULL;
goto err;
// copy the uuid from the OBJGPU uuid cache
os_mem_copy(pNv->nv_uuid_cache.uuid, pGpu->gpuUuid.uuid, GPU_UUID_LEN);
pNv->nv_uuid_cache.valid = NV_TRUE;
done:
if (isApiLockTaken)
{
rmapiLockRelease();
}
return pNv->nv_uuid_cache.uuid;
err:
if (isApiLockTaken)
{
rmapiLockRelease();
}
return NULL;
}
static NV_STATUS RmGpuUuidRawToString(

5
src/nvidia/generated/g_mem_desc_nvoc.h
View File

@ -344,6 +344,9 @@ typedef struct MEMORY_DESCRIPTOR
// Serve as a head node in a list of submemdescs
MEMORY_DESCRIPTOR_LIST *pSubMemDescList;
// Reserved for RM exclusive use
NvBool bRmExclusiveUse;
// If strung in a intrusive linked list
ListNode node;
@ -653,6 +656,8 @@ NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR);
// Temporary function for 64-bit pageSize transition
NvU64 memdescGetPageSize64(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation);
NvBool memdescAcquireRmExclusiveUse(MEMORY_DESCRIPTOR *pMemDesc);
/*!
* @brief Get PTE kind
*

1
src/nvidia/generated/g_mem_mgr_nvoc.h
View File

@ -481,7 +481,6 @@ struct MemoryManager {
NvU32 zbcSurfaces;
NvU64 overrideInitHeapMin;
NvU64 overrideHeapMax;
NvU64 fbOverrideStartKb;
NvU64 rsvdMemorySizeIncrement;
struct OBJFBSR *pFbsr[8];
struct OBJFBSR *pActiveFbsr;

19
src/nvidia/generated/g_nv_name_released.h
View File

@ -884,9 +884,13 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2236, 0x1482, 0x10de, "NVIDIA A10" },
{ 0x2237, 0x152f, 0x10de, "NVIDIA A10G" },
{ 0x2238, 0x1677, 0x10de, "NVIDIA A10M" },
{ 0x2322, 0x17a4, 0x10de, "NVIDIA H800 PCIe" },
{ 0x2324, 0x17a6, 0x10de, "NVIDIA H800" },
{ 0x2324, 0x17a8, 0x10de, "NVIDIA H800" },
{ 0x2330, 0x16c0, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2330, 0x16c1, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
{ 0x2339, 0x17fc, 0x10de, "NVIDIA H100" },
{ 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
{ 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },
{ 0x2438, 0x0000, 0x0000, "NVIDIA RTX A5500 Laptop GPU" },
@ -973,11 +977,18 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x17aa, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B5, 0x169d, 0x10de, "NVIDIA L40" },
{ 0x26B5, 0x17da, 0x10de, "NVIDIA L40" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x10de, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" },
{ 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" },
{ 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
@ -1236,6 +1247,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E37, 0x148a, 0x10DE, "GRID RTX T10-2" },
{ 0x1E37, 0x148b, 0x10DE, "GRID RTX T10-1" },
{ 0x1E37, 0x148c, 0x10DE, "GRID RTX T10-0" },
{ 0x1E37, 0x180d, 0x10DE, "NVIDIA GeForce GTX 1060" },
{ 0x1E37, 0x1820, 0x10DE, "GeForce RTX 2080" },
{ 0x1E78, 0x13f7, 0x10DE, "GRID RTX6000P-1B" },
{ 0x1E78, 0x13f8, 0x10DE, "GRID RTX6000P-2B" },
{ 0x1E78, 0x13f9, 0x10DE, "GRID RTX6000P-1Q" },
@ -1523,6 +1536,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" },
{ 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" },
{ 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" },
{ 0x2237, 0x1810, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x2237, 0x1811, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" },
{ 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" },
{ 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" },
@ -1636,6 +1651,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B5, 0x1791, 0x10DE, "NVIDIA L40-16C" },
{ 0x26B5, 0x1792, 0x10DE, "NVIDIA L40-24C" },
{ 0x26B5, 0x1793, 0x10DE, "NVIDIA L40-48C" },
{ 0x26B5, 0x1818, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x26B5, 0x181a, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x26B8, 0x174e, 0x10DE, "NVIDIA L40G-1B" },
{ 0x26B8, 0x174f, 0x10DE, "NVIDIA L40G-2B" },
{ 0x26B8, 0x1750, 0x10DE, "NVIDIA L40G-1Q" },
@ -1659,6 +1676,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" },
{ 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" },
{ 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" },
{ 0x26B8, 0x181c, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x26B8, 0x181e, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" },
{ 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" },
{ 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" },

7
src/nvidia/generated/g_profiler_v2_nvoc.h
View File

@ -115,6 +115,13 @@ struct ProfilerBase {
void (*__profilerBaseControlSerialization_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *);
NV_STATUS (*__profilerBaseMap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *);
NvBool (*__profilerBaseAccessCallback__)(struct ProfilerBase *, struct RsClient *, void *, RsAccessRight);
NvU32 maxPmaChannels;
NvU32 pmaVchIdx;
NvBool bLegacyHwpm;
struct RsResourceRef **ppBytesAvailable;
struct RsResourceRef **ppStreamBuffers;
struct RsResourceRef *pBoundCntBuf;
struct RsResourceRef *pBoundPmaBuf;
};
#ifndef __NVOC_CLASS_ProfilerBase_TYPEDEF__

5
src/nvidia/generated/g_virt_mem_allocator_nvoc.h
View File

@ -576,6 +576,11 @@ RmPhysAddr dmaPageArrayGetPhysAddr(DMA_PAGE_ARRAY *pPageArray, NvU32 pageIndex);
#define DMA_VA_LIMIT_49B NVBIT(0)
#define DMA_VA_LIMIT_57B NVBIT(1)
#define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9)
//
// Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to
// Internal VA range, so that SLI vaspaces can mirror each other.
//
#define DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS NVBIT(10)
//
// Internal device allocation flags

88
src/nvidia/src/kernel/gpu/disp/disp_common_ctrl_acpi.c
View File

@ -167,6 +167,11 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
{
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXMX_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get display mask from input buffer
// display mask is 4 byte long and available at byte 1
@ -181,27 +186,54 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
// get acpi id
acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask);
outDataSize = sizeof(NvU32);
outStatus = osCallACPI_MXMX(pGpu, acpiId, pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUON:
{
if (inOutDataSize < sizeof(NvU32))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_GPUON(pGpu, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUOFF:
{
if (inOutDataSize < sizeof(NvU32))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_GPUOFF(pGpu, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_GPUSTA:
{
if (inOutDataSize < sizeof(NvU32))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_GPUSTA(pGpu, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get acpi id from input buffer
@ -214,11 +246,17 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_MXDS_DISP_MASK_OFFSET,
sizeof(NvU32));
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_MXDS(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get acpi id from input buffer
@ -231,11 +269,17 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDS_DISP_MASK_OFFSET,
sizeof(NvU32));
outDataSize = sizeof(NvU32);
outStatus = osCallACPI_MXDS(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXDM_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get acpi id from input buffer
@ -249,10 +293,16 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
sizeof(NvU32));
outStatus = osCallACPI_MXDM(pGpu, acpiId, (NvU32*) pInOutData);
outDataSize = sizeof(NvU32);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
// get acpi id from input buffer
portMemCopy(&acpiId,
@ -260,22 +310,34 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_MXID_DISP_MASK_OFFSET,
sizeof(NvU32));
outDataSize = sizeof(NvU32);
outStatus = osCallACPI_MXID(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
portMemCopy(&acpiId,
sizeof(NvU32),
((NvU8*) pInOutData) + NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NBCI_LRST_DISP_MASK_OFFSET,
sizeof(NvU32));
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_LRST(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DDC_EDID_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
portMemCopy(&acpiId,
sizeof(NvU32),
@ -290,6 +352,11 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_NVHG_MXMX_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get acpi id from input buffer
@ -305,11 +372,17 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
// get acpi id
acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask);
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_MXMX(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS:
{
if (inOutDataSize < (NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DOS_DISP_MASK_OFFSET + sizeof(NvU32)))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
//
// get acpi id from input buffer
// acpi id is 4 byte long and available at byte 4
@ -324,20 +397,35 @@ dispcmnCtrlCmdSystemExecuteAcpiMethod_IMPL
// get acpi id
acpiId = pfmFindAcpiId(pPfm, pGpu, displayMask);
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_DOS(pGpu, acpiId, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_ROM:
{
NvU32 *pBuffer = (NvU32*) pInOutData;
if ((inOutDataSize < (2 * sizeof(NvU32))) || (inOutDataSize < pBuffer[1]))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
outDataSize = pBuffer[1];
outStatus = osCallACPI_NVHG_ROM(pGpu, (NvU32*) pInOutData, (NvU32*) pInOutData);
break;
}
case NV0073_CTRL_SYSTEM_EXECUTE_ACPI_METHOD_DCS:
{
if (inOutDataSize < sizeof(NvU32))
{
outStatus = NV_ERR_INVALID_ARGUMENT;
break;
}
// get display mask from input buffer
portMemCopy(&acpiId, sizeof(NvU32), pInOutData, sizeof(NvU32));
outDataSize = sizeof(NvU32);
outStatus = pOS->osCallACPI_NVHG_DCS(pGpu, acpiId, (NvU32*) pInOutData);
break;
}

8
src/nvidia/src/kernel/gpu/gr/kernel_graphics.c
View File

@ -1477,6 +1477,11 @@ kgraphicsMapCtxBuffer_IMPL
NvU32 updateFlags = bIsReadOnly ? (DMA_UPDATE_VASPACE_FLAGS_READ_ONLY |
DMA_UPDATE_VASPACE_FLAGS_SHADER_READ_ONLY) : DMA_UPDATE_VASPACE_FLAGS_NONE;
if (pGVAS->flags & VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS)
{
allocFlags |= DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS;
}
if (kgraphicsIsPerSubcontextContextHeaderSupported(pGpu, pKernelGraphics))
{
status = dmaMapBuffer_HAL(pGpu, GPU_GET_DMA(pGpu), pVAS, pMemDesc, &vaddr,
@ -2153,6 +2158,9 @@ deviceCtrlCmdKGrGetCaps_IMPL
return NV_ERR_NOT_SUPPORTED;
}
NV_CHECK_OR_RETURN(LEVEL_ERROR, pGrCaps != NULL, NV_ERR_INVALID_ARGUMENT);
NV_CHECK_OR_RETURN(LEVEL_ERROR, pParams->capsTblSize == NV0080_CTRL_GR_CAPS_TBL_SIZE, NV_ERR_INVALID_ARGUMENT);
SLI_LOOP_START(SLI_LOOP_FLAGS_BC_ONLY)
{
KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu);

129
src/nvidia/src/kernel/gpu/hwpm/profiler_v2/kern_profiler_v2_ctrl.c
View File

@ -42,6 +42,40 @@ profilerBaseCtrlCmdFreePmaStream_IMPL
portMemSet(&internalParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_FREE_PMA_STREAM_PARAMS));
internalParams.pmaChannelIdx = pParams->pmaChannelIdx;
{
RsResourceRef *pCountRef = NULL;
RsResourceRef *pBufferRef = NULL;
if (pProfiler->maxPmaChannels <= pParams->pmaChannelIdx)
{
goto err;
}
pCountRef = pProfiler->ppBytesAvailable[pParams->pmaChannelIdx];
pProfiler->ppBytesAvailable[pParams->pmaChannelIdx] = NULL;
pBufferRef = pProfiler->ppStreamBuffers[pParams->pmaChannelIdx];
pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = NULL;
if(pProfiler->pBoundCntBuf == pCountRef && pProfiler->pBoundPmaBuf == pBufferRef)
{
Memory *pCntMem = dynamicCast(pCountRef->pResource, Memory);
Memory *pBufMem = dynamicCast(pBufferRef->pResource, Memory);
pProfiler->pBoundCntBuf = NULL;
pProfiler->pBoundPmaBuf = NULL;
pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
}
if (pCountRef != NULL)
{
refRemoveDependant(pCountRef, RES_GET_REF(pProfiler));
}
if (pBufferRef != NULL)
{
refRemoveDependant(pBufferRef, RES_GET_REF(pProfiler));
}
}
err:
return pRmApi->Control(pRmApi,
RES_GET_CLIENT_HANDLE(pProfiler),
@ -61,10 +95,52 @@ profilerBaseCtrlCmdBindPmResources_IMPL
NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler);
NvHandle hObject = RES_GET_HANDLE(pProfiler);
NV_STATUS status = NV_OK;
RsResourceRef *pCntRef = NULL;
RsResourceRef *pBufRef = NULL;
Memory *pCntMem = NULL;
Memory *pBufMem = NULL;
NV_CHECK_OR_GOTO(LEVEL_INFO,
!pProfiler->bLegacyHwpm && pProfiler->maxPmaChannels != 0, physical_control);
if (pProfiler->maxPmaChannels <= pProfiler->pmaVchIdx)
{
return NV_ERR_INVALID_ARGUMENT;
}
pCntRef = pProfiler->ppBytesAvailable[pProfiler->pmaVchIdx];
pBufRef = pProfiler->ppStreamBuffers[pProfiler->pmaVchIdx];
NV_CHECK_OR_GOTO(LEVEL_INFO,
pCntRef != NULL && pBufRef != NULL, physical_control);
pCntMem = dynamicCast(pCntRef->pResource, Memory);
pBufMem = dynamicCast(pBufRef->pResource, Memory);
NV_ASSERT_OR_RETURN(pCntMem != NULL && pBufMem != NULL, NV_ERR_INVALID_STATE);
if (!memdescAcquireRmExclusiveUse(pCntMem->pMemDesc) ||
!memdescAcquireRmExclusiveUse(pBufMem->pMemDesc))
{
pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
return NV_ERR_INVALID_ARGUMENT;
}
pProfiler->pBoundCntBuf = pCntRef;
pProfiler->pBoundPmaBuf = pBufRef;
physical_control:
status = pRmApi->Control(pRmApi, hClient, hObject,
NVB0CC_CTRL_CMD_INTERNAL_BIND_PM_RESOURCES,
NULL, 0);
if (status != NV_OK && pCntMem != NULL && pBufMem != NULL)
{
pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
pProfiler->pBoundCntBuf = NULL;
pProfiler->pBoundPmaBuf = NULL;
}
return status;
}
@ -78,6 +154,31 @@ profilerBaseCtrlCmdUnbindPmResources_IMPL
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler);
NvHandle hObject = RES_GET_HANDLE(pProfiler);
RsResourceRef *pCntRef = NULL;
RsResourceRef *pBufRef = NULL;
pCntRef = pProfiler->pBoundCntBuf;
pBufRef = pProfiler->pBoundPmaBuf;
if (pCntRef != NULL)
{
Memory *pCntMem = dynamicCast(pCntRef->pResource, Memory);
if (pCntMem != NULL)
{
pCntMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
}
pProfiler->pBoundCntBuf = NULL;
}
if (pBufRef != NULL)
{
Memory *pBufMem = dynamicCast(pBufRef->pResource, Memory);
if (pBufMem != NULL)
{
pBufMem->pMemDesc->bRmExclusiveUse = NV_FALSE;
}
pProfiler->pBoundPmaBuf = NULL;
}
return pRmApi->Control(pRmApi, hClient, hObject,
NVB0CC_CTRL_CMD_INTERNAL_UNBIND_PM_RESOURCES,
@ -96,6 +197,7 @@ profilerBaseCtrlCmdReserveHwpmLegacy_IMPL
NvHandle hClient = RES_GET_CLIENT_HANDLE(pProfiler);
NvHandle hObject = RES_GET_HANDLE(pProfiler);
pProfiler->bLegacyHwpm = NV_TRUE;
return pRmApi->Control(pRmApi, hClient, hObject,
NVB0CC_CTRL_CMD_INTERNAL_RESERVE_HWPM_LEGACY,
pParams, sizeof(*pParams));
@ -117,6 +219,7 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL
NvBool bMemPmaBufferRegistered = NV_FALSE;
NvBool bMemPmaBytesAvailableRegistered = NV_FALSE;
NVB0CC_CTRL_INTERNAL_ALLOC_PMA_STREAM_PARAMS internalParams;
RsResourceRef *pMemoryRef = NULL;
//
// REGISTER MEMDESCs TO GSP
// These are no-op with BareMetal/No GSP
@ -150,6 +253,32 @@ profilerBaseCtrlCmdAllocPmaStream_IMPL
&internalParams, sizeof(internalParams)), fail);
pParams->pmaChannelIdx = internalParams.pmaChannelIdx;
if (pProfiler->ppBytesAvailable == NULL)
{
NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS maxPmaParams;
portMemSet(&maxPmaParams, 0, sizeof(NVB0CC_CTRL_INTERNAL_GET_MAX_PMAS_PARAMS));
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,
pRmApi->Control(pRmApi, hClient, hObject,
NVB0CC_CTRL_CMD_INTERNAL_GET_MAX_PMAS,
&maxPmaParams, sizeof(maxPmaParams)), fail);
pProfiler->maxPmaChannels = maxPmaParams.maxPmaChannels;
pProfiler->ppBytesAvailable = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*));
pProfiler->ppStreamBuffers = (RsResourceRef**)portMemAllocNonPaged(maxPmaParams.maxPmaChannels * sizeof(RsResourceRef*));
}
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,
serverutilGetResourceRef(hClient, pParams->hMemPmaBytesAvailable, &pMemoryRef), fail);
pProfiler->ppBytesAvailable[pParams->pmaChannelIdx] = pMemoryRef;
refAddDependant(pMemoryRef, RES_GET_REF(pProfiler));
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,
serverutilGetResourceRef(hClient, pParams->hMemPmaBuffer, &pMemoryRef), fail);
pProfiler->ppStreamBuffers[pParams->pmaChannelIdx] = pMemoryRef;
refAddDependant(pMemoryRef, RES_GET_REF(pProfiler));
// Copy output params to external struct.
pProfiler->pmaVchIdx = pParams->pmaChannelIdx;
pProfiler->bLegacyHwpm = NV_FALSE;
// Copy output params to external struct.
pParams->pmaBufferVA = internalParams.pmaBufferVA;

34
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/virt_mem_allocator_gm107.c
View File

@ -629,13 +629,13 @@ dmaAllocMapping_GM107
NvU64 vaAlign = NV_MAX(pLocals->pageSize, compAlign);
NvU64 vaSize = RM_ALIGN_UP(pLocals->mapLength, vaAlign);
NvU64 pageSizeLockMask = 0;
pGVAS = dynamicCast(pVAS, OBJGVASPACE);
if (FLD_TEST_DRF(OS46, _FLAGS, _PAGE_SIZE, _BOTH, flags))
{
vaAlign = NV_MAX(vaAlign, pLocals->vaspaceBigPageSize);
vaSize = RM_ALIGN_UP(pLocals->mapLength, vaAlign);
}
//
// Third party code path, nvidia_p2p_get_pages, expects on BAR1 VA to be
// always aligned at 64K.
@ -665,6 +665,14 @@ dmaAllocMapping_GM107
goto cleanup;
}
}
if (pGVAS != NULL && gvaspaceIsInternalVaRestricted(pGVAS))
{
if ((pLocals->vaRangeLo >= pGVAS->vaStartInternal && pLocals->vaRangeLo <= pGVAS->vaLimitInternal) ||
(pLocals->vaRangeHi <= pGVAS->vaLimitInternal && pLocals->vaRangeHi >= pGVAS->vaStartInternal))
{
return NV_ERR_INVALID_PARAMETER;
}
}
}
else if (pDma->getProperty(pDma, PDB_PROP_DMA_RESTRICT_VA_RANGE))
{
@ -690,7 +698,6 @@ dmaAllocMapping_GM107
// Clients can pass an allocation flag to the device or VA space constructor
// so that mappings and allocations will fail without an explicit address.
//
pGVAS = dynamicCast(pVAS, OBJGVASPACE);
if (pGVAS != NULL)
{
if ((pGVAS->flags & VASPACE_FLAGS_REQUIRE_FIXED_OFFSET) &&
@ -700,6 +707,18 @@ dmaAllocMapping_GM107
NV_PRINTF(LEVEL_ERROR, "The VA space requires all allocations to specify a fixed address\n");
goto cleanup;
}
//
// Bug 3610538 clients can allocate GPU VA, during mapping for ctx dma.
// But if clients enable RM to map internal buffers in a reserved
// range of VA for unlinked SLI in Linux, we want to tag these
// allocations as "client allocated", so that it comes outside of
// RM internal region.
//
if (gvaspaceIsInternalVaRestricted(pGVAS))
{
allocFlags.bClientAllocation = NV_TRUE;
}
}
status = vaspaceAlloc(pVAS, vaSize, vaAlign, pLocals->vaRangeLo, pLocals->vaRangeHi,
@ -2210,9 +2229,20 @@ dmaMapBuffer_GM107
vaAlign = NV_MAX(vaAlign, temp);
}
// Set this first in case we ignore DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS next
rangeLo = vaspaceGetVaStart(pVAS);
rangeHi = vaspaceGetVaLimit(pVAS);
if (flagsForAlloc & DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS)
{
OBJGVASPACE *pGVAS = dynamicCast(pVAS, OBJGVASPACE);
if (pGVAS)
{
rangeLo = pGVAS->vaStartInternal;
rangeHi = pGVAS->vaLimitInternal;
}
}
// If trying to conserve 32bit address space, map RM buffers at 4GB+
if (pDma->getProperty(pDma, PDB_PROP_DMA_ENFORCE_32BIT_POINTER) &&
(pVASpaceHeap->free > NVBIT64(32)))

5
src/nvidia/src/kernel/gpu/mem_mgr/heap.c
View File

@ -4735,8 +4735,11 @@ NV_STATUS heapResize_IMPL
if (resizeBy < 0) // Shrink the allocation
{
NvS64 newSize;
NV_ASSERT_OR_RETURN(pBlockLast->owner == NVOS32_BLOCK_TYPE_FREE, NV_ERR_NO_MEMORY);
NV_ASSERT_OR_RETURN((pBlockLast->end - pBlockLast->begin + resizeBy > 0), NV_ERR_INVALID_LIMIT);
NV_CHECK_OR_RETURN(LEVEL_ERROR, portSafeAddS64(pBlockLast->end - pBlockLast->begin, resizeBy, &newSize) &&
(newSize > 0), NV_ERR_INVALID_LIMIT);
pBlockLast->end += resizeBy;
}
else // Grow the allocation

23
src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
View File

@ -2317,6 +2317,28 @@ memdescFillPages
}
}
/*!
* @brief Acquire exclusive use for memdesc for RM.
*
* @param[inout] pMemDesc Memory descriptor
*
* @returns Boolean indicating whether we successfully acquired the memdesc for exclusive use
*/
NvBool
memdescAcquireRmExclusiveUse
(
MEMORY_DESCRIPTOR *pMemDesc
)
{
NV_CHECK_OR_RETURN(LEVEL_ERROR, pMemDesc->_pParentDescriptor == NULL &&
!pMemDesc->bRmExclusiveUse &&
pMemDesc->DupCount == 1,
NV_FALSE);
pMemDesc->bRmExclusiveUse = NV_TRUE;
return NV_TRUE;
}
//
// SubMemory per subdevice chart: (MD - Memory Descriptor, SD - subdevice)
//
@ -2451,6 +2473,7 @@ memdescCreateSubMem
pMemDescNew->bUsingSuballocator = pMemDesc->bUsingSuballocator;
pMemDescNew->_pParentDescriptor = pMemDesc;
pMemDesc->childDescriptorCnt++;
pMemDescNew->bRmExclusiveUse = pMemDesc->bRmExclusiveUse;
pMemDescNew->subMemOffset = Offset;

7
src/nvidia/src/kernel/gpu/mem_mgr/mem_mgr.c
View File

@ -2638,6 +2638,8 @@ memmgrPmaRegisterRegions_IMPL
NvU32 blackListCount;
NvU64 base, size;
NV_STATUS status = NV_OK;
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu));
blackListCount = pHeap->blackListAddresses.count;
base = pHeap->base;
@ -2764,9 +2766,9 @@ memmgrPmaRegisterRegions_IMPL
_pmaInitFailed:
portMemFree(pBlacklistPages);
if ((status == NV_OK) && (pMemoryManager->fbOverrideStartKb != 0))
if ((status == NV_OK) && (pMemsysConfig->fbOverrideStartKb != 0))
{
NvU64 allocSize = NV_ALIGN_UP(((NvU64)pMemoryManager->fbOverrideStartKb << 10), PMA_GRANULARITY);
NvU64 allocSize = NV_ALIGN_UP(((NvU64)pMemsysConfig->fbOverrideStartKb << 10), PMA_GRANULARITY);
NvU32 numPages = (NvU32)(allocSize >> PMA_PAGE_SHIFT);
PMA_ALLOCATION_OPTIONS allocOptions = {0};
@ -2785,7 +2787,6 @@ _pmaInitFailed:
portMemFree(pPages);
}
}
if (status != NV_OK)
{
if (memmgrIsPmaInitialized(pMemoryManager))

16
src/nvidia/src/kernel/gpu/mem_mgr/vaspace_api.c
View File

@ -350,6 +350,18 @@ vaspaceapiConstruct_IMPL
}
}
//
// Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to
// Internal VA range. setting internal va range to match what we use for
// windows.
//
if (allocFlags & NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT)
{
vaStartInternal = SPLIT_VAS_SERVER_RM_MANAGED_VA_START;
vaLimitInternal = SPLIT_VAS_SERVER_RM_MANAGED_VA_START +
SPLIT_VAS_SERVER_RM_MANAGED_VA_SIZE - 1;
}
// Finally call the factory
status = vmmCreateVaspace(pVmm, pParams->externalClassId,
pNvVASpaceAllocParams->index,
@ -619,6 +631,10 @@ static NV_STATUS translateAllocFlagsToVASpaceFlags(NvU32 allocFlags, NvU32 *tran
{
flags |= VASPACE_FLAGS_REQUIRE_FIXED_OFFSET;
}
if (allocFlags & NV_VASPACE_ALLOCATION_FLAGS_VA_INTERNAL_LIMIT)
{
flags |= VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS;
}
flags |= VASPACE_FLAGS_ENABLE_VMM;
// Validate the flag combinations

34
src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c
View File

@ -308,13 +308,19 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
}
else
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10)));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10),
(pMemoryManager->Ram.fbOverrideSizeMb << 10))
- pMemsysConfig->fbOverrideStartKb);
break;
}
}
case NV2080_CTRL_FB_INFO_INDEX_RAM_SIZE:
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
if (pMemoryPartitionHeap != NULL)
{
NvU32 heapSizeKb;
@ -336,11 +342,15 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
break;
}
NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbTotalMemSizeMb << 10));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10)));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbTotalMemSizeMb << 10),
(pMemoryManager->Ram.fbOverrideSizeMb << 10))
- pMemsysConfig->fbOverrideStartKb);
break;
}
case NV2080_CTRL_FB_INFO_INDEX_USABLE_RAM_SIZE:
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
if (pMemoryPartitionHeap != NULL)
{
NvU32 heapSizeKb;
@ -362,11 +372,15 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
break;
}
NV_ASSERT(0 == NvU64_HI32(pMemoryManager->Ram.fbUsableMemSize >> 10));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10), (pMemoryManager->Ram.fbOverrideSizeMb << 10)));
data = NvU64_LO32(NV_MIN((pMemoryManager->Ram.fbUsableMemSize >> 10 ),
(pMemoryManager->Ram.fbOverrideSizeMb << 10))
- pMemsysConfig->fbOverrideStartKb);
break;
}
case NV2080_CTRL_FB_INFO_INDEX_HEAP_SIZE:
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
if (bIsPmaEnabled)
{
pmaGetTotalMemory(&pHeap->pmaObject, &bytesTotal);
@ -381,6 +395,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
NV_ASSERT(NvU64_HI32(size >> 10) == 0);
data = NvU64_LO32(size >> 10);
}
data -= pMemsysConfig->fbOverrideStartKb;
break;
}
case NV2080_CTRL_FB_INFO_INDEX_HEAP_START:
@ -397,6 +412,15 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
&largestOffset, &largestFree);
}
data = NvU64_LO32(heapBase >> 10);
}
else
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
if (pMemsysConfig->fbOverrideStartKb != 0)
{
data = NvU64_LO32(pMemsysConfig->fbOverrideStartKb);
NV_ASSERT(((NvU64) data << 10ULL) == pMemsysConfig->fbOverrideStartKb);
}
else
{
@ -408,6 +432,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
data = NvU64_LO32(heapBase >> 10);
NV_ASSERT(((NvU64) data << 10ULL) == heapBase);
}
}
break;
}
case NV2080_CTRL_FB_INFO_INDEX_HEAP_FREE:
@ -487,6 +512,8 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
case NV2080_CTRL_FB_INFO_INDEX_MAPPABLE_HEAP_SIZE:
{
const MEMORY_SYSTEM_STATIC_CONFIG *pMemsysConfig =
kmemsysGetStaticConfig(pGpu, pKernelMemorySystem);
if (bIsPmaEnabled)
{
NvU32 heapSizeKb;
@ -512,6 +539,7 @@ _fbGetFbInfos(OBJGPU *pGpu, NvHandle hClient, NvHandle hObject, NV2080_CTRL_FB_I
if (data > heapSizeKb)
data = heapSizeKb;
}
data -= pMemsysConfig->fbOverrideStartKb;
break;
}
case NV2080_CTRL_FB_INFO_INDEX_BANK_COUNT:

2
src/nvidia/src/kernel/mem_mgr/gpu_vaspace.c
View File

@ -665,6 +665,7 @@ gvaspaceConstruct__IMPL
// By default allocations will be routed within RM internal va range.
pGVAS->bRMInternalRestrictedVaRange = NV_TRUE;
if (pVAS->vasLimit != pGVAS->vaLimitMax)
status = _gvaspaceReserveRange(pGVAS, pVAS->vasLimit + 1, pGVAS->vaLimitMax);
}
else
@ -1178,7 +1179,6 @@ _gvaspaceGpuStateConstruct
if (flags & VASPACE_FLAGS_RESTRICTED_RM_INTERNAL_VALIMITS)
{
NV_ASSERT_OR_RETURN(vaLimitInternal <= vaLimitMax, NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(vaLimitInternal <= vaLimit, NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(vaStartInternal <= vaLimitInternal, NV_ERR_INVALID_ARGUMENT);
NV_ASSERT_OR_RETURN(vaStartInternal >= vaStartMin, NV_ERR_INVALID_ARGUMENT);

3
src/nvidia/src/kernel/mem_mgr/mem_list.c
View File

@ -310,7 +310,8 @@ continue_alloc_object:
pPteArray = memdescGetPteArray(pMemDesc, AT_GPU);
if (!portSafeMulU32(sizeof(NvU64), pAllocParams->pageCount, &result))
if ((pAllocParams->pageCount > pMemDesc->PageCount) ||
!portSafeMulU32(sizeof(NvU64), pAllocParams->pageCount, &result))
{
memdescDestroy(pMemDesc);
return NV_ERR_INVALID_ARGUMENT;

16
src/nvidia/src/kernel/platform/nbsi/nbsi_init.c
View File

@ -1351,7 +1351,12 @@ static NV_STATUS getNbsiObjFromCache
// return the full table size
*pTotalObjSize = tempGlobSize;
rtnObjSizeWithOffset = *pTotalObjSize - rtnObjOffset;
if (!portSafeSubU32(*pTotalObjSize, rtnObjOffset, &rtnObjSizeWithOffset))
{
// Failed argument validation.
status = NV_ERR_INVALID_OFFSET;
}
else
{
if (*pRtnObjSize >= rtnObjSizeWithOffset)
{
@ -2884,7 +2889,7 @@ NV_STATUS getNbsiObjByType
pRtnObjSize,
pTotalObjSize,
pRtnGlobStatus);
if (status == NV_OK)
if (status != NV_ERR_GENERIC)
{
// It's in the cache, it may or may not fit.
return status;
@ -3054,7 +3059,12 @@ NV_STATUS getNbsiObjByType
// return the full table size
*pTotalObjSize = testObjSize;
rtnObjSizeWithOffset = *pTotalObjSize - wantedRtnObjOffset;
if (!portSafeSubU32(*pTotalObjSize, wantedRtnObjOffset, &rtnObjSizeWithOffset))
{
// Failed argument validation.
status = NV_ERR_INVALID_OFFSET;
}
else
{
if (*pRtnObjSize >= rtnObjSizeWithOffset)
{

9
src/nvidia/src/libraries/utils/nvassert.c
View File

@ -62,10 +62,15 @@ static void
_logAssertCount(void)
{
static NvU32 assertCount = 0;
NV00DE_SHARED_DATA *pSharedData = gpushareddataWriteStart(g_pGpu);
NV00DE_SHARED_DATA *pSharedData;
if (g_pGpu == NULL)
{
return;
}
pSharedData = gpushareddataWriteStart(g_pGpu);
pSharedData->gspAssertCount = ++assertCount;
gpushareddataWriteFinish(g_pGpu);
}

2
version.mk
View File

@ -1,4 +1,4 @@
NVIDIA_VERSION = 530.30.02
NVIDIA_VERSION = 530.41.03
# This file.
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))