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560.31.02

This commit is contained in:
Gaurav Juvekar 2024-07-31 11:27:06 -07:00
parent 448d5cc656
commit 315fd96d2d
No known key found for this signature in database
GPG Key ID: 7043410E102D7F5E
40 changed files with 45691 additions and 45544 deletions
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8
README.md
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@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 560.28.03.
version 560.31.02.
## How to Build
@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
560.28.03 driver release. This can be achieved by installing
560.31.02 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@ -185,7 +185,7 @@ table below).
For details on feature support and limitations, see the NVIDIA GPU driver
end user README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/560.28.03/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/560.31.02/README/kernel_open.html
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
Package for more details.
@ -831,10 +831,12 @@ Subsystem Device ID.
| NVIDIA GeForce RTX 2050 | 25AD |
| NVIDIA RTX A1000 | 25B0 1028 1878 |
| NVIDIA RTX A1000 | 25B0 103C 1878 |
| NVIDIA RTX A1000 | 25B0 103C 8D96 |
| NVIDIA RTX A1000 | 25B0 10DE 1878 |
| NVIDIA RTX A1000 | 25B0 17AA 1878 |
| NVIDIA RTX A400 | 25B2 1028 1879 |
| NVIDIA RTX A400 | 25B2 103C 1879 |
| NVIDIA RTX A400 | 25B2 103C 8D95 |
| NVIDIA RTX A400 | 25B2 10DE 1879 |
| NVIDIA RTX A400 | 25B2 17AA 1879 |
| NVIDIA A16 | 25B6 10DE 14A9 |

2
kernel-open/Kbuild
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@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.28.03\"
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"560.31.02\"
ifneq ($(SYSSRCHOST1X),)
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

2
kernel-open/common/inc/nv.h
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@ -1047,7 +1047,7 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, con
NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *);
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);

20
src/common/inc/nvBldVer.h
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@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r560_70
#define NV_BUILD_BRANCH r560_78
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r560_70
#define NV_PUBLIC_BRANCH r560_78
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r560/r560_70-107"
#define NV_BUILD_CHANGELIST_NUM (34587299)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r560/r560_78-120"
#define NV_BUILD_CHANGELIST_NUM (34643855)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r560/r560_70-107"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34587299)
#define NV_BUILD_NAME "rel/gpu_drv/r560/r560_78-120"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643855)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r560_70-2"
#define NV_BUILD_CHANGELIST_NUM (34567210)
#define NV_BUILD_BRANCH_VERSION "r560_78-2"
#define NV_BUILD_CHANGELIST_NUM (34643068)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "560.73"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34567210)
#define NV_BUILD_NAME "560.81"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34643068)
#define NV_BUILD_BRANCH_BASE_VERSION R560
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "560.28.03"
#define NV_VERSION_STRING "560.31.02"
#else

14
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@ -155,24 +155,24 @@ typedef struct NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS {
} NV0000_CTRL_VGPU_DELETE_DEVICE_PARAMS;
/*
* NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS
* NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS
*
* This command informs RM the status vgpu-vfio unregister for a GPU.
* This command informs RM the status of vgpu-vfio GPU operations such as probe and unregister.
*
* returnStatus [IN]
* This parameter provides the status vgpu-vfio unregister operation.
* This parameter provides the status of vgpu-vfio GPU operation.
*
* gpuPciId [IN]
* This parameter provides the gpu id of the GPU
*/
#define NV0000_CTRL_CMD_VGPU_VFIO_UNREGISTER_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_VGPU_VFIO_NOTIFY_RM_STATUS (0xc05) /* finn: Evaluated from "(FINN_NV01_ROOT_VGPU_INTERFACE_ID << 8) | NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS_MESSAGE_ID (0x5U)
#define NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS {
typedef struct NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS {
NvU32 returnStatus;
NvU32 gpuId;
} NV0000_CTRL_VGPU_VFIO_UNREGISTER_STATUS_PARAMS;
} NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS;
/* _ctrl0000vgpu_h_ */

31
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
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@ -3638,18 +3638,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS {
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGCR (0x20803060U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 segment;
NvU32 GPIO_set;
NvU32 GPIO_clear;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP (0x20803061U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID (0x61U)
@ -3739,25 +3727,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS {
NvU8 module_info_ext;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTMP (0x20803067U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID (0x67U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 sensor_index;
NvU8 slot_index;
NvU8 sdme;
NvU8 weme;
NvU8 mtr;
NvU8 mte;
NvU16 temperature_threshold_hi;
NvU8 sdee;
NvU8 tee;
NvU16 temperature_threshold_lo;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID (0x68U)

5
src/common/sdk/nvidia/inc/nvfixedtypes.h
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@ -372,6 +372,11 @@ typedef NvSFXP24_8 NvTemp;
*/
#define NV_TYPES_NVSFXP11_5_TO_NV_TEMP(x) ((NvTemp)(x) << 3)
/*!
* Macro to convert NvTemp to SFXP 11.5.
*/
#define NV_TYPES_NV_TEMP_TO_NVSFXP11_5(x) ((NvSFXP11_5)(x) >> 3)
/*!
* Macro to convert UFXP 5.3 to NvTemp.
*/

2
src/nvidia/arch/nvalloc/unix/include/nv.h
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@ -1047,7 +1047,7 @@ NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, con
NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *);
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);

6
src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
View File

@ -799,7 +799,9 @@ NV_STATUS NV_API_CALL nv_gpu_unbind_event
}
NV_STATUS NV_API_CALL nv_gpu_bind_event(
nvidia_stack_t *sp
nvidia_stack_t *sp,
NvU32 gpuId,
NvBool *isEventNotified
)
{
THREAD_STATE_NODE threadState;
@ -812,7 +814,7 @@ NV_STATUS NV_API_CALL nv_gpu_bind_event(
// LOCK: acquire API lock
if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK)
{
CliAddSystemEvent(NV0000_NOTIFIERS_GPU_BIND_EVENT, 0, NULL);
CliAddSystemEvent(NV0000_NOTIFIERS_GPU_BIND_EVENT, gpuId, isEventNotified);
// UNLOCK: release API lock
rmapiLockRelease();

48
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@ -1519,24 +1519,6 @@ failed:
return status;
}
static void
RmHandleNvpcfEvents(
nv_state_t *pNv
)
{
OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
THREAD_STATE_NODE threadState;
if (RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI) == NULL)
{
return;
}
gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS, NULL, 0, 0, 0);
RmUnixRmApiEpilogue(pNv, &threadState);
}
/*
* ---------------------------------------------------------------------------
*
@ -4276,7 +4258,6 @@ void NV_API_CALL rm_power_source_change_event(
THREAD_STATE_NODE threadState;
void *fp;
nv_state_t *nv;
OBJGPU *pGpu = gpumgrGetGpu(0);
NV_STATUS rmStatus = NV_OK;
NV_ENTER_RM_RUNTIME(sp,fp);
@ -4285,6 +4266,7 @@ void NV_API_CALL rm_power_source_change_event(
// LOCK: acquire API lock
if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK)
{
OBJGPU *pGpu = gpumgrGetGpu(0);
if (pGpu != NULL)
{
nv = NV_GET_NV_STATE(pGpu);
@ -5902,16 +5884,32 @@ void NV_API_CALL rm_acpi_nvpcf_notify(
nvidia_stack_t *sp
)
{
void *fp;
OBJGPU *pGpu = gpumgrGetGpu(0);
void *fp;
THREAD_STATE_NODE threadState;
NV_STATUS rmStatus = NV_OK;
NV_ENTER_RM_RUNTIME(sp,fp);
if (pGpu != NULL)
threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
// LOCK: acquire API lock
if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE,
RM_LOCK_MODULES_EVENT)) == NV_OK)
{
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
RmHandleNvpcfEvents(nv);
OBJGPU *pGpu = gpumgrGetGpu(0);
if (pGpu != NULL)
{
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
if ((rmStatus = os_ref_dynamic_power(nv, NV_DYNAMIC_PM_FINE)) ==
NV_OK)
{
gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS,
NULL, 0, 0, 0);
}
os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE);
}
rmapiLockRelease();
}
threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
NV_EXIT_RM_RUNTIME(sp,fp);
}

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src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GB100.c
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src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GH100.c
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src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GB100.c
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src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GH100.c
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56
src/nvidia/generated/g_client_resource_nvoc.c
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@ -1474,6 +1474,21 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
#endif
},
{ /* [91] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) cliresCtrlCmdVgpuVfioNotifyRMStatus_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
/*flags=*/ 0x4u,
/*accessRight=*/0x0u,
/*methodId=*/ 0xc05u,
/*paramSize=*/ sizeof(NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_RmClientResource.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "cliresCtrlCmdVgpuVfioNotifyRMStatus"
#endif
},
{ /* [92] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1488,7 +1503,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientGetAddrSpaceType"
#endif
},
{ /* [92] */
{ /* [93] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1503,7 +1518,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientGetHandleInfo"
#endif
},
{ /* [93] */
{ /* [94] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1518,7 +1533,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientGetAccessRights"
#endif
},
{ /* [94] */
{ /* [95] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1533,7 +1548,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientSetInheritedSharePolicy"
#endif
},
{ /* [95] */
{ /* [96] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1548,7 +1563,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientGetChildHandle"
#endif
},
{ /* [96] */
{ /* [97] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1563,7 +1578,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientShareObject"
#endif
},
{ /* [97] */
{ /* [98] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1578,7 +1593,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdObjectsAreDuplicates"
#endif
},
{ /* [98] */
{ /* [99] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x109u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1593,7 +1608,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdClientSubscribeToImexChannel"
#endif
},
{ /* [99] */
{ /* [100] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1608,7 +1623,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixFlushUserCache"
#endif
},
{ /* [100] */
{ /* [101] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1623,7 +1638,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixExportObjectToFd"
#endif
},
{ /* [101] */
{ /* [102] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1638,7 +1653,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixImportObjectFromFd"
#endif
},
{ /* [102] */
{ /* [103] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10bu)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1653,7 +1668,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixGetExportObjectInfo"
#endif
},
{ /* [103] */
{ /* [104] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1668,7 +1683,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixCreateExportObjectFd"
#endif
},
{ /* [104] */
{ /* [105] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1683,7 +1698,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
/*func=*/ "cliresCtrlCmdOsUnixExportObjectsToFd"
#endif
},
{ /* [105] */
{ /* [106] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -1824,7 +1839,7 @@ static NV_STATUS __nvoc_up_thunk_Notifier_cliresGetOrAllocNotifShare(struct RmCl
const struct NVOC_EXPORT_INFO __nvoc_export_info_RmClientResource =
{
/*numEntries=*/ 106,
/*numEntries=*/ 107,
/*pExportEntries=*/ __nvoc_exported_method_def_RmClientResource
};
@ -2372,6 +2387,11 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) {
pThis->__cliresCtrlCmdVgpuSetVgpuVersion__ = &cliresCtrlCmdVgpuSetVgpuVersion_IMPL;
#endif
// cliresCtrlCmdVgpuVfioNotifyRMStatus -- exported (id=0xc05)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
pThis->__cliresCtrlCmdVgpuVfioNotifyRMStatus__ = &cliresCtrlCmdVgpuVfioNotifyRMStatus_IMPL;
#endif
// cliresCtrlCmdSystemNVPCFGetPowerModeInfo -- exported (id=0x13b)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
pThis->__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__ = &cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL;
@ -2478,13 +2498,13 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) {
// cliresGetOrAllocNotifShare -- virtual inherited (notify) base (notify)
pThis->__cliresGetOrAllocNotifShare__ = &__nvoc_up_thunk_Notifier_cliresGetOrAllocNotifShare;
} // End __nvoc_init_funcTable_RmClientResource_1 with approximately 133 basic block(s).
} // End __nvoc_init_funcTable_RmClientResource_1 with approximately 134 basic block(s).
// Initialize vtable(s) for 129 virtual method(s).
// Initialize vtable(s) for 130 virtual method(s).
void __nvoc_init_funcTable_RmClientResource(RmClientResource *pThis) {
// Initialize vtable(s) with 129 per-object function pointer(s).
// Initialize vtable(s) with 130 per-object function pointer(s).
__nvoc_init_funcTable_RmClientResource_1(pThis);
}

11
src/nvidia/generated/g_client_resource_nvoc.h
View File

@ -95,7 +95,7 @@ struct RmClientResource {
struct Notifier *__nvoc_pbase_Notifier; // notify super
struct RmClientResource *__nvoc_pbase_RmClientResource; // clires
// Vtable with 129 per-object function pointers
// Vtable with 130 per-object function pointers
NvBool (*__cliresAccessCallback__)(struct RmClientResource * /*this*/, struct RsClient *, void *, RsAccessRight); // virtual override (res) base (clientres)
NvBool (*__cliresShareCallback__)(struct RmClientResource * /*this*/, struct RsClient *, struct RsResourceRef *, RS_SHARE_POLICY *); // virtual override (res) base (clientres)
NV_STATUS (*__cliresControl_Prologue__)(struct RmClientResource * /*this*/, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *); // virtual override (res) base (clientres)
@ -196,6 +196,7 @@ struct RmClientResource {
NV_STATUS (*__cliresCtrlCmdSyncGpuBoostGroupInfo__)(struct RmClientResource * /*this*/, NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS *); // exported (id=0xa04)
NV_STATUS (*__cliresCtrlCmdVgpuGetVgpuVersion__)(struct RmClientResource * /*this*/, NV0000_CTRL_VGPU_GET_VGPU_VERSION_PARAMS *); // exported (id=0x137)
NV_STATUS (*__cliresCtrlCmdVgpuSetVgpuVersion__)(struct RmClientResource * /*this*/, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *); // exported (id=0x138)
NV_STATUS (*__cliresCtrlCmdVgpuVfioNotifyRMStatus__)(struct RmClientResource * /*this*/, NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS *); // exported (id=0xc05)
NV_STATUS (*__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__)(struct RmClientResource * /*this*/, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *); // exported (id=0x13b)
NV_STATUS (*__cliresCtrlCmdSystemSyncExternalFabricMgmt__)(struct RmClientResource * /*this*/, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *); // exported (id=0x13c)
NV_STATUS (*__cliresCtrlCmdSystemPfmreqhndlrCtrl__)(struct RmClientResource * /*this*/, NV0000_CTRL_SYSTEM_PFM_REQ_HNDLR_CTRL_PARAMS *); // exported (id=0x142)
@ -457,6 +458,8 @@ NV_STATUS __nvoc_objCreate_RmClientResource(RmClientResource**, Dynamic*, NvU32,
#define cliresCtrlCmdVgpuGetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuGetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo)
#define cliresCtrlCmdVgpuSetVgpuVersion_FNPTR(pRmCliRes) pRmCliRes->__cliresCtrlCmdVgpuSetVgpuVersion__
#define cliresCtrlCmdVgpuSetVgpuVersion(pRmCliRes, vgpuVersionInfo) cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(pRmCliRes, vgpuVersionInfo)
#define cliresCtrlCmdVgpuVfioNotifyRMStatus_FNPTR(pRmCliRes) pRmCliRes->__cliresCtrlCmdVgpuVfioNotifyRMStatus__
#define cliresCtrlCmdVgpuVfioNotifyRMStatus(pRmCliRes, pVgpuDeleteParams) cliresCtrlCmdVgpuVfioNotifyRMStatus_DISPATCH(pRmCliRes, pVgpuDeleteParams)
#define cliresCtrlCmdSystemNVPCFGetPowerModeInfo_FNPTR(pRmCliRes) pRmCliRes->__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__
#define cliresCtrlCmdSystemNVPCFGetPowerModeInfo(pRmCliRes, pParams) cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(pRmCliRes, pParams)
#define cliresCtrlCmdSystemSyncExternalFabricMgmt_FNPTR(pRmCliRes) pRmCliRes->__cliresCtrlCmdSystemSyncExternalFabricMgmt__
@ -917,6 +920,10 @@ static inline NV_STATUS cliresCtrlCmdVgpuSetVgpuVersion_DISPATCH(struct RmClient
return pRmCliRes->__cliresCtrlCmdVgpuSetVgpuVersion__(pRmCliRes, vgpuVersionInfo);
}
static inline NV_STATUS cliresCtrlCmdVgpuVfioNotifyRMStatus_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS *pVgpuDeleteParams) {
return pRmCliRes->__cliresCtrlCmdVgpuVfioNotifyRMStatus__(pRmCliRes, pVgpuDeleteParams);
}
static inline NV_STATUS cliresCtrlCmdSystemNVPCFGetPowerModeInfo_DISPATCH(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams) {
return pRmCliRes->__cliresCtrlCmdSystemNVPCFGetPowerModeInfo__(pRmCliRes, pParams);
}
@ -1233,6 +1240,8 @@ NV_STATUS cliresCtrlCmdVgpuGetVgpuVersion_IMPL(struct RmClientResource *pRmCliRe
NV_STATUS cliresCtrlCmdVgpuSetVgpuVersion_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_SET_VGPU_VERSION_PARAMS *vgpuVersionInfo);
NV_STATUS cliresCtrlCmdVgpuVfioNotifyRMStatus_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS *pVgpuDeleteParams);
NV_STATUS cliresCtrlCmdSystemNVPCFGetPowerModeInfo_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS *pParams);
NV_STATUS cliresCtrlCmdSystemSyncExternalFabricMgmt_IMPL(struct RmClientResource *pRmCliRes, NV0000_CTRL_CMD_SYSTEM_SYNC_EXTERNAL_FABRIC_MGMT_PARAMS *pExtFabricMgmtParams);

30
src/nvidia/generated/g_gpu_nvoc.c
View File

@ -662,15 +662,19 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_GM107;
}
// gpuReadVgpuConfigReg -- halified (2 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd0000000UL) )) /* ChipHal: GH100 | GB100 | GB102 */
// gpuReadPassThruConfigReg -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100;
pThis->__gpuReadPassThruConfigReg__ = &gpuReadPassThruConfigReg_GH100;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
{
pThis->__gpuReadPassThruConfigReg__ = &gpuReadPassThruConfigReg_GB100;
}
// default
else
{
pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7;
pThis->__gpuReadPassThruConfigReg__ = &gpuReadPassThruConfigReg_46f6a7;
}
// gpuGetIdInfo -- halified (3 hals) body
@ -1118,17 +1122,21 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
pThis->__gpuIsSliCapableWithoutDisplay__ = &gpuIsSliCapableWithoutDisplay_491d52;
}
// gpuIsCCEnabledInHw -- halified (3 hals) body
// gpuIsCCEnabledInHw -- halified (4 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_491d52;
}
else
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd0000000UL) )) /* ChipHal: GH100 | GB100 | GB102 */
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GH100;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
{
pThis->__gpuIsCCEnabledInHw__ = &gpuIsCCEnabledInHw_GB100;
}
// default
else
{
@ -1136,17 +1144,21 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
}
}
// gpuIsDevModeEnabledInHw -- halified (3 hals) body
// gpuIsDevModeEnabledInHw -- halified (4 hals) body
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_491d52;
}
else
{
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xd0000000UL) )) /* ChipHal: GH100 | GB100 | GB102 */
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GH100;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
{
pThis->__gpuIsDevModeEnabledInHw__ = &gpuIsDevModeEnabledInHw_GB100;
}
// default
else
{
@ -1227,7 +1239,7 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
{
pThis->__gpuGetIsCmpSku__ = &gpuGetIsCmpSku_ceaee8;
}
} // End __nvoc_init_funcTable_OBJGPU_1 with approximately 140 basic block(s).
} // End __nvoc_init_funcTable_OBJGPU_1 with approximately 143 basic block(s).
// Initialize vtable(s) for 56 virtual method(s).

26
src/nvidia/generated/g_gpu_nvoc.h
View File

@ -985,7 +985,7 @@ struct OBJGPU {
NV_STATUS (*__gpuReadFunctionConfigReg__)(struct OBJGPU * /*this*/, NvU32, NvU32, NvU32 *); // halified (2 hals) body
NV_STATUS (*__gpuWriteFunctionConfigReg__)(struct OBJGPU * /*this*/, NvU32, NvU32, NvU32); // halified (2 hals) body
NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU * /*this*/, NvU32, NvU32, NvU32, THREAD_STATE_NODE *); // halified (2 hals) body
NV_STATUS (*__gpuReadVgpuConfigReg__)(struct OBJGPU * /*this*/, NvU32, NvU32 *); // halified (2 hals) body
NV_STATUS (*__gpuReadPassThruConfigReg__)(struct OBJGPU * /*this*/, NvU32, NvU32 *); // halified (3 hals) body
void (*__gpuGetIdInfo__)(struct OBJGPU * /*this*/); // halified (3 hals) body
NV_STATUS (*__gpuGenGidData__)(struct OBJGPU * /*this*/, NvU8 *, NvU32, NvU32); // halified (2 hals) body
NvU8 (*__gpuGetChipSubRev__)(struct OBJGPU * /*this*/); // halified (2 hals) body
@ -1020,8 +1020,8 @@ struct OBJGPU {
NV_STATUS (*__gpuInitOptimusSettings__)(struct OBJGPU * /*this*/); // halified (2 hals) body
NV_STATUS (*__gpuDeinitOptimusSettings__)(struct OBJGPU * /*this*/); // halified (2 hals) body
NvBool (*__gpuIsSliCapableWithoutDisplay__)(struct OBJGPU * /*this*/); // halified (2 hals) body
NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU * /*this*/); // halified (3 hals) body
NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU * /*this*/); // halified (3 hals) body
NvBool (*__gpuIsCCEnabledInHw__)(struct OBJGPU * /*this*/); // halified (4 hals) body
NvBool (*__gpuIsDevModeEnabledInHw__)(struct OBJGPU * /*this*/); // halified (4 hals) body
NvBool (*__gpuIsProtectedPcieEnabledInHw__)(struct OBJGPU * /*this*/); // halified (3 hals) body
NvBool (*__gpuIsCtxBufAllocInPmaSupported__)(struct OBJGPU * /*this*/); // halified (2 hals) body
NV_STATUS (*__gpuUpdateErrorContainmentState__)(struct OBJGPU * /*this*/, NV_ERROR_CONT_ERR_ID, NV_ERROR_CONT_LOCATION, NvU32 *); // halified (3 hals) body
@ -1613,9 +1613,9 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32,
#define gpuWriteFunctionConfigRegEx_FNPTR(pGpu) pGpu->__gpuWriteFunctionConfigRegEx__
#define gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState)
#define gpuWriteFunctionConfigRegEx_HAL(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState)
#define gpuReadVgpuConfigReg_FNPTR(pGpu) pGpu->__gpuReadVgpuConfigReg__
#define gpuReadVgpuConfigReg(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data)
#define gpuReadVgpuConfigReg_HAL(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data)
#define gpuReadPassThruConfigReg_FNPTR(pGpu) pGpu->__gpuReadPassThruConfigReg__
#define gpuReadPassThruConfigReg(pGpu, index, data) gpuReadPassThruConfigReg_DISPATCH(pGpu, index, data)
#define gpuReadPassThruConfigReg_HAL(pGpu, index, data) gpuReadPassThruConfigReg_DISPATCH(pGpu, index, data)
#define gpuGetIdInfo_FNPTR(pGpu) pGpu->__gpuGetIdInfo__
#define gpuGetIdInfo(pGpu) gpuGetIdInfo_DISPATCH(pGpu)
#define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu)
@ -1797,8 +1797,8 @@ static inline NV_STATUS gpuWriteFunctionConfigRegEx_DISPATCH(struct OBJGPU *pGpu
return pGpu->__gpuWriteFunctionConfigRegEx__(pGpu, function, reg, data, pThreadState);
}
static inline NV_STATUS gpuReadVgpuConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
return pGpu->__gpuReadVgpuConfigReg__(pGpu, index, data);
static inline NV_STATUS gpuReadPassThruConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
return pGpu->__gpuReadPassThruConfigReg__(pGpu, index, data);
}
static inline void gpuGetIdInfo_DISPATCH(struct OBJGPU *pGpu) {
@ -3114,9 +3114,11 @@ static inline NV_STATUS gpuWriteFunctionConfigRegEx_5baef9(struct OBJGPU *pGpu,
NV_ASSERT_OR_RETURN_PRECOMP(0, NV_ERR_NOT_SUPPORTED);
}
NV_STATUS gpuReadVgpuConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data);
NV_STATUS gpuReadPassThruConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data);
static inline NV_STATUS gpuReadVgpuConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
NV_STATUS gpuReadPassThruConfigReg_GB100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data);
static inline NV_STATUS gpuReadPassThruConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
return NV_ERR_NOT_SUPPORTED;
}
@ -3379,12 +3381,16 @@ static inline NvBool gpuIsCCEnabledInHw_491d52(struct OBJGPU *pGpu) {
NvBool gpuIsCCEnabledInHw_GH100(struct OBJGPU *pGpu);
NvBool gpuIsCCEnabledInHw_GB100(struct OBJGPU *pGpu);
static inline NvBool gpuIsDevModeEnabledInHw_491d52(struct OBJGPU *pGpu) {
return ((NvBool)(0 != 0));
}
NvBool gpuIsDevModeEnabledInHw_GH100(struct OBJGPU *pGpu);
NvBool gpuIsDevModeEnabledInHw_GB100(struct OBJGPU *pGpu);
static inline NvBool gpuIsProtectedPcieEnabledInHw_491d52(struct OBJGPU *pGpu) {
return ((NvBool)(0 != 0));
}

32
src/nvidia/generated/g_kernel_bif_nvoc.h
View File

@ -143,6 +143,12 @@ typedef struct
NvU32 xveDevCtrl;
} KBIF_CACHE_DATA;
typedef struct
{
// Cache link capabilities from pcie config space
NvU32 linkCap;
} KBIF_CACHE_PCIE_CONFIG_REG;
typedef struct KERNEL_HOST_VGPU_DEVICE KERNEL_HOST_VGPU_DEVICE;
@ -287,6 +293,7 @@ struct KernelBif {
KBIF_XVE_REGMAP_REF xveRegmapRef[2];
NvBool bMnocAvailable;
NvU32 barRegOffsets[7];
KBIF_CACHE_PCIE_CONFIG_REG pcieConfigReg;
};
#ifndef __NVOC_CLASS_KernelBif_TYPEDEF__
@ -872,6 +879,20 @@ void kbifDestruct_GM107(struct KernelBif *pKernelBif);
#define __nvoc_kbifDestruct(pKernelBif) kbifDestruct_GM107(pKernelBif)
NvU32 kbifGetGpuLinkCapabilities_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
#ifdef __nvoc_kernel_bif_h_disabled
static inline NvU32 kbifGetGpuLinkCapabilities(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) {
NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!");
return 0;
}
#else //__nvoc_kernel_bif_h_disabled
#define kbifGetGpuLinkCapabilities(pGpu, pKernelBif) kbifGetGpuLinkCapabilities_IMPL(pGpu, pKernelBif)
#endif //__nvoc_kernel_bif_h_disabled
#define kbifGetGpuLinkCapabilities_HAL(pGpu, pKernelBif) kbifGetGpuLinkCapabilities(pGpu, pKernelBif)
void kbifClearConfigErrors_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvBool arg3, NvU32 arg4);
@ -1420,17 +1441,6 @@ static inline NV_STATUS kbifPollDeviceOnBus(struct OBJGPU *pGpu, struct KernelBi
#define kbifPollDeviceOnBus(pGpu, pKernelBif) kbifPollDeviceOnBus_IMPL(pGpu, pKernelBif)
#endif //__nvoc_kernel_bif_h_disabled
NvU32 kbifGetGpuLinkCapabilities_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
#ifdef __nvoc_kernel_bif_h_disabled
static inline NvU32 kbifGetGpuLinkCapabilities(struct OBJGPU *pGpu, struct KernelBif *pKernelBif) {
NV_ASSERT_FAILED_PRECOMP("KernelBif was disabled!");
return 0;
}
#else //__nvoc_kernel_bif_h_disabled
#define kbifGetGpuLinkCapabilities(pGpu, pKernelBif) kbifGetGpuLinkCapabilities_IMPL(pGpu, pKernelBif)
#endif //__nvoc_kernel_bif_h_disabled
NvU32 kbifGetGpuLinkControlStatus_IMPL(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
#ifdef __nvoc_kernel_bif_h_disabled

2
src/nvidia/generated/g_nv_name_released.h
View File

@ -981,10 +981,12 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x25AD, 0x0000, 0x0000, "NVIDIA GeForce RTX 2050" },
{ 0x25B0, 0x1878, 0x1028, "NVIDIA RTX A1000" },
{ 0x25B0, 0x1878, 0x103c, "NVIDIA RTX A1000" },
{ 0x25B0, 0x8d96, 0x103c, "NVIDIA RTX A1000" },
{ 0x25B0, 0x1878, 0x10de, "NVIDIA RTX A1000" },
{ 0x25B0, 0x1878, 0x17aa, "NVIDIA RTX A1000" },
{ 0x25B2, 0x1879, 0x1028, "NVIDIA RTX A400" },
{ 0x25B2, 0x1879, 0x103c, "NVIDIA RTX A400" },
{ 0x25B2, 0x8d95, 0x103c, "NVIDIA RTX A400" },
{ 0x25B2, 0x1879, 0x10de, "NVIDIA RTX A400" },
{ 0x25B2, 0x1879, 0x17aa, "NVIDIA RTX A400" },
{ 0x25B6, 0x14a9, 0x10de, "NVIDIA A16" },

34
src/nvidia/generated/g_objtmr_nvoc.c
View File

@ -75,7 +75,7 @@ const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR =
/*pExportInfo=*/ &__nvoc_export_info_OBJTMR
};
// 9 down-thunk(s) defined to bridge methods in OBJTMR from superclasses
// 10 down-thunk(s) defined to bridge methods in OBJTMR from superclasses
// tmrRegisterIntrService: virtual override (intrserv) base (intrserv)
static void __nvoc_down_thunk_OBJTMR_intrservRegisterIntrService(OBJGPU *pGpu, struct IntrService *pTmr, IntrServiceRecord pRecords[175]) {
@ -102,6 +102,11 @@ static NV_STATUS __nvoc_down_thunk_OBJTMR_engstateStatePreInitLocked(OBJGPU *pGp
return tmrStatePreInitLocked(pGpu, (struct OBJTMR *)(((unsigned char *) pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset));
}
// tmrStateInitLocked: virtual override (engstate) base (engstate)
static NV_STATUS __nvoc_down_thunk_OBJTMR_engstateStateInitLocked(OBJGPU *pGpu, struct OBJENGSTATE *pTmr) {
return tmrStateInitLocked(pGpu, (struct OBJTMR *)(((unsigned char *) pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset));
}
// tmrStateInitUnlocked: virtual override (engstate) base (engstate)
static NV_STATUS __nvoc_down_thunk_OBJTMR_engstateStateInitUnlocked(OBJGPU *pGpu, struct OBJENGSTATE *pTmr) {
return tmrStateInitUnlocked(pGpu, (struct OBJTMR *)(((unsigned char *) pTmr) - __nvoc_rtti_OBJTMR_OBJENGSTATE.offset));
@ -123,7 +128,7 @@ static void __nvoc_down_thunk_OBJTMR_engstateStateDestroy(OBJGPU *pGpu, struct O
}
// 9 up-thunk(s) defined to bridge methods in OBJTMR to superclasses
// 8 up-thunk(s) defined to bridge methods in OBJTMR to superclasses
// tmrInitMissing: virtual inherited (engstate) base (engstate)
static void __nvoc_up_thunk_OBJENGSTATE_tmrInitMissing(struct OBJGPU *pGpu, struct OBJTMR *pEngstate) {
@ -135,11 +140,6 @@ static NV_STATUS __nvoc_up_thunk_OBJENGSTATE_tmrStatePreInitUnlocked(struct OBJG
return engstateStatePreInitUnlocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *) pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset));
}
// tmrStateInitLocked: virtual inherited (engstate) base (engstate)
static NV_STATUS __nvoc_up_thunk_OBJENGSTATE_tmrStateInitLocked(struct OBJGPU *pGpu, struct OBJTMR *pEngstate) {
return engstateStateInitLocked(pGpu, (struct OBJENGSTATE *)(((unsigned char *) pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset));
}
// tmrStatePreLoad: virtual inherited (engstate) base (engstate)
static NV_STATUS __nvoc_up_thunk_OBJENGSTATE_tmrStatePreLoad(struct OBJGPU *pGpu, struct OBJTMR *pEngstate, NvU32 arg3) {
return engstateStatePreLoad(pGpu, (struct OBJENGSTATE *)(((unsigned char *) pEngstate) + __nvoc_rtti_OBJTMR_OBJENGSTATE.offset), arg3);
@ -240,6 +240,17 @@ void __nvoc_init_dataField_OBJTMR(OBJTMR *pThis, RmHalspecOwner *pRmhalspecowner
{
pThis->setProperty(pThis, PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL, ((NvBool)(0 != 0)));
}
// NVOC Property Hal field -- PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0xc0000000UL) )) /* ChipHal: GB100 | GB102 */
{
pThis->setProperty(pThis, PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF, ((NvBool)(0 == 0)));
}
// default
else
{
pThis->setProperty(pThis, PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF, ((NvBool)(0 != 0)));
}
}
NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* );
@ -318,6 +329,10 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal
pThis->__tmrStatePreInitLocked__ = &tmrStatePreInitLocked_IMPL;
pThis->__nvoc_base_OBJENGSTATE.__engstateStatePreInitLocked__ = &__nvoc_down_thunk_OBJTMR_engstateStatePreInitLocked;
// tmrStateInitLocked -- virtual override (engstate) base (engstate)
pThis->__tmrStateInitLocked__ = &tmrStateInitLocked_IMPL;
pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_down_thunk_OBJTMR_engstateStateInitLocked;
// tmrStateInitUnlocked -- virtual override (engstate) base (engstate)
pThis->__tmrStateInitUnlocked__ = &tmrStateInitUnlocked_IMPL;
pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitUnlocked__ = &__nvoc_down_thunk_OBJTMR_engstateStateInitUnlocked;
@ -427,9 +442,6 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal
// tmrStatePreInitUnlocked -- virtual inherited (engstate) base (engstate)
pThis->__tmrStatePreInitUnlocked__ = &__nvoc_up_thunk_OBJENGSTATE_tmrStatePreInitUnlocked;
// tmrStateInitLocked -- virtual inherited (engstate) base (engstate)
pThis->__tmrStateInitLocked__ = &__nvoc_up_thunk_OBJENGSTATE_tmrStateInitLocked;
// tmrStatePreLoad -- virtual inherited (engstate) base (engstate)
pThis->__tmrStatePreLoad__ = &__nvoc_up_thunk_OBJENGSTATE_tmrStatePreLoad;
@ -447,7 +459,7 @@ static void __nvoc_init_funcTable_OBJTMR_1(OBJTMR *pThis, RmHalspecOwner *pRmhal
// tmrServiceNotificationInterrupt -- virtual inherited (intrserv) base (intrserv)
pThis->__tmrServiceNotificationInterrupt__ = &__nvoc_up_thunk_IntrService_tmrServiceNotificationInterrupt;
} // End __nvoc_init_funcTable_OBJTMR_1 with approximately 48 basic block(s).
} // End __nvoc_init_funcTable_OBJTMR_1 with approximately 49 basic block(s).
// Initialize vtable(s) for 27 virtual method(s).

21
src/nvidia/generated/g_objtmr_nvoc.h
View File

@ -220,6 +220,7 @@ struct OBJTMR {
NvU32 (*__tmrServiceInterrupt__)(OBJGPU *, struct OBJTMR * /*this*/, IntrServiceServiceInterruptArguments *); // virtual halified (3 hals) override (intrserv) base (intrserv) body
NV_STATUS (*__tmrConstructEngine__)(OBJGPU *, struct OBJTMR * /*this*/, ENGDESCRIPTOR); // virtual override (engstate) base (engstate)
NV_STATUS (*__tmrStatePreInitLocked__)(OBJGPU *, struct OBJTMR * /*this*/); // virtual override (engstate) base (engstate)
NV_STATUS (*__tmrStateInitLocked__)(OBJGPU *, struct OBJTMR * /*this*/); // virtual override (engstate) base (engstate)
NV_STATUS (*__tmrStateInitUnlocked__)(OBJGPU *, struct OBJTMR * /*this*/); // virtual override (engstate) base (engstate)
NV_STATUS (*__tmrStateLoad__)(OBJGPU *, struct OBJTMR * /*this*/, NvU32); // virtual override (engstate) base (engstate)
NV_STATUS (*__tmrStateUnload__)(OBJGPU *, struct OBJTMR * /*this*/, NvU32); // virtual override (engstate) base (engstate)
@ -234,7 +235,6 @@ struct OBJTMR {
NV_STATUS (*__tmrGetGpuPtimerOffset__)(OBJGPU *, struct OBJTMR * /*this*/, NvU32 *, NvU32 *); // halified (2 hals) body
void (*__tmrInitMissing__)(struct OBJGPU *, struct OBJTMR * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrStatePreInitUnlocked__)(struct OBJGPU *, struct OBJTMR * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrStateInitLocked__)(struct OBJGPU *, struct OBJTMR * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrStatePreLoad__)(struct OBJGPU *, struct OBJTMR * /*this*/, NvU32); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrStatePostLoad__)(struct OBJGPU *, struct OBJTMR * /*this*/, NvU32); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrStatePreUnload__)(struct OBJGPU *, struct OBJTMR * /*this*/, NvU32); // virtual inherited (engstate) base (engstate)
@ -242,13 +242,14 @@ struct OBJTMR {
NvBool (*__tmrIsPresent__)(struct OBJGPU *, struct OBJTMR * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__tmrServiceNotificationInterrupt__)(OBJGPU *, struct OBJTMR * /*this*/, IntrServiceServiceNotificationInterruptArguments *); // virtual inherited (intrserv) base (intrserv)
// 6 PDB properties
// 7 PDB properties
NvBool PDB_PROP_TMR_USE_COUNTDOWN_TIMER_FOR_RM_CALLBACKS;
NvBool PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE;
NvBool PDB_PROP_TMR_USE_OS_TIMER_FOR_CALLBACKS;
NvBool PDB_PROP_TMR_USE_PTIMER_FOR_OSTIMER_CALLBACKS;
NvBool PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS;
NvBool PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL;
NvBool PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF;
// Data members
struct TMR_EVENT_PVT *pRmActiveEventList;
@ -303,6 +304,8 @@ extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJTMR;
#define PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL_BASE_NAME PDB_PROP_TMR_USE_SECOND_COUNTDOWN_TIMER_FOR_SWRL
#define PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS_BASE_CAST
#define PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS_BASE_NAME PDB_PROP_TMR_USE_POLLING_FOR_CALLBACKS
#define PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF_BASE_CAST
#define PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF_BASE_NAME PDB_PROP_TMR_WAR_FOR_BUG_4679970_DEF
#define PDB_PROP_TMR_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE.
#define PDB_PROP_TMR_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING
#define PDB_PROP_TMR_ALARM_INTR_REMOVED_FROM_PMC_TREE_BASE_CAST
@ -330,6 +333,8 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32);
#define tmrConstructEngine(pGpu, pTmr, arg3) tmrConstructEngine_DISPATCH(pGpu, pTmr, arg3)
#define tmrStatePreInitLocked_FNPTR(pTmr) pTmr->__tmrStatePreInitLocked__
#define tmrStatePreInitLocked(pGpu, pTmr) tmrStatePreInitLocked_DISPATCH(pGpu, pTmr)
#define tmrStateInitLocked_FNPTR(pTmr) pTmr->__tmrStateInitLocked__
#define tmrStateInitLocked(pGpu, pTmr) tmrStateInitLocked_DISPATCH(pGpu, pTmr)
#define tmrStateInitUnlocked_FNPTR(pTmr) pTmr->__tmrStateInitUnlocked__
#define tmrStateInitUnlocked(pGpu, pTmr) tmrStateInitUnlocked_DISPATCH(pGpu, pTmr)
#define tmrStateLoad_FNPTR(pTmr) pTmr->__tmrStateLoad__
@ -366,8 +371,6 @@ NV_STATUS __nvoc_objCreate_OBJTMR(OBJTMR**, Dynamic*, NvU32);
#define tmrInitMissing(pGpu, pEngstate) tmrInitMissing_DISPATCH(pGpu, pEngstate)
#define tmrStatePreInitUnlocked_FNPTR(pEngstate) pEngstate->__nvoc_base_OBJENGSTATE.__engstateStatePreInitUnlocked__
#define tmrStatePreInitUnlocked(pGpu, pEngstate) tmrStatePreInitUnlocked_DISPATCH(pGpu, pEngstate)
#define tmrStateInitLocked_FNPTR(pEngstate) pEngstate->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__
#define tmrStateInitLocked(pGpu, pEngstate) tmrStateInitLocked_DISPATCH(pGpu, pEngstate)
#define tmrStatePreLoad_FNPTR(pEngstate) pEngstate->__nvoc_base_OBJENGSTATE.__engstateStatePreLoad__
#define tmrStatePreLoad(pGpu, pEngstate, arg3) tmrStatePreLoad_DISPATCH(pGpu, pEngstate, arg3)
#define tmrStatePostLoad_FNPTR(pEngstate) pEngstate->__nvoc_base_OBJENGSTATE.__engstateStatePostLoad__
@ -406,6 +409,10 @@ static inline NV_STATUS tmrStatePreInitLocked_DISPATCH(OBJGPU *pGpu, struct OBJT
return pTmr->__tmrStatePreInitLocked__(pGpu, pTmr);
}
static inline NV_STATUS tmrStateInitLocked_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) {
return pTmr->__tmrStateInitLocked__(pGpu, pTmr);
}
static inline NV_STATUS tmrStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJTMR *pTmr) {
return pTmr->__tmrStateInitUnlocked__(pGpu, pTmr);
}
@ -462,10 +469,6 @@ static inline NV_STATUS tmrStatePreInitUnlocked_DISPATCH(struct OBJGPU *pGpu, st
return pEngstate->__tmrStatePreInitUnlocked__(pGpu, pEngstate);
}
static inline NV_STATUS tmrStateInitLocked_DISPATCH(struct OBJGPU *pGpu, struct OBJTMR *pEngstate) {
return pEngstate->__tmrStateInitLocked__(pGpu, pEngstate);
}
static inline NV_STATUS tmrStatePreLoad_DISPATCH(struct OBJGPU *pGpu, struct OBJTMR *pEngstate, NvU32 arg3) {
return pEngstate->__tmrStatePreLoad__(pGpu, pEngstate, arg3);
}
@ -880,6 +883,8 @@ NV_STATUS tmrConstructEngine_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, ENGDESCRIPT
NV_STATUS tmrStatePreInitLocked_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr);
NV_STATUS tmrStateInitLocked_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr);
NV_STATUS tmrStateInitUnlocked_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr);
NV_STATUS tmrStateLoad_IMPL(OBJGPU *pGpu, struct OBJTMR *pTmr, NvU32 arg3);

226
src/nvidia/generated/g_subdevice_nvoc.c
View File

@ -7935,21 +7935,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
{ /* [521] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessMGCR_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803060u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMGCR"
#endif
},
{ /* [522] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessMTCAP_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
@ -7962,7 +7947,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTCAP"
#endif
},
{ /* [523] */
{ /* [522] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -7977,7 +7962,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPMTU"
#endif
},
{ /* [524] */
{ /* [523] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -7992,7 +7977,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMCIA"
#endif
},
{ /* [525] */
{ /* [524] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8007,7 +7992,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPMLP"
#endif
},
{ /* [526] */
{ /* [525] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8022,7 +8007,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessGHPKT"
#endif
},
{ /* [527] */
{ /* [526] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8037,22 +8022,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPDDR"
#endif
},
{ /* [528] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) subdeviceCtrlCmdNvlinkPRMAccessMTMP_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*flags=*/ 0x44u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x20803067u,
/*paramSize=*/ sizeof(NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_Subdevice.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTMP"
#endif
},
{ /* [529] */
{ /* [527] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8067,7 +8037,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPTT"
#endif
},
{ /* [530] */
{ /* [528] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8082,7 +8052,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPCNT"
#endif
},
{ /* [531] */
{ /* [529] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8097,7 +8067,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMGIR"
#endif
},
{ /* [532] */
{ /* [530] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8112,7 +8082,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPAOS"
#endif
},
{ /* [533] */
{ /* [531] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8127,7 +8097,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPHCR"
#endif
},
{ /* [534] */
{ /* [532] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8142,7 +8112,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessSLTP"
#endif
},
{ /* [535] */
{ /* [533] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8157,7 +8127,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPGUID"
#endif
},
{ /* [536] */
{ /* [534] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8172,7 +8142,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPRT"
#endif
},
{ /* [537] */
{ /* [535] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8187,7 +8157,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPTYS"
#endif
},
{ /* [538] */
{ /* [536] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8202,7 +8172,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessSLRG"
#endif
},
{ /* [539] */
{ /* [537] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8217,7 +8187,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPMAOS"
#endif
},
{ /* [540] */
{ /* [538] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8232,7 +8202,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPLR"
#endif
},
{ /* [541] */
{ /* [539] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8247,7 +8217,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkGetSupportedCounters"
#endif
},
{ /* [542] */
{ /* [540] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8262,7 +8232,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMORD"
#endif
},
{ /* [543] */
{ /* [541] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8277,7 +8247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTRC_CAP"
#endif
},
{ /* [544] */
{ /* [542] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8292,7 +8262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTRC_CONF"
#endif
},
{ /* [545] */
{ /* [543] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8307,7 +8277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTRC_CTRL"
#endif
},
{ /* [546] */
{ /* [544] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8322,7 +8292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTEIM"
#endif
},
{ /* [547] */
{ /* [545] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8337,7 +8307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTIE"
#endif
},
{ /* [548] */
{ /* [546] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8352,7 +8322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTIM"
#endif
},
{ /* [549] */
{ /* [547] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8367,7 +8337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMPSCR"
#endif
},
{ /* [550] */
{ /* [548] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8382,7 +8352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMTSR"
#endif
},
{ /* [551] */
{ /* [549] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8397,7 +8367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPPSLS"
#endif
},
{ /* [552] */
{ /* [550] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8412,7 +8382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessMLPC"
#endif
},
{ /* [553] */
{ /* [551] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8427,7 +8397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdNvlinkPRMAccessPLIB"
#endif
},
{ /* [554] */
{ /* [552] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8442,7 +8412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdSetNvlinkHwErrorInjectSettings"
#endif
},
{ /* [555] */
{ /* [553] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8457,7 +8427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGetNvlinkHwErrorInjectSettings"
#endif
},
{ /* [556] */
{ /* [554] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8472,7 +8442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetDmemUsage"
#endif
},
{ /* [557] */
{ /* [555] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8487,7 +8457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetEngineArch"
#endif
},
{ /* [558] */
{ /* [556] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8502,7 +8472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerQueueInfo"
#endif
},
{ /* [559] */
{ /* [557] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8517,7 +8487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlGet"
#endif
},
{ /* [560] */
{ /* [558] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8532,7 +8502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnUstreamerControlSet"
#endif
},
{ /* [561] */
{ /* [559] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8547,7 +8517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferInfo"
#endif
},
{ /* [562] */
{ /* [560] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8562,7 +8532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlcnGetCtxBufferSize"
#endif
},
{ /* [563] */
{ /* [561] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8577,7 +8547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetClientExposedCounters"
#endif
},
{ /* [564] */
{ /* [562] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8592,7 +8562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetEciCounters"
#endif
},
{ /* [565] */
{ /* [563] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8607,7 +8577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdEccGetVolatileCounts"
#endif
},
{ /* [566] */
{ /* [564] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x8u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8622,7 +8592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaRange"
#endif
},
{ /* [567] */
{ /* [565] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10244u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8637,7 +8607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaSetupInstanceMemBlock"
#endif
},
{ /* [568] */
{ /* [566] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10004u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8652,7 +8622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetRange"
#endif
},
{ /* [569] */
{ /* [567] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x108u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8667,7 +8637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdFlaGetFabricMemStats"
#endif
},
{ /* [570] */
{ /* [568] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40549u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8682,7 +8652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGspGetFeatures"
#endif
},
{ /* [571] */
{ /* [569] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8697,7 +8667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGspGetRmHeapStats"
#endif
},
{ /* [572] */
{ /* [570] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x248u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8712,7 +8682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGrmgrGetGrFsInfo"
#endif
},
{ /* [573] */
{ /* [571] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x3u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8727,7 +8697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixGc6BlockerRefCnt"
#endif
},
{ /* [574] */
{ /* [572] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x9u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8742,7 +8712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAllowDisallowGcoff"
#endif
},
{ /* [575] */
{ /* [573] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x1u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8757,7 +8727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixAudioDynamicPower"
#endif
},
{ /* [576] */
{ /* [574] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xbu)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8772,7 +8742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixVidmemPersistenceStatus"
#endif
},
{ /* [577] */
{ /* [575] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x7u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8787,7 +8757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdOsUnixUpdateTgpStatus"
#endif
},
{ /* [578] */
{ /* [576] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8802,7 +8772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalBootloadGspVgpuPluginTask"
#endif
},
{ /* [579] */
{ /* [577] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8817,7 +8787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalShutdownGspVgpuPluginTask"
#endif
},
{ /* [580] */
{ /* [578] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8832,7 +8802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalPgpuAddVgpuType"
#endif
},
{ /* [581] */
{ /* [579] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8847,7 +8817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalEnumerateVgpuPerPgpu"
#endif
},
{ /* [582] */
{ /* [580] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8862,7 +8832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalClearGuestVmInfo"
#endif
},
{ /* [583] */
{ /* [581] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8877,7 +8847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetVgpuFbUsage"
#endif
},
{ /* [584] */
{ /* [582] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8892,7 +8862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuEncoderCapacity"
#endif
},
{ /* [585] */
{ /* [583] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8907,7 +8877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalCleanupGspVgpuPluginResources"
#endif
},
{ /* [586] */
{ /* [584] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8922,7 +8892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuFsEncoding"
#endif
},
{ /* [587] */
{ /* [585] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8937,7 +8907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalGetPgpuMigrationSupport"
#endif
},
{ /* [588] */
{ /* [586] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8952,7 +8922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalSetVgpuMgrConfig"
#endif
},
{ /* [589] */
{ /* [587] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8967,7 +8937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdVgpuMgrInternalFreeStates"
#endif
},
{ /* [590] */
{ /* [588] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8982,7 +8952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlCmdGetAvailableHshubMask"
#endif
},
{ /* [591] */
{ /* [589] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x158u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -8997,7 +8967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Subdevic
/*func=*/ "subdeviceCtrlSetEcThrottleMode"
#endif
},
{ /* [592] */
{ /* [590] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
@ -9173,7 +9143,7 @@ static NV_STATUS __nvoc_up_thunk_Notifier_subdeviceGetOrAllocNotifShare(struct S
const struct NVOC_EXPORT_INFO __nvoc_export_info_Subdevice =
{
/*numEntries=*/ 593,
/*numEntries=*/ 591,
/*pExportEntries=*/ __nvoc_exported_method_def_Subdevice
};
@ -9856,11 +9826,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdNvlinkPRMAccessMTSDE__ = &subdeviceCtrlCmdNvlinkPRMAccessMTSDE_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessMGCR -- exported (id=0x20803060)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessMGCR__ = &subdeviceCtrlCmdNvlinkPRMAccessMGCR_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessMTCAP -- exported (id=0x20803061)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessMTCAP__ = &subdeviceCtrlCmdNvlinkPRMAccessMTCAP_IMPL;
@ -9891,11 +9856,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
pThis->__subdeviceCtrlCmdNvlinkPRMAccessPDDR__ = &subdeviceCtrlCmdNvlinkPRMAccessPDDR_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessMTMP -- exported (id=0x20803067)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessMTMP__ = &subdeviceCtrlCmdNvlinkPRMAccessMTMP_IMPL;
#endif
// subdeviceCtrlCmdNvlinkPRMAccessPPTT -- exported (id=0x20803068)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
pThis->__subdeviceCtrlCmdNvlinkPRMAccessPPTT__ = &subdeviceCtrlCmdNvlinkPRMAccessPPTT_IMPL;
@ -10522,16 +10482,6 @@ static void __nvoc_init_funcTable_Subdevice_1(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x118u)
pThis->__subdeviceCtrlCmdKGrGetInfo__ = &subdeviceCtrlCmdKGrGetInfo_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
// Vtable initialization 2/3
static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdKGrGetInfoV2 -- exported (id=0x20801228)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x118u)
@ -10542,6 +10492,16 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x10au)
pThis->__subdeviceCtrlCmdKGrGetCapsV2__ = &subdeviceCtrlCmdKGrGetCapsV2_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_1 with approximately 263 basic block(s).
// Vtable initialization 2/3
static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdKGrGetCtxswModes -- exported (id=0x20801235)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
@ -11847,16 +11807,6 @@ static void __nvoc_init_funcTable_Subdevice_2(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
pThis->__subdeviceCtrlCmdIsEgpuBridge__ = &subdeviceCtrlCmdIsEgpuBridge_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
// Vtable initialization 3/3
static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdInternalGpuGetGspRmFreeHeap -- exported (id=0x20800aeb)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
@ -11867,6 +11817,16 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
pThis->__subdeviceCtrlCmdInternalBusFlushWithSysmembar__ = &subdeviceCtrlCmdInternalBusFlushWithSysmembar_IMPL;
#endif
} // End __nvoc_init_funcTable_Subdevice_2 with approximately 263 basic block(s).
// Vtable initialization 3/3
static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// subdeviceCtrlCmdInternalBusSetupP2pMailboxLocal -- exported (id=0x20800a71)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
@ -12516,13 +12476,13 @@ static void __nvoc_init_funcTable_Subdevice_3(Subdevice *pThis, RmHalspecOwner *
// subdeviceGetOrAllocNotifShare -- virtual inherited (notify) base (notify)
pThis->__subdeviceGetOrAllocNotifShare__ = &__nvoc_up_thunk_Notifier_subdeviceGetOrAllocNotifShare;
} // End __nvoc_init_funcTable_Subdevice_3 with approximately 143 basic block(s).
} // End __nvoc_init_funcTable_Subdevice_3 with approximately 141 basic block(s).
// Initialize vtable(s) for 623 virtual method(s).
// Initialize vtable(s) for 621 virtual method(s).
void __nvoc_init_funcTable_Subdevice(Subdevice *pThis, RmHalspecOwner *pRmhalspecowner) {
// Initialize vtable(s) with 623 per-object function pointer(s).
// Initialize vtable(s) with 621 per-object function pointer(s).
// To reduce stack pressure with some unoptimized builds, the logic is distributed among 3 functions.
__nvoc_init_funcTable_Subdevice_1(pThis, pRmhalspecowner);
__nvoc_init_funcTable_Subdevice_2(pThis, pRmhalspecowner);

20
src/nvidia/generated/g_subdevice_nvoc.h
View File

@ -143,7 +143,7 @@ struct Subdevice {
struct Notifier *__nvoc_pbase_Notifier; // notify super
struct Subdevice *__nvoc_pbase_Subdevice; // subdevice
// Vtable with 623 per-object function pointers
// Vtable with 621 per-object function pointers
void (*__subdevicePreDestruct__)(struct Subdevice * /*this*/); // virtual override (res) base (gpures)
NV_STATUS (*__subdeviceInternalControlForward__)(struct Subdevice * /*this*/, NvU32, void *, NvU32); // virtual override (gpures) base (gpures)
NV_STATUS (*__subdeviceCtrlCmdBiosGetInfoV2__)(struct Subdevice * /*this*/, NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *); // halified (2 hals) exported (id=0x20800810) body
@ -260,14 +260,12 @@ struct Subdevice {
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMTWE__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS *); // exported (id=0x2080305d)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMTEWE__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS *); // exported (id=0x2080305e)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMTSDE__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS *); // exported (id=0x2080305f)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMGCR__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS *); // exported (id=0x20803060)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMTCAP__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS *); // exported (id=0x20803061)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPMTU__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS *); // exported (id=0x20803062)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMCIA__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS *); // exported (id=0x20803063)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPMLP__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS *); // exported (id=0x20803064)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessGHPKT__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS *); // exported (id=0x20803065)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPDDR__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS *); // exported (id=0x20803066)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMTMP__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS *); // exported (id=0x20803067)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPTT__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS *); // exported (id=0x20803068)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessPPCNT__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS *); // exported (id=0x20803069)
NV_STATUS (*__subdeviceCtrlCmdNvlinkPRMAccessMGIR__)(struct Subdevice * /*this*/, NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS *); // exported (id=0x2080306a)
@ -1073,8 +1071,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdNvlinkPRMAccessMTEWE(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMTEWE_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessMTSDE_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTSDE__
#define subdeviceCtrlCmdNvlinkPRMAccessMTSDE(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMTSDE_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessMGCR_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMGCR__
#define subdeviceCtrlCmdNvlinkPRMAccessMGCR(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMGCR_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessMTCAP_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTCAP__
#define subdeviceCtrlCmdNvlinkPRMAccessMTCAP(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMTCAP_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPMTU_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPMTU__
@ -1087,8 +1083,6 @@ NV_STATUS __nvoc_objCreate_Subdevice(Subdevice**, Dynamic*, NvU32, struct CALL_C
#define subdeviceCtrlCmdNvlinkPRMAccessGHPKT(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessGHPKT_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPDDR_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPDDR__
#define subdeviceCtrlCmdNvlinkPRMAccessPDDR(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPDDR_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessMTMP_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTMP__
#define subdeviceCtrlCmdNvlinkPRMAccessMTMP(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessMTMP_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPPTT_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPTT__
#define subdeviceCtrlCmdNvlinkPRMAccessPPTT(arg_this, arg2) subdeviceCtrlCmdNvlinkPRMAccessPPTT_DISPATCH(arg_this, arg2)
#define subdeviceCtrlCmdNvlinkPRMAccessPPCNT_FNPTR(arg_this) arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPCNT__
@ -2591,10 +2585,6 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTSDE_DISPATCH(struct Sub
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTSDE__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMGCR_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMGCR__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTCAP_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTCAP__(arg_this, arg2);
}
@ -2619,10 +2609,6 @@ static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPDDR_DISPATCH(struct Subd
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPDDR__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTMP_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessMTMP__(arg_this, arg2);
}
static inline NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPTT_DISPATCH(struct Subdevice *arg_this, NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS *arg2) {
return arg_this->__subdeviceCtrlCmdNvlinkPRMAccessPPTT__(arg_this, arg2);
}
@ -4895,8 +4881,6 @@ NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTEWE_IMPL(struct Subdevice *arg1, NV20
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTSDE_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMGCR_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTCAP_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPMTU_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS *arg2);
@ -4909,8 +4893,6 @@ NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessGHPKT_IMPL(struct Subdevice *arg1, NV20
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPDDR_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessMTMP_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPTT_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS *arg2);
NV_STATUS subdeviceCtrlCmdNvlinkPRMAccessPPCNT_IMPL(struct Subdevice *arg1, NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS *arg2);

1
src/nvidia/generated/g_system_nvoc.h
View File

@ -468,6 +468,7 @@ struct OBJSYS {
struct OBJHALMGR *pHalMgr;
struct Fabric *pFabric;
struct GpuDb *pGpuDb;
NvBool bIsGridBuild;
};
#ifndef __NVOC_CLASS_OBJSYS_TYPEDEF__

2
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
View File

@ -137,7 +137,7 @@ struct DACP2060EXTERNALDEVICE
NvBool enableFrmCmpMatchIntSlave; // Enable the frmCmpMatchInt for slave, if this bit is set.
NvBool isFrmCmpMatchIntMasterEnabled; // To enable frmCmpMatchInt for master when gsync framecount exceeds (2^24 - 1000)
TMR_EVENT *pTimerEvent; // Used for supporting gsyncFrameCountTimerService_P2060
TMR_EVENT *pTimerEvents[NV_MAX_DEVICES]; // Used for supporting gsyncFrameCountTimerService_P2060
} FrameCountData;
struct {

3
src/nvidia/inc/kernel/gpu/external_device/external_device.h
View File

@ -104,7 +104,7 @@ struct DACEXTERNALDEVICE
NvBool Scheduled;
NvU32 TimeOut;
TMR_EVENT *pTimerEvent;
TMR_EVENT *pTimerEvents[NV_MAX_DEVICES];
} WatchdogControl;
};
@ -126,6 +126,7 @@ NV_STATUS readregu008_extdevice(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*);
NV_STATUS readregu008_extdeviceTargeted(OBJGPU *, PDACEXTERNALDEVICE, NvU8, NvU8*);
void extdevDestroy (OBJGPU *);
NV_STATUS extdevServiceWatchdog(OBJGPU *, OBJTMR *, TMR_EVENT *);
NV_STATUS extdevScheduleWatchdog(OBJGPU *, PDACEXTERNALDEVICE);
NV_STATUS extdevCancelWatchdog (OBJGPU *, PDACEXTERNALDEVICE);
void extdevGsyncService(OBJGPU *, NvU8, NvU8, NvU8, NvBool);

8
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@ -54,6 +54,13 @@ typedef struct GSP_VF_INFO
NvBool b64bitBar2;
} GSP_VF_INFO;
// Cache config registers from pcie space
typedef struct
{
// Link capabilities
NvU32 linkCap;
} GSP_PCIE_CONFIG_REG;
typedef struct GspSMInfo_t
{
NvU32 version;
@ -210,6 +217,7 @@ typedef struct GspSystemInfo
GSP_VF_INFO gspVFInfo;
NvBool bIsPrimary;
NvBool isGridBuild;
GSP_PCIE_CONFIG_REG pcieConfigReg;
NvU32 gridBuildCsp;
NvBool bPreserveVideoMemoryAllocations;
NvBool bTdrEventSupported;

66
src/nvidia/src/kernel/gpu/arch/blackwell/kern_gpu_gb100.c
View File

@ -34,6 +34,9 @@
#include "os/os.h"
#include "nverror.h"
#include "published/blackwell/gb100/dev_boot.h"
#include "published/blackwell/gb100/dev_boot_addendum.h"
#include "published/blackwell/gb100/dev_pcfg_pf0.h"
//
@ -145,6 +148,38 @@ gpuGetChildrenPresent_GB102(OBJGPU *pGpu, NvU32 *pNumEntries)
return gpuChildrenPresent_GB102;
}
/*!
* @brief Read the non-private registers on vGPU through mirror space
*
* @param[in] pGpu GPU object pointer
* @param[in] index Register offset in PCIe config space
* @param[out] pData Value of the register
*
* @returns NV_OK on success
*/
NV_STATUS
gpuReadPassThruConfigReg_GB100
(
OBJGPU *pGpu,
NvU32 index,
NvU32 *pData
)
{
NvU32 domain = gpuGetDomain(pGpu);
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU8 function = 0;
if (pGpu->hPci == NULL)
{
pGpu->hPci = osPciInitHandle(domain, bus, device, function, NULL, NULL);
}
*pData = osPciReadDword(pGpu->hPci, index);
return NV_OK;
}
/*!
* @brief Get GPU ID based on PCIE config reads.
* Also determine other properties of the PCIE capabilities.
@ -292,3 +327,34 @@ gpuHandleSecFault_GB100
0,
SEC_FAULT_ERROR);
}
/*!
* Check if CC bit has been set in the scratch register
*
* @param[in] pGpu GPU object pointer
*/
NvBool
gpuIsCCEnabledInHw_GB100
(
OBJGPU *pGpu
)
{
NvU32 val = GPU_REG_RD32(pGpu, NV_PMC_SCRATCH_RESET_2_CC);
return FLD_TEST_DRF(_PMC, _SCRATCH_RESET_2_CC, _MODE_ENABLED, _TRUE, val);
}
/*!
* Check if dev mode bit has been set in the scratch register
*
* @param[in] pGpu GPU object pointer
*/
NvBool
gpuIsDevModeEnabledInHw_GB100
(
OBJGPU *pGpu
)
{
NvU32 val = GPU_REG_RD32(pGpu, NV_PMC_SCRATCH_RESET_2_CC);
return FLD_TEST_DRF(_PMC, _SCRATCH_RESET_2_CC, _DEV_ENABLED, _TRUE, val);
}

2
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
View File

@ -93,7 +93,7 @@ gpuReadBusConfigReg_GH100
* @returns NV_OK on success
*/
NV_STATUS
gpuReadVgpuConfigReg_GH100
gpuReadPassThruConfigReg_GH100
(
OBJGPU *pGpu,
NvU32 index,

11
src/nvidia/src/kernel/gpu/bif/arch/blackwell/kernel_bif_gb100.c
View File

@ -750,6 +750,17 @@ kbifCacheMnocSupport_GB100
pKernelBif->bMnocAvailable = NV_FALSE;
if (IS_PASSTHRU(pGpu))
{
//
// Long story short, when in recovery mode, RM will never come into picture
// Conversely, if RM is up, that means we have the valid boot ROM image
// and thus MNOC capability will always be available
//
pKernelBif->bMnocAvailable = NV_TRUE;
return;
}
// Read vendorID from DVSEC
if (GPU_BUS_CFG_CYCLE_RD32(pGpu, NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1,
&regVal) != NV_OK)

8
src/nvidia/src/kernel/gpu/bif/kernel_bif.c
View File

@ -85,6 +85,9 @@ kbifConstructEngine_IMPL
// Cache VF info
kbifCacheVFInfo_HAL(pGpu, pKernelBif);
// Cache GPU link capabilities
kbifGetGpuLinkCapabilities(pGpu, pKernelBif);
// Used to track when the link has gone into Recovery, which can cause CEs.
pKernelBif->EnteredRecoverySinceErrorsLastChecked = NV_FALSE;
@ -842,9 +845,12 @@ kbifGetGpuLinkCapabilities_IMPL
if (NV_OK != GPU_BUS_CFG_RD32(pGpu, addrLinkCap, &data))
{
NV_PRINTF(LEVEL_ERROR, "Unable to read %x\n", addrLinkCap);
return 0;
data = 0;
}
// Cache link capabilities here to be used by GSP-RM
pKernelBif->pcieConfigReg.linkCap = data;
return data;
}

85
src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c
View File

@ -163,8 +163,6 @@ extdevConstruct_P2060
KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu);
NvU32 iface, head, i;
NvU32 numHeads = kdispGetNumHeads(pKernelDisplay);
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
NV_STATUS status;
if ( !extdevConstruct_Base(pGpu, pExternalDevice) )
{
@ -209,15 +207,6 @@ extdevConstruct_P2060
pThis->FrameCountData.enableFrmCmpMatchIntSlave = NV_FALSE;
pThis->FrameCountData.head = NV_P2060_MAX_HEADS_PER_GPU;
pThis->FrameCountData.iface = NV_P2060_MAX_IFACES_PER_GSYNC;
status = tmrEventCreate(pTmr,
&pThis->FrameCountData.pTimerEvent,
gsyncFrameCountTimerService_P2060,
pThis,
TMR_FLAG_RECUR);
if (status != NV_OK)
{
goto fail_tmr_event_create;
}
for (iface = 0; iface < NV_P2060_MAX_IFACES_PER_GSYNC; iface++)
{
@ -251,10 +240,6 @@ extdevConstruct_P2060
}
return pExternalDevice;
fail_tmr_event_create:
extdevDestroy_Base(pGpu, pExternalDevice);
return NULL;
}
/*
@ -535,9 +520,12 @@ gsyncAttachExternalDevice_P2060
OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys);
OBJGSYNC *pGsync = NULL;
OBJGPU *pOtherGpu = NULL;
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
DACP2060EXTERNALDEVICE *pThis, *pExt2060Temp;
PDACEXTERNALDEVICE pExtdev;
NvU8 i, id = 0, regCtrl2 = 0;
NvU32 iface, connector, uniqueId = 0, pOtherGpuId = 0, bSkipResetForVM = 0, index = 0;
NvU32 gpuInstance = gpuGetInstance(pGpu);
NvU32 tempIface;
NvBool bExtDevFound = NV_FALSE;
NV_STATUS rmStatus = NV_OK;
@ -664,7 +652,8 @@ gsyncAttachExternalDevice_P2060
}
}
pThis = (PDACP2060EXTERNALDEVICE)*ppExtdevs;
pExtdev = *ppExtdevs;
pThis = (PDACP2060EXTERNALDEVICE)pExtdev;
if (uniqueId == 0x0)
{
@ -699,6 +688,36 @@ gsyncAttachExternalDevice_P2060
//
connector = iface + 1;
//
// Create timer events per GPU attached to a DACEXTERNALDEVICE instance.
// These events should be deleted when a GPU instance decrements its
// reference to a DACEXTERNALDEVICE instance. This is not done in the base
// instance that utilizes the timer events since the base uses a nop
// attachment logic that will not be executed by the child instance types.
//
rmStatus = tmrEventCreate(pTmr,
&pExtdev->WatchdogControl.pTimerEvents[gpuInstance],
extdevServiceWatchdog,
pExtdev,
TMR_FLAG_RECUR);
if (rmStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "failed to create P2060 watchdog timer event.\n");
return NV_FALSE;
}
rmStatus = tmrEventCreate(pTmr,
&pThis->FrameCountData.pTimerEvents[gpuInstance],
gsyncFrameCountTimerService_P2060,
pThis,
TMR_FLAG_RECUR);
if (rmStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "failed to create P2060 frame count timer event.\n");
goto fail_tmr_event_create;
}
//
// If adding a check before the gsyncAttachGpu call and returning before
// that please add the following code:
@ -719,7 +738,7 @@ gsyncAttachExternalDevice_P2060
if (rmStatus != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "failed to attach P2060 gsync to gpu.\n");
return NV_FALSE;
goto fail_tmr_event_create;
}
if (pThis->ExternalDevice.deviceId == DAC_EXTERNAL_DEVICE_P2061)
@ -739,13 +758,26 @@ gsyncAttachExternalDevice_P2060
{
NV_PRINTF(LEVEL_ERROR,
"Failed to enable non-framelock interrupts on gsync GPU.\n");
return NV_FALSE;
goto fail_tmr_event_create;
}
pThis->isNonFramelockInterruptEnabled = NV_TRUE;
pThis->interruptEnabledInterface = iface;
}
return NV_TRUE;
fail_tmr_event_create:
if (pThis->FrameCountData.pTimerEvents[gpuInstance] != NULL)
{
tmrEventDestroy(pTmr, pThis->FrameCountData.pTimerEvents[gpuInstance]);
pThis->FrameCountData.pTimerEvents[gpuInstance] = NULL;
}
if (pExtdev->WatchdogControl.pTimerEvents[gpuInstance])
{
tmrEventDestroy(pTmr, pExtdev->WatchdogControl.pTimerEvents[gpuInstance]);
pExtdev->WatchdogControl.pTimerEvents[gpuInstance] = NULL;
}
return NV_FALSE;
}
/*
@ -771,9 +803,16 @@ extdevDestroy_P2060
{
if (pThis->Iface[iface].GpuInfo.gpuId == pGpu->gpuId)
{
NvU32 gpuInstance = gpuGetInstance(pGpu);
pThis->gpuAttachMask &= ~NVBIT(pGpu->gpuInstance);
pExternalDevice->ReferenceCount--;
tmrEventDestroy(pTmr, pThis->FrameCountData.pTimerEvents[gpuInstance]);
pThis->FrameCountData.pTimerEvents[gpuInstance] = NULL;
tmrEventDestroy(pTmr, pExternalDevice->WatchdogControl.pTimerEvents[gpuInstance]);
pExternalDevice->WatchdogControl.pTimerEvents[gpuInstance] = NULL;
if (pThis->Iface[iface].GpuInfo.connected)
{
if (pExternalDevice->ReferenceCount == 0)
@ -833,10 +872,8 @@ extdevDestroy_P2060
cleanup:
if (pExternalDevice->ReferenceCount == 0)
{
// And continue the chain running.
tmrEventDestroy(pTmr, pThis->FrameCountData.pTimerEvent);
pThis->FrameCountData.pTimerEvent = NULL;
extdevDestroy_Base(pGpu, pExternalDevice);
// And continue the chain running.
extdevDestroy_Base(pGpu, pExternalDevice);
}
}
@ -5032,7 +5069,7 @@ NV_STATUS gsyncFrameCountTimerService_P2060
pThis = (PDACP2060EXTERNALDEVICE)pGsync->pExtDev;
// disable the timer callback
tmrEventCancel(pTmr, pThis->FrameCountData.pTimerEvent);
tmrEventCancel(pTmr, pThis->FrameCountData.pTimerEvents[gpuGetInstance(pGpu)]);
//
// read the gsync and gpu frame count values.Cache the difference between them.
@ -5290,7 +5327,7 @@ gsyncUpdateFrameCount_P2060
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
status = tmrEventScheduleRel(pTmr,
pThis->FrameCountData.pTimerEvent,
pThis->FrameCountData.pTimerEvents[gpuGetInstance(pGpu)],
(NV_P2060_FRAME_COUNT_TIMER_INTERVAL / 5));
if (status == NV_OK)

82
src/nvidia/src/kernel/gpu/external_device/kern_external_device.c
View File

@ -47,44 +47,12 @@ PDACEXTERNALDEVICE extdevGetExtDev
return NULL;
}
// Service the Watchdog
static
NV_STATUS extdevServiceWatchdog
(
OBJGPU *pGpu,
OBJTMR *pTmr,
TMR_EVENT *pTmrEvent
)
{
PDACEXTERNALDEVICE pExtDevice = NULL;
PDACEXTERNALDEVICEIFACE pdsif = NULL;
pExtDevice = extdevGetExtDev(pGpu);
// No gsync and no gvo, return NV_ERR_GENERIC
if (!pExtDevice)
{
return NV_ERR_GENERIC;
}
pdsif = pExtDevice->pI;
// lower the flag, since it's no longer waiting to run
pExtDevice->WatchdogControl.Scheduled = NV_FALSE;
return pdsif->Watchdog(pGpu, pTmr, pExtDevice);
}
//
// RMCONFIG: when the EXTDEV feature is disabled there are #defines in
// extdev.h that stub this routine out.
//
void extdevDestroy_Base(OBJGPU *pGpu, PDACEXTERNALDEVICE pExternalDevice)
{
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
tmrEventDestroy(pTmr, pExternalDevice->WatchdogControl.pTimerEvent);
pExternalDevice->WatchdogControl.pTimerEvent = NULL;
portMemFree(pExternalDevice->pI);
}
@ -128,32 +96,13 @@ extdevConstruct_Base
// Init data members
{
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
NV_STATUS status;
pThis->MaxGpus = 1; // default, only connect to 1 gpu
pThis->WatchdogControl.Scheduled = NV_FALSE;
pThis->WatchdogControl.TimeOut = 1000000000; // 1 second in ns
status = tmrEventCreate(pTmr,
&pThis->WatchdogControl.pTimerEvent,
extdevServiceWatchdog,
pThis,
TMR_FLAG_RECUR);
if (status != NV_OK)
{
goto fail_tmr_event_create;
}
}
return pThis;
fail_tmr_event_create:
portMemFree(pThis->pI);
pThis->pI = NULL;
return NULL;
}
void
@ -177,6 +126,33 @@ extdevDestroy(OBJGPU *pGpu)
}
}
// Service the Watchdog
NV_STATUS extdevServiceWatchdog
(
OBJGPU *pGpu,
OBJTMR *pTmr,
TMR_EVENT *pTmrEvent
)
{
PDACEXTERNALDEVICE pExtDevice = NULL;
PDACEXTERNALDEVICEIFACE pdsif = NULL;
pExtDevice = extdevGetExtDev(pGpu);
// No gsync and no gvo, return NV_ERR_GENERIC
if (!pExtDevice)
{
return NV_ERR_GENERIC;
}
pdsif = pExtDevice->pI;
// lower the flag, since it's no longer waiting to run
pExtDevice->WatchdogControl.Scheduled = NV_FALSE;
return pdsif->Watchdog(pGpu, pTmr, pExtDevice);
}
// Schedule Watchdog
NV_STATUS extdevScheduleWatchdog
(
@ -193,7 +169,7 @@ NV_STATUS extdevScheduleWatchdog
pExtDevice->WatchdogControl.Scheduled = NV_TRUE;
rmStatus = tmrEventScheduleRel(pTmr,
pExtDevice->WatchdogControl.pTimerEvent,
pExtDevice->WatchdogControl.pTimerEvents[gpuGetInstance(pGpu)],
pExtDevice->WatchdogControl.TimeOut);
if (NV_OK != rmStatus)
@ -215,7 +191,7 @@ NV_STATUS extdevCancelWatchdog
OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
// cancel first...
tmrEventCancel(pTmr, pExtDevice->WatchdogControl.pTimerEvent);
tmrEventCancel(pTmr, pExtDevice->WatchdogControl.pTimerEvents[gpuGetInstance(pGpu)]);
// ... then lower the flag!
pExtDevice->WatchdogControl.Scheduled = NV_FALSE;

2
src/nvidia/src/kernel/gpu/gpu.c
View File

@ -5199,7 +5199,7 @@ gpuReadBusConfigCycle_IMPL
if (IS_PASSTHRU(pGpu) && !bIsCCFeatureEnabled)
{
gpuReadVgpuConfigReg_HAL(pGpu, index, pData);
gpuReadPassThruConfigReg_HAL(pGpu, index, pData);
}
else
{

11
src/nvidia/src/kernel/gpu/timer/timer.c
View File

@ -1593,6 +1593,17 @@ tmrStatePreInitLocked_IMPL
return NV_OK;
}
NV_STATUS
tmrStateInitLocked_IMPL
(
OBJGPU *pGpu,
OBJTMR *pTmr
)
{
return NV_OK;
}
/*!
* TODO: document
*/

17
src/nvidia/src/kernel/rmapi/client_resource.c
View File

@ -4555,6 +4555,23 @@ cliresCtrlCmdSyncGpuBoostGroupInfo_IMPL
return status;
}
NV_STATUS
cliresCtrlCmdVgpuVfioNotifyRMStatus_IMPL
(
RmClientResource *pRmCliRes,
NV0000_CTRL_VGPU_VFIO_NOTIFY_RM_STATUS_PARAMS *pVgpuStatusParams
)
{
if (osIsVgpuVfioPresent() != NV_OK)
return NV_ERR_NOT_SUPPORTED;
osWakeRemoveVgpu(pVgpuStatusParams->gpuId, pVgpuStatusParams->returnStatus);
return NV_OK;
}
NV_STATUS
cliresCtrlCmdVgpuGetVgpuVersion_IMPL
(

3
src/nvidia/src/kernel/vgpu/rpc.c
View File

@ -8874,6 +8874,9 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
// Cache FLR and 64b Bar0 support
rpcInfo->bFlrSupported = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_FLR_SUPPORTED);
rpcInfo->b64bBar0Supported = pKernelBif->getProperty(pKernelBif, PDB_PROP_KBIF_64BIT_BAR0_SUPPORTED);
// Cache pcie link capabilities from config space
rpcInfo->pcieConfigReg.linkCap = pKernelBif->pcieConfigReg.linkCap;
}
if (IS_SIMULATION(pGpu))

2
version.mk
View File

@ -1,4 +1,4 @@
NVIDIA_VERSION = 560.28.03
NVIDIA_VERSION = 560.31.02
# This file.
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))