535.86.10
This commit is contained in:
parent
337e28efda
commit
29f830f1bb
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@ -2,6 +2,8 @@
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## Release 535 Entries
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### [535.86.10] 2023-07-31
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### [535.86.05] 2023-07-18
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### [535.54.03] 2023-06-14
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@ -1,7 +1,7 @@
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# NVIDIA Linux Open GPU Kernel Module Source
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This is the source release of the NVIDIA Linux open GPU kernel modules,
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version 535.86.05.
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version 535.86.10.
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## How to Build
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@ -17,7 +17,7 @@ as root:
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Note that the kernel modules built here must be used with GSP
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firmware and user-space NVIDIA GPU driver components from a corresponding
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535.86.05 driver release. This can be achieved by installing
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535.86.10 driver release. This can be achieved by installing
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the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
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option. E.g.,
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@ -180,7 +180,7 @@ software applications.
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## Compatible GPUs
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The open-gpu-kernel-modules can be used on any Turing or later GPU
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(see the table below). However, in the 535.86.05 release,
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(see the table below). However, in the 535.86.10 release,
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GeForce and Workstation support is still considered alpha-quality.
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To enable use of the open kernel modules on GeForce and Workstation GPUs,
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@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
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parameter to 1. For more details, see the NVIDIA GPU driver end user
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README here:
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https://us.download.nvidia.com/XFree86/Linux-x86_64/535.86.05/README/kernel_open.html
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https://us.download.nvidia.com/XFree86/Linux-x86_64/535.86.10/README/kernel_open.html
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In the below table, if three IDs are listed, the first is the PCI Device
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ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
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@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
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EXTRA_CFLAGS += -I$(src)
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EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
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EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.86.05\"
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.86.10\"
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ifneq ($(SYSSRCHOST1X),)
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EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
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@ -2703,7 +2703,15 @@ static void init_channel_manager_conf(uvm_channel_manager_t *manager)
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// access through the bus, because no cache coherence message is exchanged.
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if (uvm_gpu_is_coherent(gpu->parent)) {
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manager->conf.gpfifo_loc = UVM_BUFFER_LOCATION_SYS;
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manager->conf.gpput_loc = UVM_BUFFER_LOCATION_SYS;
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// On GPUs with limited ESCHED addressing range, e.g., Volta on P9, RM
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// cannot guarantee that USERD/GPPUT physical address is accessible by
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// ESCHED. We set GPPUT location to vidmem where physical addresses are
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// all accessible by ESCHED. We use the max_host_va as a proxy for the
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// PA limitation, since all architectures with 40b VA limits also have
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// 40b PA limits.
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manager->conf.gpput_loc = gpu->parent->max_host_va == (1ull << 40) ? UVM_BUFFER_LOCATION_VID :
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UVM_BUFFER_LOCATION_SYS;
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}
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else {
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// By default we place GPFIFO and GPPUT on vidmem as it potentially has
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@ -46,11 +46,6 @@ NvlStatus nvlink_lib_unload(void);
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*/
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NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params);
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/*
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* Gets number of devices with type deviceType
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*/
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NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
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#ifdef __cplusplus
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}
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#endif
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@ -43,11 +43,11 @@
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#endif
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r536_62-214"
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#define NV_BUILD_CHANGELIST_NUM (33069717)
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#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r536_62-219"
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#define NV_BUILD_CHANGELIST_NUM (33114094)
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#define NV_BUILD_TYPE "Official"
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r536_62-214"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33069717)
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#define NV_BUILD_NAME "rel/gpu_drv/r535/r536_62-219"
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#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33114094)
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#else /* Windows builds */
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#define NV_BUILD_BRANCH_VERSION "r536_62-3"
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@ -4,7 +4,7 @@
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#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
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(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
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#define NV_VERSION_STRING "535.86.05"
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#define NV_VERSION_STRING "535.86.10"
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#else
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@ -439,11 +439,6 @@ NvlStatus nvlink_lib_register_link(nvlink_device *dev, nvlink_link *link);
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*/
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NvlStatus nvlink_lib_unregister_link(nvlink_link *link);
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/*
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* Gets number of devices with type deviceType
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*/
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NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
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/************************************************************************************************/
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/******************************* NVLink link management functions *******************************/
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@ -46,11 +46,6 @@ NvlStatus nvlink_lib_unload(void);
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*/
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NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params);
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/*
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* Gets number of devices with type deviceType
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*/
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NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
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#ifdef __cplusplus
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}
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#endif
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@ -171,6 +171,7 @@ nvlink_lib_is_registerd_device_with_reduced_config(void)
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{
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NvlStatus lock_status = NVL_SUCCESS;
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nvlink_device *dev = NULL;
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NvBool bIsReducedConfg = NV_FALSE;
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// Acquire top-level lock
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lock_status = nvlink_lib_top_lock_acquire();
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{
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if (dev->bReducedNvlinkConfig == NV_TRUE)
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{
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return NV_TRUE;
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bIsReducedConfg = NV_TRUE;
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break;
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}
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}
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// Release and free top-level lock
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// Release top-level lock
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nvlink_lib_top_lock_release();
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nvlink_lib_top_lock_free();
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return NV_FALSE;
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}
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/*
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* Get the number of devices that have the device type deviceType
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*/
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NvlStatus
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nvlink_lib_return_device_count_by_type
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(
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NvU32 deviceType,
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NvU32 *numDevices
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)
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{
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NvlStatus lock_status = NVL_SUCCESS;
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nvlink_device *dev = NULL;
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NvU32 device_count = 0;
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if (nvlink_lib_is_initialized())
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{
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// Acquire top-level lock
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lock_status = nvlink_lib_top_lock_acquire();
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if (lock_status != NVL_SUCCESS)
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{
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NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
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"%s: Failed to acquire top-level lock\n",
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__FUNCTION__));
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return lock_status;
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}
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// Top-level lock is now acquired
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// Loop through device list
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FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node)
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{
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if (dev->type == deviceType)
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{
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device_count++;
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}
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}
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// Release top-level lock
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nvlink_lib_top_lock_release();
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}
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*numDevices = device_count;
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return NVL_SUCCESS;
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return bIsReducedConfg;
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}
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@ -583,12 +583,9 @@ typedef struct
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NvBool bDisabledRemoteEndLinkMaskCached;
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} lr10_device;
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#define NVSWITCH_NUM_DEVICES_PER_DELTA_LR10 6
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typedef struct {
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NvU32 switchPhysicalId;
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NvU64 accessLinkMask;
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NvU64 trunkLinkMask;
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NvU64 linkMask;
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} lr10_links_connected_to_disabled_remote_end;
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#define NVSWITCH_GET_CHIP_DEVICE_LR10(_device) \
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#include "nvswitch/lr10/dev_nvlipt_ip.h"
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#include "nvswitch/lr10/dev_nport_ip.h"
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#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 12 // This must be incremented if any entries are added to the array below
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#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 8 // This must be incremented if any entries are added to the array below
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lr10_links_connected_to_disabled_remote_end nvswitchDisconnetedRemoteLinkMasks[] =
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{
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{
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0x8, // switchPhysicalId
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0x56A000500, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x8, // switchPhysicalId
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0x56A000500 //linkMask
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},
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{
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0x9, // switchPhysicalId
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0x509009900, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x9, // switchPhysicalId
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0x509009900 //linkMask
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},
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{
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0xa, // switchPhysicalId
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0x0, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0xb, // switchPhysicalId
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0x56A000600 //linkMask
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},
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{
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0xb, // switchPhysicalId
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0x56A000600, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0xc, // switchPhysicalId
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0x4A9009400 //linkMask
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},
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{
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0xc, // switchPhysicalId
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0x4A9009400, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x18, // switchPhysicalId
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0x56A000500 //linkMask
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},
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{
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0xd, // switchPhysicalId
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0x0, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x19, // switchPhysicalId
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0x509009900 //linkMask
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},
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{
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0x18, // switchPhysicalId
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0x56A000500, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x1b, // switchPhysicalId
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0x56A000600 //linkMask
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},
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{
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0x19, // switchPhysicalId
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0x509009900, // accessLinkMask
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0xFF00FF // trunkLinkMask
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},
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{
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0x1a, // switchPhysicalId
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0x0, // accessLinkMask
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0xFF00FF // trunkLinkMask
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},
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{
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0x1b, // switchPhysicalId
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0x56A000600, // accessLinkMask
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0xFF00FF // trunkLinkMask
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},
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{
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0x1c, // switchPhysicalId
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0x4A9009400, // accessLinkMask
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0xFF00FF // trunkLinkMask
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},
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{
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0x1d, // switchPhysicalId
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0x0, // accessLinkMask
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0xFF00FF // trunkLinkMask
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0x1c, // switchPhysicalId
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0x4A9009400 //linkMask
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},
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};
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ct_assert(sizeof(nvswitchDisconnetedRemoteLinkMasks)/sizeof(lr10_links_connected_to_disabled_remote_end) == NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK);
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if (nvswitch_does_link_need_termination_enabled(device, link))
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{
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if (mode == NVLINK_LINKSTATE_INITPHASE1)
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{
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status = nvswitch_link_termination_setup(device, link);
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NvU32 val;
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NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL;
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NVSWITCH_BIOS_NVLINK_CONFIG *bios_config;
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NvlStatus status;
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lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
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bios_config = nvswitch_get_bios_nvlink_config(device);
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if ((bios_config == NULL) || (bios_config->bit_address == 0))
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__FUNCTION__, link->linkNumber);
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return;
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}
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val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE,
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_DISABLED, val);
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NVSWITCH_LINK_WR32_LR10(device, link->linkNumber,
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NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val);
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status = nvswitch_link_termination_setup(device, link);
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if (status != NVL_SUCCESS)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: Failed to enable termination on link #%d\n", __FUNCTION__, link->linkNumber);
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return;
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}
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// add link to disabledRemoteEndLinkMask
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chip_device->disabledRemoteEndLinkMask |= NVBIT64(link->linkNumber);
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// Set link to invalid and unregister from corelib
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device->link[link->linkNumber].valid = NV_FALSE;
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nvlink_lib_unregister_link(link);
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nvswitch_destroy_link(link);
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return;
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}
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@ -2518,8 +2488,6 @@ nvswitch_does_link_need_termination_enabled_lr10
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NvU32 i;
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NvU32 physicalId;
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lr10_device *chip_device;
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NvU32 numNvswitches;
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NvlStatus status;
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physicalId = nvswitch_read_physical_id(device);
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chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
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chip_device->disabledRemoteEndLinkMask = 0;
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if (nvlink_lib_is_registerd_device_with_reduced_config())
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{
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for (i = 0; i < NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK; ++i)
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for (i = 0; i < NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK; ++i)
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{
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if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId)
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{
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if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId)
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{
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chip_device->disabledRemoteEndLinkMask |=
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nvswitchDisconnetedRemoteLinkMasks[i].accessLinkMask;
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status = nvlink_lib_return_device_count_by_type(NVLINK_DEVICE_TYPE_NVSWITCH, &numNvswitches);
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if (status != NVL_SUCCESS)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: Failed to get nvswitch device count!\n", __FUNCTION__);
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break;
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}
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if (numNvswitches <= NVSWITCH_NUM_DEVICES_PER_DELTA_LR10)
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{
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chip_device->disabledRemoteEndLinkMask |=
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nvswitchDisconnetedRemoteLinkMasks[i].trunkLinkMask;
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}
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break;
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}
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chip_device->disabledRemoteEndLinkMask =
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nvswitchDisconnetedRemoteLinkMasks[i].linkMask;
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break;
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}
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}
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}
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chip_device->bDisabledRemoteEndLinkMaskCached = NV_TRUE;
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}
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@ -1006,9 +1006,6 @@ struct OBJGPU {
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NvU32 subdeviceInstance;
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NvS32 numaNodeId;
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_GPU_UUID gpuUuid;
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NvU32 gpuPhysicalId;
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NvU32 gpuTerminatedLinkMask;
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NvBool gpuLinkTerminationEnabled;
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NvBool gspRmInitialized;
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_GPU_PCIE_PEER_CLIQUE pciePeerClique;
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NvU32 i2cPortForExtdev;
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#define gpuUpdateUserSharedData_HAL(pGpu) gpuUpdateUserSharedData(pGpu)
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void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0);
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#ifdef __nvoc_gpu_h_disabled
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static inline void gpuGetTerminatedLinkMask(struct OBJGPU *pGpu, NvU32 arg0) {
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NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
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}
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#else //__nvoc_gpu_h_disabled
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#define gpuGetTerminatedLinkMask(pGpu, arg0) gpuGetTerminatedLinkMask_GA100(pGpu, arg0)
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#endif //__nvoc_gpu_h_disabled
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#define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0)
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NV_STATUS gpuJtVersionSanityCheck_TU102(struct OBJGPU *pGpu);
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@ -1,4 +1,4 @@
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NVIDIA_VERSION = 535.86.05
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NVIDIA_VERSION = 535.86.10
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# This file.
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VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
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