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525.147.05

This commit is contained in:
Bernhard Stoeckner 2023-10-31 14:37:42 +01:00
parent 1f3ce1beab
commit 207a166fc3
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GPG Key ID: 7D23DC2750FAC2E1
114 changed files with 7252 additions and 842 deletions
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6
CHANGELOG.md
View File

@ -2,8 +2,14 @@
## Release 525 Entries
### [525.147.05] 2023-10-31
### [525.125.06] 2023-06-26
#### Fixed
- Fix nvidia_p2p_get_pages(): Fix double-free in register-callback error path, [#557](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/557) by @BrendanCunningham
### [525.116.04] 2023-05-09
### [525.116.03] 2023-04-25

15
README.md
View File

@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 525.125.06.
version 525.147.05.
## How to Build
@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
525.125.06 driver release. This can be achieved by installing
525.147.05 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@ -167,7 +167,7 @@ for the target kernel.
## Compatible GPUs
The open-gpu-kernel-modules can be used on any Turing or later GPU
(see the table below). However, in the 525.125.06 release,
(see the table below). However, in the 525.147.05 release,
GeForce and Workstation support is still considered alpha-quality.
To enable use of the open kernel modules on GeForce and Workstation GPUs,
@ -175,7 +175,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
parameter to 1. For more details, see the NVIDIA GPU driver end user
README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/525.125.06/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/525.147.05/README/kernel_open.html
In the below table, if three IDs are listed, the first is the PCI Device
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@ -645,12 +645,15 @@ Subsystem Device ID.
| NVIDIA A100-SXM4-80GB | 20B2 10DE 147F |
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1622 |
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1623 |
| NVIDIA PG509-210 | 20B2 10DE 1625 |
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A7 |
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A8 |
| NVIDIA A100 80GB PCIe | 20B5 10DE 1533 |
| NVIDIA A100 80GB PCIe | 20B5 10DE 1642 |
| NVIDIA PG506-232 | 20B6 10DE 1492 |
| NVIDIA A30 | 20B7 10DE 1532 |
| NVIDIA A30 | 20B7 10DE 1804 |
| NVIDIA A30 | 20B7 10DE 1852 |
| NVIDIA A100-PCIE-40GB | 20F1 10DE 145F |
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179B |
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179C |
@ -821,6 +824,7 @@ Subsystem Device ID.
| NVIDIA GeForce RTX 4090 Laptop GPU | 2717 |
| NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 |
| NVIDIA GeForce RTX 4090 Laptop GPU | 2757 |
| NVIDIA RTX 5000 Ada Generation Embedded GPU | 2770 |
| NVIDIA GeForce RTX 4070 Ti | 2782 |
| NVIDIA GeForce RTX 4070 | 2786 |
| NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 |
@ -834,11 +838,14 @@ Subsystem Device ID.
| NVIDIA RTX 3500 Ada Generation Laptop GPU | 27BB |
| NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 |
| NVIDIA GeForce RTX 4060 Ti | 2803 |
| NVIDIA GeForce RTX 4060 Ti | 2805 |
| NVIDIA GeForce RTX 4070 Laptop GPU | 2820 |
| NVIDIA RTX 3000 Ada Generation Laptop GPU | 2838 |
| NVIDIA GeForce RTX 4070 Laptop GPU | 2860 |
| NVIDIA GeForce RTX 4060 | 2882 |
| NVIDIA GeForce RTX 4060 Laptop GPU | 28A0 |
| NVIDIA GeForce RTX 4050 Laptop GPU | 28A1 |
| NVIDIA RTX 2000 Ada Generation Laptop GPU | 28B8 |
| NVIDIA GeForce RTX 4060 Laptop GPU | 28E0 |
| NVIDIA GeForce RTX 4050 Laptop GPU | 28E1 |
| NVIDIA RTX 2000 Ada Generation Embedded GPU | 28F8 |

3
kernel-open/Kbuild
View File

@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.125.06\"
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"525.147.05\"
EXTRA_CFLAGS += -Wno-unused-function
@ -268,6 +268,7 @@ NV_HEADER_PRESENCE_TESTS = \
asm/opal-api.h \
sound/hdaudio.h \
asm/pgtable_types.h \
asm/page.h \
linux/stringhash.h \
linux/dma-map-ops.h \
rdma/peer_mem.h \

1
kernel-open/common/inc/nv-hypervisor.h
View File

@ -57,6 +57,7 @@ typedef struct
void *waitQueue;
void *nv;
NvU32 *vgpuTypeIds;
NvU8 **vgpuNames;
NvU32 numVgpuTypes;
NvU32 domain;
NvU8 bus;

59
kernel-open/common/inc/nv-mm.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -36,12 +36,21 @@ typedef int vm_fault_t;
* pin_user_pages() was added by commit eddb1c228f7951d399240
* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6-rc1 (2020-01-30)
*
* Removed vmas parameter from pin_user_pages() by commit 40896a02751
* ("mm/gup: remove vmas parameter from pin_user_pages()")
* in linux-next, expected in v6.5-rc1 (2023-05-17)
*
*/
#include <linux/mm.h>
#include <linux/sched.h>
#if defined(NV_PIN_USER_PAGES_PRESENT)
#define NV_PIN_USER_PAGES pin_user_pages
#if defined(NV_PIN_USER_PAGES_HAS_ARGS_VMAS)
#define NV_PIN_USER_PAGES pin_user_pages
#else
#define NV_PIN_USER_PAGES(start, nr_pages, gup_flags, pages, vmas) \
pin_user_pages(start, nr_pages, gup_flags, pages)
#endif // NV_PIN_USER_PAGES_HAS_ARGS_VMAS
#define NV_UNPIN_USER_PAGE unpin_user_page
#else
#define NV_PIN_USER_PAGES NV_GET_USER_PAGES
@ -64,11 +73,18 @@ typedef int vm_fault_t;
* commit 8e50b8b07f462ab4b91bc1491b1c91bd75e4ad40 which cherry-picked the
* replacement of the write and force parameters with gup_flags
*
* Removed vmas parameter from get_user_pages() by commit 7bbf9c8c99
* ("mm/gup: remove unused vmas parameter from get_user_pages()")
* in linux-next, expected in v6.5-rc1 (2023-05-17)
*
*/
#if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS)
#define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \
get_user_pages(start, nr_pages, flags, pages)
#elif defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS)
#define NV_GET_USER_PAGES get_user_pages
#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS)
#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS)
#define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \
get_user_pages(current, current->mm, start, nr_pages, flags, pages, vmas)
#else
@ -81,13 +97,13 @@ typedef int vm_fault_t;
int write = flags & FOLL_WRITE;
int force = flags & FOLL_FORCE;
#if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE)
#if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS)
return get_user_pages(start, nr_pages, write, force, pages, vmas);
#else
// NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE
// NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS
return get_user_pages(current, current->mm, start, nr_pages, write,
force, pages, vmas);
#endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE
#endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS
}
#endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS
@ -100,15 +116,22 @@ typedef int vm_fault_t;
* 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code")
* in v5.9-rc1 (2020-08-11). *
*
* Removed unused vmas parameter from pin_user_pages_remote() by commit
* 83bcc2e132("mm/gup: remove unused vmas parameter from pin_user_pages_remote()")
* in linux-next, expected in v6.5-rc1 (2023-05-14)
*
*/
#if defined(NV_PIN_USER_PAGES_REMOTE_PRESENT)
#if defined (NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK)
#if defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS)
#define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked)
#else
#elif defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS)
#define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote
#endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK
#else
#define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
pin_user_pages_remote(mm, start, nr_pages, flags, pages, locked)
#endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS
#else
#define NV_PIN_USER_PAGES_REMOTE NV_GET_USER_PAGES_REMOTE
#endif // NV_PIN_USER_PAGES_REMOTE_PRESENT
@ -135,22 +158,30 @@ typedef int vm_fault_t;
* commit 64019a2e467a ("mm/gup: remove task_struct pointer for
* all gup code") in v5.9-rc1 (2020-08-11).
*
* Removed vmas parameter from get_user_pages_remote() by commit a4bde14d549
* ("mm/gup: remove vmas parameter from get_user_pages_remote()")
* in linux-next, expected in v6.5-rc1 (2023-05-14)
*
*/
#if defined(NV_GET_USER_PAGES_REMOTE_PRESENT)
#if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED)
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
get_user_pages_remote(mm, start, nr_pages, flags, pages, locked)
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS)
#define NV_GET_USER_PAGES_REMOTE get_user_pages_remote
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED)
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS)
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked)
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS)
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS)
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas)
#else
// NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE
// NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS
static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
unsigned long start,
unsigned long nr_pages,
@ -167,7 +198,7 @@ typedef int vm_fault_t;
}
#endif // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED
#else
#if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE)
#if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS)
static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
unsigned long start,
unsigned long nr_pages,
@ -185,7 +216,7 @@ typedef int vm_fault_t;
#else
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
get_user_pages(NULL, mm, start, nr_pages, flags, pages, vmas)
#endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE
#endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS
#endif // NV_GET_USER_PAGES_REMOTE_PRESENT
/*

327
kernel-open/conftest.sh
View File

@ -450,6 +450,9 @@ compile_test() {
#if defined(NV_ASM_PGTABLE_TYPES_H_PRESENT)
#include <asm/pgtable_types.h>
#endif
#if defined(NV_ASM_PAGE_H_PRESENT)
#include <asm/page.h>
#endif
#include <asm/set_memory.h>
#else
#include <asm/cacheflush.h>
@ -472,6 +475,9 @@ compile_test() {
#if defined(NV_ASM_PGTABLE_TYPES_H_PRESENT)
#include <asm/pgtable_types.h>
#endif
#if defined(NV_ASM_PAGE_H_PRESENT)
#include <asm/page.h>
#endif
#include <asm/set_memory.h>
#else
#include <asm/cacheflush.h>
@ -529,6 +535,9 @@ compile_test() {
#if defined(NV_ASM_PGTABLE_TYPES_H_PRESENT)
#include <asm/pgtable_types.h>
#endif
#if defined(NV_ASM_PAGE_H_PRESENT)
#include <asm/page.h>
#endif
#include <asm/set_memory.h>
#else
#include <asm/cacheflush.h>
@ -556,6 +565,9 @@ compile_test() {
#if defined(NV_ASM_PGTABLE_TYPES_H_PRESENT)
#include <asm/pgtable_types.h>
#endif
#if defined(NV_ASM_PAGE_H_PRESENT)
#include <asm/page.h>
#endif
#include <asm/set_memory.h>
#else
#include <asm/cacheflush.h>
@ -959,9 +971,9 @@ compile_test() {
compile_check_conftest "$CODE" "NV_VFIO_MIGRATION_OPS_HAS_MIGRATION_GET_DATA_SIZE" "" "types"
;;
mdev_parent)
mdev_parent_ops)
#
# Determine if the struct mdev_parent type is present.
# Determine if the struct mdev_parent_ops type is present.
#
# Added by commit 42930553a7c1 ("vfio-mdev: de-polute the
# namespace, rename parent_device & parent_ops") in v4.10
@ -969,12 +981,28 @@ compile_test() {
CODE="
#include <linux/pci.h>
#include <linux/mdev.h>
struct mdev_parent_ops conftest_mdev_parent;
struct mdev_parent_ops conftest_mdev_parent_ops;
"
compile_check_conftest "$CODE" "NV_MDEV_PARENT_OPS_STRUCT_PRESENT" "" "types"
;;
mdev_parent)
#
# Determine if the struct mdev_parent type is present.
#
# Added by commit 89345d5177aa ("vfio/mdev: embedd struct mdev_parent in
# the parent data structure") in v6.1
#
CODE="
#include <linux/pci.h>
#include <linux/mdev.h>
struct mdev_parent conftest_mdev_parent;
"
compile_check_conftest "$CODE" "NV_MDEV_PARENT_STRUCT_PRESENT" "" "types"
;;
mdev_parent_dev)
#
# Determine if mdev_parent_dev() function is present or not
@ -992,6 +1020,23 @@ compile_test() {
compile_check_conftest "$CODE" "NV_MDEV_PARENT_DEV_PRESENT" "" "functions"
;;
vfio_free_device)
#
# Determine if vfio_free_device() function is present or not
#
# Removed by commit 913447d06f03 ("vfio: Remove vfio_free_device")
# in v6.2
#
CODE="
#include <linux/pci.h>
#include <linux/vfio.h>
void conftest_vfio_free_device() {
vfio_free_device();
}"
compile_check_conftest "$CODE" "NV_VFIO_FREE_DEVICE_PRESENT" "" "functions"
;;
mdev_from_dev)
#
# Determine if mdev_from_dev() function is present or not.
@ -1164,7 +1209,6 @@ compile_test() {
compile_check_conftest "$CODE" "NV_VFIO_UNINIT_GROUP_DEV_PRESENT" "" "functions"
;;
vfio_pci_core_available)
# Determine if VFIO_PCI_CORE is available
#
@ -1187,6 +1231,23 @@ compile_test() {
compile_check_conftest "$CODE" "NV_VFIO_PCI_CORE_PRESENT" "" "generic"
;;
vfio_alloc_device)
#
# Determine if vfio_alloc_device() function is present or not.
#
# Added by commit cb9ff3f3b84c (vfio: Add helpers for unifying vfio_device
# life cycle) in v6.1
#
CODE="
#include <linux/vfio.h>
void conftest_vfio_alloc_device() {
vfio_alloc_device();
}"
compile_check_conftest "$CODE" "NV_VFIO_ALLOC_DEVICE_PRESENT" "" "functions"
;;
vfio_register_emulated_iommu_dev)
#
# Determine if vfio_register_emulated_iommu_dev() function is present or not.
@ -2254,6 +2315,10 @@ compile_test() {
# commit 768ae309a961 ("mm: replace get_user_pages() write/force
# parameters with gup_flags") in v4.9 (2016-10-13)
#
# Removed vmas parameter from get_user_pages() by commit 7bbf9c8c99
# ("mm/gup: remove unused vmas parameter from get_user_pages()")
# in linux-next, expected in v6.5-rc1
#
# linux-4.4.168 cherry-picked commit 768ae309a961 without
# c12d2da56d0e which is covered in Conftest #3.
#
@ -2263,22 +2328,28 @@ compile_test() {
# passing conftest's
#
set_get_user_pages_defines () {
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_HAS_ARGS_FLAGS" ]; then
@ -2286,6 +2357,7 @@ compile_test() {
else
echo "#undef NV_GET_USER_PAGES_HAS_ARGS_FLAGS" | append_conftest "functions"
fi
}
# Conftest #1: Check if get_user_pages accepts 6 arguments.
@ -2306,14 +2378,15 @@ compile_test() {
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE"
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE_VMAS"
rm -f conftest$$.o
return
fi
# Conftest #2: Check if get_user_pages has gup_flags instead of
# write and force parameters. And that gup doesn't accept a
# task_struct and mm_struct as its first arguments.
# task_struct and mm_struct as its first arguments. get_user_pages
# has vm_area_struct as its last argument.
# Return if available.
# Fall through to conftest #3 on failure.
@ -2331,16 +2404,17 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_FLAGS"
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_FLAGS_VMAS"
rm -f conftest$$.o
return
fi
# Conftest #3: Check if get_user_pages has gup_flags instead of
# write and force parameters AND that gup has task_struct and
# mm_struct as its first arguments.
# write and force parameters. The gup has task_struct and
# mm_struct as its first arguments. get_user_pages
# has vm_area_struct as its last argument.
# Return if available.
# Fall through to default case if absent.
# Fall through to conftest #4 on failure.
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
@ -2358,12 +2432,35 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS"
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS_VMAS"
rm -f conftest$$.o
return
fi
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE"
# Conftest #4: gup doesn't accept a task_struct and mm_struct as
# its first arguments. check if get_user_pages() does not take
# vmas argument.
# Fall through to default case otherwise.
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
long get_user_pages(unsigned long start,
unsigned long nr_pages,
unsigned int gup_flags,
struct page **pages) {
return 0;
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_FLAGS"
rm -f conftest$$.o
return
fi
set_get_user_pages_defines "NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE_VMAS"
return
;;
@ -2390,6 +2487,10 @@ compile_test() {
# commit 64019a2e467a ("mm/gup: remove task_struct pointer for
# all gup code") in v5.9-rc1 (2020-08-11).
#
# Removed vmas parameter from get_user_pages_remote() by commit
# a4bde14d549 ("mm/gup: remove vmas parameter from get_user_pages_remote()")
# in linux-next, expected in v6.5-rc1
#
#
# This function sets the NV_GET_USER_PAGES_REMOTE_* macros as per
@ -2402,22 +2503,28 @@ compile_test() {
echo "#define NV_GET_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" | append_conftest "functions"
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED" | append_conftest "functions"
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS" ]; then
echo "#define NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS" | append_conftest "functions"
else
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" ]; then
@ -2425,6 +2532,7 @@ compile_test() {
else
echo "#undef NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED" | append_conftest "functions"
fi
}
# conftest #1: check if get_user_pages_remote() is available
@ -2447,8 +2555,8 @@ compile_test() {
fi
#
# conftest #2: check if get_user_pages_remote() has write and
# force arguments. Return if these arguments are present
# conftest #2: check if get_user_pages_remote() has write, force
# and vmas arguments. Return if these arguments are present
# Fall through to conftest #3 if these args are absent.
#
echo "$CONFTEST_PREAMBLE
@ -2468,14 +2576,14 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE"
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE_VMAS"
rm -f conftest$$.o
return
fi
#
# conftest #3: check if get_user_pages_remote() has gpu_flags
# arguments. Return if these arguments are present
# conftest #3: check if get_user_pages_remote() has gpu_flags and
# vmas arguments. Return if these arguments are present
# Fall through to conftest #4 if these args are absent.
#
echo "$CONFTEST_PREAMBLE
@ -2494,13 +2602,14 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS"
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_VMAS"
rm -f conftest$$.o
return
fi
#
# conftest #4: check if get_user_pages_remote() has locked argument
# conftest #4: check if get_user_pages_remote() has locked and
# vmas argument
# Return if these arguments are present. Fall through to conftest #5
# if these args are absent.
#
@ -2521,7 +2630,7 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED"
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED_VMAS"
rm -f conftest$$.o
return
fi
@ -2545,10 +2654,34 @@ compile_test() {
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED_VMAS"
rm -f conftest$$.o
fi
#
# conftest #6: check if get_user_pages_remote() does not take
# vmas argument.
#
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
long get_user_pages_remote(struct mm_struct *mm,
unsigned long start,
unsigned long nr_pages,
unsigned int gup_flags,
struct page **pages,
int *locked) {
return 0;
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_get_user_pages_remote_defines "NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED"
rm -f conftest$$.o
fi
;;
pin_user_pages)
@ -2560,17 +2693,65 @@ compile_test() {
# pin_user_pages() was added by commit eddb1c228f7951d399240
# ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in
# v5.6-rc1 (2020-01-30)
#
# Removed vmas parameter from pin_user_pages() by commit
# 40896a02751("mm/gup: remove vmas parameter from pin_user_pages()")
# in linux-next, expected in v6.5-rc1
set_pin_user_pages_defines () {
if [ "$1" = "" ]; then
echo "#undef NV_PIN_USER_PAGES_PRESENT" | append_conftest "functions"
else
echo "#define NV_PIN_USER_PAGES_PRESENT" | append_conftest "functions"
fi
if [ "$1" = "NV_PIN_USER_PAGES_HAS_ARGS_VMAS" ]; then
echo "#define NV_PIN_USER_PAGES_HAS_ARGS_VMAS" | append_conftest "functions"
else
echo "#undef NV_PIN_USER_PAGES_HAS_ARGS_VMAS" | append_conftest "functions"
fi
}
# conftest #1: check if pin_user_pages() is available
# return if not available.
# Fall through to conftest #2 if it is present
#
CODE="
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
void conftest_pin_user_pages(void) {
pin_user_pages();
}"
}" > conftest$$.c
compile_check_conftest "$CODE" "NV_PIN_USER_PAGES_PRESENT" "" "functions"
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_pin_user_pages_defines ""
rm -f conftest$$.o
return
fi
# conftest #2: Check if pin_user_pages() has vmas argument
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
long pin_user_pages(unsigned long start,
unsigned long nr_pages,
unsigned int gup_flags,
struct page **pages,
struct vm_area_struct **vmas) {
return 0;
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_pin_user_pages_defines "NV_PIN_USER_PAGES_HAS_ARGS_VMAS"
rm -f conftest$$.o
else
set_pin_user_pages_defines "NV_PIN_USER_PAGES_PRESENT"
fi
;;
pin_user_pages_remote)
@ -2583,6 +2764,10 @@ compile_test() {
# pin_user_pages_remote() removed 'tsk' parameter by
# commit 64019a2e467a ("mm/gup: remove task_struct pointer for
# all gup code") in v5.9-rc1 (2020-08-11).
#
# Removed unused vmas parameter from pin_user_pages_remote() by
# commit 83bcc2e132 ("mm/gup: remove unused vmas parameter from
# pin_user_pages_remote()") in linux-next, expected in v6.5-rc1
#
# This function sets the NV_PIN_USER_PAGES_REMOTE_* macros as per
@ -2595,10 +2780,16 @@ compile_test() {
echo "#define NV_PIN_USER_PAGES_REMOTE_PRESENT" | append_conftest "functions"
fi
if [ "$1" = "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" ]; then
echo "#define NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" | append_conftest "functions"
if [ "$1" = "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS" ]; then
echo "#define NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS" | append_conftest "functions"
else
echo "#undef NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK" | append_conftest "functions"
echo "#undef NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS" | append_conftest "functions"
fi
if [ "$1" = "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS" ]; then
echo "#define NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS" | append_conftest "functions"
else
echo "#undef NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS" | append_conftest "functions"
fi
}
@ -2621,7 +2812,11 @@ compile_test() {
return
fi
# conftest #2: Check if pin_user_pages_remote() has tsk argument
# conftest #2: Check if pin_user_pages_remote() has tsk and
# vmas argument
# Return if these arguments are present else fall through to
# conftest #3
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
long pin_user_pages_remote(struct task_struct *tsk,
@ -2639,11 +2834,34 @@ compile_test() {
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK"
set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS"
rm -f conftest$$.o
return
fi
# conftest #3: Check if pin_user_pages_remote() has vmas argument
echo "$CONFTEST_PREAMBLE
#include <linux/mm.h>
long pin_user_pages_remote(struct mm_struct *mm,
unsigned long start,
unsigned long nr_pages,
unsigned int gup_flags,
struct page **pages,
struct vm_area_struct **vmas,
int *locked) {
return 0;
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS"
rm -f conftest$$.o
else
set_pin_user_pages_remote_defines "NV_PIN_USER_PAGES_REMOTE_PRESENT"
fi
;;
vfio_pin_pages_has_vfio_device_arg)
@ -5112,23 +5330,6 @@ compile_test() {
compile_check_conftest "$CODE" "NV_GPIO_TO_IRQ_PRESENT" "" "functions"
;;
migrate_vma_setup)
#
# Determine if migrate_vma_setup() function is present
#
# migrate_vma_setup() function was added by commit
# a7d1f22bb74f32cf3cd93f52776007e161f1a738 ("mm: turn migrate_vma
# upside down) in v5.4.
# (2019-08-20).
CODE="
#include <linux/migrate.h>
int conftest_migrate_vma_setup(void) {
migrate_vma_setup();
}"
compile_check_conftest "$CODE" "NV_MIGRATE_VMA_SETUP_PRESENT" "" "functions"
;;
migrate_vma_added_flags)
#
# Determine if migrate_vma structure has flags

15
kernel-open/nvidia-drm/nvidia-drm-drv.c
View File

@ -855,8 +855,23 @@ static struct drm_driver nv_drm_driver = {
.ioctls = nv_drm_ioctls,
.num_ioctls = ARRAY_SIZE(nv_drm_ioctls),
/*
* linux-next commit 71a7974ac701 ("drm/prime: Unexport helpers for fd/handle
* conversion") unexports drm_gem_prime_handle_to_fd() and
* drm_gem_prime_fd_to_handle().
*
* Prior linux-next commit 6b85aa68d9d5 ("drm: Enable PRIME import/export for
* all drivers") made these helpers the default when .prime_handle_to_fd /
* .prime_fd_to_handle are unspecified, so it's fine to just skip specifying
* them if the helpers aren't present.
*/
#if NV_IS_EXPORT_SYMBOL_PRESENT_drm_gem_prime_handle_to_fd
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
#endif
#if NV_IS_EXPORT_SYMBOL_PRESENT_drm_gem_prime_fd_to_handle
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
#endif
.gem_prime_import = nv_drm_gem_prime_import,
.gem_prime_import_sg_table = nv_drm_gem_prime_import_sg_table,

2
kernel-open/nvidia-drm/nvidia-drm.Kbuild
View File

@ -54,6 +54,8 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_atomic_available
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_inc
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test
NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group

8
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
View File

@ -65,6 +65,9 @@
static bool output_rounding_fix = true;
module_param_named(output_rounding_fix, output_rounding_fix, bool, 0400);
static bool disable_vrr_memclk_switch = false;
module_param_named(disable_vrr_memclk_switch, disable_vrr_memclk_switch, bool, 0400);
/* These parameters are used for fault injection tests. Normally the defaults
* should be used. */
MODULE_PARM_DESC(fail_malloc, "Fail the Nth call to nvkms_alloc");
@ -82,6 +85,11 @@ NvBool nvkms_output_rounding_fix(void)
return output_rounding_fix;
}
NvBool nvkms_disable_vrr_memclk_switch(void)
{
return disable_vrr_memclk_switch;
}
#define NVKMS_SYNCPT_STUBS_NEEDED
/*************************************************************************

2
kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
View File

@ -112,6 +112,8 @@ typedef struct {
NvBool nvkms_output_rounding_fix(void);
NvBool nvkms_disable_vrr_memclk_switch(void);
void nvkms_call_rm (void *ops);
void* nvkms_alloc (size_t size,
NvBool zero);

2
kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
View File

@ -81,7 +81,6 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_memory_uc
NV_CONFTEST_FUNCTION_COMPILE_TESTS += set_pages_uc
NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64
NV_CONFTEST_FUNCTION_COMPILE_TESTS += ioasid_get
NV_CONFTEST_FUNCTION_COMPILE_TESTS += migrate_vma_setup
NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmget_not_zero
NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info
@ -104,3 +103,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += make_device_exclusive_range
NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup

4
kernel-open/nvidia-uvm/uvm_ce_test.c
View File

@ -179,7 +179,7 @@ static NV_STATUS test_membar(uvm_gpu_t *gpu)
for (i = 0; i < REDUCTIONS; ++i) {
uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE);
gpu->parent->ce_hal->semaphore_reduction_inc(&push, host_mem_gpu_va, REDUCTIONS + 1);
gpu->parent->ce_hal->semaphore_reduction_inc(&push, host_mem_gpu_va, REDUCTIONS);
}
// Without a sys membar the channel tracking semaphore can and does complete
@ -528,7 +528,7 @@ static NV_STATUS test_semaphore_reduction_inc(uvm_gpu_t *gpu)
for (i = 0; i < REDUCTIONS; i++) {
uvm_push_set_flag(&push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE);
gpu->parent->ce_hal->semaphore_reduction_inc(&push, gpu_va, i+1);
gpu->parent->ce_hal->semaphore_reduction_inc(&push, gpu_va, REDUCTIONS);
}
status = uvm_push_end_and_wait(&push);

2
kernel-open/nvidia-uvm/uvm_migrate_pageable.h
View File

@ -50,7 +50,7 @@ typedef struct
#if defined(CONFIG_MIGRATE_VMA_HELPER)
#define UVM_MIGRATE_VMA_SUPPORTED 1
#else
#if defined(CONFIG_DEVICE_PRIVATE) && defined(NV_MIGRATE_VMA_SETUP_PRESENT)
#if NV_IS_EXPORT_SYMBOL_PRESENT_migrate_vma_setup
#define UVM_MIGRATE_VMA_SUPPORTED 1
#endif
#endif

5
kernel-open/nvidia/nv-p2p.c
View File

@ -506,8 +506,13 @@ static int nv_p2p_get_pages(
(*page_table)->page_size = page_size_index;
os_free_mem(physical_addresses);
physical_addresses = NULL;
os_free_mem(wreqmb_h);
wreqmb_h = NULL;
os_free_mem(rreqmb_h);
rreqmb_h = NULL;
if (free_callback != NULL)
{

14
kernel-open/nvidia/nv.c
View File

@ -4505,19 +4505,19 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
* as the starting address for all DMA mappings.
*/
saved_dma_mask = pci_dev->dma_mask;
if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64)) != 0)
if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64)) != 0)
{
goto done;
}
dma_addr = pci_map_single(pci_dev, NULL, 1, DMA_BIDIRECTIONAL);
if (pci_dma_mapping_error(pci_dev, dma_addr))
dma_addr = dma_map_single(&pci_dev->dev, NULL, 1, DMA_BIDIRECTIONAL);
if (dma_mapping_error(&pci_dev->dev, dma_addr))
{
pci_set_dma_mask(pci_dev, saved_dma_mask);
dma_set_mask(&pci_dev->dev, saved_dma_mask);
goto done;
}
pci_unmap_single(pci_dev, dma_addr, 1, DMA_BIDIRECTIONAL);
dma_unmap_single(&pci_dev->dev, dma_addr, 1, DMA_BIDIRECTIONAL);
/*
* From IBM: "For IODA2, native DMA bypass or KVM TCE-based implementation
@ -4549,7 +4549,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
*/
nv_printf(NV_DBG_WARNINGS,
"NVRM: DMA window limited by platform\n");
pci_set_dma_mask(pci_dev, saved_dma_mask);
dma_set_mask(&pci_dev->dev, saved_dma_mask);
goto done;
}
else if ((dma_addr & saved_dma_mask) != 0)
@ -4568,7 +4568,7 @@ NvU64 NV_API_CALL nv_get_dma_start_address(
*/
nv_printf(NV_DBG_WARNINGS,
"NVRM: DMA window limited by memory size\n");
pci_set_dma_mask(pci_dev, saved_dma_mask);
dma_set_mask(&pci_dev->dev, saved_dma_mask);
goto done;
}
}

5
kernel-open/nvidia/nvlink_export.h
View File

@ -46,6 +46,11 @@ NvlStatus nvlink_lib_unload(void);
*/
NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params);
/*
* Gets number of devices with type deviceType
*/
NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
#ifdef __cplusplus
}
#endif

3
kernel-open/nvidia/nvlink_os.h
View File

@ -30,6 +30,9 @@ extern "C" {
#include "nvlink_common.h"
#define TOP_LEVEL_LOCKING_DISABLED 1
#define PER_LINK_LOCKING_DISABLED 1
#define NVLINK_FREE(x) nvlink_free((void *)x)
// Memory management functions

6
src/common/displayport/src/dp_evoadapter.cpp
View File

@ -1165,8 +1165,12 @@ bool EvoMainLink::train(const LinkConfiguration & link, bool force,
// 1. CR or EQ phase failed.
// 2. The request link bandwidth is NOT RBR
//
if (!requestRmLC.lowerConfig())
{
// If no valid link config could be found, break here.
break;
}
fallback = true;
requestRmLC.lowerConfig();
}
else
{

20
src/common/inc/nvBldVer.h
View File

@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r529_03
#define NV_BUILD_BRANCH r529_18
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r529_03
#define NV_PUBLIC_BRANCH r529_18
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r529_03-397"
#define NV_BUILD_CHANGELIST_NUM (32911090)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r529_18-534"
#define NV_BUILD_CHANGELIST_NUM (33451322)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r525/r529_03-397"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32911090)
#define NV_BUILD_NAME "rel/gpu_drv/r525/r529_18-534"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33451322)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r529_03-3"
#define NV_BUILD_CHANGELIST_NUM (32911090)
#define NV_BUILD_BRANCH_VERSION "r529_18-2"
#define NV_BUILD_CHANGELIST_NUM (33403873)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "529.08"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32911090)
#define NV_BUILD_NAME "529.19"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33403873)
#define NV_BUILD_BRANCH_BASE_VERSION R525
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "525.125.06"
#define NV_VERSION_STRING "525.147.05"
#else

17
src/common/inc/nvlog_defs.h
View File

@ -112,23 +112,12 @@ struct _NVLOG_BUFFER
#endif // NVOS_IS_UNIX
//
// Due to this file's peculiar location, NvPort may or may not be includable
// This hack will go away when NvLog is moved into common/shared
//
#if NVOS_IS_MACINTOSH
#if !PORT_IS_KERNEL_BUILD
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
typedef struct PORT_MUTEX PORT_MUTEX;
#else
#include "nvport/nvport.h"
#endif
typedef struct PORT_RWLOCK PORT_RWLOCK;
#elif !defined(PORT_IS_KERNEL_BUILD)
typedef struct PORT_SPINLOCK PORT_SPINLOCK;
typedef struct PORT_MUTEX PORT_MUTEX;
#else
#if PORT_IS_KERNEL_BUILD
#include "nvport/nvport.h"
#endif
@ -149,6 +138,8 @@ typedef struct _NVLOG_LOGGER
PORT_SPINLOCK* mainLock;
/** Lock for creating/deleting pBuffers and accessing them from RmCtrls */
PORT_MUTEX* buffersLock;
/** Lock for registering/deregistering flush callbacks */
PORT_RWLOCK *flushCbsLock;
} NVLOG_LOGGER;
extern NVLOG_LOGGER NvLogLogger;

23
src/common/inc/swref/published/hopper/gh100/dev_fb.h
View File

@ -20,7 +20,7 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fb_h
#define __gh100_dev_fb_h_
#define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */
@ -29,4 +29,25 @@
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00100A38 /* RW-4R */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */
#define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */
#endif // __gh100_dev_fb_h__

29
src/common/inc/swref/published/hopper/gh100/dev_fbpa.h Normal file
View File

@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_fbpa_h_
#define __gh100_dev_fbpa_h_
#define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 4 /* */
#define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x009025A0+(i)*4) /* RW-4A */
#endif // __gh100_dev_fbpa_h_

33
src/common/inc/swref/published/hopper/gh100/dev_ltc.h Normal file
View File

@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_ltc_h_
#define __gh100_dev_ltc_h_
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_dev_ltc_h_

52
src/common/inc/swref/published/hopper/gh100/dev_nv_xpl.h Normal file
View File

@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gh100_dev_nv_xpl_h_
#define __gh100_dev_nv_xpl_h_
#define NV_XPL_DL_ERR_COUNT_RBUF 0x00000a54 /* R--4R */
#define NV_XPL_DL_ERR_COUNT_RBUF__PRIV_LEVEL_MASK 0x00000b08 /* */
#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR 15:0 /* R-EVF */
#define NV_XPL_DL_ERR_COUNT_RBUF_CORR_ERR_INIT 0x0000 /* R-E-V */
#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR 31:16 /* R-EVF */
#define NV_XPL_DL_ERR_COUNT_RBUF_UNCORR_ERR_INIT 0x0000 /* R-E-V */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT 0x00000a58 /* R--4R */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT__PRIV_LEVEL_MASK 0x00000b08 /* */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR 15:0 /* R-EVF */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_CORR_ERR_INIT 0x0000 /* R-E-V */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR 31:16 /* R-EVF */
#define NV_XPL_DL_ERR_COUNT_SEQ_LUT_UNCORR_ERR_INIT 0x0000 /* R-E-V */
#define NV_XPL_DL_ERR_RESET 0x00000a5c /* RW-4R */
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT 0:0 /* RWCVF */
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */
#define NV_XPL_DL_ERR_RESET_RBUF_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT 1:1 /* RWCVF */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_DONE 0x0 /* RWC-V */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_CORR_ERR_COUNT_PENDING 0x1 /* -W--T */
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT 16:16 /* RWCVF */
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */
#define NV_XPL_DL_ERR_RESET_RBUF_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT 17:17 /* RWCVF */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_DONE 0x0 /* RWC-V */
#define NV_XPL_DL_ERR_RESET_SEQ_LUT_UNCORR_ERR_COUNT_PENDING 0x1 /* -W--T */
#endif // __gh100_dev_nv_xpl_h__

3
src/common/inc/swref/published/hopper/gh100/dev_xtl_ep_pri.h
View File

@ -24,4 +24,7 @@
#ifndef __gh100_dev_xtl_ep_pri_h__
#define __gh100_dev_xtl_ep_pri_h__
#define NV_EP_PCFGM 0x92FFF:0x92000 /* RW--D */
#define NV_XTL_EP_PRI_DED_ERROR_STATUS 0x0000043C /* RW-4R */
#define NV_XTL_EP_PRI_RAM_ERROR_INTR_STATUS 0x000003C8 /* RW-4R */
#endif // __gh100_dev_xtl_ep_pri_h__

6
src/common/inc/swref/published/hopper/gh100/hwproject.h
View File

@ -21,3 +21,9 @@
* DEALINGS IN THE SOFTWARE.
*/
#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 52
#define NV_LTC_PRI_STRIDE 8192
#define NV_LTS_PRI_STRIDE 512
#define NV_FBPA_PRI_STRIDE 16384
#define NV_SCAL_LITTER_NUM_FBPAS 24
#define NV_XPL_BASE_ADDRESS 540672
#define NV_XTL_BASE_ADDRESS 593920

12
src/common/inc/swref/published/hopper/gh100/pri_nv_xal_ep.h
View File

@ -47,5 +47,17 @@
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1
#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT 0x0010f364 /* RW-4R */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_REORDER_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT 0x0010f37c /* RW-4R */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIUF */
#define NV_XAL_EP_P2PREQ_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
#endif // __gh100_pri_nv_xal_ep_h__

5
src/common/inc/swref/published/nvswitch/ls10/dev_nvlipt_lnk_ip.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -635,4 +635,7 @@
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT 28:28 /* RWIVF */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_SUPPORTED 0x00000001 /* RWI-V */
#define NV_NVLIPT_LNK_CTRL_CAP_LOCAL_LINK_CHANNEL_ALI_SUPPORT_NOT_SUPPORTED 0x00000000 /* RW--V */
#define NV_NVLIPT_LNK_SCRATCH_WARM 0x000007c0 /* RW-4R */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#endif // __ls10_dev_nvlipt_lnk_ip_h__

28
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h Normal file
View File

@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the Software),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __ls10_ptop_discovery_ip_h__
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#endif // __ls10_ptop_discovery_ip_h__

5
src/common/nvlink/interface/nvlink.h
View File

@ -439,6 +439,11 @@ NvlStatus nvlink_lib_register_link(nvlink_device *dev, nvlink_link *link);
*/
NvlStatus nvlink_lib_unregister_link(nvlink_link *link);
/*
* Gets number of devices with type deviceType
*/
NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
/************************************************************************************************/
/******************************* NVLink link management functions *******************************/

5
src/common/nvlink/interface/nvlink_export.h
View File

@ -46,6 +46,11 @@ NvlStatus nvlink_lib_unload(void);
*/
NvlStatus nvlink_lib_ioctl_ctrl(nvlink_ioctrl_params *ctrl_params);
/*
* Gets number of devices with type deviceType
*/
NvlStatus nvlink_lib_return_device_count_by_type(NvU32 deviceType, NvU32 *numDevices);
#ifdef __cplusplus
}
#endif

3
src/common/nvlink/interface/nvlink_os.h
View File

@ -30,6 +30,9 @@ extern "C" {
#include "nvlink_common.h"
#define TOP_LEVEL_LOCKING_DISABLED 1
#define PER_LINK_LOCKING_DISABLED 1
#define NVLINK_FREE(x) nvlink_free((void *)x)
// Memory management functions

50
src/common/nvlink/kernel/nvlink/nvlink_lib_mgmt.c
View File

@ -187,13 +187,59 @@ nvlink_lib_is_registerd_device_with_reduced_config(void)
{
if (dev->bReducedNvlinkConfig == NV_TRUE)
{
// Release top-level lock
nvlink_lib_top_lock_release();
return NV_TRUE;
}
}
// Release and free top-level lock
// Release top-level lock
nvlink_lib_top_lock_release();
nvlink_lib_top_lock_free();
return NV_FALSE;
}
/*
* Get the number of devices that have the device type deviceType
*/
NvlStatus
nvlink_lib_return_device_count_by_type
(
NvU32 deviceType,
NvU32 *numDevices
)
{
NvlStatus lock_status = NVL_SUCCESS;
nvlink_device *dev = NULL;
NvU32 device_count = 0;
if (nvlink_lib_is_initialized())
{
// Acquire top-level lock
lock_status = nvlink_lib_top_lock_acquire();
if (lock_status != NVL_SUCCESS)
{
NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
"%s: Failed to acquire top-level lock\n",
__FUNCTION__));
return lock_status;
}
// Top-level lock is now acquired
// Loop through device list
FOR_EACH_DEVICE_REGISTERED(dev, nvlinkLibCtx.nv_devicelist_head, node)
{
if (dev->type == deviceType)
{
device_count++;
}
}
// Release top-level lock
nvlink_lib_top_lock_release();
}
*numDevices = device_count;
return NVL_SUCCESS;
}

32
src/common/nvlink/kernel/nvlink/nvlink_lock.c
View File

@ -26,14 +26,18 @@
#include "nvlink_lock.h"
//
// Only enabling locking for testing purposes at the moment.
// Disabled at all other times.
//
#define LOCKING_DISABLED 1
// Only enabling top level locking for linux as required by Bug 4108674.
// Per link locking is still disabled at all times. It will be enabled
// after other locking related clean up is done.
//
static void _sort_links(nvlink_link **, NvU32, NvBool (*)(void *, void *));
static NvBool _compare(void *, void *);
#if defined(NV_LINUX)
#undef TOP_LEVEL_LOCKING_DISABLED
# define TOP_LEVEL_LOCKING_DISABLED 0
#endif /* defined(NV_LINUX) */
/*
* Allocate top level lock. Return NVL_SUCCESS if
* the lock was allocated else return NVL_ERR_GENERIC.
@ -41,7 +45,7 @@ static NvBool _compare(void *, void *);
NvlStatus
nvlink_lib_top_lock_alloc(void)
{
if (LOCKING_DISABLED)
if (TOP_LEVEL_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -82,7 +86,7 @@ nvlink_lib_top_lock_alloc(void)
NvlStatus
nvlink_lib_top_lock_free(void)
{
if (LOCKING_DISABLED)
if (TOP_LEVEL_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -115,7 +119,7 @@ nvlink_lib_link_lock_alloc
nvlink_link *link
)
{
if (LOCKING_DISABLED)
if (PER_LINK_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -158,7 +162,7 @@ nvlink_lib_link_lock_free
nvlink_link *link
)
{
if (LOCKING_DISABLED)
if (PER_LINK_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -188,7 +192,7 @@ nvlink_lib_link_lock_free
NvlStatus
nvlink_lib_top_lock_acquire(void)
{
if (LOCKING_DISABLED)
if (TOP_LEVEL_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -223,7 +227,7 @@ nvlink_lib_top_lock_acquire(void)
NvlStatus
nvlink_lib_top_lock_release(void)
{
if (LOCKING_DISABLED)
if (TOP_LEVEL_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
@ -265,13 +269,12 @@ nvlink_lib_link_locks_acquire
int numLinks
)
{
if (LOCKING_DISABLED)
if (PER_LINK_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
int i;
nvlink_link *link_prev = NULL;
// Check if array of links is already empty before attempting to release.
@ -328,13 +331,12 @@ nvlink_lib_link_locks_release
int numLinks
)
{
int i;
if (LOCKING_DISABLED)
if (PER_LINK_LOCKING_DISABLED)
{
return NVL_SUCCESS;
}
int i;
nvlink_link *link_prev = NULL;
// Check if array of links is already empty before attempting to release.

24
src/common/nvswitch/common/inc/soe/soeifcore.h
View File

@ -40,62 +40,62 @@ enum
/*!
* Read the BIOS Size
*/
RM_SOE_CORE_CMD_READ_BIOS_SIZE,
RM_SOE_CORE_CMD_READ_BIOS_SIZE = 0x0,
/*!
* Read the BIOS
*/
RM_SOE_CORE_CMD_READ_BIOS,
RM_SOE_CORE_CMD_READ_BIOS = 0x1,
/*!
* Run DMA self-test
*/
RM_SOE_CORE_CMD_DMA_SELFTEST,
RM_SOE_CORE_CMD_DMA_SELFTEST = 0x2,
/*!
* Perform I2C transaction
*/
RM_SOE_CORE_CMD_I2C_ACCESS,
RM_SOE_CORE_CMD_I2C_ACCESS = 0x3,
/*!
* Issue NPORT Reset
*/
RM_SOE_CORE_CMD_ISSUE_NPORT_RESET,
RM_SOE_CORE_CMD_ISSUE_NPORT_RESET = 0x4,
/*!
* Restore NPORT state
*/
RM_SOE_CORE_CMD_RESTORE_NPORT_STATE,
RM_SOE_CORE_CMD_RESTORE_NPORT_STATE = 0x5,
/*!
* Set NPORT TPROD state
*/
RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE,
RM_SOE_CORE_CMD_SET_NPORT_TPROD_STATE = 0x6,
/*!
* Read VRs
*/
RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES,
RM_SOE_CORE_CMD_GET_VOLTAGE_VALUES = 0x7,
/*!
* Init PLM2 protected registers
*/
RM_SOE_CORE_CMD_INIT_L2_STATE,
RM_SOE_CORE_CMD_INIT_L2_STATE = 0x8,
/*!
* Read Power
*/
RM_SOE_CORE_CMD_GET_POWER_VALUES,
RM_SOE_CORE_CMD_GET_POWER_VALUES = 0x9,
/*!
* Set NPORT interrupts
*/
RM_SOE_CORE_CMD_SET_NPORT_INTRS,
RM_SOE_CORE_CMD_SET_NPORT_INTRS = 0xA,
/*!
* Disable NPORT fatal interrupt
*/
RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR,
RM_SOE_CORE_CMD_DISABLE_NPORT_FATAL_INTR = 0xF,
};
// Timeout for SOE reset callback function

116
src/common/nvswitch/common/inc/soe/soeififr.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -27,6 +27,7 @@
#include "flcnifcmn.h"
#define INFOROM_FS_FILE_NAME_SIZE 3
#define INFOROM_BBX_OBJ_XID_ENTRIES 10
enum
{
@ -36,6 +37,17 @@ enum
RM_SOE_IFR_BBX_SHUTDOWN,
RM_SOE_IFR_BBX_SXID_ADD,
RM_SOE_IFR_BBX_SXID_GET,
RM_SOE_IFR_BBX_DATA_GET,
};
enum
{
RM_SOE_IFR_BBX_GET_NONE,
RM_SOE_IFR_BBX_GET_SXID,
RM_SOE_IFR_BBX_GET_SYS_INFO,
RM_SOE_IFR_BBX_GET_TIME_INFO,
RM_SOE_IFR_BBX_GET_TEMP_DATA,
RM_SOE_IFR_BBX_GET_TEMP_SAMPLES,
};
typedef struct
@ -70,9 +82,18 @@ typedef struct
typedef struct
{
NvU8 cmdType;
NvU32 sizeInBytes;
RM_FLCN_U64 dmaHandle;
} RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS;
typedef struct
{
NvU8 cmdType;
NvU32 sizeInBytes;
RM_FLCN_U64 dmaHandle;
NvU8 dataType;
} RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS;
typedef union
{
NvU8 cmdType;
@ -80,6 +101,99 @@ typedef union
RM_SOE_IFR_CMD_BBX_INIT_PARAMS bbxInit;
RM_SOE_IFR_CMD_BBX_SXID_ADD_PARAMS bbxSxidAdd;
RM_SOE_IFR_CMD_BBX_SXID_GET_PARAMS bbxSxidGet;
RM_SOE_IFR_CMD_BBX_GET_DATA_PARAMS bbxDataGet;
} RM_SOE_IFR_CMD;
// entry of getSxid
typedef struct
{
NvU32 sxid;
NvU32 timestamp;
} RM_SOE_BBX_SXID_ENTRY;
// SXID data array return to getSxid
typedef struct
{
NvU32 sxidCount;
RM_SOE_BBX_SXID_ENTRY sxidFirst[INFOROM_BBX_OBJ_XID_ENTRIES];
RM_SOE_BBX_SXID_ENTRY sxidLast[INFOROM_BBX_OBJ_XID_ENTRIES];
} RM_SOE_BBX_GET_SXID_DATA;
// NVSwitch system version information returning with the command GET_SYS_INFO
typedef struct
{
NvU32 driverLo; //Driver Version Low 32 bits
NvU16 driverHi; //Driver Version High 16 bits
NvU32 vbiosVersion; //VBIOS Version
NvU8 vbiosVersionOem; //VBIOS OEM Version byte
NvU8 osType; //OS Type (UNIX/WIN/WIN2K/WIN9x/OTHER)
NvU32 osVersion; //OS Version (Build|MINOR|MAJOR)
} RM_SOE_BBX_GET_SYS_INFO_DATA;
// NVSwitch time information returning with the command GET_TIME_INFO
typedef struct
{
NvU32 timeStart; //Timestamp (EPOCH) when the driver was loaded on the GPU for the first time
NvU32 timeEnd; //Timestamp (EPOCH) when the data was last flushed
NvU32 timeRun; //Amount of time (in seconds) driver was loaded, and GPU has run
NvU32 time24Hours; //Timestamp (EPOCH) of when the first 24 operational hours is hit
NvU32 time100Hours; //Timestamp (EPOCH) of when the first 100 operational hours is hit
} RM_SOE_BBX_GET_TIME_INFO_DATA;
#define RM_SOE_BBX_TEMP_DAY_ENTRIES 5
#define RM_SOE_BBX_TEMP_WEEK_ENTRIES 5
#define RM_SOE_BBX_TEMP_MNT_ENTRIES 5
#define RM_SOE_BBX_TEMP_ALL_ENTRIES 5
#define RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES 23
#define RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES 5
#define RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES 3
#define RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES 20
#define RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES 21
#define RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES 168
#define RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES 1096
#define RM_SOE_BBX_NUM_COMPRESSION_PERIODS 8
// NVSwitch Temperature Entry
typedef struct
{
NvU16 value; //Temperature (SFXP 9.7 format in Celsius)
NvU32 timestamp; //Timestamp (EPOCH) of when the entry is recorded
} RM_SOE_BBX_TEMP_ENTRY;
// NVSwitch Temperature Data returning with the command GET_TEMP_DATA
typedef struct
{
NvU32 tempMaxDayIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxDay[RM_SOE_BBX_TEMP_DAY_ENTRIES];
NvU32 tempMaxWeekIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES];
NvU32 tempMaxMntIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES];
NvU32 tempMaxAllIdx;
RM_SOE_BBX_TEMP_ENTRY tempMaxAll[RM_SOE_BBX_TEMP_ALL_ENTRIES];
NvU32 tempMinDayIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinDay[RM_SOE_BBX_TEMP_DAY_ENTRIES];
NvU32 tempMinWeekIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinWeek[RM_SOE_BBX_TEMP_WEEK_ENTRIES];
NvU32 tempMinMntIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinMnt[RM_SOE_BBX_TEMP_MNT_ENTRIES];
NvU32 tempMinAllIdx;
RM_SOE_BBX_TEMP_ENTRY tempMinAll[RM_SOE_BBX_TEMP_ALL_ENTRIES];
NvU32 tempSumDelta;
NvU32 tempSumHour[RM_SOE_BBX_TEMP_SUM_HOUR_ENTRIES];
NvU32 tempSumDay[RM_SOE_BBX_TEMP_SUM_DAY_ENTRIES];
NvU32 tempSumMnt[RM_SOE_BBX_TEMP_SUM_MNT_ENTRIES];
NvU32 tempHistogramThld[RM_SOE_BBX_TEMP_HISTOGRAM_THLD_ENTRIES];
NvU32 tempHistogramTime[RM_SOE_BBX_TEMP_HISTOGRAM_TIME_ENTRIES];
RM_SOE_BBX_TEMP_ENTRY tempHourlyMaxSample[RM_SOE_BBX_TEMP_HOURLY_MAX_ENTRIES];
} RM_SOE_BBX_GET_TEMP_DATA;
// NVSwitch Temperature Compressed Samples returning with the command GET_TEMP_SAMPLES
typedef struct
{
NvU32 compressionPeriodIdx;
NvU32 compressionPeriod[RM_SOE_BBX_NUM_COMPRESSION_PERIODS];
RM_SOE_BBX_TEMP_ENTRY tempCompressionBuffer[RM_SOE_BBX_TEMP_COMPRESS_BUFFER_ENTRIES];
} RM_SOE_BBX_GET_TEMP_SAMPLES;
#endif // _SOEIFIFR_H_

198
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -830,6 +830,7 @@ typedef enum nvswitch_err_type
NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006,
NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007,
NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008,
NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009,
NVSWITCH_ERR_HW_HOST_LAST,
@ -2967,6 +2968,197 @@ typedef struct
NVSWITCH_SXID_ENTRY sxidLast[NVSWITCH_SXID_ENTRIES_NUM];
} NVSWITCH_GET_SXIDS_PARAMS;
/*
* CTRL_NVSWITCH_GET_SYS_INFO
*
* Control to get the NVSwitch system version information from inforom cache
*
* Parameters:
* driverLo [OUT]
* The driver version low 32 bits. Example: driverLo = 54531 (Driver 545.31)
* driverHi [OUT]
* The driver version high 16 bits
* vbiosVersion [OUT]
* The vbios version number. Example: vbiosVersion=0x96104100 (release 96.10.41.00)
* vbiosVersionOem [OUT]
* The vbios OEM version byte.
* osType [OUT]
* The OS type. Example: osType=0x05 (UNIX)
* osVersion [OUT]
* The OS version number. [BUILD[31:16]|MINOR[15:8]|MAJOR[7:0]]
*/
typedef struct
{
NvU32 driverLo;
NvU16 driverHi;
NvU32 vbiosVersion;
NvU8 vbiosVersionOem;
NvU8 osType;
NvU32 osVersion;
} NVSWITCH_GET_SYS_INFO_PARAMS;
/*
* CTRL_NVSWITCH_GET_TIME_INFO
*
* Control to get the NVSwitch time information from inforom cache
*
* Parameters:
* timeStart [OUT]
* The timestamp (EPOCH) when driver load onto the NVSwitch for the 1st time
* timeEnd [OUT]
* The timestamp (EPOCH) when the data was last flushed
* timeRun [OUT]
* The amount of time (in seconds) driver was loaded/running
* time24Hours [OUT]
* The timestamp (EPOCH) when the first 24 operational hours is hit
* time100Hours [OUT]
* The timestamp (EPOCH) when the first 100 operational hours is hit
*/
typedef struct
{
NvU32 timeStart;
NvU32 timeEnd;
NvU32 timeRun;
NvU32 time24Hours;
NvU32 time100Hours;
} NVSWITCH_GET_TIME_INFO_PARAMS;
#define NVSWITCH_TEMP_DAY_ENTRIES 5
#define NVSWITCH_TEMP_WEEK_ENTRIES 5
#define NVSWITCH_TEMP_MNT_ENTRIES 5
#define NVSWITCH_TEMP_ALL_ENTRIES 5
#define NVSWITCH_TEMP_SUM_HOUR_ENTRIES 23
#define NVSWITCH_TEMP_SUM_DAY_ENTRIES 5
#define NVSWITCH_TEMP_SUM_MNT_ENTRIES 3
#define NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES 20
#define NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES 21
#define NVSWITCH_TEMP_HOURLY_MAX_ENTRIES 168
/*
* NVSWITCH_TEMP_ENTRY
*
* This structure represents the NVSwitch TEMP with its timestamp.
*
* value
* This parameter specifies the NVSwitch Temperature
* (SFXP 9.7 format in Celsius).
*
* timestamp
* This parameter specifies the timestamp (EPOCH) of the entry.
*/
typedef struct
{
NvU16 value;
NvU32 timestamp;
} NVSWITCH_TEMP_ENTRY;
/*
* CTRL_NVSWITCH_GET_TEMP_DATA
*
* Control to get the NVSwitch device historical temperature information from inforom cache
*
* Parameters:
* tempMaxDayIdx [OUT]
* The current index to the maximum day temperature array
* tempMaxDay[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days
* tempMaxWeekIdx [OUT]
* The current index to the maximum week temperature array
* tempMaxWeek[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks
* tempMaxMntIdx [OUT]
* The current index to the maximum month temperature array
* tempMaxMnt[] [OUT]
* The maximum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months
* tempMaxAllIdx [OUT]
* The current index to the maximum temperature array
* tempMaxAll[] [OUT]
* The maximum temperature array for the device
* tempMinDayIdx [OUT]
* The current index to the minimum day temperature array
* tempMinDay[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_DAY_ENTRIES days
* tempMinWeekIdx [OUT]
* The current index to the minimum week temperature array
* tempMinWeek[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_WEEK_ENTRIES weeks
* tempMinMntIdx [OUT]
* The current index to the minimum month temperature array
* tempMinMnt[] [OUT]
* The minimum temperature array for last NVSWITCH_TEMP_MNT_ENTRIES months
* tempMinAllIdx [OUT]
* The current index to the minimum temperature array
* tempMinAll[] [OUT]
* The minimum temperature array for the device
* tempSumDelta [OUT]
* The total sum of temperature change in 0.1C granularity
* tempSumHour[] [OUT]
* The moving average of temperature per hour, for last NVSWITCH_TEMP_SUM_HOUR_ENTRIES hours
* tempSumDay[] [OUT]
* The moving average of temperature per day, for last NVSWITCH_TEMP_SUM_DAY_ENTRIES days
* tempSumMnt[] [OUT]
* The moving average of temperature per month, for last NVSWITCH_TEMP_SUM_MNT_ENTRIES months
* tempHistogramThld[] [OUT]
* The histogram of temperature crossing various thresholds (5/10/15/.../95/100)
* tempHistogramTime[] [OUT]
* The histogram of time was in various temperature ranges (0..5/5..10/.../100..)
* tempHourlyMaxSample[] [OUT]
* The maximum hourly temperature array for the device
*/
typedef struct
{
NvU32 tempMaxDayIdx;
NVSWITCH_TEMP_ENTRY tempMaxDay[NVSWITCH_TEMP_DAY_ENTRIES];
NvU32 tempMaxWeekIdx;
NVSWITCH_TEMP_ENTRY tempMaxWeek[NVSWITCH_TEMP_WEEK_ENTRIES];
NvU32 tempMaxMntIdx;
NVSWITCH_TEMP_ENTRY tempMaxMnt[NVSWITCH_TEMP_MNT_ENTRIES];
NvU32 tempMaxAllIdx;
NVSWITCH_TEMP_ENTRY tempMaxAll[NVSWITCH_TEMP_ALL_ENTRIES];
NvU32 tempMinDayIdx;
NVSWITCH_TEMP_ENTRY tempMinDay[NVSWITCH_TEMP_DAY_ENTRIES];
NvU32 tempMinWeekIdx;
NVSWITCH_TEMP_ENTRY tempMinWeek[NVSWITCH_TEMP_WEEK_ENTRIES];
NvU32 tempMinMntIdx;
NVSWITCH_TEMP_ENTRY tempMinMnt[NVSWITCH_TEMP_MNT_ENTRIES];
NvU32 tempMinAllIdx;
NVSWITCH_TEMP_ENTRY tempMinAll[NVSWITCH_TEMP_ALL_ENTRIES];
NvU32 tempSumDelta;
NvU32 tempSumHour[NVSWITCH_TEMP_SUM_HOUR_ENTRIES];
NvU32 tempSumDay[NVSWITCH_TEMP_SUM_DAY_ENTRIES];
NvU32 tempSumMnt[NVSWITCH_TEMP_SUM_MNT_ENTRIES];
NvU32 tempHistogramThld[NVSWITCH_TEMP_HISTOGRAM_THLD_ENTRIES];
NvU32 tempHistogramTime[NVSWITCH_TEMP_HISTOGRAM_TIME_ENTRIES];
NVSWITCH_TEMP_ENTRY tempHourlyMaxSample[NVSWITCH_TEMP_HOURLY_MAX_ENTRIES];
} NVSWITCH_GET_TEMP_DATA_PARAMS;
#define NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES 1096
#define NVSWITCH_NUM_COMPRESSION_PERIODS 8
/*
* CTRL_NVSWITCH_GET_TEMP_DATA
*
* Control to get the NVSwitch device temperature information from inforom cache
*
* Parameters:
* compressionPeriodIdx [OUT]
* The current index to the sample period array
* compressionPeriod[] [OUT]
* The samples period array (seconds)
* tempCompressionBuffer[] [OUT]
* The temperature array sampling at a specific period in compressionPeriod[]
*/
typedef struct
{
NvU32 compressionPeriodIdx;
NvU32 compressionPeriod[NVSWITCH_NUM_COMPRESSION_PERIODS];
NVSWITCH_TEMP_ENTRY tempCompressionBuffer[NVSWITCH_TEMP_COMPRESS_BUFFER_ENTRIES];
} NVSWITCH_GET_TEMP_SAMPLES_PARAMS;
/*
* CTRL_NVSWITCH_GET_FOM_VALUES
* This command gives the FOM values to MODS
@ -3841,6 +4033,10 @@ typedef struct
#define CTRL_NVSWITCH_GET_VOLTAGE 0x54
#define CTRL_NVSWITCH_GET_BOARD_PART_NUMBER 0x55
#define CTRL_NVSWITCH_GET_POWER 0x56
#define CTRL_NVSWITCH_GET_SYS_INFO 0x57
#define CTRL_NVSWITCH_GET_TIME_INFO 0x58
#define CTRL_NVSWITCH_GET_TEMP_DATA 0x59
#define CTRL_NVSWITCH_GET_TEMP_SAMPLES 0x60
#ifdef __cplusplus
}

7
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@ -52,6 +52,7 @@
_op(void, nvswitch_destroy_device_state, (nvswitch_device *device), _arch) \
_op(void, nvswitch_determine_platform, (nvswitch_device *device), _arch) \
_op(NvU32, nvswitch_get_num_links, (nvswitch_device *device), _arch) \
_op(NvU8, nvswitch_get_num_links_per_nvlipt,(nvswitch_device *device), _arch) \
_op(NvBool, nvswitch_is_link_valid, (nvswitch_device *device, NvU32 link_id), _arch) \
_op(void, nvswitch_set_fatal_error, (nvswitch_device *device, NvBool device_fatal, NvU32 link_id), _arch) \
_op(NvU32, nvswitch_get_swap_clk_default, (nvswitch_device *device), _arch) \
@ -138,6 +139,9 @@
_op(NvlStatus, nvswitch_inforom_nvl_update_link_correctable_error_info, (nvswitch_device *device, void *pNvlGeneric, void *pData, NvU8 linkId, NvU8 nvliptInstance, NvU8 localLinkIdx, void *pErrorCounts, NvBool *bDirty), _arch) \
_op(NvlStatus, nvswitch_inforom_nvl_get_max_correctable_error_rate, (nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_inforom_nvl_get_errors, (nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *p), _arch) \
_op(NvlStatus, nvswitch_inforom_nvl_setL1Threshold, (nvswitch_device *device, void *pNvlGeneric, NvU32 word1, NvU32 word2), _arch) \
_op(NvlStatus, nvswitch_inforom_nvl_getL1Threshold, (nvswitch_device *device, void *pNvlGeneric, NvU32 *word1, NvU32 *word2), _arch) \
_op(NvlStatus, nvswitch_inforom_nvl_setup_nvlink_state, (nvswitch_device *device, INFOROM_NVLINK_STATE *pNvlinkState, NvU8 version), _arch) \
_op(NvlStatus, nvswitch_inforom_ecc_get_errors, (nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *p), _arch) \
_op(void, nvswitch_load_uuid, (nvswitch_device *device), _arch) \
_op(void, nvswitch_i2c_set_hw_speed_mode, (nvswitch_device *device, NvU32 port, NvU32 speedMode), _arch) \
@ -153,6 +157,7 @@
_op(NvlStatus, nvswitch_bbx_unload, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_bbx_load, (nvswitch_device *device, NvU64 time_ns, NvU8 osType, NvU32 osVersion), _arch) \
_op(NvlStatus, nvswitch_bbx_get_sxid, (nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS * params), _arch) \
_op(NvlStatus, nvswitch_bbx_get_data, (nvswitch_device *device, NvU8 dataType, void * params), _arch) \
_op(NvlStatus, nvswitch_smbpbi_alloc, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_smbpbi_post_init_hal, (nvswitch_device *device), _arch) \
_op(void, nvswitch_smbpbi_destroy_hal, (nvswitch_device *device), _arch) \
@ -208,6 +213,7 @@
_op(void, nvswitch_reset_persistent_link_hw_state, (nvswitch_device *device, NvU32 linkNumber), _arch)\
_op(void, nvswitch_store_topology_information, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(void, nvswitch_init_lpwr_regs, (nvlink_link *link), _arch) \
_op(void, nvswitch_program_l1_scratch_reg, (nvswitch_device *device, NvU32 linkNumber), _arch) \
_op(NvlStatus, nvswitch_set_training_mode, (nvswitch_device *device), _arch) \
_op(NvU32, nvswitch_get_sublink_width, (nvswitch_device *device, NvU32 linkNumber), _arch) \
_op(NvBool, nvswitch_i2c_is_device_access_allowed, (nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead), _arch) \
@ -228,6 +234,7 @@
_op(NvlStatus, nvswitch_ctrl_get_board_part_number, (nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p), _arch) \
_op(NvBool, nvswitch_does_link_need_termination_enabled, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_link_termination_setup, (nvswitch_device *device, nvlink_link *link), _arch) \
_op(NvlStatus, nvswitch_check_io_sanity, (nvswitch_device *device), _arch) \
#define NVSWITCH_HAL_FUNCTION_LIST_LS10(_op, _arch) \
_op(NvlStatus, nvswitch_launch_ALI, (nvswitch_device *device), _arch) \

94
src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v3_nvswitch.h Normal file
View File

@ -0,0 +1,94 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _INFOROM_NVL_V3_NVSWITCH_H_
#define _INFOROM_NVL_V3_NVSWITCH_H_
#include "inforom/inforom_nvswitch.h"
#define LUT_ELEMENT(block, dir, subtype, type, sev) \
{ INFOROM_NVL_ERROR_TYPE ## type, \
FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _SEVERITY, sev, 0) | \
FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, dir, 0), \
block ## dir ## subtype ## type, \
INFOROM_NVL_ERROR_BLOCK_TYPE_ ## block \
}
NvlStatus inforom_nvl_v3_map_error
(
INFOROM_NVLINK_ERROR_TYPES error,
NvU8 *pHeader,
NvU16 *pMetadata,
NvU8 *pErrorSubtype,
INFOROM_NVL_ERROR_BLOCK_TYPE *pBlockType
);
NvlStatus
inforom_nvl_v3_encode_nvlipt_error_subtype
(
NvU8 localLinkIdx,
NvU8 *pSubtype
);
NvBool
inforom_nvl_v3_should_replace_error_rate_entry
(
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate,
NvU32 flitCrcRate,
NvU32 *pLaneCrcRates
);
void
inforom_nvl_v3_seconds_to_day_and_month
(
NvU32 sec,
NvU32 *pDay,
NvU32 *pMonth
);
void
inforom_nvl_v3_update_error_rate_entry
(
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate,
NvU32 newSec,
NvU32 newFlitCrcRate,
NvU32 *pNewLaneCrcRates
);
NvlStatus
inforom_nvl_v3_map_error_to_userspace_error
(
nvswitch_device *device,
INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorLog,
NVSWITCH_NVLINK_ERROR_ENTRY *pNvlError
);
void
inforom_nvl_v3_update_correctable_error_rates
(
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState,
NvU8 link,
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts
);
#endif //_INFOROM_NVL_V3_NVSWITCH_H_

37
src/common/nvswitch/kernel/inc/inforom/inforom_nvl_v4_nvswitch.h Normal file
View File

@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _INFOROM_NVL_V4_NVSWITCH_H_
#define _INFOROM_NVL_V4_NVSWITCH_H_
#include "inforom/inforom_nvswitch.h"
void
inforom_nvl_v4_update_correctable_error_rates
(
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState,
NvU8 link,
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts
);
#endif //_INFOROM_NVL_V4_NVSWITCH_H_

12
src/common/nvswitch/kernel/inc/inforom/inforom_nvswitch.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -46,6 +46,12 @@
(destName)[2] = (srcName)[2]; \
}
#define m_inforom_nvl_get_new_errors_per_minute(value, pSum) \
do \
{ \
*pSum = (*pSum - (*pSum / 60)) + value; \
} while (NV_FALSE) \
//
// OS type defines.
//
@ -99,6 +105,7 @@ struct inforom
INFOROM_IMG_OBJECT_V1_00 object;
} IMG;
INFOROM_NVLINK_STATE *pNvlinkState;
INFOROM_ECC_STATE *pEccState;
INFOROM_OMS_STATE *pOmsState;
@ -149,6 +156,8 @@ NvlStatus nvswitch_inforom_nvlink_get_max_correctable_error_rate(nvswitch_device
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params);
NvlStatus nvswitch_inforom_nvlink_get_errors(nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params);
NvlStatus nvswitch_inforom_nvlink_setL1Threshold(nvswitch_device *device, NvU32 word1, NvU32 word2);
NvlStatus nvswitch_inforom_nvlink_getL1Threshold(nvswitch_device *device, NvU32 *word1, NvU32 *word2);
// InfoROM ECC APIs
NvlStatus nvswitch_inforom_ecc_load(nvswitch_device *device);
@ -175,6 +184,7 @@ NvlStatus nvswitch_inforom_bbx_add_sxid(nvswitch_device *device,
NvU32 data1, NvU32 data2);
NvlStatus nvswitch_inforom_bbx_get_sxid(nvswitch_device *device,
NVSWITCH_GET_SXIDS_PARAMS *params);
NvlStatus nvswitch_inforom_bbx_get_data(nvswitch_device *device, NvU8 dataType, void *params);
// InfoROM DEM APIs
NvlStatus nvswitch_inforom_dem_load(nvswitch_device *device);

33
src/common/nvswitch/kernel/inc/lr10/inforom_lr10.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -58,6 +58,29 @@ nvswitch_inforom_nvl_get_errors_lr10
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params
);
NvlStatus nvswitch_inforom_nvl_setL1Threshold_lr10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 word1,
NvU32 word2
);
NvlStatus nvswitch_inforom_nvl_getL1Threshold_lr10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 *word1,
NvU32 *word2
);
NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_lr10
(
nvswitch_device *device,
INFOROM_NVLINK_STATE *pNvlinkState,
NvU8 version
);
NvlStatus
nvswitch_inforom_ecc_log_error_event_lr10
(
@ -146,4 +169,12 @@ nvswitch_bbx_get_sxid_lr10
NVSWITCH_GET_SXIDS_PARAMS * params
);
NvlStatus
nvswitch_bbx_get_data_lr10
(
nvswitch_device *device,
NvU8 dataType,
void *params
);
#endif //_INFOROM_LR10_H_

6
src/common/nvswitch/kernel/inc/lr10/lr10.h
View File

@ -583,9 +583,12 @@ typedef struct
NvBool bDisabledRemoteEndLinkMaskCached;
} lr10_device;
#define NVSWITCH_NUM_DEVICES_PER_DELTA_LR10 6
typedef struct {
NvU32 switchPhysicalId;
NvU64 linkMask;
NvU64 accessLinkMask;
NvU64 trunkLinkMask;
} lr10_links_connected_to_disabled_remote_end;
#define NVSWITCH_GET_CHIP_DEVICE_LR10(_device) \
@ -649,6 +652,7 @@ void nvswitch_setup_link_loopback_mode_lr10(nvswitch_device *device, NvU32
void nvswitch_reset_persistent_link_hw_state_lr10(nvswitch_device *device, NvU32 linkNumber);
void nvswitch_store_topology_information_lr10(nvswitch_device *device, nvlink_link *link);
void nvswitch_init_lpwr_regs_lr10(nvlink_link *link);
void nvswitch_program_l1_scratch_reg_lr10(nvswitch_device *device, NvU32 linkNumber);
NvlStatus nvswitch_set_training_mode_lr10(nvswitch_device *device);
NvBool nvswitch_i2c_is_device_access_allowed_lr10(nvswitch_device *device, NvU32 port, NvU8 addr, NvBool bIsRead);
NvU32 nvswitch_get_sublink_width_lr10(nvswitch_device *device,NvU32 linkNumber);

46
src/common/nvswitch/kernel/inc/ls10/inforom_ls10.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -44,6 +44,43 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10
NvBool *bDirty
);
NvlStatus
nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params
);
NvlStatus
nvswitch_inforom_nvl_get_errors_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params
);
NvlStatus nvswitch_inforom_nvl_setL1Threshold_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 word1,
NvU32 word2
);
NvlStatus nvswitch_inforom_nvl_getL1Threshold_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 *word1,
NvU32 *word2
);
NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_ls10
(
nvswitch_device *device,
INFOROM_NVLINK_STATE *pNvlinkState,
NvU8 version
);
void
nvswitch_initialize_oms_state_ls10
(
@ -117,4 +154,11 @@ nvswitch_bbx_get_sxid_ls10
NVSWITCH_GET_SXIDS_PARAMS * params
);
NvlStatus
nvswitch_bbx_get_data_ls10
(
nvswitch_device *device,
NvU8 dataType,
void *params
);
#endif //_INFOROM_LS10_H_

26
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@ -175,6 +175,9 @@
#define NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10 (NVSWITCH_NUM_LINKS_LS10/NUM_NVLIPT_ENGINE_LS10)
#define NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(_physlinknum) \
((_physlinknum)/NVSWITCH_LINKS_PER_NVLIPT_LS10)
#define NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LS10(_physlinknum) \
((_physlinknum)%NVSWITCH_NUM_LINKS_PER_NVLIPT_LS10)
@ -526,10 +529,20 @@ typedef struct
{
NvBool bLinkErrorsCallBackEnabled;
NvBool bLinkStateCallBackEnabled;
NvBool bResetAndDrainRetry;
NvU64 lastRetrainTime;
NvU64 lastLinkUpTime;
} NVLINK_LINK_ERROR_REPORTING_STATE;
typedef struct
{
NVLINK_LINK_ERROR_INFO_ERR_MASKS fatalIntrMask;
NVLINK_LINK_ERROR_INFO_ERR_MASKS nonFatalIntrMask;
} NVLINK_LINK_ERROR_REPORTING_DATA;
typedef struct
{
NVLINK_LINK_ERROR_REPORTING_STATE state;
NVLINK_LINK_ERROR_REPORTING_DATA data;
} NVLINK_LINK_ERROR_REPORTING;
typedef struct
@ -817,10 +830,6 @@ typedef const struct
#define nvswitch_corelib_write_discovery_token_ls10 nvswitch_corelib_write_discovery_token_lr10
#define nvswitch_corelib_read_discovery_token_ls10 nvswitch_corelib_read_discovery_token_lr10
#define nvswitch_inforom_nvl_get_minion_data_ls10 nvswitch_inforom_nvl_get_minion_data_lr10
#define nvswitch_inforom_nvl_set_minion_data_ls10 nvswitch_inforom_nvl_set_minion_data_lr10
#define nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10 nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10
#define nvswitch_inforom_nvl_get_errors_ls10 nvswitch_inforom_nvl_get_errors_lr10
#define nvswitch_inforom_ecc_log_error_event_ls10 nvswitch_inforom_ecc_log_error_event_lr10
#define nvswitch_inforom_ecc_get_errors_ls10 nvswitch_inforom_ecc_get_errors_lr10
#define nvswitch_inforom_bbx_get_sxid_ls10 nvswitch_inforom_bbx_get_sxid_lr10
@ -835,7 +844,6 @@ typedef const struct
#define nvswitch_setup_link_loopback_mode_ls10 nvswitch_setup_link_loopback_mode_lr10
#define nvswitch_link_lane_reversed_ls10 nvswitch_link_lane_reversed_lr10
#define nvswitch_request_tl_link_state_ls10 nvswitch_request_tl_link_state_lr10
#define nvswitch_i2c_get_port_info_ls10 nvswitch_i2c_get_port_info_lr10
#define nvswitch_i2c_set_hw_speed_mode_ls10 nvswitch_i2c_set_hw_speed_mode_lr10
@ -896,10 +904,6 @@ NvlStatus nvswitch_corelib_set_tx_mode_lr10(nvlink_link *link, NvU64 mode, NvU32
NvlStatus nvswitch_corelib_get_tl_link_mode_lr10(nvlink_link *link, NvU64 *mode);
void nvswitch_init_buffer_ready_lr10(nvswitch_device *device, nvlink_link *link, NvBool bNportBufferReady);
NvlStatus nvswitch_inforom_nvl_get_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData);
NvlStatus nvswitch_inforom_nvl_set_minion_data_lr10(nvswitch_device *device, void *pNvlGeneric, NvU8 linkId, NvU32 *seedData, NvU32 size, NvBool *bDirty);
NvlStatus nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params);
NvlStatus nvswitch_inforom_nvl_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params);
NvlStatus nvswitch_inforom_ecc_log_error_event_lr10(nvswitch_device *device, INFOROM_ECC_OBJECT *pEccGeneric, INFOROM_NVS_ECC_ERROR_EVENT *err_event);
NvlStatus nvswitch_inforom_ecc_get_errors_lr10(nvswitch_device *device, NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS *params);
NvlStatus nvswitch_inforom_bbx_get_sxid_lr10(nvswitch_device *device, NVSWITCH_GET_SXIDS_PARAMS *params);
@ -934,6 +938,7 @@ void nvswitch_corelib_clear_link_state_lr10(nvlink_link *link);
NvlStatus nvswitch_corelib_set_dl_link_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags);
NvlStatus nvswitch_corelib_set_tx_mode_ls10(nvlink_link *link, NvU64 mode, NvU32 flags);
void nvswitch_init_lpwr_regs_ls10(nvlink_link *link);
void nvswitch_program_l1_scratch_reg_ls10(nvswitch_device *device, NvU32 linkNumber);
NvlStatus nvswitch_minion_service_falcon_interrupts_ls10(nvswitch_device *device, NvU32 instance);
@ -991,6 +996,7 @@ NvlStatus nvswitch_reset_and_drain_links_ls10(nvswitch_device *device, NvU64 lin
void nvswitch_service_minion_all_links_ls10(nvswitch_device *device);
NvlStatus nvswitch_ctrl_get_board_part_number_ls10(nvswitch_device *device, NVSWITCH_GET_BOARD_PART_NUMBER_VECTOR *p);
void nvswitch_create_deferred_link_state_check_task_ls10(nvswitch_device *device, NvU32 nvlipt_instance, NvU32 link);
NvlStatus nvswitch_request_tl_link_state_ls10(nvlink_link *link, NvU32 tlLinkState, NvBool bSync);
//
// SU generated functions

7
src/common/nvswitch/kernel/inc/ls10/minion_nvlink_defines_public_ls10.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -46,6 +46,9 @@ typedef enum _MINION_STATUS
MINION_ALARM_BUSY = 80,
} MINION_STATUS;
#define LINKSTATUS_RESET 0x0
#define LINKSTATUS_UNINIT 0x1
#define LINKSTATUS_LANESHUTDOWN 0x13
#define LINKSTATUS_EMERGENCY_SHUTDOWN 0x29
#define LINKSTATUS_INITPHASE1 0x24
#define LINKSTATUS_ACTIVE_PENDING 0x25
#endif // _MINION_NVLINK_DEFINES_PUBLIC_H_

206
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@ -444,7 +444,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56,
0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033,
0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105,
0xbf1200a0, 0x7eff001a, 0x3e00b63c, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000,
0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000,
0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000,
0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03,
0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e,
@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da,
0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028,
0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09,
0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7c8,
0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb,
0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130,
0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04,
0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249,
@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00,
0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204,
0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014,
0x95f90e99, 0x1e0a00f8, 0x00b99f7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f,
0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f,
0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8,
0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00,
0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000,
@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503,
0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0,
0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01,
0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8,
0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8,
0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e,
0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0,
0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00,
@ -1347,17 +1347,17 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00409631, 0x31251df4, 0xf4005a96, 0xd0331e1c, 0xefc41b00, 0x04f9c4ff, 0xc4151bf4, 0x94b30af9,
0xa9180b02, 0x00903307, 0xf8060a08, 0xf8a4bd00, 0x0f12f900, 0xb2b1b202, 0x00a0b3a0, 0xf0a93f22,
0x1bf40894, 0xa3107e17, 0x0010b300, 0x181a2006, 0x060f0809, 0x1bf4a926, 0xb2f4bd05, 0xb211fbfa,
0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb75f7e00, 0xf400f800, 0xdcdff830, 0xf9000005,
0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xdcdff830, 0xf9000005,
0xfeffbf22, 0x99900149, 0xa0a0b210, 0xb3020a9f, 0xbf340000, 0x94943d0a, 0x41fe07b2, 0x902bb201,
0x010c0f11, 0x1db21920, 0x00b7767e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001,
0xfe00b75f, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825,
0x010c0f11, 0x1db21920, 0x00b7797e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001,
0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825,
0x05dcdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600,
0xcf185200, 0xfe94bd07, 0x22900142, 0x01ff1014, 0xcf3529a0, 0x7ecab207, 0xb200a310, 0x080a352b,
0xb27e1ab2, 0xa4b300a7, 0x2bbf2c00, 0x1ab20cb2, 0x00a43f7e, 0x1e00a4b3, 0x4bb21ab2, 0x00a4577e,
0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xdcd99fbf, 0xbf000005,
0xf4f9a699, 0x317e070b, 0x45fb003a, 0xb202f908, 0x00a0b3c0, 0x00c0b324, 0xb6aabf20, 0x804c07b4,
0x7e0db200, 0xb300b776, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317,
0xb2aabf13, 0x07b4b6cd, 0x767e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200,
0x7e0db200, 0xb300b779, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317,
0xb2aabf13, 0x07b4b6cd, 0x797e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200,
0xea7e4200, 0x030000a5, 0xa0b3a1b2, 0x3bb23600, 0x1cb22ab2, 0x00a54d7e, 0xa4b3a0b2, 0x1ab21e00,
0x117eb4bd, 0xa0b200a4, 0x1000a4b3, 0x0c0040b3, 0xf0061918, 0x49a0ff94, 0x1bb22ab2, 0x00a60c7e,
0x41fb0ab2, 0x00f800f8, 0xaeb200f8, 0xb30eaa98, 0xbd0a00a0, 0xa6023ef4, 0x0fea9800, 0x0e00a0b3,
@ -1366,40 +1366,40 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa0b222f9, 0xd2b2c132, 0xb0b3020a, 0x0cb85e00, 0xbd000140, 0x04c998d4, 0x440090b3, 0x08001433,
0x3c0390b3, 0xb93fcf3f, 0x1bf4f926, 0x01cf1832, 0x2601b918, 0x271bf4f9, 0x1802ce18, 0xddbc02bf,
0x909dbc90, 0xb80394b6, 0x00014099, 0x269009bc, 0x0b1bf4ef, 0xa4bd29a0, 0x00a6a83e, 0x9001dd90,
0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65c,
0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65f,
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65c7e7c, 0x0f79bf00,
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05dcdff0, 0x82f90000, 0x49feffbf,
0x30999001, 0xa00147fe, 0x08a9989f, 0xb1b0a6b2, 0xb0f10509, 0x843d0a91, 0x779090b2, 0x0369982c,
0x7fa0f4bd, 0x08f409a6, 0x0804bd07, 0x0a90b401, 0x1bf409a6, 0x00803335, 0xa85a3e32, 0x0c6a9800,
0xb24010bc, 0x7e4bb27c, 0xbf00b65c, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b,
0x3e011190, 0xbd00a82d, 0x0314bd24, 0x056998f1, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18,
0xb24010bc, 0x7e4bb27c, 0xbf00b65f, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b,
0x3e011190, 0xbd00a82d, 0xbdf10314, 0x05699824, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18,
0x09f0b408, 0x6b3ef3a0, 0xf10f00a8, 0x1bf45fa6, 0xbc05b205, 0xdd3e0009, 0x1a0a00a7, 0x59a6f109,
0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6,
0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0,
0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b78d7e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06,
0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65c7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56,
0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b7907e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06,
0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65f7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56,
0x110cf49f, 0x18f496a6, 0xf495a630, 0x093e451b, 0x98a600a9, 0xa62f0bf4, 0x371bf497, 0x90010998,
0x09b50199, 0xa9373e01, 0x04099800, 0xb5019990, 0x373e0409, 0x099800a9, 0x01999002, 0x3e0209b5,
0x9800a937, 0x99900309, 0x0309b501, 0x00a9373e, 0x999009bf, 0x9009a001, 0x39980111, 0xf419a605,
0x49fe8508, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408,
0x0005dcdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f,
0x5c7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6737e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419,
0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6737e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6737e, 0x900149fe,
0x5f7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6767e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419,
0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6767e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6767e, 0x900149fe,
0x12a01099, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005dcdf,
0xbf82f900, 0xf830f4ff, 0x900149fe, 0x9fa06099, 0x18049992, 0xf4bd1cae, 0xa9989fa0, 0x0aa2b205,
0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x887e2001,
0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x8b7e2001,
0x05b200b6, 0x4490a3b2, 0xaa723e30, 0x08299800, 0x0bf439a6, 0xb22ab231, 0xb2010c3b, 0xa8887e4d,
0x04499800, 0x1f0094b3, 0xb3034998, 0x98180094, 0x94b30249, 0x49bf3b00, 0x18f491a6, 0x3e30b209,
0xb200aa65, 0x0bb0b419, 0x6ab291b2, 0x00b6a17e, 0x35a6a3b2, 0x0ab91bf4, 0xf503a603, 0xb301a30b,
0xb200aa65, 0x0bb0b419, 0x6ab291b2, 0x00b6a47e, 0x35a6a3b2, 0x0ab91bf4, 0xf503a603, 0xb301a30b,
0xb20c0014, 0x3e743d03, 0xb200aa8f, 0x94010703, 0x54bd0738, 0x9b3e86b2, 0x2a9800ab, 0xbce4bd0c,
0x4cfe1053, 0x16e1b001, 0xb258cc90, 0xb65c7e1b, 0x00adb300, 0x90b400f3, 0xa6f00f16, 0xd80cf59f,
0xb294bd00, 0x1591b02a, 0x00a5ea7e, 0xa9b3a4b2, 0xbf00d600, 0x4c6bb22a, 0x4db20080, 0x00b7767e,
0x4cfe1053, 0x16e1b001, 0xb258cc90, 0xb65f7e1b, 0x00adb300, 0x90b400f3, 0xa6f00f16, 0xd80cf59f,
0xb294bd00, 0x1591b02a, 0x00a5ea7e, 0xa9b3a4b2, 0xbf00d600, 0x4c6bb22a, 0x4db20080, 0x00b7797e,
0xadb3a0b2, 0xb200a700, 0xb21bb22a, 0x014dfe4c, 0x7e50dd90, 0xb200a4be, 0x00adb3a0, 0x2ab20090,
0x0c014b90, 0x014dfe01, 0x7e54dd90, 0xb200a640, 0x00a4b3a0, 0x15b0b478, 0xfe0c2c98, 0xaa90014a,
0xa6287e30, 0x0c90b400, 0x1bf491a6, 0x14b0b41e, 0x90014afe, 0x5d7e30aa, 0x90b400a9, 0x059f9815,
@ -1407,8 +1407,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x9800ab25, 0xe0b402f9, 0xf491a614, 0xfeb5061b, 0xa6f9bf02, 0x091bf491, 0x893efea0, 0xf99800ab,
0xf491a601, 0xfeb5061b, 0xb24bb201, 0xa60c7e2a, 0x0004b300, 0x01559013, 0x98806690, 0x59a60529,
0xfefa08f5, 0x46007033, 0xb2042f98, 0xb2e4bd8d, 0x00f1b02a, 0x70dc020b, 0xfe000000, 0x11900141,
0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb7487efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd,
0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6737e01,
0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb74b7efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd,
0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6767e01,
0x0b90b400, 0x08f409a6, 0x032f98ec, 0xb59039bc, 0x9fa60929, 0xbd0808f4, 0x0929b594, 0x49fea4bd,
0x60999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4,
0x000005dc, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3,
@ -1416,8 +1416,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, 0x94b30479, 0x05000a01,
0x00aee23e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xea7e3ab2, 0xa2b200a5, 0x1e00a9b3,
0x0c3c9802, 0x40fe7bb2, 0x34009001, 0x287e0ab2, 0x0ab200a6, 0xcc0570b5, 0xc17e708b, 0xa0b200a6,
0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, 0x7e2ab200, 0xbf00b78d,
0x070b943a, 0xb200804c, 0xb7767e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, 0x7e2ab200, 0xbf00b790,
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
@ -1427,7 +1427,7 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x90335b90, 0x3ab21100, 0x00a9d97e, 0xadb3a0b2, 0xb400db00, 0x40b40d00, 0x014ffe11, 0xb250ff90,
0x070d942e, 0x4101f1b0, 0x3ab20080, 0x4cb2010b, 0x7e0011b0, 0xb200a5e4, 0xb22cb20b, 0x014dfe3a,
0x7e4cdd90, 0xb400a4be, 0xa0b214e0, 0x3ab21cb2, 0x0db2b4bd, 0x00a5e67e, 0x91000db3, 0x13b0b400,
0x90014afe, 0x5d7e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x5c7e48cc, 0xa0b200b6, 0x6d00a4b3,
0x90014afe, 0x5d7e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x5f7e48cc, 0xa0b200b6, 0x6d00a4b3,
0x011290b4, 0xf491a6f0, 0x4e98321b, 0x70efcd01, 0x0600f4b3, 0x2918700f, 0xff94f006, 0xbb909ebc,
0x49b5029f, 0xae993e01, 0xb20bb200, 0x7e2cb23a, 0xb200a43f, 0x00a4b3a0, 0x0265bb34, 0x90014afe,
0xaa7e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xe53e0b91, 0x020000ac, 0x00aec93e,
@ -1440,88 +1440,88 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa6287e0a, 0xcc0ab200, 0xc17e702b, 0xa8b200a6, 0xad00adb3, 0x7021cd00, 0x420147fe, 0x77900080,
0xb0383e44, 0x0c00b400, 0x79a094bd, 0x09a6f009, 0x00091bf4, 0xb03f3e02, 0xa6f00900, 0x090df409,
0x3f3e0300, 0xc0b400b0, 0x0704b60b, 0x0db2e4bd, 0xb4bd5ab2, 0xb00021b0, 0xe47e0171, 0x5abf00a5,
0x2cb20bb2, 0x767e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500,
0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500,
0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a,
0x967e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff,
0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff,
0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2,
0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90,
0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9c7e0ab2, 0x09bf00b7, 0x4c0090b3,
0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3,
0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5,
0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990,
0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b,
0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302,
0xb63004f8, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200,
0xb200b776, 0x00adb3a5, 0x093f04ae, 0x9f4a9d33, 0x01091804, 0x97469d33, 0x02091804, 0x8f469d33,
0x03091804, 0x87539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4,
0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045b0bf5, 0xd6b00505, 0x5a0cf503, 0x013db504,
0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200,
0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33,
0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4,
0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, 0x5d0cf503, 0x013db504,
0x0e01d4b3, 0xb5500049, 0xd83e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, 0xd4f00b0e, 0xff94f0ff,
0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, 0x0bb23ab2, 0x00a60c7e,
0x09023a98, 0xa60305ff, 0x080bf5a9, 0x07a5b604, 0xb5303b90, 0xcf7e033a, 0xa5b200b6, 0xf500adb3,
0x033b9803, 0x3a90c009, 0x3fbb9034, 0xb604b9fd, 0x9c7e03b5, 0xa5b200b7, 0xd900adb3, 0x0147fe03,
0x900148fe, 0x44bd4077, 0x90017990, 0x91b03c88, 0xb3453e09, 0xa0e4bd00, 0x0044b38e, 0x0c3a980f,
0xfe0cb4bd, 0x00b2683e, 0x4bb23ab2, 0x797e7cb2, 0xa5b200a5, 0x9d00adb3, 0xf0793f03, 0x0bf40194,
0x0c3a9812, 0xff0c4bb2, 0x00b6737e, 0x00b3423e, 0x307e7ab2, 0xa0b300a3, 0x3a980f00, 0x0c4bb20c,
0xb2683efd, 0xf0793f00, 0x1bf40294, 0x0c3a980e, 0xfd0c4bb2, 0x00b3373e, 0xb209b0b4, 0xb2010c3a,
0xa6407e8d, 0x00a0b300, 0xb2793f5d, 0xc724bd3f, 0x99900299, 0x0a91b001, 0xb354f598, 0xb4390054,
0x22bc09b0, 0xbc030c00, 0x04b60002, 0x4001b803, 0x31bc0001, 0x7e1ab210, 0xbc00b796, 0x09b80030,
0x20000143, 0x5302b595, 0xb50af0b4, 0x81a0540f, 0x00b3023e, 0x90012290, 0x24b318ff, 0x2f3ebe14,
0x8ebf00b6, 0x7f58793f, 0x077d1802, 0x9803ee98, 0x99c70d3a, 0x00f3f002, 0xcb70ffcc, 0x4bb21f96,
0x0cd8e6cb, 0xf0d6cb01, 0x01e0f6eb, 0x00a2e67e, 0xb20c3a98, 0x7e6cb24b, 0xb200b673, 0x00adb3a5,
0x449002b4, 0x033b9801, 0x08f54ba6, 0x94bdfeeb, 0xa0b0bbbc, 0x7e8ab289, 0xb200b7b2, 0x00adb3a5,
0x37b20294, 0x7f9884bd, 0x9088bc54, 0xb69098bc, 0x99b80394, 0xbc000140, 0x91b09039, 0x00f9b30b,
0x3c980253, 0x0fa0b403, 0x24bdb43d, 0xbdc0ccbc, 0xb78d7e44, 0x0f60b400, 0x00b4603e, 0xb20d3a98,
0x0c41b02b, 0x00a2f67e, 0xb500a933, 0x0c3a9800, 0xb2014cfe, 0x38cc902b, 0x00b65c7e, 0x0c00adb3,
0x0be0b402, 0x980e90b4, 0x99c703ef, 0xf59fa6d8, 0x98008e1b, 0x2bb20d3a, 0xee7e010c, 0x4cfe00a2,
0xb23ab201, 0x30cc902b, 0x00a5947e, 0x1306a4b3, 0xb20c3a98, 0x7efd0c2b, 0x3e00b673, 0xb300b45d,
0x01cb00ad, 0xf01c9074, 0x99bc0093, 0x0069bc90, 0x19e4017f, 0x1bf4ffff, 0x3e026009, 0x9800b45d,
0x4cfe0c3a, 0xff1be401, 0x34cc90ff, 0x00b65c7e, 0x9800adb3, 0x3af03401, 0x26369034, 0x100df4f9,
0x1be40260, 0x3a98ffff, 0xb4523e0c, 0x0c3a9800, 0xfd0c2bb2, 0x00b6737e, 0x7000adb3, 0x01229001,
0xa6033a98, 0x3708f52a, 0xb264b2ff, 0x3db43d6e, 0xbdf4bdd4, 0xb4943ec4, 0x73e97f00, 0x0d0a0094,
0xb48e3e01, 0x00d03300, 0x90010b06, 0xff9001cc, 0x02ee9001, 0x08f4faa6, 0x00c4b3e3, 0x547cb50b,
0x00b5d03e, 0xa600b933, 0x01399800, 0xf40296b0, 0x0309300c, 0x79b56db2, 0xbde4bd54, 0xb4d33ef4,
0x73d97f00, 0x7c0a0090, 0xee90e969, 0x01ff9001, 0x9802dd90, 0xf9a60339, 0x3ee908f4, 0xbd00b54a,
0xb5f10194, 0x24bd5479, 0x243e1bb2, 0x407f00b5, 0xffff09e4, 0x0f260bf4, 0xf4bfa6f1, 0x0be40b1b,
0x1c3effff, 0x3a9800b5, 0xff0ce40c, 0xb6737eff, 0x00adb300, 0x0be400b9, 0x19b2ffff, 0x90012290,
0x91b20244, 0xa6033998, 0xc508f429, 0xb9a6f109, 0x00a00bf5, 0x980c3a98, 0x737e0a3c, 0xadb300b6,
0xb5008c00, 0xd03e0a31, 0x6f7f00b5, 0xc19294bd, 0x5179b501, 0xbd00f3f0, 0x527fb504, 0x00b5883e,
0x4c584b7f, 0x0c3a9801, 0xf0010090, 0xc3f000b3, 0x02449000, 0x00b6737e, 0x5200a4b3, 0x980be0b4,
0x999001e9, 0x01e9b570, 0x08f401a6, 0x08607cd6, 0x0c0c3a98, 0xff0be4f0, 0xb6737eff, 0x00a4b300,
0x014cfe2d, 0xffff0be4, 0xcc903ab2, 0xa5797e40, 0x00a4b300, 0x46903419, 0xf0517f98, 0xf9bcff94,
0x517fb5f0, 0x00b5d03e, 0xa5b2030a, 0x00b5db3e, 0x90018890, 0x8db31877, 0xfefd9014, 0x99900149,
0x7e9abf3c, 0x3e00b746, 0x0500b5f1, 0xb5f33e03, 0xb204bd00, 0x7e3ab20b, 0xb300a60c, 0x981a0050,
0x04bd0c3a, 0x00b6c57e, 0xb50d3a98, 0x467e0c30, 0x30b500b7, 0x0149fe0d, 0xbf509990, 0x05dcd99f,
0x99bf0000, 0xf9a65ab2, 0x3e110bf4, 0x0500b635, 0xb5f13e01, 0x3a317e00, 0x3085fb00, 0xa0b202f9,
0x00a5e87e, 0x7e0c0a98, 0x9800b6c5, 0x467e0d0a, 0x0ab200b7, 0x00b7467e, 0x01fba4bd, 0xafb2a9bf,
0xb9a6020a, 0x900d18f4, 0xf9bc01b9, 0xa0a4bd98, 0xbf00f8c9, 0x0aafb2a9, 0xf4b9a602, 0xb9900b18,
0xbca4bd01, 0x00f899fc, 0xafb2b9bf, 0xc9a6cab2, 0x0a0708f4, 0xb500f8f1, 0xfca002fb, 0xf801fcb5,
0x98a9bf00, 0xb9bc02af, 0xbfa9a090, 0xf49ba6fb, 0x9bbb0808, 0x98a9a002, 0xaabf01a9, 0x1bf4a9a6,
0xf8f10a05, 0x00a0b300, 0xb7467e08, 0xf400f800, 0xdcdff830, 0xf9000005, 0xfeffbf32, 0x99900149,
0xa0a0b214, 0xb3b3b29f, 0x024200a0, 0xf4a2a6fd, 0xab903a0c, 0x0141fe01, 0x9002b4b6, 0x1ab21011,
0x00b7b27e, 0x2700a4b3, 0x1db219bf, 0xe4bd2cb2, 0xdfbf90a0, 0xb201e990, 0x99fcbc9e, 0x08f490a6,
0xa0ddbff4, 0xb72b3e3d, 0xfe020a00, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4,
0xfb003a31, 0x00f80835, 0x002944da, 0x41c77e00, 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xda00f801,
0x00002944, 0x0041427e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x300042d7,
0xacf000a6, 0x01a6f00b, 0xf801aab9, 0xffb4f000, 0x000b947e, 0x7e7e00f8, 0x00f8000b, 0xa0b202f9,
0x4c7ea43d, 0xa6b00038, 0x0b9cf000, 0x9ab20aa0, 0x02f901fb, 0xa43da0b2, 0x00382a7e, 0xf000a6b0,
0x0aa00b9c, 0x01fb9ab2, 0xdfe430f4, 0x000005dc, 0xffbf82f9, 0xfe0149fe, 0x99900145, 0x0147fe3c,
0x55909fa0, 0x34779024, 0x00141cd9, 0xfe9abf00, 0x080c014b, 0x0d2cbb90, 0x00c17eff, 0x00a43300,
0x0c30b4eb, 0x9433393f, 0x3118e20c, 0x00103304, 0x0119330f, 0x043d00b0, 0x00b96e3e, 0xd9023f98,
0x0000142c, 0x58043198, 0x5fa00a34, 0x39989f3f, 0x18369003, 0x090159b5, 0x3379a0ff, 0x7e1800f4,
0x320032f7, 0x00ad33a0, 0x01090129, 0x00142cdf, 0x72f92000, 0x0043f012, 0xae3e14bd, 0x41bc00b8,
0x0006b102, 0x060df401, 0x7e010040, 0xd9000b94, 0x00001424, 0x2ce49abf, 0x6bb2ffff, 0x00de0db2,
0x7e000013, 0xa000af12, 0x00adb37a, 0x5bbf00d4, 0x90015c98, 0x0eb2041d, 0xbc20207c, 0x00da1010,
0x7e000013, 0x32002136, 0x00ad33a0, 0xb4bd00c5, 0xda01004c, 0x00001300, 0x08f414a6, 0xb95d3ea4,
0x023f9800, 0x00142cd9, 0x04349800, 0xa00a3258, 0x989f3f5f, 0x38900339, 0x0159b518, 0x79a0ff09,
0x1600f433, 0x0032f77e, 0xad33a032, 0xdf008400, 0x0000142c, 0x26e4f120, 0x24bdffff, 0x00b94e3e,
0xb11262bc, 0xf4010016, 0x0041060d, 0x0b947e01, 0x985bbf00, 0x2d90015c, 0xda1eb204, 0x00001300,
0x0020d07e, 0xffff4ce4, 0x322021bc, 0xb28bb2a0, 0x1300de1d, 0x417c0000, 0x00a43340, 0x1424d935,
0x9abf0000, 0x00ac3c7e, 0xa4b37aa0, 0xb4bd1300, 0xda01004c, 0x00001300, 0x08f426a6, 0x985bbfa6,
0x7ab2015c, 0x040ed4bd, 0x0021367e, 0xb034a032, 0x7e3ab22d, 0x33000f81, 0xfe71000d, 0x0f3a0130,
0x38f13002, 0x09033318, 0x014afe04, 0x30399130, 0xb4bd3b31, 0x7e38aa90, 0x3e000f71, 0xf900b7e8,
0x2930d902, 0xa0b20000, 0x640b9abf, 0x0000de7e, 0xa4331009, 0x00896100, 0x9fcf02a6, 0x00f5f100,
0x009ff610, 0x02a6008a, 0xbd10004b, 0x27104dc4, 0x8b7ee4bd, 0xa4330019, 0x30d91500, 0xbf000029,
0x009b7e9a, 0x3e040900, 0xb200ba13, 0x03e84b0a, 0x0016fc7e, 0x02a40089, 0x0200aab8, 0x0aa5b600,
0xf601aa92, 0x114f009a, 0x0099b801, 0x9ff60002, 0x32943d00, 0x0001fb9a, 0x00000000, 0x00000000,
0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5ee3e, 0x9007a5b6, 0x3ab5303b, 0xb6d27e03, 0xb3a5b200,
0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79f7e03, 0xb3a5b200, 0x03d900ad,
0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3483e, 0x8ea0e4bd, 0x0f0044b3,
0xbd0c3a98, 0x3efe0cb4, 0xb200b26b, 0xb24bb23a, 0xa5797e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f,
0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b676, 0xb200b345, 0xa3307e7a, 0x00a0b300, 0x0c3a980f,
0xfd0c4bb2, 0x00b26b3e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b33a, 0x3ab209b0,
0x8db2010c, 0x00a6407e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5,
0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x997e1ab2, 0x30bc00b7,
0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b305, 0xff900122, 0x1424b318,
0xb6323ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff,
0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e6, 0x4bb20c3a, 0x767e6cb2, 0xa5b200b6,
0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb57e8ab2, 0xa5b200b7,
0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090,
0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7907e, 0x3e0f60b4, 0x9800b463,
0x2bb20d3a, 0x7e0c41b0, 0x3300a2f6, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65f,
0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ee7e01,
0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a594, 0x981306a4, 0x2bb20c3a, 0x767efd0c, 0x603e00b6,
0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x603e0260,
0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65f, 0x019800ad, 0x343af034, 0xf9263690,
0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b4553e, 0xb20c3a98, 0x7efd0c2b, 0xb300b676, 0x017000ad,
0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4973e, 0x9473e97f,
0x010d0a00, 0x00b4913e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3,
0x3e547cb5, 0x3300b5d3, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd,
0x00b4d63e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x4d3ee908,
0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb5273e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6,
0xff0be40b, 0xb51f3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6767e, 0xb900adb3, 0xff0be400, 0x9019b2ff,
0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6767e0a,
0x00adb300, 0x31b5008c, 0xb5d33e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5,
0x7f00b58b, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b676, 0xb45200a4,
0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6767e,
0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5797e, 0x1900a4b3, 0x98469034, 0x94f0517f,
0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90,
0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6,
0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099,
0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb,
0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4,
0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6,
0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002,
0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01,
0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf,
0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4,
0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc,
0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699,
0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901,
0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000,
0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800,
0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a,
0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001,
0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e,
0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971,
0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0,
0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8b13e14,
0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff,
0x1300de0d, 0x127e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020,
0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414,
0x00b9603e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5,
0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff,
0xbc00b951, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2,
0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433,
0x001424d9, 0x7e9abf00, 0xa000ac3c, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426,
0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100,
0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xeb3e000f,
0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02,
0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915,
0x9abf0000, 0x00009b7e, 0x163e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa,
0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x7f8cbe99, 0x0e2a64d9, 0x6c95f843, 0x38bac675,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcaafe5ce, 0x6ff4be12, 0x691b2548, 0xa6e91959,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x59305452, 0xfe64d88a, 0xe474c23b, 0xfee62bd9,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xd0954f7e, 0x7caea789, 0x40b32eb9, 0x80368ac3,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

206
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005dcdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@ -444,7 +444,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xfeffbf22, 0x99900149, 0x0142fe14, 0x94bd9fa0, 0xa00c2290, 0x3da37e29, 0x00a03300, 0xda040b56,
0x00002944, 0x2db2bcb2, 0x0042d77e, 0xa433a032, 0x41fe4300, 0x10119001, 0x8e7e1ab2, 0xa0320033,
0x3100a433, 0x2bbf1cbf, 0x24d1a4bd, 0x7e000014, 0xa000b06d, 0x00a0b31a, 0x7eb43d1a, 0xb300b105,
0xbf1200a0, 0x7eff001a, 0x3e00b63c, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000,
0xbf1200a0, 0x7eff001a, 0x3e00b63f, 0x00003371, 0x0149feff, 0xbf149990, 0x05dcd99f, 0x99bf0000,
0xf9a60a32, 0x7e070bf4, 0xfb003a31, 0x0e090c25, 0xa43da9a0, 0x30f400f8, 0x05dcdfd8, 0x62f90000,
0x30f4ffbf, 0x0149fef4, 0xa04c9990, 0xb2a93f9f, 0x01a398a6, 0x0d019033, 0x60489d33, 0x35a33e03,
0x04301800, 0x1b010d33, 0x03329801, 0x3d043198, 0x10dc4ba4, 0xd501004c, 0x00000644, 0x0038327e,
@ -646,7 +646,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x01b024a1, 0x08113001, 0x300c1130, 0x050d1c01, 0xda00c04e, 0x000005d0, 0x005d0a7e, 0x001404da,
0x0c040b00, 0x59377e08, 0x00ad3300, 0x4d4c00f6, 0x00c3f171, 0x00d8db00, 0xa1300000, 0x00a13028,
0x3010a130, 0xa13014a1, 0x20a13018, 0xb024a130, 0x11300101, 0x0c113008, 0x0d1c0130, 0x00804e09,
0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7c8,
0x0005d4da, 0x5d0a7e00, 0x1428da00, 0x040b0000, 0x377e080c, 0xad330059, 0x4c00a900, 0xc3f1b7cb,
0xb4db0000, 0x30000000, 0xa13028a1, 0x10a13000, 0x3014a130, 0xa13018a1, 0x24a13020, 0x300c1130,
0x01b01c01, 0x08113001, 0xc04e0a0d, 0x05d8da00, 0x0a7e0000, 0x1cda005d, 0x0b000014, 0x7e080c04,
0x33005937, 0x7e5c00a4, 0x7e005c97, 0x7e004db4, 0x7e005931, 0x7e000a74, 0x7e003cf7, 0x7e005249,
@ -662,7 +662,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x3d071bf4, 0xc700f8a4, 0x96b024f9, 0x0b9cf002, 0x00f89a32, 0x0089050f, 0x9ff60180, 0xb8060f00,
0x00010099, 0xf8009ff6, 0x02008900, 0x0099cf01, 0x1000008f, 0xf4049ffd, 0x34da181b, 0x7e008204,
0xf0001a27, 0x1bf401a4, 0x0a02f809, 0x3d00f824, 0xd900f8a4, 0x00001430, 0x34da99bf, 0x98000014,
0x95f90e99, 0x1e0a00f8, 0x00b99f7e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f,
0x95f90e99, 0x1e0a00f8, 0x00b9a27e, 0x0600a033, 0x00f802f8, 0x0100008f, 0xf6590049, 0x00f8009f,
0x00900089, 0xf00099ce, 0x0bf40194, 0xf1008e20, 0x00e9ce00, 0x9ffdef0f, 0x00e9f704, 0x5200eeb8,
0x00e9ce02, 0xf7049ffd, 0x00f800e9, 0x7e0a004a, 0xe7001a27, 0xb30114aa, 0x4f1e06a4, 0xf9cf4f00,
0xe899c700, 0x110f94b3, 0xf000f9cf, 0x9cf0ff94, 0xf89a320b, 0xf8a43d00, 0x8902f900, 0xce009000,
@ -751,7 +751,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00f0b305, 0x0a09584a, 0x90014afe, 0xafb508aa, 0x010f9801, 0xb60093f0, 0xa9b50294, 0x02afb503,
0xb2100918, 0x18a9351b, 0xb5020f98, 0x099804af, 0x05a9b503, 0xa0a000bf, 0x005b0b7e, 0xf001a6b0,
0x9a120b9c, 0x59ab3e01, 0xfb020a00, 0xe27e1c15, 0x943d0059, 0xf001a6b0, 0xa6f00bac, 0xa29a3c01,
0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a09f8,
0x4c8900f8, 0x9ebf0005, 0xb5019f98, 0x9ea0019f, 0x005a267e, 0x0801a4b3, 0x00f8a43d, 0xff0a02f8,
0x12f900f8, 0x000f8c89, 0xf20a99bf, 0x380090b3, 0x000fa881, 0xf10a10bf, 0x2c0004b3, 0x000a747e,
0x19a00109, 0x000f9889, 0x948990a0, 0xff0f0010, 0x90899fa0, 0x90a0000f, 0x000f9489, 0x587e9fa0,
0x10a00037, 0x12f911fb, 0x000f8c89, 0xb4bd04bd, 0xb44c90a0, 0x0fac8a00, 0x0b947e00, 0x0cb4bd00,
@ -1347,17 +1347,17 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00409631, 0x31251df4, 0xf4005a96, 0xd0331e1c, 0xefc41b00, 0x04f9c4ff, 0xc4151bf4, 0x94b30af9,
0xa9180b02, 0x00903307, 0xf8060a08, 0xf8a4bd00, 0x0f12f900, 0xb2b1b202, 0x00a0b3a0, 0xf0a93f22,
0x1bf40894, 0xa3107e17, 0x0010b300, 0x181a2006, 0x060f0809, 0x1bf4a926, 0xb2f4bd05, 0xb211fbfa,
0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb75f7e00, 0xf400f800, 0xdcdff830, 0xf9000005,
0xb3020aa9, 0xbf1200c0, 0xb6cdb29a, 0x804c07b4, 0xb7627e00, 0xf400f800, 0xdcdff830, 0xf9000005,
0xfeffbf22, 0x99900149, 0xa0a0b210, 0xb3020a9f, 0xbf340000, 0x94943d0a, 0x41fe07b2, 0x902bb201,
0x010c0f11, 0x1db21920, 0x00b7767e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001,
0xfe00b75f, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825,
0x010c0f11, 0x1db21920, 0x00b7797e, 0x1700a4b3, 0x0abf193f, 0x1db22bb2, 0x0cfd94f0, 0x7e192001,
0xfe00b762, 0x99900149, 0xd99fbf10, 0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40825,
0x05dcdff8, 0x42f90000, 0x49feffbf, 0x18999001, 0x9fa0a1b2, 0xc0b2b4b2, 0xa0b3d3b2, 0xc0b35600,
0xcf185200, 0xfe94bd07, 0x22900142, 0x01ff1014, 0xcf3529a0, 0x7ecab207, 0xb200a310, 0x080a352b,
0xb27e1ab2, 0xa4b300a7, 0x2bbf2c00, 0x1ab20cb2, 0x00a43f7e, 0x1e00a4b3, 0x4bb21ab2, 0x00a4577e,
0x1200a4b3, 0x0e0030b3, 0x32a022bf, 0x00a5323e, 0x49fe020a, 0x18999001, 0xdcd99fbf, 0xbf000005,
0xf4f9a699, 0x317e070b, 0x45fb003a, 0xb202f908, 0x00a0b3c0, 0x00c0b324, 0xb6aabf20, 0x804c07b4,
0x7e0db200, 0xb300b776, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317,
0xb2aabf13, 0x07b4b6cd, 0x767e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200,
0x7e0db200, 0xb300b779, 0xb21000a4, 0xa3307e0a, 0xa5773e00, 0xfb020a00, 0x00a0b301, 0x00c0b317,
0xb2aabf13, 0x07b4b6cd, 0x797e100c, 0x00f800b7, 0x00f8020a, 0xb3b242f9, 0xa2b2c4b2, 0xa0b30200,
0xea7e4200, 0x030000a5, 0xa0b3a1b2, 0x3bb23600, 0x1cb22ab2, 0x00a54d7e, 0xa4b3a0b2, 0x1ab21e00,
0x117eb4bd, 0xa0b200a4, 0x1000a4b3, 0x0c0040b3, 0xf0061918, 0x49a0ff94, 0x1bb22ab2, 0x00a60c7e,
0x41fb0ab2, 0x00f800f8, 0xaeb200f8, 0xb30eaa98, 0xbd0a00a0, 0xa6023ef4, 0x0fea9800, 0x0e00a0b3,
@ -1366,40 +1366,40 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa0b222f9, 0xd2b2c132, 0xb0b3020a, 0x0cb85e00, 0xbd000140, 0x04c998d4, 0x440090b3, 0x08001433,
0x3c0390b3, 0xb93fcf3f, 0x1bf4f926, 0x01cf1832, 0x2601b918, 0x271bf4f9, 0x1802ce18, 0xddbc02bf,
0x909dbc90, 0xb80394b6, 0x00014099, 0x269009bc, 0x0b1bf4ef, 0xa4bd29a0, 0x00a6a83e, 0x9001dd90,
0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65c,
0xd4b318cc, 0x040ab314, 0xabbf21fb, 0xf009acb2, 0x0bf4b9a6, 0x03aa980d, 0x7e01cbb5, 0xf800b65f,
0xb232f900, 0xbdb2b2a1, 0x3ef00304, 0xbf00a6f0, 0x01009019, 0x93a61ab2, 0x0a090df4, 0xa6f73e03,
0xf493a600, 0x020a091b, 0x00a6f73e, 0x00a6aa7e, 0x08f402a6, 0xfba4bddd, 0xf830f431, 0x0005dcdf,
0xbf82f900, 0x0149feff, 0xb2289990, 0xb29fa0a3, 0x00a9b3b8, 0xb0b30084, 0x47fe7f00, 0x05a49801,
0x54bd24bd, 0x779014bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65c7e7c, 0x0f79bf00,
0x14bd54bd, 0x779024bd, 0xa7613e24, 0x0c3a9800, 0x02bc94bd, 0xb279a0b0, 0xb65f7e7c, 0x0f79bf00,
0xf49fa6ff, 0x643d090b, 0x00a74f3e, 0x90015590, 0x04a60100, 0x33d908f4, 0x90070060, 0x24bc0111,
0x03399820, 0x18f429a6, 0xbd01060b, 0xa7523e04, 0xb24bb200, 0x16fc7e1a, 0xf45aa600, 0x1190060d,
0x06399801, 0x19a6f43d, 0x0f050cf4, 0xbd8f2001, 0xa7973ea4, 0xfe020a00, 0x99900149, 0xd99fbf28,
0x000005dc, 0xf9a699bf, 0x7e070bf4, 0xfb003a31, 0x30f40885, 0x05dcdff0, 0x82f90000, 0x49feffbf,
0x30999001, 0xa00147fe, 0x08a9989f, 0xb1b0a6b2, 0xb0f10509, 0x843d0a91, 0x779090b2, 0x0369982c,
0x7fa0f4bd, 0x08f409a6, 0x0804bd07, 0x0a90b401, 0x1bf409a6, 0x00803335, 0xa85a3e32, 0x0c6a9800,
0xb24010bc, 0x7e4bb27c, 0xbf00b65c, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b,
0x3e011190, 0xbd00a82d, 0x0314bd24, 0x056998f1, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18,
0xb24010bc, 0x7e4bb27c, 0xbf00b65f, 0xa6ff0f79, 0x0f1bf49f, 0x09012290, 0xf439a6f1, 0x43b2051b,
0x3e011190, 0xbd00a82d, 0xbdf10314, 0x05699824, 0x08f419a6, 0x0020b3cb, 0xf429a61e, 0x60b50f18,
0x09f0b408, 0x6b3ef3a0, 0xf10f00a8, 0x1bf45fa6, 0xbc05b205, 0xdd3e0009, 0x1a0a00a7, 0x59a6f109,
0xb50d0bf4, 0x90b40865, 0xbd95a009, 0x0149fea4, 0xbf309990, 0x05dcd99f, 0x99bf0000, 0x0bf4f9a6,
0x3a317e07, 0x1085fb00, 0xd9f830f4, 0x000005dc, 0x99bf82f9, 0x90014ffe, 0xa3b228ff, 0xb4b2f9a0,
0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b78d7e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06,
0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65c7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56,
0xc033d0b2, 0xdab20e00, 0x140cb43d, 0x00b7907e, 0xbd0142fe, 0x24229014, 0xff07fe08, 0xfb05fc06,
0x00a93a3e, 0xbd0c3a98, 0xb014bc94, 0x2cb229a0, 0x00b65f7e, 0xf00f29bf, 0x0df49fa6, 0xa6fd0f56,
0x110cf49f, 0x18f496a6, 0xf495a630, 0x093e451b, 0x98a600a9, 0xa62f0bf4, 0x371bf497, 0x90010998,
0x09b50199, 0xa9373e01, 0x04099800, 0xb5019990, 0x373e0409, 0x099800a9, 0x01999002, 0x3e0209b5,
0x9800a937, 0x99900309, 0x0309b501, 0x00a9373e, 0x999009bf, 0x9009a001, 0x39980111, 0xf419a605,
0x49fe8508, 0x28999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x85fb003a, 0xf830f408,
0x0005dcdf, 0xb222f900, 0xb2ffbfa1, 0x03aa98b2, 0x49fe1bbf, 0x10999001, 0xa00140fe, 0x0c00909f,
0x5c7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6737e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419,
0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6737e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6737e, 0x900149fe,
0x5f7e0cb2, 0x0cbf00b6, 0xb2031a98, 0xb6767e2b, 0x011b9800, 0xb9a6ff09, 0x98101bf4, 0x12b50419,
0x0292b502, 0x00a9b13e, 0xb2031a98, 0xb6767e2c, 0x031a9800, 0xfd0c1bbf, 0x00b6767e, 0x900149fe,
0x12a01099, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x25fb003a, 0xc830f408, 0x0005dcdf,
0xbf82f900, 0xf830f4ff, 0x900149fe, 0x9fa06099, 0x18049992, 0xf4bd1cae, 0xa9989fa0, 0x0aa2b205,
0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x887e2001,
0x0b91b005, 0x1a00e933, 0x0c2b9802, 0xfe092c98, 0xf100014a, 0xfe44aa90, 0xa6b20144, 0x8b7e2001,
0x05b200b6, 0x4490a3b2, 0xaa723e30, 0x08299800, 0x0bf439a6, 0xb22ab231, 0xb2010c3b, 0xa8887e4d,
0x04499800, 0x1f0094b3, 0xb3034998, 0x98180094, 0x94b30249, 0x49bf3b00, 0x18f491a6, 0x3e30b209,
0xb200aa65, 0x0bb0b419, 0x6ab291b2, 0x00b6a17e, 0x35a6a3b2, 0x0ab91bf4, 0xf503a603, 0xb301a30b,
0xb200aa65, 0x0bb0b419, 0x6ab291b2, 0x00b6a47e, 0x35a6a3b2, 0x0ab91bf4, 0xf503a603, 0xb301a30b,
0xb20c0014, 0x3e743d03, 0xb200aa8f, 0x94010703, 0x54bd0738, 0x9b3e86b2, 0x2a9800ab, 0xbce4bd0c,
0x4cfe1053, 0x16e1b001, 0xb258cc90, 0xb65c7e1b, 0x00adb300, 0x90b400f3, 0xa6f00f16, 0xd80cf59f,
0xb294bd00, 0x1591b02a, 0x00a5ea7e, 0xa9b3a4b2, 0xbf00d600, 0x4c6bb22a, 0x4db20080, 0x00b7767e,
0x4cfe1053, 0x16e1b001, 0xb258cc90, 0xb65f7e1b, 0x00adb300, 0x90b400f3, 0xa6f00f16, 0xd80cf59f,
0xb294bd00, 0x1591b02a, 0x00a5ea7e, 0xa9b3a4b2, 0xbf00d600, 0x4c6bb22a, 0x4db20080, 0x00b7797e,
0xadb3a0b2, 0xb200a700, 0xb21bb22a, 0x014dfe4c, 0x7e50dd90, 0xb200a4be, 0x00adb3a0, 0x2ab20090,
0x0c014b90, 0x014dfe01, 0x7e54dd90, 0xb200a640, 0x00a4b3a0, 0x15b0b478, 0xfe0c2c98, 0xaa90014a,
0xa6287e30, 0x0c90b400, 0x1bf491a6, 0x14b0b41e, 0x90014afe, 0x5d7e30aa, 0x90b400a9, 0x059f9815,
@ -1407,8 +1407,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x9800ab25, 0xe0b402f9, 0xf491a614, 0xfeb5061b, 0xa6f9bf02, 0x091bf491, 0x893efea0, 0xf99800ab,
0xf491a601, 0xfeb5061b, 0xb24bb201, 0xa60c7e2a, 0x0004b300, 0x01559013, 0x98806690, 0x59a60529,
0xfefa08f5, 0x46007033, 0xb2042f98, 0xb2e4bd8d, 0x00f1b02a, 0x70dc020b, 0xfe000000, 0x11900141,
0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb7487efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd,
0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6737e01,
0x0111b05c, 0x00a5e47e, 0xbf042c98, 0x048bb22a, 0xb74b7efb, 0x981ebf00, 0xa0b2042c, 0x2ab2b4bd,
0xe67e0db2, 0x04b300a5, 0xff040600, 0x013e04bd, 0x2a9800ac, 0xb003bc0c, 0x00904cb2, 0xb6767e01,
0x0b90b400, 0x08f409a6, 0x032f98ec, 0xb59039bc, 0x9fa60929, 0xbd0808f4, 0x0929b594, 0x49fea4bd,
0x60999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b, 0x30f4003a, 0x3885fb08, 0xd9cc30f4,
0x000005dc, 0x99bf82f9, 0xfef830f4, 0xff90014f, 0xb0f9a05c, 0xc8b20be1, 0xa3b2d6b2, 0x8400b9b3,
@ -1416,8 +1416,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa0b200a6, 0x5e00adb3, 0xbc17bf02, 0x7998f068, 0xf59fa601, 0x98024d08, 0x94b30479, 0x05000a01,
0x00aee23e, 0x3e0069b3, 0x027f9802, 0xf9a6f009, 0x022a0bf5, 0xea7e3ab2, 0xa2b200a5, 0x1e00a9b3,
0x0c3c9802, 0x40fe7bb2, 0x34009001, 0x287e0ab2, 0x0ab200a6, 0xcc0570b5, 0xc17e708b, 0xa0b200a6,
0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, 0x7e2ab200, 0xbf00b78d,
0x070b943a, 0xb200804c, 0xb7767e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe900adb3, 0x0d00b401, 0x01a6f001, 0x01ce0bf5, 0x01d00cf5, 0x804cb43d, 0x7e2ab200, 0xbf00b790,
0x070b943a, 0xb200804c, 0xb7797e2d, 0x0ca1b000, 0xb600adb3, 0x05291801, 0x76042f18, 0xf4f00894,
0xe59fffff, 0xe966ff09, 0x01980bf5, 0xffffe9e4, 0x08f589a6, 0xf4bd018e, 0x18902fbc, 0x9d330999,
0x90018200, 0xf4b301ff, 0xfc3ef207, 0x8e3c00ae, 0xf59f26f2, 0xc4016d08, 0x94f0fffd, 0x529dbcff,
0x0df456a6, 0x9065b205, 0xa43d10d9, 0x3db029bc, 0x3ee4bdc4, 0xb100ada7, 0xf5006fd6, 0xb401450c,
@ -1427,7 +1427,7 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x90335b90, 0x3ab21100, 0x00a9d97e, 0xadb3a0b2, 0xb400db00, 0x40b40d00, 0x014ffe11, 0xb250ff90,
0x070d942e, 0x4101f1b0, 0x3ab20080, 0x4cb2010b, 0x7e0011b0, 0xb200a5e4, 0xb22cb20b, 0x014dfe3a,
0x7e4cdd90, 0xb400a4be, 0xa0b214e0, 0x3ab21cb2, 0x0db2b4bd, 0x00a5e67e, 0x91000db3, 0x13b0b400,
0x90014afe, 0x5d7e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x5c7e48cc, 0xa0b200b6, 0x6d00a4b3,
0x90014afe, 0x5d7e34aa, 0x3a9800a9, 0x0db0b40c, 0x90014cfe, 0x5f7e48cc, 0xa0b200b6, 0x6d00a4b3,
0x011290b4, 0xf491a6f0, 0x4e98321b, 0x70efcd01, 0x0600f4b3, 0x2918700f, 0xff94f006, 0xbb909ebc,
0x49b5029f, 0xae993e01, 0xb20bb200, 0x7e2cb23a, 0xb200a43f, 0x00a4b3a0, 0x0265bb34, 0x90014afe,
0xaa7e34aa, 0x60b300a6, 0x90b42000, 0x8085bc0b, 0xb09095bc, 0xe53e0b91, 0x020000ac, 0x00aec93e,
@ -1440,88 +1440,88 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa6287e0a, 0xcc0ab200, 0xc17e702b, 0xa8b200a6, 0xad00adb3, 0x7021cd00, 0x420147fe, 0x77900080,
0xb0383e44, 0x0c00b400, 0x79a094bd, 0x09a6f009, 0x00091bf4, 0xb03f3e02, 0xa6f00900, 0x090df409,
0x3f3e0300, 0xc0b400b0, 0x0704b60b, 0x0db2e4bd, 0xb4bd5ab2, 0xb00021b0, 0xe47e0171, 0x5abf00a5,
0x2cb20bb2, 0x767e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500,
0x2cb20bb2, 0x797e3db2, 0x7ebf00b7, 0x3bb2a0b2, 0x2cb25ab2, 0xe67e0db2, 0x04b300a5, 0x3ab24500,
0x117eb4bd, 0xa0b200a4, 0x3700a4b3, 0x01bb7000, 0xf404a602, 0x40b2050d, 0xb2101b90, 0xb03bbc6a,
0x967e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff,
0x997e0cb2, 0x4afe00b7, 0x0240bb01, 0xbc30aa90, 0xaa7e6060, 0x14bd00a6, 0x6d004db3, 0xb280b2ff,
0x7e3bb25a, 0x3e00a60c, 0x0000b04d, 0x0149fe02, 0xbf4c9990, 0x05dcd99f, 0x99bf0000, 0xf9a60ab2,
0x7e070bf4, 0xf4003a31, 0x85fb0830, 0xf830f424, 0x0005dcd9, 0xbf32f900, 0x014ffe99, 0xb214ff90,
0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9c7e0ab2, 0x09bf00b7, 0x4c0090b3,
0xbdf9a0a1, 0xb2b2b294, 0x0140fec3, 0x9003204b, 0x09a01000, 0x9f7e0ab2, 0x09bf00b7, 0x4c0090b3,
0x4800a4b3, 0x09bf91a0, 0xbf0192b5, 0x1000490f, 0xbf04f9b5, 0xb520090f, 0x09bf05f9, 0xbf0693b5,
0x3501090f, 0x09bf1cf9, 0xbf2c9a35, 0xb5f0090f, 0x0fbf0af9, 0xb540f990, 0x0fbf0ef9, 0xb5c0f990,
0x0abf0ff9, 0x00b0ea3e, 0x49fea4bd, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699, 0x317e070b,
0x35fb003a, 0xd030f408, 0x0005dcdf, 0xbf82f900, 0x0149feff, 0xb2509990, 0x059fa0a3, 0x00a9b302,
0xb63004f8, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200,
0xb200b776, 0x00adb3a5, 0x093f04ae, 0x9f4a9d33, 0x01091804, 0x97469d33, 0x02091804, 0x8f469d33,
0x03091804, 0x87539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4,
0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045b0bf5, 0xd6b00505, 0x5a0cf503, 0x013db504,
0xb63004fb, 0x0b9cf000, 0xbd2ca935, 0x0ca9b594, 0x00a5ea7e, 0x3abfa0b2, 0x804cb4bd, 0x7e0db200,
0xb200b779, 0x00adb3a5, 0x093f04b1, 0xa24a9d33, 0x01091804, 0x9a469d33, 0x02091804, 0x92469d33,
0x03091804, 0x8a539d33, 0x040e1804, 0x18050918, 0x0d18060f, 0xffe4f007, 0xf0ff94f0, 0x94b6fff4,
0x10f4b608, 0xb6059efd, 0xf9fd18d4, 0x05dffd05, 0x045e0bf5, 0xd6b00505, 0x5d0cf503, 0x013db504,
0x0e01d4b3, 0xb5500049, 0xd83e0239, 0x0d1800b1, 0x09091808, 0x180a0f18, 0xd4f00b0e, 0xff94f0ff,
0xb6fff4f0, 0xf4b60894, 0x059dfd10, 0xfd18e4b6, 0xeffd05f9, 0x023eb505, 0x0bb23ab2, 0x00a60c7e,
0x09023a98, 0xa60305ff, 0x080bf5a9, 0x07a5b604, 0xb5303b90, 0xcf7e033a, 0xa5b200b6, 0xf500adb3,
0x033b9803, 0x3a90c009, 0x3fbb9034, 0xb604b9fd, 0x9c7e03b5, 0xa5b200b7, 0xd900adb3, 0x0147fe03,
0x900148fe, 0x44bd4077, 0x90017990, 0x91b03c88, 0xb3453e09, 0xa0e4bd00, 0x0044b38e, 0x0c3a980f,
0xfe0cb4bd, 0x00b2683e, 0x4bb23ab2, 0x797e7cb2, 0xa5b200a5, 0x9d00adb3, 0xf0793f03, 0x0bf40194,
0x0c3a9812, 0xff0c4bb2, 0x00b6737e, 0x00b3423e, 0x307e7ab2, 0xa0b300a3, 0x3a980f00, 0x0c4bb20c,
0xb2683efd, 0xf0793f00, 0x1bf40294, 0x0c3a980e, 0xfd0c4bb2, 0x00b3373e, 0xb209b0b4, 0xb2010c3a,
0xa6407e8d, 0x00a0b300, 0xb2793f5d, 0xc724bd3f, 0x99900299, 0x0a91b001, 0xb354f598, 0xb4390054,
0x22bc09b0, 0xbc030c00, 0x04b60002, 0x4001b803, 0x31bc0001, 0x7e1ab210, 0xbc00b796, 0x09b80030,
0x20000143, 0x5302b595, 0xb50af0b4, 0x81a0540f, 0x00b3023e, 0x90012290, 0x24b318ff, 0x2f3ebe14,
0x8ebf00b6, 0x7f58793f, 0x077d1802, 0x9803ee98, 0x99c70d3a, 0x00f3f002, 0xcb70ffcc, 0x4bb21f96,
0x0cd8e6cb, 0xf0d6cb01, 0x01e0f6eb, 0x00a2e67e, 0xb20c3a98, 0x7e6cb24b, 0xb200b673, 0x00adb3a5,
0x449002b4, 0x033b9801, 0x08f54ba6, 0x94bdfeeb, 0xa0b0bbbc, 0x7e8ab289, 0xb200b7b2, 0x00adb3a5,
0x37b20294, 0x7f9884bd, 0x9088bc54, 0xb69098bc, 0x99b80394, 0xbc000140, 0x91b09039, 0x00f9b30b,
0x3c980253, 0x0fa0b403, 0x24bdb43d, 0xbdc0ccbc, 0xb78d7e44, 0x0f60b400, 0x00b4603e, 0xb20d3a98,
0x0c41b02b, 0x00a2f67e, 0xb500a933, 0x0c3a9800, 0xb2014cfe, 0x38cc902b, 0x00b65c7e, 0x0c00adb3,
0x0be0b402, 0x980e90b4, 0x99c703ef, 0xf59fa6d8, 0x98008e1b, 0x2bb20d3a, 0xee7e010c, 0x4cfe00a2,
0xb23ab201, 0x30cc902b, 0x00a5947e, 0x1306a4b3, 0xb20c3a98, 0x7efd0c2b, 0x3e00b673, 0xb300b45d,
0x01cb00ad, 0xf01c9074, 0x99bc0093, 0x0069bc90, 0x19e4017f, 0x1bf4ffff, 0x3e026009, 0x9800b45d,
0x4cfe0c3a, 0xff1be401, 0x34cc90ff, 0x00b65c7e, 0x9800adb3, 0x3af03401, 0x26369034, 0x100df4f9,
0x1be40260, 0x3a98ffff, 0xb4523e0c, 0x0c3a9800, 0xfd0c2bb2, 0x00b6737e, 0x7000adb3, 0x01229001,
0xa6033a98, 0x3708f52a, 0xb264b2ff, 0x3db43d6e, 0xbdf4bdd4, 0xb4943ec4, 0x73e97f00, 0x0d0a0094,
0xb48e3e01, 0x00d03300, 0x90010b06, 0xff9001cc, 0x02ee9001, 0x08f4faa6, 0x00c4b3e3, 0x547cb50b,
0x00b5d03e, 0xa600b933, 0x01399800, 0xf40296b0, 0x0309300c, 0x79b56db2, 0xbde4bd54, 0xb4d33ef4,
0x73d97f00, 0x7c0a0090, 0xee90e969, 0x01ff9001, 0x9802dd90, 0xf9a60339, 0x3ee908f4, 0xbd00b54a,
0xb5f10194, 0x24bd5479, 0x243e1bb2, 0x407f00b5, 0xffff09e4, 0x0f260bf4, 0xf4bfa6f1, 0x0be40b1b,
0x1c3effff, 0x3a9800b5, 0xff0ce40c, 0xb6737eff, 0x00adb300, 0x0be400b9, 0x19b2ffff, 0x90012290,
0x91b20244, 0xa6033998, 0xc508f429, 0xb9a6f109, 0x00a00bf5, 0x980c3a98, 0x737e0a3c, 0xadb300b6,
0xb5008c00, 0xd03e0a31, 0x6f7f00b5, 0xc19294bd, 0x5179b501, 0xbd00f3f0, 0x527fb504, 0x00b5883e,
0x4c584b7f, 0x0c3a9801, 0xf0010090, 0xc3f000b3, 0x02449000, 0x00b6737e, 0x5200a4b3, 0x980be0b4,
0x999001e9, 0x01e9b570, 0x08f401a6, 0x08607cd6, 0x0c0c3a98, 0xff0be4f0, 0xb6737eff, 0x00a4b300,
0x014cfe2d, 0xffff0be4, 0xcc903ab2, 0xa5797e40, 0x00a4b300, 0x46903419, 0xf0517f98, 0xf9bcff94,
0x517fb5f0, 0x00b5d03e, 0xa5b2030a, 0x00b5db3e, 0x90018890, 0x8db31877, 0xfefd9014, 0x99900149,
0x7e9abf3c, 0x3e00b746, 0x0500b5f1, 0xb5f33e03, 0xb204bd00, 0x7e3ab20b, 0xb300a60c, 0x981a0050,
0x04bd0c3a, 0x00b6c57e, 0xb50d3a98, 0x467e0c30, 0x30b500b7, 0x0149fe0d, 0xbf509990, 0x05dcd99f,
0x99bf0000, 0xf9a65ab2, 0x3e110bf4, 0x0500b635, 0xb5f13e01, 0x3a317e00, 0x3085fb00, 0xa0b202f9,
0x00a5e87e, 0x7e0c0a98, 0x9800b6c5, 0x467e0d0a, 0x0ab200b7, 0x00b7467e, 0x01fba4bd, 0xafb2a9bf,
0xb9a6020a, 0x900d18f4, 0xf9bc01b9, 0xa0a4bd98, 0xbf00f8c9, 0x0aafb2a9, 0xf4b9a602, 0xb9900b18,
0xbca4bd01, 0x00f899fc, 0xafb2b9bf, 0xc9a6cab2, 0x0a0708f4, 0xb500f8f1, 0xfca002fb, 0xf801fcb5,
0x98a9bf00, 0xb9bc02af, 0xbfa9a090, 0xf49ba6fb, 0x9bbb0808, 0x98a9a002, 0xaabf01a9, 0x1bf4a9a6,
0xf8f10a05, 0x00a0b300, 0xb7467e08, 0xf400f800, 0xdcdff830, 0xf9000005, 0xfeffbf32, 0x99900149,
0xa0a0b214, 0xb3b3b29f, 0x024200a0, 0xf4a2a6fd, 0xab903a0c, 0x0141fe01, 0x9002b4b6, 0x1ab21011,
0x00b7b27e, 0x2700a4b3, 0x1db219bf, 0xe4bd2cb2, 0xdfbf90a0, 0xb201e990, 0x99fcbc9e, 0x08f490a6,
0xa0ddbff4, 0xb72b3e3d, 0xfe020a00, 0x99900149, 0xd99fbf14, 0x000005dc, 0xf9a699bf, 0x7e070bf4,
0xfb003a31, 0x00f80835, 0x002944da, 0x41c77e00, 0x00a63000, 0xf00bacf0, 0xaab901a6, 0xda00f801,
0x00002944, 0x0041427e, 0xf000a630, 0xa6f00bac, 0x01aab901, 0x44da00f8, 0x7e000029, 0x300042d7,
0xacf000a6, 0x01a6f00b, 0xf801aab9, 0xffb4f000, 0x000b947e, 0x7e7e00f8, 0x00f8000b, 0xa0b202f9,
0x4c7ea43d, 0xa6b00038, 0x0b9cf000, 0x9ab20aa0, 0x02f901fb, 0xa43da0b2, 0x00382a7e, 0xf000a6b0,
0x0aa00b9c, 0x01fb9ab2, 0xdfe430f4, 0x000005dc, 0xffbf82f9, 0xfe0149fe, 0x99900145, 0x0147fe3c,
0x55909fa0, 0x34779024, 0x00141cd9, 0xfe9abf00, 0x080c014b, 0x0d2cbb90, 0x00c17eff, 0x00a43300,
0x0c30b4eb, 0x9433393f, 0x3118e20c, 0x00103304, 0x0119330f, 0x043d00b0, 0x00b96e3e, 0xd9023f98,
0x0000142c, 0x58043198, 0x5fa00a34, 0x39989f3f, 0x18369003, 0x090159b5, 0x3379a0ff, 0x7e1800f4,
0x320032f7, 0x00ad33a0, 0x01090129, 0x00142cdf, 0x72f92000, 0x0043f012, 0xae3e14bd, 0x41bc00b8,
0x0006b102, 0x060df401, 0x7e010040, 0xd9000b94, 0x00001424, 0x2ce49abf, 0x6bb2ffff, 0x00de0db2,
0x7e000013, 0xa000af12, 0x00adb37a, 0x5bbf00d4, 0x90015c98, 0x0eb2041d, 0xbc20207c, 0x00da1010,
0x7e000013, 0x32002136, 0x00ad33a0, 0xb4bd00c5, 0xda01004c, 0x00001300, 0x08f414a6, 0xb95d3ea4,
0x023f9800, 0x00142cd9, 0x04349800, 0xa00a3258, 0x989f3f5f, 0x38900339, 0x0159b518, 0x79a0ff09,
0x1600f433, 0x0032f77e, 0xad33a032, 0xdf008400, 0x0000142c, 0x26e4f120, 0x24bdffff, 0x00b94e3e,
0xb11262bc, 0xf4010016, 0x0041060d, 0x0b947e01, 0x985bbf00, 0x2d90015c, 0xda1eb204, 0x00001300,
0x0020d07e, 0xffff4ce4, 0x322021bc, 0xb28bb2a0, 0x1300de1d, 0x417c0000, 0x00a43340, 0x1424d935,
0x9abf0000, 0x00ac3c7e, 0xa4b37aa0, 0xb4bd1300, 0xda01004c, 0x00001300, 0x08f426a6, 0x985bbfa6,
0x7ab2015c, 0x040ed4bd, 0x0021367e, 0xb034a032, 0x7e3ab22d, 0x33000f81, 0xfe71000d, 0x0f3a0130,
0x38f13002, 0x09033318, 0x014afe04, 0x30399130, 0xb4bd3b31, 0x7e38aa90, 0x3e000f71, 0xf900b7e8,
0x2930d902, 0xa0b20000, 0x640b9abf, 0x0000de7e, 0xa4331009, 0x00896100, 0x9fcf02a6, 0x00f5f100,
0x009ff610, 0x02a6008a, 0xbd10004b, 0x27104dc4, 0x8b7ee4bd, 0xa4330019, 0x30d91500, 0xbf000029,
0x009b7e9a, 0x3e040900, 0xb200ba13, 0x03e84b0a, 0x0016fc7e, 0x02a40089, 0x0200aab8, 0x0aa5b600,
0xf601aa92, 0x114f009a, 0x0099b801, 0x9ff60002, 0x32943d00, 0x0001fb9a, 0x00000000, 0x00000000,
0x09023a98, 0xf4a9a6ff, 0x04bd091b, 0x00b5ee3e, 0x9007a5b6, 0x3ab5303b, 0xb6d27e03, 0xb3a5b200,
0x03f500ad, 0x09033b98, 0x343a90c0, 0xfd3fbb90, 0xb5b604b9, 0xb79f7e03, 0xb3a5b200, 0x03d900ad,
0xfe0147fe, 0x77900148, 0x9044bd40, 0x88900179, 0x0991b03c, 0x00b3483e, 0x8ea0e4bd, 0x0f0044b3,
0xbd0c3a98, 0x3efe0cb4, 0xb200b26b, 0xb24bb23a, 0xa5797e7c, 0xb3a5b200, 0x039d00ad, 0x94f0793f,
0x120bf401, 0xb20c3a98, 0x7eff0c4b, 0x3e00b676, 0xb200b345, 0xa3307e7a, 0x00a0b300, 0x0c3a980f,
0xfd0c4bb2, 0x00b26b3e, 0x94f0793f, 0x0e1bf402, 0xb20c3a98, 0x3efd0c4b, 0xb400b33a, 0x3ab209b0,
0x8db2010c, 0x00a6407e, 0x5d00a0b3, 0x3fb2793f, 0x99c724bd, 0x01999002, 0x980a91b0, 0x54b354f5,
0xb0b43900, 0x0022bc09, 0x02bc030c, 0x0304b600, 0x014001b8, 0x1031bc00, 0x997e1ab2, 0x30bc00b7,
0x4309b800, 0x95200001, 0xb45302b5, 0x0fb50af0, 0x3e81a054, 0x9000b305, 0xff900122, 0x1424b318,
0xb6323ebe, 0x3f8ebf00, 0x027f5879, 0x98077d18, 0x3a9803ee, 0x0299c70d, 0xcc00f3f0, 0x96cb70ff,
0xcb4bb21f, 0x010cd8e6, 0xebf0d6cb, 0x7e01e0f6, 0x9800a2e6, 0x4bb20c3a, 0x767e6cb2, 0xa5b200b6,
0xb400adb3, 0x01449002, 0xa6033b98, 0xeb08f54b, 0xbc94bdfe, 0x89a0b0bb, 0xb57e8ab2, 0xa5b200b7,
0x9400adb3, 0xbd37b202, 0x547f9884, 0xbc9088bc, 0x94b69098, 0x4099b803, 0x39bc0001, 0x0b91b090,
0x5300f9b3, 0x033c9802, 0x3d0fa0b4, 0xbc24bdb4, 0x44bdc0cc, 0x00b7907e, 0x3e0f60b4, 0x9800b463,
0x2bb20d3a, 0x7e0c41b0, 0x3300a2f6, 0x00b500a9, 0xfe0c3a98, 0x2bb2014c, 0x7e38cc90, 0xb300b65f,
0x020c00ad, 0xb40be0b4, 0xef980e90, 0xd899c703, 0x1bf59fa6, 0x3a98008e, 0x0c2bb20d, 0xa2ee7e01,
0x014cfe00, 0x2bb23ab2, 0x7e30cc90, 0xb300a594, 0x981306a4, 0x2bb20c3a, 0x767efd0c, 0x603e00b6,
0xadb300b4, 0x7401cb00, 0x93f01c90, 0x9099bc00, 0x7f0069bc, 0xff19e401, 0x091bf4ff, 0x603e0260,
0x3a9800b4, 0x014cfe0c, 0xffff1be4, 0x7e34cc90, 0xb300b65f, 0x019800ad, 0x343af034, 0xf9263690,
0x60100df4, 0xff1be402, 0x0c3a98ff, 0x00b4553e, 0xb20c3a98, 0x7efd0c2b, 0xb300b676, 0x017000ad,
0x98012290, 0x2aa6033a, 0xff3708f5, 0x6eb264b2, 0xd43db43d, 0xc4bdf4bd, 0x00b4973e, 0x9473e97f,
0x010d0a00, 0x00b4913e, 0x0600d033, 0xcc90010b, 0x01ff9001, 0xa602ee90, 0xe308f4fa, 0x0b00c4b3,
0x3e547cb5, 0x3300b5d3, 0x00a600b9, 0xb0013998, 0x0cf40296, 0xb2030930, 0x5479b56d, 0xf4bde4bd,
0x00b4d63e, 0x9073d97f, 0x697c0a00, 0x01ee90e9, 0x9001ff90, 0x399802dd, 0xf4f9a603, 0x4d3ee908,
0x94bd00b5, 0x79b5f101, 0xb224bd54, 0xb5273e1b, 0xe4407f00, 0xf4ffff09, 0xf10f260b, 0x1bf4bfa6,
0xff0be40b, 0xb51f3eff, 0x0c3a9800, 0xffff0ce4, 0x00b6767e, 0xb900adb3, 0xff0be400, 0x9019b2ff,
0x44900122, 0x9891b202, 0x29a60339, 0x09c508f4, 0xf5b9a6f1, 0x9800a00b, 0x3c980c3a, 0xb6767e0a,
0x00adb300, 0x31b5008c, 0xb5d33e0a, 0xbd6f7f00, 0x01c19294, 0xf05179b5, 0x04bd00f3, 0x3e527fb5,
0x7f00b58b, 0x014c584b, 0x900c3a98, 0xb3f00100, 0x00c3f000, 0x7e024490, 0xb300b676, 0xb45200a4,
0xe9980be0, 0x70999001, 0xa601e9b5, 0xd608f401, 0x9808607c, 0xf00c0c3a, 0xffff0be4, 0x00b6767e,
0x2d00a4b3, 0xe4014cfe, 0xb2ffff0b, 0x40cc903a, 0x00a5797e, 0x1900a4b3, 0x98469034, 0x94f0517f,
0xf0f9bcff, 0x3e517fb5, 0x0a00b5d3, 0x3ea5b203, 0x9000b5de, 0x77900188, 0x148db318, 0x49fefd90,
0x3c999001, 0x497e9abf, 0xf43e00b7, 0x030500b5, 0x00b5f63e, 0x0bb204bd, 0x0c7e3ab2, 0x50b300a6,
0x3a981a00, 0x7e04bd0c, 0x9800b6c8, 0x30b50d3a, 0xb7497e0c, 0x0d30b500, 0x900149fe, 0x9fbf5099,
0x0005dcd9, 0xb299bf00, 0xf4f9a65a, 0x383e110b, 0x010500b6, 0x00b5f43e, 0x003a317e, 0xf93085fb,
0x7ea0b202, 0x9800a5e8, 0xc87e0c0a, 0x0a9800b6, 0xb7497e0d, 0x7e0ab200, 0xbd00b749, 0xbf01fba4,
0x0aafb2a9, 0xf4b9a602, 0xb9900d18, 0x98f9bc01, 0xc9a0a4bd, 0xa9bf00f8, 0x020aafb2, 0x18f4b9a6,
0x01b9900b, 0xfcbca4bd, 0xbf00f899, 0xb2afb2b9, 0xf4c9a6ca, 0xf10a0708, 0xfbb500f8, 0xb5fca002,
0x00f801fc, 0xaf98a9bf, 0x90b9bc02, 0xfbbfa9a0, 0x08f49ba6, 0x029bbb08, 0xa998a9a0, 0xa6aabf01,
0x051bf4a9, 0x00f8f10a, 0x0800a0b3, 0x00b7497e, 0x30f400f8, 0x05dcdff8, 0x32f90000, 0x49feffbf,
0x14999001, 0x9fa0a0b2, 0xa0b3b3b2, 0xfd024200, 0x0cf4a2a6, 0x01ab903a, 0xb60141fe, 0x119002b4,
0x7e1ab210, 0xb300b7b5, 0xbf2700a4, 0xb21db219, 0xa0e4bd2c, 0x90dfbf90, 0x9eb201e9, 0xa699fcbc,
0xf408f490, 0x3da0ddbf, 0x00b72e3e, 0x49fe020a, 0x14999001, 0xdcd99fbf, 0xbf000005, 0xf4f9a699,
0x317e070b, 0x35fb003a, 0xda00f808, 0x00002944, 0x0041c77e, 0xf000a630, 0xa6f00bac, 0x01aab901,
0x44da00f8, 0x7e000029, 0x30004142, 0xacf000a6, 0x01a6f00b, 0xf801aab9, 0x2944da00, 0xd77e0000,
0xa6300042, 0x0bacf000, 0xb901a6f0, 0x00f801aa, 0x7effb4f0, 0xf8000b94, 0x0b7e7e00, 0xf900f800,
0x3da0b202, 0x384c7ea4, 0x00a6b000, 0xa00b9cf0, 0xfb9ab20a, 0xb202f901, 0x7ea43da0, 0xb000382a,
0x9cf000a6, 0xb20aa00b, 0xf401fb9a, 0xdcdfe430, 0xf9000005, 0xfeffbf82, 0x45fe0149, 0x3c999001,
0xa00147fe, 0x2455909f, 0xd9347790, 0x0000141c, 0x4bfe9abf, 0x90080c01, 0xff0d2cbb, 0x0000c17e,
0xeb00a433, 0x3f0c30b4, 0x0c943339, 0x043118e2, 0x0f001033, 0xb0011933, 0x3e043d00, 0x9800b971,
0x2cd9023f, 0x98000014, 0x34580431, 0x3f5fa00a, 0x0339989f, 0xb5183690, 0xff090159, 0xf43379a0,
0xf77e1800, 0xa0320032, 0x2900ad33, 0xdf010901, 0x0000142c, 0x1272f920, 0xbd0043f0, 0xb8b13e14,
0x0241bc00, 0x010006b1, 0x40060df4, 0x947e0100, 0x24d9000b, 0xbf000014, 0xff2ce49a, 0xb26bb2ff,
0x1300de0d, 0x127e0000, 0x7aa000af, 0xd400adb3, 0x985bbf00, 0x1d90015c, 0x7c0eb204, 0x10bc2020,
0x1300da10, 0x367e0000, 0xa0320021, 0xc500ad33, 0x4cb4bd00, 0x00da0100, 0xa6000013, 0xa408f414,
0x00b9603e, 0xd9023f98, 0x0000142c, 0x58043498, 0x5fa00a32, 0x39989f3f, 0x18389003, 0x090159b5,
0x3379a0ff, 0x7e1600f4, 0x320032f7, 0x00ad33a0, 0x2cdf0084, 0x20000014, 0xff26e4f1, 0x3e24bdff,
0xbc00b951, 0x16b11262, 0x0df40100, 0x01004106, 0x000b947e, 0x5c985bbf, 0x042d9001, 0x00da1eb2,
0x7e000013, 0xe40020d0, 0xbcffff4c, 0xa0322021, 0x1db28bb2, 0x001300de, 0x40417c00, 0x3500a433,
0x001424d9, 0x7e9abf00, 0xa000ac3c, 0x00a4b37a, 0x4cb4bd13, 0x00da0100, 0xa6000013, 0xa608f426,
0x5c985bbf, 0xbd7ab201, 0x7e040ed4, 0x32002136, 0x2db034a0, 0x817e3ab2, 0x0d33000f, 0x30fe7100,
0x020f3a01, 0x1838f130, 0x04090333, 0x30014afe, 0x31303991, 0x90b4bd3b, 0x717e38aa, 0xeb3e000f,
0x02f900b7, 0x002930d9, 0xbfa0b200, 0x7e640b9a, 0x090000de, 0x00a43310, 0xa6008961, 0x009fcf02,
0x1000f5f1, 0x8a009ff6, 0x4b02a600, 0xc4bd1000, 0xbd27104d, 0x198b7ee4, 0x00a43300, 0x2930d915,
0x9abf0000, 0x00009b7e, 0x163e0409, 0x0ab200ba, 0x7e03e84b, 0x890016fc, 0xb802a400, 0x000200aa,
0x920aa5b6, 0x9af601aa, 0x01114f00, 0x020099b8, 0x009ff600, 0x9a32943d, 0x000001fb, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x7f8cbe99, 0x0e2a64d9, 0x6c95f843, 0x38bac675,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xcaafe5ce, 0x6ff4be12, 0x691b2548, 0xa6e91959,
0xb32dc4cc, 0x58018cca, 0x7c52cad0, 0x4a5277fe, 0x59305452, 0xfe64d88a, 0xe474c23b, 0xfee62bd9,
0x705ea2e7, 0x0577e70f, 0xcf75f41f, 0xfe6e071a, 0xd0954f7e, 0x7caea789, 0x40b32eb9, 0x80368ac3,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

22
src/common/nvswitch/kernel/inforom/ifrbbx_nvswitch.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -124,9 +124,27 @@ nvswitch_inforom_bbx_get_sxid
status = device->hal.nvswitch_bbx_get_sxid(device, params);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "nvswitch_inforom_bbx_load failed, status=%d\n", status);
NVSWITCH_PRINT(device, ERROR, "nvswitch_bbx_get_sxid failed, status=%d\n", status);
}
return status;
}
NvlStatus
nvswitch_inforom_bbx_get_data
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
NvlStatus status;
status = device->hal.nvswitch_bbx_get_data(device, dataType, params);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: (type=%d) failed, status=%d\n", __FUNCTION__, dataType, status);
}
return status;
}

408
src/common/nvswitch/kernel/inforom/ifrnvlink_nvswitch.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -32,7 +32,188 @@ nvswitch_inforom_nvlink_flush
struct nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
NvlStatus status = NVL_SUCCESS;
struct inforom *pInforom = device->pInforom;
PINFOROM_NVLINK_STATE pNvlinkState;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState != NULL && pNvlinkState->bDirty)
{
status = nvswitch_inforom_write_object(device, "NVL",
pNvlinkState->pFmt, pNvlinkState->pNvl,
pNvlinkState->pPackedObject);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"Failed to flush NVL object to InfoROM, rc: %d\n", status);
}
else
{
pNvlinkState->bDirty = NV_FALSE;
}
}
return status;
}
static void
_inforom_nvlink_get_correctable_error_counts
(
nvswitch_device *device,
NvU32 linkId,
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts
)
{
NvlStatus status;
NvU32 lane, idx;
NVSWITCH_NVLINK_GET_COUNTERS_PARAMS p = { 0 };
ct_assert(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE <=
INFOROM_NVL_OBJECT_MAX_SUBLINK_WIDTH);
nvswitch_os_memset(pErrorCounts, 0, sizeof(*pErrorCounts));
p.linkId = linkId;
p.counterMask = NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT
| NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY
| NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7
| NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7;
status = device->hal.nvswitch_ctrl_get_counters(device, &p);
if (status != NVL_SUCCESS)
{
return;
}
pErrorCounts->flitCrc =
p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT)];
pErrorCounts->txLinkReplay =
p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_REPLAY)];
pErrorCounts->rxLinkReplay =
p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_REPLAY)];
pErrorCounts->linkRecovery =
p.nvlinkCounters[BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_TX_ERR_RECOVERY)];
for (lane = 0; lane < NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE__SIZE; lane++)
{
idx = BIT_IDX_32(NVSWITCH_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(lane));
pErrorCounts->laneCrc[lane] = p.nvlinkCounters[idx];
}
}
static void
_inforom_nvlink_update_correctable_error_rates
(
nvswitch_device *device,
struct inforom *pInforom
)
{
PINFOROM_NVLINK_STATE pNvlinkState = pInforom->pNvlinkState;
NvU64 enabledLinkMask;
NvU32 linkId, publicId, localLinkIdx;
NvBool bDirty = NV_FALSE;
NvBool bDirtyTemp;
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS errorCounts = { 0 };
if (pNvlinkState == NULL)
{
return;
}
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
FOR_EACH_INDEX_IN_MASK(64, linkId, enabledLinkMask)
{
if (device->hal.nvswitch_get_link_public_id(device, linkId, &publicId) != NVL_SUCCESS)
{
continue;
}
if (device->hal.nvswitch_get_link_local_idx(device, linkId, &localLinkIdx) != NVL_SUCCESS)
{
continue;
}
_inforom_nvlink_get_correctable_error_counts(device, linkId, &errorCounts);
if (device->hal.nvswitch_inforom_nvl_update_link_correctable_error_info(device,
pNvlinkState->pNvl, &pNvlinkState->correctableErrorRateState, linkId,
publicId, localLinkIdx, &errorCounts, &bDirtyTemp) != NVL_SUCCESS)
{
continue;
}
bDirty |= bDirtyTemp;
}
FOR_EACH_INDEX_IN_MASK_END;
pNvlinkState->bDirty |= bDirty;
}
static void _nvswitch_nvlink_1hz_callback
(
nvswitch_device *device
)
{
struct inforom *pInforom = device->pInforom;
if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL) ||
pInforom->pNvlinkState->bCallbackPending)
{
return;
}
pInforom->pNvlinkState->bCallbackPending = NV_TRUE;
_inforom_nvlink_update_correctable_error_rates(device, pInforom);
pInforom->pNvlinkState->bCallbackPending = NV_FALSE;
}
static void
_inforom_nvlink_start_correctable_error_recording
(
nvswitch_device *device,
struct inforom *pInforom
)
{
PINFOROM_NVLINK_STATE pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return;
}
if (pNvlinkState->bDisableCorrectableErrorLogging)
{
NVSWITCH_PRINT(device, INFO,
"%s: Correctable error recording disabled by regkey or unsupported\n",
__FUNCTION__);
return;
}
pNvlinkState->bCallbackPending = NV_FALSE;
nvswitch_task_create(device, &_nvswitch_nvlink_1hz_callback,
NVSWITCH_INTERVAL_1SEC_IN_NS, 0);
}
NvlStatus
@ -41,7 +222,82 @@ nvswitch_inforom_nvlink_load
nvswitch_device *device
)
{
return -NVL_ERR_NOT_SUPPORTED;
NvlStatus status;
NvU8 version = 0;
NvU8 subversion = 0;
INFOROM_NVLINK_STATE *pNvlinkState = NULL;
struct inforom *pInforom = device->pInforom;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
status = nvswitch_inforom_get_object_version_info(device, "NVL", &version,
&subversion);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, WARN, "no NVL object found, rc:%d\n", status);
return NVL_SUCCESS;
}
if (!INFOROM_OBJECT_SUBVERSION_SUPPORTS_NVSWITCH(subversion))
{
NVSWITCH_PRINT(device, WARN, "NVL v%u.%u not supported\n",
version, subversion);
return -NVL_ERR_NOT_SUPPORTED;
}
NVSWITCH_PRINT(device, INFO, "NVL v%u.%u found\n", version, subversion);
pNvlinkState = nvswitch_os_malloc(sizeof(INFOROM_NVLINK_STATE));
if (pNvlinkState == NULL)
{
return -NVL_NO_MEM;
}
nvswitch_os_memset(pNvlinkState, 0, sizeof(INFOROM_NVLINK_STATE));
pNvlinkState->bDirty = NV_FALSE;
pNvlinkState->bDisableFatalErrorLogging = NV_FALSE;
pNvlinkState->bDisableCorrectableErrorLogging = NV_TRUE;
status = device->hal.nvswitch_inforom_nvl_setup_nvlink_state(device, pNvlinkState, version);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to set up NVL object, rc:%d\n", status);
goto nvswitch_inforom_nvlink_version_fail;
}
status = nvswitch_inforom_read_object(device, "NVL", pNvlinkState->pFmt,
pNvlinkState->pPackedObject,
pNvlinkState->pNvl);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to read NVL object, rc:%d\n", status);
goto nvswitch_inforom_read_fail;
}
status = nvswitch_inforom_add_object(pInforom, &pNvlinkState->pNvl->header);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to cache NVL object header, rc:%d\n",
status);
goto nvswitch_inforom_read_fail;
}
pInforom->pNvlinkState = pNvlinkState;
_inforom_nvlink_start_correctable_error_recording(device, pInforom);
return NVL_SUCCESS;
nvswitch_inforom_read_fail:
nvswitch_os_free(pNvlinkState->pPackedObject);
nvswitch_os_free(pNvlinkState->pNvl);
nvswitch_inforom_nvlink_version_fail:
nvswitch_os_free(pNvlinkState);
return status;
}
void
@ -50,30 +306,29 @@ nvswitch_inforom_nvlink_unload
nvswitch_device *device
)
{
return;
}
INFOROM_NVLINK_STATE *pNvlinkState;
struct inforom *pInforom = device->pInforom;
NvlStatus
nvswitch_inforom_nvlink_get_minion_data
(
nvswitch_device *device,
NvU8 linkId,
NvU32 *seedData
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (pInforom == NULL)
{
return;
}
NvlStatus
nvswitch_inforom_nvlink_set_minion_data
(
nvswitch_device *device,
NvU8 linkId,
NvU32 *seedData,
NvU32 size
)
{
return -NVL_ERR_NOT_SUPPORTED;
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return;
}
if (nvswitch_inforom_nvlink_flush(device) != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to flush NVL object on object unload\n");
}
nvswitch_os_free(pNvlinkState->pPackedObject);
nvswitch_os_free(pNvlinkState->pNvl);
nvswitch_os_free(pNvlinkState);
pInforom->pNvlinkState = NULL;
}
NvlStatus
@ -83,7 +338,35 @@ nvswitch_inforom_nvlink_log_error_event
void *error_event
)
{
return -NVL_ERR_NOT_SUPPORTED;
NvlStatus status;
NvBool bDirty = NV_FALSE;
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
status = device->hal.nvswitch_inforom_nvl_log_error_event(device,
pNvlinkState->pNvl,
(INFOROM_NVLINK_ERROR_EVENT *)error_event,
&bDirty);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Failed to log error to inforom, rc:%d\n",
status);
}
pNvlinkState->bDirty |= bDirty;
return status;
}
NvlStatus
@ -93,7 +376,14 @@ nvswitch_inforom_nvlink_get_max_correctable_error_rate
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
struct inforom *pInforom = device->pInforom;
if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL))
{
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_inforom_nvl_get_max_correctable_error_rate(device, params);
}
NvlStatus
@ -103,5 +393,67 @@ nvswitch_inforom_nvlink_get_errors
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
struct inforom *pInforom = device->pInforom;
if ((pInforom == NULL) || (pInforom->pNvlinkState == NULL))
{
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_inforom_nvl_get_errors(device, params);
}
NvlStatus nvswitch_inforom_nvlink_setL1Threshold
(
nvswitch_device *device,
NvU32 word1,
NvU32 word2
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_inforom_nvl_setL1Threshold(device,
pNvlinkState->pNvl,
word1,
word2);
}
NvlStatus nvswitch_inforom_nvlink_getL1Threshold
(
nvswitch_device *device,
NvU32 *word1,
NvU32 *word2
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
return device->hal.nvswitch_inforom_nvl_getL1Threshold(device,
pNvlinkState->pNvl,
word1,
word2);
}

619
src/common/nvswitch/kernel/inforom/inforom_nvl_v3_nvswitch.c Normal file
View File

@ -0,0 +1,619 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "common_nvswitch.h"
#include "inforom/inforom_nvswitch.h"
#include "inforom/inforom_nvl_v3_nvswitch.h"
#include "lr10/lr10.h"
NvlStatus inforom_nvl_v3_map_error
(
INFOROM_NVLINK_ERROR_TYPES error,
NvU8 *pHeader,
NvU16 *pMetadata,
NvU8 *pErrorSubtype,
INFOROM_NVL_ERROR_BLOCK_TYPE *pBlockType
)
{
static const struct
{ NvU8 header;
NvU16 metadata;
NvU8 errorSubtype;
INFOROM_NVL_ERROR_BLOCK_TYPE blockType;
} lut[] =
{
LUT_ELEMENT(DL, _RX, _FAULT_DL_PROTOCOL_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _RX, _FAULT_SUBLINK_CHANGE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _RX, _FLIT_CRC_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _RX, _LANE0_CRC_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _RX, _LANE1_CRC_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _RX, _LANE2_CRC_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _RX, _LANE3_CRC_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _RX, _LINK_REPLAY_EVENTS_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _TX, _FAULT_RAM_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _TX, _FAULT_INTERFACE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _TX, _FAULT_SUBLINK_CHANGE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _TX, _LINK_REPLAY_EVENTS_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(DL, _NA, _LTSSM_FAULT_UP_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _NA, _LTSSM_FAULT_DOWN_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _NA, _LINK_RECOVERY_EVENTS_CORR, _ACCUM, _CORRECTABLE),
LUT_ELEMENT(TLC, _RX, _DL_HDR_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DL_DATA_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DL_CTRL_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_AE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_BE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_ADDR_ALIGN_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _PKTLEN_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSVD_PACKET_STATUS_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DATLEN_GT_RMW_REQ_MAX_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DATLEN_LT_ATR_RSP_MIN_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_CR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_COLLAPSED_RESPONSE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _HDR_OVERFLOW_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DATA_OVERFLOW_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _STOMP_DETECTED_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSVD_CMD_ENC_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSVD_DAT_LEN_ENC_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _INVALID_PO_FOR_CACHE_ATTR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _RSP_STATUS_HW_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _RX, _RSP_STATUS_UR_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _RX, _RSP_STATUS_PRIV_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _RX, _POISON_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _RX, _AN1_HEARTBEAT_TIMEOUT_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _RX, _ILLEGAL_PRI_WRITE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _DL_CREDIT_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _TX, _NCISOC_HDR_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _TX, _NCISOC_PARITY_ERR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _TX, _ILLEGAL_PRI_WRITE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC0_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC1_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC2_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC3_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC4_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC5_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC6_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _AN1_TIMEOUT_VC7_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _POISON_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _RSP_STATUS_HW_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _RSP_STATUS_UR_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _RSP_STATUS_PRIV_ERR_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _SLEEP_WHILE_ACTIVE_LINK_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PHYCTL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_CLKCTL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _CLKCTL_ILLEGAL_REQUEST_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PLL_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _RSTSEQ_PHYARB_TIMEOUT_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(NVLIPT, _NA, _ILLEGAL_LINK_STATE_REQUEST_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _FAILED_MINION_REQUEST_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _RESERVED_REQUEST_VALUE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _LINK_STATE_WRITE_WHILE_BUSY_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(NVLIPT, _NA, _LINK_STATE_REQUEST_TIMEOUT_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
// TODO 3014908 log these in the NVL object until we have ECC object support
LUT_ELEMENT(TLC, _RX, _HDR_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DAT0_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _RX, _DAT1_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(TLC, _TX, _CREQ_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _RSP_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _COM_DAT_RAM_ECC_DBE_NONFATAL, _COUNT, _UNCORRECTABLE_NONFATAL),
LUT_ELEMENT(TLC, _TX, _RSP1_DAT_RAM_ECC_DBE_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _NA, _PHY_A_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _RX, _CRC_COUNTER_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _TX, _PL_ERROR_FATAL, _COUNT, _UNCORRECTABLE_FATAL),
LUT_ELEMENT(DL, _RX, _PL_ERROR_FATAL, _COUNT, _UNCORRECTABLE_FATAL)
};
ct_assert(INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL == 0);
ct_assert(INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL == 1);
ct_assert(INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR == 2);
ct_assert(INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR == 3);
ct_assert(INFOROM_NVLINK_DL_RX_LANE1_CRC_CORR == 4);
ct_assert(INFOROM_NVLINK_DL_RX_LANE2_CRC_CORR == 5);
ct_assert(INFOROM_NVLINK_DL_RX_LANE3_CRC_CORR == 6);
ct_assert(INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR == 7);
ct_assert(INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL == 8);
ct_assert(INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL == 9);
ct_assert(INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL == 10);
ct_assert(INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR == 11);
ct_assert(INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL == 12);
ct_assert(INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL == 13);
ct_assert(INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR == 14);
ct_assert(INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL == 15);
ct_assert(INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL == 16);
ct_assert(INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL == 17);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL == 18);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL == 19);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL == 20);
ct_assert(INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL == 21);
ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL == 22);
ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL == 23);
ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL == 24);
ct_assert(INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL == 25);
ct_assert(INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL == 26);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL == 27);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL == 28);
ct_assert(INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL == 29);
ct_assert(INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL == 30);
ct_assert(INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL == 31);
ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL == 32);
ct_assert(INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL == 33);
ct_assert(INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL == 34);
ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL == 35);
ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL == 36);
ct_assert(INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL == 37);
ct_assert(INFOROM_NVLINK_TLC_RX_POISON_NONFATAL == 38);
ct_assert(INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL == 39);
ct_assert(INFOROM_NVLINK_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL == 40);
ct_assert(INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL == 41);
ct_assert(INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL == 42);
ct_assert(INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL == 43);
ct_assert(INFOROM_NVLINK_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL == 44);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL == 45);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL == 46);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL == 47);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL == 48);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL == 49);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL == 50);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL == 51);
ct_assert(INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL == 52);
ct_assert(INFOROM_NVLINK_TLC_TX_POISON_NONFATAL == 53);
ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL == 54);
ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL == 55);
ct_assert(INFOROM_NVLINK_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL == 56);
ct_assert(INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL == 57);
ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL == 58);
ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL == 59);
ct_assert(INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL == 60);
ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL == 61);
ct_assert(INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL == 62);
ct_assert(INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL == 63);
ct_assert(INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL == 64);
ct_assert(INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL == 65);
ct_assert(INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL == 66);
ct_assert(INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL == 67);
ct_assert(INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL == 68);
ct_assert(INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL == 69);
ct_assert(INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL == 70);
ct_assert(INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL == 71);
ct_assert(INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL == 72);
ct_assert(INFOROM_NVLINK_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL == 73);
ct_assert(INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL == 74);
ct_assert(INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL == 75);
ct_assert(INFOROM_NVLINK_DL_PHY_A_FATAL == 76);
ct_assert(INFOROM_NVLINK_DL_RX_CRC_COUNTER_FATAL == 77);
ct_assert(INFOROM_NVLINK_DL_TX_PL_ERROR_FATAL == 78);
ct_assert(INFOROM_NVLINK_DL_RX_PL_ERROR_FATAL == 79);
ct_assert(NV_ARRAY_ELEMENTS(lut) == INFOROM_NVLINK_MAX_ERROR_TYPE);
if (error >= NV_ARRAY_ELEMENTS(lut))
{
return -NVL_BAD_ARGS;
}
*pHeader = lut[error].header;
*pMetadata = lut[error].metadata;
*pErrorSubtype = lut[error].errorSubtype;
*pBlockType = lut[error].blockType;
return NVL_SUCCESS;
}
NvlStatus
inforom_nvl_v3_encode_nvlipt_error_subtype
(
NvU8 localLinkIdx,
NvU8 *pSubtype
)
{
static const NvBool linkIdxValidLut[] =
{
NV_TRUE,
NV_TRUE,
NV_TRUE,
NV_FALSE,
NV_FALSE,
NV_FALSE,
NV_TRUE,
NV_TRUE,
NV_TRUE,
NV_TRUE,
NV_TRUE,
NV_TRUE
};
ct_assert(NVLIPT_NA_SLEEP_WHILE_ACTIVE_LINK_FATAL_COUNT == 0);
ct_assert(NVLIPT_NA_RSTSEQ_PHYCTL_TIMEOUT_FATAL_COUNT == 1);
ct_assert(NVLIPT_NA_RSTSEQ_CLKCTL_TIMEOUT_FATAL_COUNT == 2);
ct_assert(NVLIPT_NA_CLKCTL_ILLEGAL_REQUEST_FATAL_COUNT == 3);
ct_assert(NVLIPT_NA_RSTSEQ_PLL_TIMEOUT_FATAL_COUNT == 4);
ct_assert(NVLIPT_NA_RSTSEQ_PHYARB_TIMEOUT_FATAL_COUNT == 5);
ct_assert(NVLIPT_NA_ILLEGAL_LINK_STATE_REQUEST_NONFATAL_COUNT == 6);
ct_assert(NVLIPT_NA_FAILED_MINION_REQUEST_NONFATAL_COUNT == 7);
ct_assert(NVLIPT_NA_RESERVED_REQUEST_VALUE_NONFATAL_COUNT == 8);
ct_assert(NVLIPT_NA_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL_COUNT == 9);
ct_assert(NVLIPT_NA_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL_COUNT == 10);
ct_assert(NVLIPT_NA_LINK_STATE_REQUEST_TIMEOUT_NONFATAL_COUNT == 11);
if ((localLinkIdx >= NV_INFOROM_NVL_OBJECT_V3_NVLIPT_ERROR_LINK_ID_COMMON) ||
(*pSubtype >= NV_ARRAY_ELEMENTS(linkIdxValidLut)))
{
return -NVL_BAD_ARGS;
}
if (linkIdxValidLut[*pSubtype])
{
*pSubtype = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR,
_LINK_ID, localLinkIdx, *pSubtype);
}
else
{
*pSubtype = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID,
_COMMON, *pSubtype);
}
return NVL_SUCCESS;
}
NvBool
inforom_nvl_v3_should_replace_error_rate_entry
(
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate,
NvU32 flitCrcRate,
NvU32 *pLaneCrcRates
)
{
NvU32 i;
NvU64 currentLaneCrcRateSum = 0;
NvU64 maxLaneCrcRateSum = 0;
for (i = 0; i < NV_ARRAY_ELEMENTS(pErrorRate->laneCrcErrorsPerMinute); i++)
{
currentLaneCrcRateSum += pLaneCrcRates[i];
maxLaneCrcRateSum += pErrorRate->laneCrcErrorsPerMinute[i];
}
return (flitCrcRate > pErrorRate->flitCrcErrorsPerMinute) ||
(currentLaneCrcRateSum > maxLaneCrcRateSum);
}
void
inforom_nvl_v3_seconds_to_day_and_month
(
NvU32 sec,
NvU32 *pDay,
NvU32 *pMonth
)
{
*pDay = sec / (60 * 60 * 24);
*pMonth = *pDay / 30;
}
void
inforom_nvl_v3_update_error_rate_entry
(
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate,
NvU32 newSec,
NvU32 newFlitCrcRate,
NvU32 *pNewLaneCrcRates
)
{
pErrorRate->lastUpdated = newSec;
pErrorRate->flitCrcErrorsPerMinute = newFlitCrcRate;
nvswitch_os_memcpy(pErrorRate->laneCrcErrorsPerMinute, pNewLaneCrcRates,
sizeof(pErrorRate->laneCrcErrorsPerMinute));
}
NvlStatus
inforom_nvl_v3_map_error_to_userspace_error
(
nvswitch_device *device,
INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorLog,
NVSWITCH_NVLINK_ERROR_ENTRY *pNvlError
)
{
static const NvU32 DL_RX_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_DL_RX_FAULT_DL_PROTOCOL_FATAL,
NVSWITCH_NVLINK_ERR_DL_RX_FAULT_SUBLINK_CHANGE_FATAL,
NVSWITCH_NVLINK_ERR_DL_RX_FLIT_CRC_CORR,
NVSWITCH_NVLINK_ERR_DL_RX_LANE0_CRC_CORR,
NVSWITCH_NVLINK_ERR_DL_RX_LANE1_CRC_CORR,
NVSWITCH_NVLINK_ERR_DL_RX_LANE2_CRC_CORR,
NVSWITCH_NVLINK_ERR_DL_RX_LANE3_CRC_CORR,
NVSWITCH_NVLINK_ERR_DL_RX_LINK_REPLAY_EVENTS_CORR
};
static const NvU32 DL_TX_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_DL_TX_FAULT_RAM_FATAL,
NVSWITCH_NVLINK_ERR_DL_TX_FAULT_INTERFACE_FATAL,
NVSWITCH_NVLINK_ERR_DL_TX_FAULT_SUBLINK_CHANGE_FATAL,
NVSWITCH_NVLINK_ERR_DL_TX_LINK_REPLAY_EVENTS_CORR
};
static const NvU32 DL_NA_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_UP_FATAL,
NVSWITCH_NVLINK_ERR_DL_LTSSM_FAULT_DOWN_FATAL,
NVSWITCH_NVLINK_ERR_DL_LINK_RECOVERY_EVENTS_CORR
};
static const NvU32 TLC_RX_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_TLC_RX_DL_HDR_PARITY_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DL_DATA_PARITY_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DL_CTRL_PARITY_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_AE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_BE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_ADDR_ALIGN_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_PKTLEN_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_CR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_HDR_OVERFLOW_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DATA_OVERFLOW_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_STOMP_DETECTED_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_CMD_ENC_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSVD_DAT_LEN_ENC_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_POISON_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_ILLEGAL_PRI_WRITE_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_HDR_RAM_ECC_DBE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DAT0_RAM_ECC_DBE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_RX_DAT1_RAM_ECC_DBE_FATAL
};
static const NvU32 TLC_TX_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_NCISOC_PARITY_ERR_FATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_ILLEGAL_PRI_WRITE_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_POISON_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_HW_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_UR_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_RSP_STATUS_PRIV_ERR_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_RSP_DAT_RAM_ECC_DBE_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL,
NVSWITCH_NVLINK_ERR_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL
};
static const NvU32 LIPT_ERRORS[] =
{
NVSWITCH_NVLINK_ERR_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_FAILED_MINION_REQUEST_NONFATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL,
NVSWITCH_NVLINK_ERR_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL
};
NvU32 subType = 0;
NvU8 nvliptInstance = 0, localLinkIdx = 0;
NvU8 numLinksPerNvlipt = device->hal.nvswitch_get_num_links_per_nvlipt(device);;
if ((pErrorLog == NULL) || (pNvlError == NULL))
{
return -NVL_BAD_ARGS;
}
subType = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _SUBTYPE, pErrorLog->errorSubtype);
nvliptInstance = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _NVLIPT_INSTANCE_ID, pErrorLog->metadata);
pNvlError->timeStamp = pErrorLog->data.event.lastError;
if (pErrorLog->header == INFOROM_NVL_ERROR_TYPE_COUNT)
{
pNvlError->count = (NvU64)pErrorLog->data.event.totalCount;
}
else if (pErrorLog->header == INFOROM_NVL_ERROR_TYPE_ACCUM)
{
pNvlError->count = pErrorLog->data.accum.totalCount.hi;
pNvlError->count = (pNvlError->count << 32) | pErrorLog->data.accum.totalCount.lo;
}
else
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL0, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL1, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL2, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL3, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL4, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _DL5, pErrorLog->metadata))
{
localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, pErrorLog->metadata);
pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx;
if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _NA, pErrorLog->metadata) &&
(subType < (sizeof(DL_NA_ERRORS) / sizeof(DL_NA_ERRORS[0]))))
{
pNvlError->error = DL_NA_ERRORS[subType];
return NVL_SUCCESS;
}
else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _RX, pErrorLog->metadata) &&
(subType < (sizeof(DL_RX_ERRORS) / sizeof(DL_RX_ERRORS[0]))))
{
pNvlError->error = DL_RX_ERRORS[subType];
return NVL_SUCCESS;
}
else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _TX, pErrorLog->metadata) &&
(subType < (sizeof(DL_TX_ERRORS) / sizeof(DL_TX_ERRORS[0]))))
{
pNvlError->error = DL_TX_ERRORS[subType];
return NVL_SUCCESS;
}
}
else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC0, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC1, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC2, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC3, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC4, pErrorLog->metadata) ||
FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _TLC5, pErrorLog->metadata))
{
localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, pErrorLog->metadata)
- NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC0;
pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx;
if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _RX, pErrorLog->metadata) &&
(subType < (sizeof(TLC_RX_ERRORS) / sizeof(TLC_RX_ERRORS[0]))))
{
pNvlError->error = TLC_RX_ERRORS[subType];
return NVL_SUCCESS;
}
else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _DIRECTION, _TX, pErrorLog->metadata) &&
(subType < (sizeof(TLC_TX_ERRORS) / sizeof(TLC_TX_ERRORS[0]))))
{
pNvlError->error = TLC_TX_ERRORS[subType];
return NVL_SUCCESS;
}
}
else if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID, _NVLIPT, pErrorLog->metadata))
{
if (subType < (sizeof(LIPT_ERRORS) / sizeof(LIPT_ERRORS[0])))
{
if (FLD_TEST_DRF(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID, _COMMON, pErrorLog->errorSubtype))
{
localLinkIdx = 0; //common nvlipt error
}
else
{
localLinkIdx = DRF_VAL(_INFOROM_NVL_OBJECT_V3, _NVLIPT_ERROR, _LINK_ID, pErrorLog->errorSubtype);
}
pNvlError->instance = nvliptInstance * numLinksPerNvlipt + localLinkIdx;
pNvlError->error = LIPT_ERRORS[subType];
return NVL_SUCCESS;
}
}
return -NVL_ERR_NOT_SUPPORTED;
}
void
inforom_nvl_v3_update_correctable_error_rates
(
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState,
NvU8 link,
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts
)
{
NvU32 i;
NvU32 tempFlitCrc, tempRxLinkReplay, tempTxLinkReplay, tempLinkRecovery;
NvU32 tempLaneCrc[4];
//
// If the registers have decreased from last reported, then
// they must have been reset or have overflowed. Set the last
// register value to 0.
//
if (pCounts->flitCrc < pState->lastRead[link].flitCrc)
{
pState->lastRead[link].flitCrc = 0;
}
for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++)
{
if (pCounts->laneCrc[i] < pState->lastRead[link].laneCrc[i])
{
pState->lastRead[link].laneCrc[i] = 0;
}
}
// Get number of new errors since the last register read
tempFlitCrc = pCounts->flitCrc;
pCounts->flitCrc -= pState->lastRead[link].flitCrc;
// Update errors per minute with error delta
m_inforom_nvl_get_new_errors_per_minute(pCounts->flitCrc,
&pState->errorsPerMinute[link].flitCrc);
// Save the current register value for the next callback
pState->lastRead[link].flitCrc = tempFlitCrc;
for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++)
{
tempLaneCrc[i] = pCounts->laneCrc[i];
pCounts->laneCrc[i] -= pState->lastRead[link].laneCrc[i];
m_inforom_nvl_get_new_errors_per_minute(pCounts->laneCrc[i],
&pState->errorsPerMinute[link].laneCrc[i]);
pState->lastRead[link].laneCrc[i] = tempLaneCrc[i];
}
//
// We don't track rates for the following errors. We just need to stash
// the current register value and update pCounts with the delta since
// the last register read.
//
if (pCounts->rxLinkReplay < pState->lastRead[link].rxLinkReplay)
{
pState->lastRead[link].rxLinkReplay = 0;
}
tempRxLinkReplay = pCounts->rxLinkReplay;
pCounts->rxLinkReplay -= pState->lastRead[link].rxLinkReplay;
pState->lastRead[link].rxLinkReplay = tempRxLinkReplay;
if (pCounts->txLinkReplay < pState->lastRead[link].txLinkReplay)
{
pState->lastRead[link].txLinkReplay = 0;
}
tempTxLinkReplay = pCounts->txLinkReplay;
pCounts->txLinkReplay -= pState->lastRead[link].txLinkReplay;
pState->lastRead[link].txLinkReplay = tempTxLinkReplay;
if (pCounts->linkRecovery < pState->lastRead[link].linkRecovery)
{
pState->lastRead[link].linkRecovery = 0;
}
tempLinkRecovery = pCounts->linkRecovery;
pCounts->linkRecovery -= pState->lastRead[link].linkRecovery;
pState->lastRead[link].linkRecovery = tempLinkRecovery;
}

108
src/common/nvswitch/kernel/inforom/inforom_nvl_v4_nvswitch.c Normal file
View File

@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "common_nvswitch.h"
#include "inforom/inforom_nvswitch.h"
#include "inforom/inforom_nvl_v4_nvswitch.h"
#include "ls10/ls10.h"
void
inforom_nvl_v4_update_correctable_error_rates
(
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState,
NvU8 link,
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pCounts
)
{
NvU32 i;
NvU32 tempFlitCrc, tempRxLinkReplay, tempTxLinkReplay, tempLinkRecovery;
NvU32 tempLaneCrc[4];
//
// If the registers have decreased from last reported, then
// they must have been reset or have overflowed. Set the last
// register value to 0.
//
if (pCounts->flitCrc < pState->lastRead[link].flitCrc)
{
pState->lastRead[link].flitCrc = 0;
}
for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++)
{
if (pCounts->laneCrc[i] < pState->lastRead[link].laneCrc[i])
{
pState->lastRead[link].laneCrc[i] = 0;
}
}
// Get number of new errors since the last register read
tempFlitCrc = pCounts->flitCrc;
pCounts->flitCrc -= pState->lastRead[link].flitCrc;
// Update errors per minute with error delta
m_inforom_nvl_get_new_errors_per_minute(pCounts->flitCrc,
&pState->errorsPerMinute[link].flitCrc);
// Save the current register value for the next callback
pState->lastRead[link].flitCrc = tempFlitCrc;
for (i = 0; i < NV_ARRAY_ELEMENTS(pState->lastRead[link].laneCrc); i++)
{
tempLaneCrc[i] = pCounts->laneCrc[i];
pCounts->laneCrc[i] -= pState->lastRead[link].laneCrc[i];
m_inforom_nvl_get_new_errors_per_minute(pCounts->laneCrc[i],
&pState->errorsPerMinute[link].laneCrc[i]);
pState->lastRead[link].laneCrc[i] = tempLaneCrc[i];
}
//
// We don't track rates for the following errors. We just need to stash
// the current register value and update pCounts with the delta since
// the last register read.
//
if (pCounts->rxLinkReplay < pState->lastRead[link].rxLinkReplay)
{
pState->lastRead[link].rxLinkReplay = 0;
}
tempRxLinkReplay = pCounts->rxLinkReplay;
pCounts->rxLinkReplay -= pState->lastRead[link].rxLinkReplay;
pState->lastRead[link].rxLinkReplay = tempRxLinkReplay;
if (pCounts->txLinkReplay < pState->lastRead[link].txLinkReplay)
{
pState->lastRead[link].txLinkReplay = 0;
}
tempTxLinkReplay = pCounts->txLinkReplay;
pCounts->txLinkReplay -= pState->lastRead[link].txLinkReplay;
pState->lastRead[link].txLinkReplay = tempTxLinkReplay;
if (pCounts->linkRecovery < pState->lastRead[link].linkRecovery)
{
pState->lastRead[link].linkRecovery = 0;
}
tempLinkRecovery = pCounts->linkRecovery;
pCounts->linkRecovery -= pState->lastRead[link].linkRecovery;
pState->lastRead[link].linkRecovery = tempLinkRecovery;
}

490
src/common/nvswitch/kernel/lr10/inforom_lr10.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -31,12 +31,15 @@
#include "nvswitch/lr10/dev_pmgr.h"
#include "nvVer.h"
#include "regkey_nvswitch.h"
#include "inforom/inforom_nvl_v3_nvswitch.h"
#include "soe/soeififr.h"
//
// TODO: Split individual object hals to their own respective files
//
static void _oms_parse(nvswitch_device *device, INFOROM_OMS_STATE *pOmsState);
static void _oms_refresh(nvswitch_device *device, INFOROM_OMS_STATE *pOmsState);
NvlStatus
nvswitch_inforom_nvl_log_error_event_lr10
(
@ -46,7 +49,147 @@ nvswitch_inforom_nvl_log_error_event_lr10
NvBool *bDirty
)
{
return -NVL_ERR_NOT_SUPPORTED;
NvlStatus status;
INFOROM_NVL_OBJECT_V3S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v3s;
INFOROM_NVLINK_ERROR_EVENT *pErrorEvent = (INFOROM_NVLINK_ERROR_EVENT *)pNvlErrorEvent;
INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorEntry;
NvU32 i;
NvU32 sec;
NvU8 header = 0;
NvU16 metadata = 0;
NvU8 errorSubtype;
NvU64 accumTotalCount;
INFOROM_NVL_ERROR_BLOCK_TYPE blockType;
if (pErrorEvent->nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n",
INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, pErrorEvent->nvliptInstance);
return -NVL_BAD_ARGS;
}
if (pErrorEvent->localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u internal links (internal link = %u requested)\n",
INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, pErrorEvent->localLinkIdx);
return -NVL_BAD_ARGS;
}
sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS);
status = inforom_nvl_v3_map_error(pErrorEvent->error, &header, &metadata,
&errorSubtype, &blockType);
if (status != NVL_SUCCESS)
{
return status;
}
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA,
_NVLIPT_INSTANCE_ID, pErrorEvent->nvliptInstance, metadata);
if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_DL)
{
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID,
NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(pErrorEvent->localLinkIdx),
metadata);
}
else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_TLC)
{
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID,
NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(pErrorEvent->localLinkIdx),
metadata);
}
else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT)
{
metadata = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA,
_BLOCK_ID, _NVLIPT, metadata);
status = inforom_nvl_v3_encode_nvlipt_error_subtype(pErrorEvent->localLinkIdx,
&errorSubtype);
if (status != NVL_SUCCESS)
{
return status;
}
}
for (i = 0; i < INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES; i++)
{
pErrorEntry = &pNvlObject->errorLog[i];
if ((pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) ||
((pErrorEntry->metadata == metadata) &&
(pErrorEntry->errorSubtype == errorSubtype)))
{
break;
}
}
if (i >= INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES)
{
NVSWITCH_PRINT(device, ERROR, "%s: NVL error log is full -- unable to log error\n",
__FUNCTION__);
return -NVL_ERR_INVALID_STATE;
}
if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID)
{
pErrorEntry->header = header;
pErrorEntry->metadata = metadata;
pErrorEntry->errorSubtype = errorSubtype;
}
if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_ACCUM)
{
accumTotalCount = NvU64_ALIGN32_VAL(&pErrorEntry->data.accum.totalCount);
if (accumTotalCount != NV_U64_MAX)
{
if (pErrorEvent->count > NV_U64_MAX - accumTotalCount)
{
accumTotalCount = NV_U64_MAX;
}
else
{
accumTotalCount += pErrorEvent->count;
}
NvU64_ALIGN32_PACK(&pErrorEntry->data.accum.totalCount, &accumTotalCount);
if (sec < pErrorEntry->data.accum.lastUpdated)
{
NVSWITCH_PRINT(device, ERROR,
"%s: System clock reporting earlier time than error timestamp\n",
__FUNCTION__);
}
pErrorEntry->data.accum.lastUpdated = sec;
*bDirty = NV_TRUE;
}
}
else if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_COUNT)
{
if (pErrorEntry->data.event.totalCount != NV_U32_MAX)
{
pErrorEntry->data.event.totalCount++;
if (sec < pErrorEntry->data.event.lastError)
{
NVSWITCH_PRINT(device, ERROR,
"%s: System clock reporting earlier time than error timestamp\n",
__FUNCTION__);
}
else
{
pErrorEntry->data.event.avgEventDelta =
(pErrorEntry->data.event.avgEventDelta + sec -
pErrorEntry->data.event.lastError) >> 1;
}
pErrorEntry->data.event.lastError = sec;
*bDirty = NV_TRUE;
}
}
else
{
return -NVL_ERR_INVALID_STATE;
}
return NVL_SUCCESS;
}
NvlStatus
@ -56,7 +199,37 @@ nvswitch_inforom_nvl_get_max_correctable_error_rate_lr10
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
NvU8 linkID = params->linkId;
if (linkID >= NVSWITCH_NUM_LINKS_LR10)
{
return -NVL_BAD_ARGS;
}
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
nvswitch_os_memset(params, 0, sizeof(NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS));
params->linkId = linkID;
nvswitch_os_memcpy(&params->dailyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v3s.maxCorrectableErrorRates.dailyMaxCorrectableErrorRates[0][linkID],
sizeof(params->dailyMaxCorrectableErrorRates));
nvswitch_os_memcpy(&params->monthlyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v3s.maxCorrectableErrorRates.monthlyMaxCorrectableErrorRates[0][linkID],
sizeof(params->monthlyMaxCorrectableErrorRates));
return NVL_SUCCESS;
}
NvlStatus
@ -66,8 +239,64 @@ nvswitch_inforom_nvl_get_errors_lr10
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
NvU32 maxReadSize = sizeof(params->errorLog)/sizeof(NVSWITCH_NVLINK_ERROR_ENTRY);
NvU32 errorLeftCount = 0, errorReadCount = 0, errIndx = 0;
NvU32 errorStart = params->errorIndex;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (errorStart >= INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES)
{
return -NVL_BAD_ARGS;
}
nvswitch_os_memset(params->errorLog, 0, sizeof(params->errorLog));
while (((errorStart + errorLeftCount) < INFOROM_NVL_OBJECT_V3S_NUM_ERROR_ENTRIES) &&
(pNvlinkState->pNvl->v3s.errorLog[errorStart + errorLeftCount].header != INFOROM_NVL_ERROR_TYPE_INVALID))
{
errorLeftCount++;
}
if (errorLeftCount > maxReadSize)
{
errorReadCount = maxReadSize;
}
else
{
errorReadCount = errorLeftCount;
}
params->errorIndex = errorStart + errorReadCount;
params->errorCount = errorReadCount;
if (errorReadCount > 0)
{
for (errIndx = 0; errIndx < errorReadCount; errIndx++)
{
if (inforom_nvl_v3_map_error_to_userspace_error(device,
&pNvlinkState->pNvl->v3s.errorLog[errorStart+errIndx],
&params->errorLog[errIndx]) != NVL_SUCCESS)
{
return -NVL_ERR_NOT_SUPPORTED;
}
}
}
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_lr10
(
nvswitch_device *device,
@ -79,9 +308,251 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_lr10
void *pNvlErrorCounts,
NvBool *bDirty
)
{
INFOROM_NVL_OBJECT_V3S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v3s;
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V3S *pState =
&((INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE *)pData)->v3s;
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts =
(INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *)pNvlErrorCounts;
NvU32 i;
NvU32 sec;
NvU32 day, month, currentEntryDay, currentEntryMonth;
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate;
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pOldestErrorRate = NULL;
INFOROM_NVL_OBJECT_V3S_MAX_CORRECTABLE_ERROR_RATES *pCorrErrorRates;
NvBool bUpdated = NV_FALSE;
INFOROM_NVLINK_ERROR_EVENT errorEvent;
NvU32 currentFlitCrcRate;
NvU32 *pCurrentLaneCrcRates;
if (bDirty == NULL)
{
return -NVL_BAD_ARGS;
}
*bDirty = NV_FALSE;
if (linkId >= INFOROM_NVL_OBJECT_V3S_NUM_LINKS)
{
NVSWITCH_PRINT(device, ERROR,
"object does not store data for more than %u links (linkId = %u requested)\n",
INFOROM_NVL_OBJECT_V3S_NUM_LINKS, linkId);
return -NVL_BAD_ARGS;
}
if (nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n",
INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, nvliptInstance);
return -NVL_BAD_ARGS;
}
if (localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u internal links (internal link = %u requested)\n",
INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, localLinkIdx);
return -NVL_BAD_ARGS;
}
sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS);
inforom_nvl_v3_seconds_to_day_and_month(sec, &day, &month);
inforom_nvl_v3_update_correctable_error_rates(pState, linkId, pErrorCounts);
currentFlitCrcRate = pState->errorsPerMinute[linkId].flitCrc;
pCurrentLaneCrcRates = pState->errorsPerMinute[linkId].laneCrc;
pCorrErrorRates = &pNvlObject->maxCorrectableErrorRates;
for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->dailyMaxCorrectableErrorRates); i++)
{
pErrorRate = &pCorrErrorRates->dailyMaxCorrectableErrorRates[i][linkId];
inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, &currentEntryDay,
&currentEntryMonth);
if ((pErrorRate->lastUpdated == 0) || (currentEntryDay == day))
{
if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate,
currentFlitCrcRate,
pCurrentLaneCrcRates))
{
inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
pOldestErrorRate = NULL;
break;
}
else if ((pOldestErrorRate == NULL) ||
(pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated))
{
pOldestErrorRate = pErrorRate;
}
}
if (pOldestErrorRate != NULL)
{
inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->monthlyMaxCorrectableErrorRates); i++)
{
pErrorRate = &pCorrErrorRates->monthlyMaxCorrectableErrorRates[i][linkId];
inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, &currentEntryDay,
&currentEntryMonth);
if ((pErrorRate->lastUpdated == 0) || (currentEntryMonth == month))
{
if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate,
currentFlitCrcRate,
pCurrentLaneCrcRates))
{
inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
pOldestErrorRate = NULL;
break;
}
else if ((pOldestErrorRate == NULL) ||
(pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated))
{
pOldestErrorRate = pErrorRate;
}
}
if (pOldestErrorRate != NULL)
{
inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
*bDirty = bUpdated;
// Update aggregate error counts for each correctable error
errorEvent.nvliptInstance = nvliptInstance;
errorEvent.localLinkIdx = localLinkIdx;
if (pErrorCounts->flitCrc > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR;
errorEvent.count = pErrorCounts->flitCrc;
nvswitch_inforom_nvl_log_error_event_lr10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->rxLinkReplay > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR;
errorEvent.count = pErrorCounts->rxLinkReplay;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_lr10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->txLinkReplay > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR;
errorEvent.count = pErrorCounts->txLinkReplay;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_lr10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->linkRecovery > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR;
errorEvent.count = pErrorCounts->linkRecovery;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_lr10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
for (i = 0; i < 4; i++)
{
if (pErrorCounts->laneCrc[i] == 0)
{
continue;
}
errorEvent.error = INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR + i;
errorEvent.count = pErrorCounts->laneCrc[i];
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_lr10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_setL1Threshold_lr10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 word1,
NvU32 word2
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus nvswitch_inforom_nvl_getL1Threshold_lr10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 *word1,
NvU32 *word2
)
{
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_lr10
(
nvswitch_device *device,
INFOROM_NVLINK_STATE *pNvlinkState,
NvU8 version
)
{
if (version != 3)
{
NVSWITCH_PRINT(device, WARN, "NVL v%u not supported\n", version);
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState->pFmt = INFOROM_NVL_OBJECT_V3S_FMT;
pNvlinkState->pPackedObject = nvswitch_os_malloc(INFOROM_NVL_OBJECT_V3S_PACKED_SIZE);
if (pNvlinkState->pPackedObject == NULL)
{
return -NVL_NO_MEM;
}
pNvlinkState->pNvl = nvswitch_os_malloc(sizeof(INFOROM_NVL_OBJECT));
if (pNvlinkState->pNvl == NULL)
{
nvswitch_os_free(pNvlinkState->pPackedObject);
return -NVL_NO_MEM;
}
pNvlinkState->bDisableCorrectableErrorLogging = NV_FALSE;
return NVL_SUCCESS;
}
static
NvlStatus
_inforom_ecc_find_useable_entry_index
@ -810,3 +1281,14 @@ nvswitch_bbx_get_sxid_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_bbx_get_data_lr10
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
}

412
src/common/nvswitch/kernel/lr10/intr_lr10.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -3492,11 +3492,16 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event;
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
pending = report.raw_pending & report.mask;
if (pending == 0)
{
@ -3505,6 +3510,7 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_PRIV_ERR, 1);
if (nvswitch_test_flags(pending, bit))
@ -3512,6 +3518,11 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_0_lr10
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_PRIV_ERR, "RX Rsp Status PRIV Error");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0, _RXRSPSTATUS_PRIV_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_PRIV_ERR_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -3544,12 +3555,17 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event;
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -3557,12 +3573,20 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_DAT_ECC_DBE_ERR, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_CREQ_RAM_DAT_ECC_DBE_ERR, "CREQ RAM DAT ECC DBE Error");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _CREQ_RAM_DAT_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_TX_CREQ_DAT_RAM_ECC_DBE_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_ECC_LIMIT_ERR, 1);
@ -3591,6 +3615,13 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_0_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_COM_RAM_DAT_ECC_DBE_ERR, "COM RAM DAT ECC DBE Error");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _COM_RAM_DAT_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_TX_COM_DAT_RAM_ECC_DBE_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _COM_RAM_ECC_LIMIT_ERR, 1);
@ -3642,14 +3673,19 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_lr10
NvU32 link
)
{
NvU32 pending, bit, unhandled, injected;
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event;
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_NON_FATAL_REPORT_EN_1);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -3667,6 +3703,8 @@ _nvswitch_service_nvltlc_rx_lnk_nonfatal_1_lr10
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _AN1_HEARTBEAT_TIMEOUT_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_AN1_HEARTBEAT_TIMEOUT_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
//
// WAR Bug 200627368: Mask off HBTO to avoid a storm
// During the start of reset_and_drain, all links on the GPU
@ -3719,12 +3757,17 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_1);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_NON_FATAL_REPORT_EN_1);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -3732,12 +3775,19 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_1);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_1);
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC0, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC0, "AN1 Timeout VC0");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC0, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC0_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC1, 1);
@ -3745,6 +3795,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC1, "AN1 Timeout VC1");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC1, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC1_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC2, 1);
@ -3752,6 +3808,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC2, "AN1 Timeout VC2");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC2, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC2_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC3, 1);
@ -3760,6 +3822,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC3, "AN1 Timeout VC3");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC3, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC3_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC4, 1);
@ -3768,6 +3835,11 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC4, "AN1 Timeout VC4");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC4, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC4_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC5, 1);
@ -3775,6 +3847,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC5, "AN1 Timeout VC5");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC5, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC5_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC6, 1);
@ -3782,6 +3860,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC6, "AN1 Timeout VC6");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC6, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC6_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_1, _AN1_TIMEOUT_VC7, 1);
@ -3789,6 +3873,12 @@ _nvswitch_service_nvltlc_tx_lnk_nonfatal_1_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLTLC_TX_LNK_AN1_TIMEOUT_VC7, "AN1 Timeout VC7");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_1, _AN1_TIMEOUT_VC7, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_AN1_TIMEOUT_VC7_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -3890,11 +3980,16 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_NON_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
pending = report.raw_pending & report.mask;
if (pending == 0)
{
@ -3903,12 +3998,19 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _ILLEGALLINKSTATEREQUEST, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST, "_HW_NVLIPT_LNK_ILLEGALLINKSTATEREQUEST");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _ILLEGALLINKSTATEREQUEST, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_ILLEGAL_LINK_STATE_REQUEST_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1);
@ -3916,6 +4018,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_FAILEDMINIONREQUEST, "_FAILEDMINIONREQUEST");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _FAILEDMINIONREQUEST, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_FAILED_MINION_REQUEST_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RESERVEDREQUESTVALUE, 1);
@ -3923,6 +4031,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_RESERVEDREQUESTVALUE, "_RESERVEDREQUESTVALUE");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RESERVEDREQUESTVALUE, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_RESERVED_REQUEST_VALUE_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINKSTATEWRITEWHILEBUSY, 1);
@ -3930,6 +4044,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINKSTATEWRITEWHILEBUSY, "_LINKSTATEWRITEWHILEBUSY");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _LINKSTATEWRITEWHILEBUSY, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_WRITE_WHILE_BUSY_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _LINK_STATE_REQUEST_TIMEOUT, 1);
@ -3937,6 +4057,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_LINK_STATE_REQUEST_TIMEOUT, "_LINK_STATE_REQUEST_TIMEOUT");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _LINK_STATE_REQUEST_TIMEOUT, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_LINK_STATE_REQUEST_TIMEOUT_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 1);
@ -3944,6 +4070,12 @@ _nvswitch_service_nvlipt_lnk_nonfatal_lr10
{
NVSWITCH_REPORT_NONFATAL(_HW_NVLIPT_LNK_WRITE_TO_LOCKED_SYSTEM_REG_ERR, "_WRITE_TO_LOCKED_SYSTEM_REG_ERR");
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _WRITE_TO_LOCKED_SYSTEM_REG_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_WRITE_TO_LOCKED_SYSTEM_REG_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -4456,12 +4588,16 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLDL, _NVLDL_TOP, _INTR);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLDL, _NVLDL_TOP, _INTR_STALL_EN);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -4474,6 +4610,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_RAM, "TX Fault Ram", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_TX_FAULT_RAM_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_INTERFACE, 1);
@ -4481,6 +4619,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_INTERFACE, "TX Fault Interface", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_TX_FAULT_INTERFACE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _TX_FAULT_SUBLINK_CHANGE, 1);
@ -4488,6 +4628,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_TX_FAULT_SUBLINK_CHANGE, "TX Fault Sublink Change", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_TX_FAULT_SUBLINK_CHANGE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_SUBLINK_CHANGE, 1);
@ -4495,6 +4637,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_SUBLINK_CHANGE, "RX Fault Sublink Change", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_RX_FAULT_SUBLINK_CHANGE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _RX_FAULT_DL_PROTOCOL, 1);
@ -4502,6 +4646,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_RX_FAULT_DL_PROTOCOL, "RX Fault DL Protocol", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_RX_FAULT_DL_PROTOCOL_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_DOWN, 1);
@ -4509,6 +4655,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_DOWN, "LTSSM Fault Down", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_DOWN_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_FAULT_UP, 1);
@ -4516,6 +4664,8 @@ nvswitch_service_nvldl_fatal_link_lr10
{
NVSWITCH_REPORT_FATAL(_HW_DLPL_LTSSM_FAULT_UP, "LTSSM Fault Up", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
error_event.error = INFOROM_NVLINK_DL_LTSSM_FAULT_UP_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
bit = DRF_NUM(_NVLDL_TOP, _INTR, _LTSSM_PROTOCOL, 1);
@ -4621,12 +4771,17 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -4634,12 +4789,19 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_SYS, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_PARITY_ERR, "NCISOC Parity Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_SYS_ERR_REPORT_INJECT_0, _NCISOC_PARITY_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_PARITY_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_HDR_ECC_DBE_ERR, 1);
@ -4647,6 +4809,12 @@ _nvswitch_service_nvltlc_tx_sys_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_SYS_NCISOC_HDR_ECC_DBE_ERR, "NCISOC HDR ECC DBE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_SYS_ERR_REPORT_INJECT_0, _NCISOC_HDR_ECC_DBE_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_NCISOC_HDR_ECC_DBE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_SYS, _ERR_STATUS_0, _NCISOC_DAT_ECC_DBE_ERR, 1);
@ -4729,12 +4897,17 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -4742,6 +4915,7 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _NCISOC_PARITY_ERR, 1);
if (nvswitch_test_flags(pending, bit))
@ -4755,6 +4929,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_HDR_RAM_ECC_DBE_ERR, "HDR RAM ECC DBE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _HDR_RAM_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_RX_HDR_RAM_ECC_DBE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _HDR_RAM_ECC_LIMIT_ERR, 1);
@ -4769,6 +4950,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT0_RAM_ECC_DBE_ERR, "DAT0 RAM ECC DBE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _DAT0_RAM_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_RX_DAT0_RAM_ECC_DBE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT0_RAM_ECC_LIMIT_ERR, 1);
@ -4783,6 +4971,13 @@ _nvswitch_service_nvltlc_rx_sys_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_SYS_DAT1_RAM_ECC_DBE_ERR, "DAT1 RAM ECC DBE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_RX_SYS, _ERR_REPORT_INJECT_0, _DAT1_RAM_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_RX_DAT1_RAM_ECC_DBE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_SYS, _ERR_STATUS_0, _DAT1_RAM_ECC_LIMIT_ERR, 1);
@ -4830,12 +5025,17 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -4843,12 +5043,19 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _TXDLCREDITPARITYERR, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TXDLCREDITPARITYERR, "TX DL Credit Parity Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _TX_LNK_ERR_REPORT_INJECT_0, _TXDLCREDITPARITYERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_TX_DL_CREDIT_PARITY_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_TX_LNK, _ERR_STATUS_0, _CREQ_RAM_HDR_ECC_DBE_ERR, 1);
@ -4884,6 +5091,13 @@ _nvswitch_service_nvltlc_tx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_TX_LNK_RSP1_RAM_DAT_ECC_DBE_ERR, "RSP1 RAM DAT ECC DBE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC_TX_LNK, _ERR_REPORT_INJECT_0, _RSP1_RAM_DAT_ECC_DBE_ERR, 0x0, injected))
{
// TODO 3014908 log these in the NVL object until we have ECC object support
error_event.error = INFOROM_NVLINK_TLC_TX_RSP1_DAT_RAM_ECC_DBE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -4923,11 +5137,17 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_0);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -4935,12 +5155,19 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLHDRPARITYERR, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLHDRPARITYERR, "RX DL HDR Parity Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLHDRPARITYERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DL_HDR_PARITY_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLDATAPARITYERR, 1);
@ -4948,6 +5175,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLDATAPARITYERR, "RX DL Data Parity Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLDATAPARITYERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DL_DATA_PARITY_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXDLCTRLPARITYERR, 1);
@ -4955,6 +5188,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDLCTRLPARITYERR, "RX DL Ctrl Parity Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXDLCTRLPARITYERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DL_CTRL_PARITY_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDAEERR, 1);
@ -4962,6 +5201,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDAEERR, "RX Invalid DAE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDAEERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_AE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDBEERR, 1);
@ -4969,6 +5214,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDBEERR, "RX Invalid BE Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDBEERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_BE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXINVALIDADDRALIGNERR, 1);
@ -4976,6 +5227,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXINVALIDADDRALIGNERR, "RX Invalid Addr Align Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXINVALIDADDRALIGNERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_ADDR_ALIGN_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXPKTLENERR, 1);
@ -4983,6 +5240,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXPKTLENERR, "RX Packet Length Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXPKTLENERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_PKTLEN_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCMDENCERR, 1);
@ -4990,6 +5253,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCMDENCERR, "RSV Cmd Encoding Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCMDENCERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CMD_ENC_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVDATLENENCERR, 1);
@ -4997,6 +5266,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVDATLENENCERR, "RSV Data Length Encoding Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVDATLENENCERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_DAT_LEN_ENC_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVPKTSTATUSERR, 1);
@ -5004,6 +5279,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVPKTSTATUSERR, "RSV Packet Status Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVPKTSTATUSERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_PACKET_STATUS_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBEREQERR, 1);
@ -5011,6 +5292,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBEREQERR, "RSV Packet Status Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCACHEATTRPROBEREQERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_REQ_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RSVCACHEATTRPROBERSPERR, 1);
@ -5018,6 +5305,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RSVCACHEATTRPROBERSPERR, "RSV CacheAttr Probe Rsp Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RSVCACHEATTRPROBERSPERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSVD_CACHE_ATTR_PROBE_RSP_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENGTRMWREQMAXERR, 1);
@ -5025,6 +5318,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENGTRMWREQMAXERR, "Data Length RMW Req Max Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _DATLENGTRMWREQMAXERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_GT_RMW_REQ_MAX_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _DATLENLTATRRSPMINERR, 1);
@ -5032,6 +5331,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_DATLENLTATRRSPMINERR, "Data Len Lt ATR RSP Min Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _DATLENLTATRRSPMINERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DATLEN_LT_ATR_RSP_MIN_ERR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCACHEATTRPOERR, 1);
@ -5039,6 +5344,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCACHEATTRPOERR, "Invalid Cache Attr PO Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALIDCACHEATTRPOERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_PO_FOR_CACHE_ATTR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALIDCRERR, 1);
@ -5046,6 +5357,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_INVALIDCRERR, "Invalid CR Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALIDCRERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_CR_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_HW_ERR, 1);
@ -5053,6 +5370,13 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_HW_ERR, "RX Rsp Status HW Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
// TODO 200564153 _RX_RSPSTATUS_HW_ERR should be reported as non-fatal
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXRSPSTATUS_HW_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_HW_ERR_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _RXRSPSTATUS_UR_ERR, 1);
@ -5060,6 +5384,13 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_RXRSPSTATUS_UR_ERR, "RX Rsp Status UR Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
// TODO 200564153 _RX_RSPSTATUS_UR_ERR should be reported as non-fatal
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _RXRSPSTATUS_UR_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_RSP_STATUS_UR_ERR_NONFATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_0, _INVALID_COLLAPSED_RESPONSE_ERR, 1);
@ -5067,6 +5398,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_0_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RX_LNK_INVALID_COLLAPSED_RESPONSE_ERR, "Invalid Collapsed Response Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_0, _INVALID_COLLAPSED_RESPONSE_ERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_INVALID_COLLAPSED_RESPONSE_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -5106,12 +5443,17 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10
{
NvU32 pending, bit, unhandled;
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_STATUS_1);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FATAL_REPORT_EN_1);
report.mask = report.raw_enable;
pending = report.raw_pending & report.mask;
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
if (pending == 0)
{
return -NVL_NOT_FOUND;
@ -5119,12 +5461,19 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_FIRST_1);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLTLC, _NVLTLC_RX_LNK, _ERR_REPORT_INJECT_1);
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXHDROVFERR, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXHDROVFERR, "RX HDR OVF Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXHDROVFERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_HDR_OVERFLOW_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXDATAOVFERR, 1);
@ -5132,6 +5481,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_RXDATAOVFERR, "RX Data OVF Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _RXDATAOVFERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_DATA_OVERFLOW_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _STOMPDETERR, 1);
@ -5139,6 +5494,12 @@ _nvswitch_service_nvltlc_rx_lnk_fatal_1_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLTLC_STOMPDETERR, "Stomp Det Error", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLTLC, _RX_LNK_ERR_REPORT_INJECT_1, _STOMPDETERR, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_TLC_RX_STOMP_DETECTED_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLTLC_RX_LNK, _ERR_STATUS_1, _RXPOISONERR, 1);
@ -5253,6 +5614,8 @@ _nvswitch_service_nvlipt_common_fatal_lr10
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, contain, unhandled;
NvU32 link, local_link_idx;
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_FATAL_REPORT_EN_0);
@ -5267,9 +5630,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10
return -NVL_NOT_FOUND;
}
error_event.nvliptInstance = (NvU8) instance;
unhandled = pending;
report.raw_first = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_FIRST_0);
contain = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_CONTAIN_EN_0);
injected = NVSWITCH_NVLIPT_RD32_LR10(device, instance, _NVLIPT_COMMON, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _CLKCTL_ILLEGAL_REQUEST, 1);
if (nvswitch_test_flags(pending, bit))
@ -5284,6 +5650,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10
}
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _CLKCTL_ILLEGAL_REQUEST, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_CLKCTL_ILLEGAL_REQUEST_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _RSTSEQ_PLL_TIMEOUT, 1);
@ -5299,6 +5671,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10
}
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _RSTSEQ_PLL_TIMEOUT, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PLL_TIMEOUT_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_COMMON, _ERR_STATUS_0, _RSTSEQ_PHYARB_TIMEOUT, 1);
@ -5314,6 +5692,12 @@ _nvswitch_service_nvlipt_common_fatal_lr10
}
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_COMMON, _ERR_REPORT_INJECT_0, _RSTSEQ_PHYARB_TIMEOUT, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYARB_TIMEOUT_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);
@ -5360,6 +5744,8 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10
{
NVSWITCH_INTERRUPT_LOG_TYPE report = { 0 };
NvU32 pending, bit, unhandled;
INFOROM_NVLINK_ERROR_EVENT error_event = { 0 };
NvU32 injected;
report.raw_pending = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
report.raw_enable = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FATAL_REPORT_EN_0);
@ -5371,14 +5757,24 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10
return -NVL_NOT_FOUND;
}
error_event.nvliptInstance = (NvU8) nvlipt_instance;
error_event.localLinkIdx = (NvU8) NVSWITCH_NVLIPT_GET_LOCAL_LINK_ID_LR10(link);
unhandled = pending;
report.raw_first = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_FIRST_0);
injected = NVSWITCH_LINK_RD32_LR10(device, link, NVLIPT_LNK, _NVLIPT_LNK, _ERR_REPORT_INJECT_0);
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _SLEEPWHILEACTIVELINK, 1);
if (nvswitch_test_flags(pending, bit))
{
NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_SLEEPWHILEACTIVELINK, "No non-empty link is detected", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _SLEEPWHILEACTIVELINK, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_SLEEP_WHILE_ACTIVE_LINK_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_PHYCTL_TIMEOUT, 1);
@ -5386,6 +5782,12 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_PHYCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from PHYCTL", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RSTSEQ_PHYCTL_TIMEOUT, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_PHYCTL_TIMEOUT_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _RSTSEQ_CLKCTL_TIMEOUT, 1);
@ -5393,6 +5795,12 @@ _nvswitch_service_nvlipt_lnk_fatal_lr10
{
NVSWITCH_REPORT_FATAL(_HW_NVLIPT_LNK_RSTSEQ_CLKCTL_TIMEOUT, "Reset sequencer timed out waiting for a handshake from CLKCTL", NV_FALSE);
nvswitch_clear_flags(&unhandled, bit);
if (FLD_TEST_DRF_NUM(_NVLIPT_LNK, _ERR_REPORT_INJECT_0, _RSTSEQ_CLKCTL_TIMEOUT, 0x0, injected))
{
error_event.error = INFOROM_NVLINK_NVLIPT_RSTSEQ_CLKCTL_TIMEOUT_FATAL;
nvswitch_inforom_nvlink_log_error_event(device, &error_event);
}
}
NVSWITCH_UNHANDLED_CHECK(device, unhandled);

117
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@ -43,40 +43,68 @@
#include "nvswitch/lr10/dev_nvlipt_ip.h"
#include "nvswitch/lr10/dev_nport_ip.h"
#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 8 // This must be incremented if any entries are added to the array below
#define NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK 12 // This must be incremented if any entries are added to the array below
lr10_links_connected_to_disabled_remote_end nvswitchDisconnetedRemoteLinkMasks[] =
{
{
0x8, // switchPhysicalId
0x56A000500 //linkMask
0x8, // switchPhysicalId
0x56A000500, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x9, // switchPhysicalId
0x509009900 //linkMask
0x9, // switchPhysicalId
0x509009900, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0xb, // switchPhysicalId
0x56A000600 //linkMask
0xa, // switchPhysicalId
0x0, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0xc, // switchPhysicalId
0x4A9009400 //linkMask
0xb, // switchPhysicalId
0x56A000600, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x18, // switchPhysicalId
0x56A000500 //linkMask
0xc, // switchPhysicalId
0x4A9009400, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x19, // switchPhysicalId
0x509009900 //linkMask
0xd, // switchPhysicalId
0x0, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1b, // switchPhysicalId
0x56A000600 //linkMask
0x18, // switchPhysicalId
0x56A000500, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1c, // switchPhysicalId
0x4A9009400 //linkMask
0x19, // switchPhysicalId
0x509009900, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1a, // switchPhysicalId
0x0, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1b, // switchPhysicalId
0x56A000600, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1c, // switchPhysicalId
0x4A9009400, // accessLinkMask
0xFF00FF // trunkLinkMask
},
{
0x1d, // switchPhysicalId
0x0, // accessLinkMask
0xFF00FF // trunkLinkMask
},
};
ct_assert(sizeof(nvswitchDisconnetedRemoteLinkMasks)/sizeof(lr10_links_connected_to_disabled_remote_end) == NUM_SWITCH_WITH_DISCONNETED_REMOTE_LINK);
@ -538,6 +566,11 @@ nvswitch_init_lpwr_regs_lr10
NvU8 softwareDesired, hardwareDisable;
NvBool bLpEnable;
if (nvswitch_is_link_in_reset(device, link))
{
return;
}
if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO)
{
return;
@ -653,6 +686,15 @@ nvswitch_init_lpwr_regs_lr10
tempRegVal);
}
void
nvswitch_program_l1_scratch_reg_lr10
(
nvswitch_device *device,
NvU32 linkNumber
)
{
// Not Implemented for LR10
}
void
nvswitch_init_buffer_ready_lr10
@ -841,7 +883,6 @@ nvswitch_corelib_set_dl_link_mode_lr10
if (nvswitch_does_link_need_termination_enabled(device, link))
{
if (mode == NVLINK_LINKSTATE_INITPHASE1)
{
status = nvswitch_link_termination_setup(device, link);
@ -2368,6 +2409,8 @@ nvswitch_load_link_disable_settings_lr10
NvU32 val;
NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL;
NVSWITCH_BIOS_NVLINK_CONFIG *bios_config;
NvlStatus status;
lr10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
bios_config = nvswitch_get_bios_nvlink_config(device);
if ((bios_config == NULL) || (bios_config->bit_address == 0))
@ -2408,15 +2451,16 @@ nvswitch_load_link_disable_settings_lr10
__FUNCTION__, link->linkNumber);
return;
}
val = FLD_SET_DRF(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, _LINK_DISABLE,
_DISABLED, val);
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber,
NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_MODE_CTRL, val);
// Set link to invalid and unregister from corelib
device->link[link->linkNumber].valid = NV_FALSE;
nvlink_lib_unregister_link(link);
nvswitch_destroy_link(link);
status = nvswitch_link_termination_setup(device, link);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to enable termination on link #%d\n", __FUNCTION__, link->linkNumber);
return;
}
// add link to disabledRemoteEndLinkMask
chip_device->disabledRemoteEndLinkMask |= NVBIT64(link->linkNumber);
return;
}
@ -2484,6 +2528,8 @@ nvswitch_does_link_need_termination_enabled_lr10
NvU32 i;
NvU32 physicalId;
lr10_device *chip_device;
NvU32 numNvswitches;
NvlStatus status;
physicalId = nvswitch_read_physical_id(device);
chip_device = NVSWITCH_GET_CHIP_DEVICE_LR10(device);
@ -2510,8 +2556,22 @@ nvswitch_does_link_need_termination_enabled_lr10
{
if (nvswitchDisconnetedRemoteLinkMasks[i].switchPhysicalId == physicalId)
{
chip_device->disabledRemoteEndLinkMask =
nvswitchDisconnetedRemoteLinkMasks[i].linkMask;
chip_device->disabledRemoteEndLinkMask |=
nvswitchDisconnetedRemoteLinkMasks[i].accessLinkMask;
status = nvlink_lib_return_device_count_by_type(NVLINK_DEVICE_TYPE_NVSWITCH, &numNvswitches);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to get nvswitch device count!\n", __FUNCTION__);
break;
}
if (numNvswitches <= NVSWITCH_NUM_DEVICES_PER_DELTA_LR10)
{
chip_device->disabledRemoteEndLinkMask |=
nvswitchDisconnetedRemoteLinkMasks[i].trunkLinkMask;
}
break;
}
}
@ -2520,7 +2580,6 @@ nvswitch_does_link_need_termination_enabled_lr10
chip_device->bDisabledRemoteEndLinkMaskCached = NV_TRUE;
}
// return NV_TRUE if the link is inside of disabledRemoteEndLinkMask
return ((BIT64(link->linkNumber) & chip_device->disabledRemoteEndLinkMask) != 0);
#else
return NV_FALSE;

40
src/common/nvswitch/kernel/lr10/lr10.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -3655,6 +3655,15 @@ nvswitch_initialize_device_state_lr10
goto nvswitch_initialize_device_state_exit;
}
retval = nvswitch_check_io_sanity(device);
if (NVL_SUCCESS != retval)
{
NVSWITCH_PRINT(device, ERROR,
"%s: IO sanity test failed\n",
__FUNCTION__);
goto nvswitch_initialize_device_state_exit;
}
NVSWITCH_PRINT(device, SETUP,
"%s: MMIO discovery\n",
__FUNCTION__);
@ -4579,15 +4588,6 @@ _nvswitch_get_info_revision_minor_ext
return (DRF_VAL(_PSMC, _BOOT_42, _MINOR_EXTENDED_REVISION, val));
}
static NvBool
_nvswitch_inforom_nvl_supported
(
nvswitch_device *device
)
{
return NV_FALSE;
}
static NvBool
_nvswitch_inforom_bbx_supported
(
@ -6370,6 +6370,15 @@ nvswitch_get_num_links_lr10
return num_links;
}
static NvU8
nvswitch_get_num_links_per_nvlipt_lr10
(
nvswitch_device *device
)
{
return NVSWITCH_LINKS_PER_NVLIPT;
}
NvBool
nvswitch_is_link_valid_lr10
(
@ -7647,7 +7656,7 @@ nvswitch_ctrl_get_sw_info_lr10
switch (p->index[i])
{
case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED:
p->info[i] = (NvU32)_nvswitch_inforom_nvl_supported(device);
p->info[i] = NV_TRUE;
break;
case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED:
p->info[i] = (NvU32)_nvswitch_inforom_bbx_supported(device);
@ -7830,6 +7839,15 @@ nvswitch_ctrl_get_nvlink_error_threshold_lr10
return -NVL_ERR_NOT_SUPPORTED;
}
NvlStatus
nvswitch_check_io_sanity_lr10
(
nvswitch_device *device
)
{
return NVL_SUCCESS;
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

769
src/common/nvswitch/kernel/ls10/inforom_ls10.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -30,6 +30,8 @@
#include "rmsoecmdif.h"
#include "flcn/flcn_nvswitch.h"
#include "rmflcncmdif_nvswitch.h"
#include "inforom/inforom_nvl_v3_nvswitch.h"
#include "inforom/inforom_nvl_v4_nvswitch.h"
NvlStatus
nvswitch_inforom_nvl_log_error_event_ls10
@ -40,7 +42,252 @@ nvswitch_inforom_nvl_log_error_event_ls10
NvBool *bDirty
)
{
return -NVL_ERR_NOT_IMPLEMENTED;
NvlStatus status;
INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s;
INFOROM_NVLINK_ERROR_EVENT *pErrorEvent = (INFOROM_NVLINK_ERROR_EVENT *)pNvlErrorEvent;
INFOROM_NVL_OBJECT_V3_ERROR_ENTRY *pErrorEntry;
NvU32 i;
NvU32 sec;
NvU8 header = 0;
NvU16 metadata = 0;
NvU8 errorSubtype;
NvU64 accumTotalCount;
INFOROM_NVL_ERROR_BLOCK_TYPE blockType;
if (pErrorEvent->nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n",
INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, pErrorEvent->nvliptInstance);
return -NVL_BAD_ARGS;
}
if (pErrorEvent->localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u internal links (internal link = %u requested)\n",
INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, pErrorEvent->localLinkIdx);
return -NVL_BAD_ARGS;
}
sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS);
status = inforom_nvl_v3_map_error(pErrorEvent->error, &header, &metadata,
&errorSubtype, &blockType);
if (status != NVL_SUCCESS)
{
return status;
}
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA,
_NVLIPT_INSTANCE_ID, pErrorEvent->nvliptInstance, metadata);
if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_DL)
{
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID,
NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_DL(pErrorEvent->localLinkIdx),
metadata);
}
else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_TLC)
{
metadata = FLD_SET_DRF_NUM(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA, _BLOCK_ID,
NV_INFOROM_NVL_OBJECT_V3_ERROR_METADATA_BLOCK_ID_TLC(pErrorEvent->localLinkIdx),
metadata);
}
else if (blockType == INFOROM_NVL_ERROR_BLOCK_TYPE_NVLIPT)
{
metadata = FLD_SET_DRF(_INFOROM_NVL_OBJECT_V3, _ERROR_METADATA,
_BLOCK_ID, _NVLIPT, metadata);
status = inforom_nvl_v3_encode_nvlipt_error_subtype(pErrorEvent->localLinkIdx,
&errorSubtype);
if (status != NVL_SUCCESS)
{
return status;
}
}
for (i = 0; i < INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES; i++)
{
pErrorEntry = &pNvlObject->errorLog[i];
if ((pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID) ||
((pErrorEntry->metadata == metadata) &&
(pErrorEntry->errorSubtype == errorSubtype)))
{
break;
}
}
if (i >= INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES)
{
NVSWITCH_PRINT(device, ERROR, "%s: NVL error log is full -- unable to log error\n",
__FUNCTION__);
return -NVL_ERR_INVALID_STATE;
}
if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_INVALID)
{
pErrorEntry->header = header;
pErrorEntry->metadata = metadata;
pErrorEntry->errorSubtype = errorSubtype;
}
if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_ACCUM)
{
accumTotalCount = NvU64_ALIGN32_VAL(&pErrorEntry->data.accum.totalCount);
if (accumTotalCount != NV_U64_MAX)
{
if (pErrorEvent->count > NV_U64_MAX - accumTotalCount)
{
accumTotalCount = NV_U64_MAX;
}
else
{
accumTotalCount += pErrorEvent->count;
}
NvU64_ALIGN32_PACK(&pErrorEntry->data.accum.totalCount, &accumTotalCount);
if (sec < pErrorEntry->data.accum.lastUpdated)
{
NVSWITCH_PRINT(device, ERROR,
"%s: System clock reporting earlier time than error timestamp\n",
__FUNCTION__);
}
pErrorEntry->data.accum.lastUpdated = sec;
*bDirty = NV_TRUE;
}
}
else if (pErrorEntry->header == INFOROM_NVL_ERROR_TYPE_COUNT)
{
if (pErrorEntry->data.event.totalCount != NV_U32_MAX)
{
pErrorEntry->data.event.totalCount++;
if (sec < pErrorEntry->data.event.lastError)
{
NVSWITCH_PRINT(device, ERROR,
"%s: System clock reporting earlier time than error timestamp\n",
__FUNCTION__);
}
else
{
pErrorEntry->data.event.avgEventDelta =
(pErrorEntry->data.event.avgEventDelta + sec -
pErrorEntry->data.event.lastError) >> 1;
}
pErrorEntry->data.event.lastError = sec;
*bDirty = NV_TRUE;
}
}
else
{
return -NVL_ERR_INVALID_STATE;
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_inforom_nvl_get_max_correctable_error_rate_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS *params
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
NvU8 linkID = params->linkId;
if (linkID >= NVSWITCH_NUM_LINKS_LS10)
{
return -NVL_BAD_ARGS;
}
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
nvswitch_os_memset(params, 0, sizeof(NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS));
params->linkId = linkID;
nvswitch_os_memcpy(&params->dailyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v4s.maxCorrectableErrorRates.dailyMaxCorrectableErrorRates[0][linkID],
sizeof(params->dailyMaxCorrectableErrorRates));
nvswitch_os_memcpy(&params->monthlyMaxCorrectableErrorRates, &pNvlinkState->pNvl->v4s.maxCorrectableErrorRates.monthlyMaxCorrectableErrorRates[0][linkID],
sizeof(params->monthlyMaxCorrectableErrorRates));
return NVL_SUCCESS;
}
NvlStatus
nvswitch_inforom_nvl_get_errors_ls10
(
nvswitch_device *device,
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS *params
)
{
struct inforom *pInforom = device->pInforom;
INFOROM_NVLINK_STATE *pNvlinkState;
NvU32 maxReadSize = sizeof(params->errorLog)/sizeof(NVSWITCH_NVLINK_ERROR_ENTRY);
NvU32 errorLeftCount = 0, errorReadCount = 0, errIndx = 0;
NvU32 errorStart = params->errorIndex;
if (pInforom == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState = pInforom->pNvlinkState;
if (pNvlinkState == NULL)
{
return -NVL_ERR_NOT_SUPPORTED;
}
if (errorStart >= INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES)
{
return -NVL_BAD_ARGS;
}
nvswitch_os_memset(params->errorLog, 0, sizeof(params->errorLog));
while (((errorStart + errorLeftCount) < INFOROM_NVL_OBJECT_V4S_NUM_ERROR_ENTRIES) &&
(pNvlinkState->pNvl->v4s.errorLog[errorStart + errorLeftCount].header != INFOROM_NVL_ERROR_TYPE_INVALID))
{
errorLeftCount++;
}
if (errorLeftCount > maxReadSize)
{
errorReadCount = maxReadSize;
}
else
{
errorReadCount = errorLeftCount;
}
params->errorIndex = errorStart + errorReadCount;
params->errorCount = errorReadCount;
if (errorReadCount > 0)
{
for (errIndx = 0; errIndx < errorReadCount; errIndx++)
{
if (inforom_nvl_v3_map_error_to_userspace_error(device,
&pNvlinkState->pNvl->v4s.errorLog[errorStart+errIndx],
&params->errorLog[errIndx]) != NVL_SUCCESS)
{
return -NVL_ERR_NOT_SUPPORTED;
}
}
}
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10
@ -55,7 +302,258 @@ NvlStatus nvswitch_inforom_nvl_update_link_correctable_error_info_ls10
NvBool *bDirty
)
{
return -NVL_ERR_NOT_IMPLEMENTED;
INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s;
INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE_V4S *pState =
&((INFOROM_NVL_CORRECTABLE_ERROR_RATE_STATE *)pData)->v4s;
INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *pErrorCounts =
(INFOROM_NVLINK_CORRECTABLE_ERROR_COUNTS *)pNvlErrorCounts;
NvU32 i;
NvU32 sec;
NvU32 day, month, currentEntryDay, currentEntryMonth;
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pErrorRate;
INFOROM_NVL_OBJECT_V3_CORRECTABLE_ERROR_RATE *pOldestErrorRate = NULL;
INFOROM_NVL_OBJECT_V4S_MAX_CORRECTABLE_ERROR_RATES *pCorrErrorRates;
NvBool bUpdated = NV_FALSE;
INFOROM_NVLINK_ERROR_EVENT errorEvent;
NvU32 currentFlitCrcRate;
NvU32 *pCurrentLaneCrcRates;
if (bDirty == NULL)
{
return -NVL_BAD_ARGS;
}
*bDirty = NV_FALSE;
if (linkId >= INFOROM_NVL_OBJECT_V4S_NUM_LINKS)
{
NVSWITCH_PRINT(device, ERROR,
"object does not store data for more than %u links (linkId = %u requested)\n",
INFOROM_NVL_OBJECT_V4S_NUM_LINKS, linkId);
return -NVL_BAD_ARGS;
}
if (nvliptInstance > INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u NVLIPTs (NVLIPT = %u requested)\n",
INFOROM_NVL_OBJECT_V3_NVLIPT_INSTANCE_MAX, nvliptInstance);
return -NVL_BAD_ARGS;
}
if (localLinkIdx > INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX)
{
NVSWITCH_PRINT(device, ERROR,
"object cannot log data for more than %u internal links (internal link = %u requested)\n",
INFOROM_NVL_OBJECT_V3_BLOCK_ID_MAX, localLinkIdx);
return -NVL_BAD_ARGS;
}
sec = (NvU32) (nvswitch_os_get_platform_time_epoch() / NVSWITCH_INTERVAL_1SEC_IN_NS);
inforom_nvl_v3_seconds_to_day_and_month(sec, &day, &month);
inforom_nvl_v4_update_correctable_error_rates(pState, linkId, pErrorCounts);
currentFlitCrcRate = pState->errorsPerMinute[linkId].flitCrc;
pCurrentLaneCrcRates = pState->errorsPerMinute[linkId].laneCrc;
pCorrErrorRates = &pNvlObject->maxCorrectableErrorRates;
for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->dailyMaxCorrectableErrorRates); i++)
{
pErrorRate = &pCorrErrorRates->dailyMaxCorrectableErrorRates[i][linkId];
inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, &currentEntryDay,
&currentEntryMonth);
if ((pErrorRate->lastUpdated == 0) || (currentEntryDay == day))
{
if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate,
currentFlitCrcRate,
pCurrentLaneCrcRates))
{
inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
pOldestErrorRate = NULL;
break;
}
else if ((pOldestErrorRate == NULL) ||
(pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated))
{
pOldestErrorRate = pErrorRate;
}
}
if (pOldestErrorRate != NULL)
{
inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
for (i = 0; i < NV_ARRAY_ELEMENTS(pCorrErrorRates->monthlyMaxCorrectableErrorRates); i++)
{
pErrorRate = &pCorrErrorRates->monthlyMaxCorrectableErrorRates[i][linkId];
inforom_nvl_v3_seconds_to_day_and_month(pErrorRate->lastUpdated, &currentEntryDay,
&currentEntryMonth);
if ((pErrorRate->lastUpdated == 0) || (currentEntryMonth == month))
{
if (inforom_nvl_v3_should_replace_error_rate_entry(pErrorRate,
currentFlitCrcRate,
pCurrentLaneCrcRates))
{
inforom_nvl_v3_update_error_rate_entry(pErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
pOldestErrorRate = NULL;
break;
}
else if ((pOldestErrorRate == NULL) ||
(pErrorRate->lastUpdated < pOldestErrorRate->lastUpdated))
{
pOldestErrorRate = pErrorRate;
}
}
if (pOldestErrorRate != NULL)
{
inforom_nvl_v3_update_error_rate_entry(pOldestErrorRate, sec,
currentFlitCrcRate,
pCurrentLaneCrcRates);
bUpdated = NV_TRUE;
}
*bDirty = bUpdated;
// Update aggregate error counts for each correctable error
errorEvent.nvliptInstance = nvliptInstance;
errorEvent.localLinkIdx = localLinkIdx;
if (pErrorCounts->flitCrc > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_RX_FLIT_CRC_CORR;
errorEvent.count = pErrorCounts->flitCrc;
nvswitch_inforom_nvl_log_error_event_ls10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->rxLinkReplay > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_RX_LINK_REPLAY_EVENTS_CORR;
errorEvent.count = pErrorCounts->rxLinkReplay;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_ls10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->txLinkReplay > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_TX_LINK_REPLAY_EVENTS_CORR;
errorEvent.count = pErrorCounts->txLinkReplay;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_ls10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
if (pErrorCounts->linkRecovery > 0)
{
errorEvent.error = INFOROM_NVLINK_DL_LINK_RECOVERY_EVENTS_CORR;
errorEvent.count = pErrorCounts->linkRecovery;
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_ls10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
for (i = 0; i < 4; i++)
{
if (pErrorCounts->laneCrc[i] == 0)
{
continue;
}
errorEvent.error = INFOROM_NVLINK_DL_RX_LANE0_CRC_CORR + i;
errorEvent.count = pErrorCounts->laneCrc[i];
bUpdated = NV_FALSE;
nvswitch_inforom_nvl_log_error_event_ls10(device,
pNvlGeneric, &errorEvent, &bUpdated);
*bDirty |= bUpdated;
}
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_setL1Threshold_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 word1,
NvU32 word2
)
{
INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s;
pNvlObject->l1ThresholdData.word1 = word1;
pNvlObject->l1ThresholdData.word2 = word2;
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_getL1Threshold_ls10
(
nvswitch_device *device,
void *pNvlGeneric,
NvU32 *word1,
NvU32 *word2
)
{
INFOROM_NVL_OBJECT_V4S *pNvlObject = &((PINFOROM_NVL_OBJECT)pNvlGeneric)->v4s;
*word1 = pNvlObject->l1ThresholdData.word1;
*word2 = pNvlObject->l1ThresholdData.word2;
return NVL_SUCCESS;
}
NvlStatus nvswitch_inforom_nvl_setup_nvlink_state_ls10
(
nvswitch_device *device,
INFOROM_NVLINK_STATE *pNvlinkState,
NvU8 version
)
{
if (version != 4)
{
NVSWITCH_PRINT(device, WARN, "NVL v%u not supported\n", version);
return -NVL_ERR_NOT_SUPPORTED;
}
pNvlinkState->pFmt = INFOROM_NVL_OBJECT_V4S_FMT;
pNvlinkState->pPackedObject = nvswitch_os_malloc(INFOROM_NVL_OBJECT_V4S_PACKED_SIZE);
if (pNvlinkState->pPackedObject == NULL)
{
return -NVL_NO_MEM;
}
pNvlinkState->pNvl = nvswitch_os_malloc(sizeof(INFOROM_NVL_OBJECT));
if (pNvlinkState->pNvl == NULL)
{
nvswitch_os_free(pNvlinkState->pPackedObject);
return -NVL_NO_MEM;
}
pNvlinkState->bDisableCorrectableErrorLogging = NV_FALSE;
return NVL_SUCCESS;
}
NvlStatus
@ -271,5 +769,268 @@ nvswitch_bbx_get_sxid_ls10
NVSWITCH_GET_SXIDS_PARAMS *params
)
{
return -NVL_ERR_NOT_SUPPORTED;
NvlStatus status;
void *pDmaBuf;
NvU64 dmaHandle;
FLCN *pFlcn;
RM_FLCN_CMD_SOE bbxCmd;
NvU32 cmdSeqDesc;
NVSWITCH_TIMEOUT timeout;
NvU32 transferSize;
RM_SOE_BBX_GET_SXID_DATA bbxSxidData;
NvU32 sxidIdx;
if (!nvswitch_is_inforom_supported_ls10(device))
{
NVSWITCH_PRINT(device, INFO, "%s: InfoROM is not supported\n", __FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
if (params == NULL)
{
return -NVL_BAD_ARGS;
}
transferSize = sizeof(bbxSxidData);
status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize,
(device->dma_addr_width == 32));
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status);
return status;
}
status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle,
transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_sxid_ls10_free_and_exit;
}
nvswitch_os_memset(pDmaBuf, 0, transferSize);
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
bbxCmd.hdr.size = sizeof(bbxCmd);
bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_SXID_GET;
bbxCmd.cmd.ifr.bbxSxidGet.sizeInBytes = transferSize;
RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxSxidGet.dmaHandle, &dmaHandle);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&bbxCmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: BBX cmd %d failed. rc:%d\n",
__FUNCTION__, bbxCmd.cmd.ifr.cmdType, status);
goto nvswitch_bbx_get_sxid_ls10_unmap_and_exit;
}
status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle,
transferSize,
NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_sxid_ls10_unmap_and_exit;
}
nvswitch_os_memcpy((NvU8 *)&bbxSxidData, (NvU8 *)pDmaBuf, sizeof(bbxSxidData));
// Copy out SXIDs
params->sxidCount = bbxSxidData.sxidCount;
for (sxidIdx = 0; sxidIdx < INFOROM_BBX_OBJ_XID_ENTRIES; sxidIdx++)
{
params->sxidFirst[sxidIdx].sxid = bbxSxidData.sxidFirst[sxidIdx].sxid;
params->sxidFirst[sxidIdx].timestamp = bbxSxidData.sxidFirst[sxidIdx].timestamp;
params->sxidLast[sxidIdx].sxid = bbxSxidData.sxidLast[sxidIdx].sxid;
params->sxidLast[sxidIdx].timestamp = bbxSxidData.sxidLast[sxidIdx].timestamp;
}
nvswitch_bbx_get_sxid_ls10_unmap_and_exit:
nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle,
transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM);
nvswitch_bbx_get_sxid_ls10_free_and_exit:
nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize);
return status;
}
NvlStatus
nvswitch_bbx_get_data_ls10
(
nvswitch_device *device,
NvU8 dataType,
void *params
)
{
NvlStatus status;
void *pDmaBuf;
NvU64 dmaHandle;
FLCN *pFlcn;
RM_FLCN_CMD_SOE bbxCmd;
NvU32 cmdSeqDesc;
NVSWITCH_TIMEOUT timeout;
NvU32 transferSize;
if (!nvswitch_is_inforom_supported_ls10(device))
{
NVSWITCH_PRINT(device, ERROR, "%s: InfoROM is not supported\n", __FUNCTION__);
return -NVL_ERR_NOT_SUPPORTED;
}
if (params == NULL)
{
NVSWITCH_PRINT(device, ERROR, "%s: params is NULL\n", __FUNCTION__);
return -NVL_BAD_ARGS;
}
switch (dataType)
{
case RM_SOE_IFR_BBX_GET_SYS_INFO:
transferSize = sizeof(NVSWITCH_GET_SYS_INFO_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TIME_INFO:
transferSize = sizeof(NVSWITCH_GET_TIME_INFO_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TEMP_DATA:
transferSize = sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS);
break;
case RM_SOE_IFR_BBX_GET_TEMP_SAMPLES:
transferSize = sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS);
break;
default:
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
return -NVL_BAD_ARGS;
break;
}
status = nvswitch_os_alloc_contig_memory(device->os_handle, &pDmaBuf, transferSize,
(device->dma_addr_width == 32));
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to allocate contig memory. rc:%d\n", __FUNCTION__, status);
return status;
}
status = nvswitch_os_map_dma_region(device->os_handle, pDmaBuf, &dmaHandle,
transferSize, NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to map DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_data_ls10_free_and_exit;
}
nvswitch_os_memset(pDmaBuf, 0, transferSize);
pFlcn = device->pSoe->pFlcn;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
nvswitch_os_memset(&bbxCmd, 0, sizeof(bbxCmd));
bbxCmd.hdr.unitId = RM_SOE_UNIT_IFR;
bbxCmd.hdr.size = sizeof(bbxCmd);
bbxCmd.cmd.ifr.cmdType = RM_SOE_IFR_BBX_DATA_GET;
bbxCmd.cmd.ifr.bbxDataGet.sizeInBytes = transferSize;
bbxCmd.cmd.ifr.bbxDataGet.dataType = dataType;
RM_FLCN_U64_PACK(&bbxCmd.cmd.ifr.bbxDataGet.dmaHandle, &dmaHandle);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&bbxCmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: BX_GET_DATA type=%d failed. rc:%d\n",
__FUNCTION__, dataType, status);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
status = nvswitch_os_sync_dma_region_for_cpu(device->os_handle, dmaHandle,
transferSize,
NVSWITCH_DMA_DIR_TO_SYSMEM);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to sync DMA region. rc:%d\n", __FUNCTION__, status);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
if (dataType == RM_SOE_IFR_BBX_GET_SYS_INFO)
{
NVSWITCH_GET_SYS_INFO_PARAMS bbxSysInfoData = {0};
nvswitch_os_memcpy((NvU8 *)&bbxSysInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxSysInfoData, sizeof(NVSWITCH_GET_SYS_INFO_PARAMS));
}
else if (dataType == RM_SOE_IFR_BBX_GET_TIME_INFO)
{
NVSWITCH_GET_TIME_INFO_PARAMS bbxTimeInfoData = {0};
nvswitch_os_memcpy((NvU8 *)&bbxTimeInfoData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)&bbxTimeInfoData, sizeof(NVSWITCH_GET_TIME_INFO_PARAMS));
}
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_DATA)
{
NVSWITCH_GET_TEMP_DATA_PARAMS *pBbxTempData = NULL;
pBbxTempData = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
if (pBbxTempData == NULL)
{
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
status = -NVL_NO_MEM;
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_os_memset(pBbxTempData, 0, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_memcpy((NvU8 *)pBbxTempData, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempData, sizeof(NVSWITCH_GET_TEMP_DATA_PARAMS));
nvswitch_os_free(pBbxTempData);
}
else if (dataType == RM_SOE_IFR_BBX_GET_TEMP_SAMPLES)
{
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *pBbxTempSamples = NULL;
pBbxTempSamples = nvswitch_os_malloc(sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
if (pBbxTempSamples == NULL)
{
NVSWITCH_PRINT(device, ERROR, "Out of memory: dataType %d", dataType);
status = -NVL_NO_MEM;
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_os_memset(pBbxTempSamples, 0, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_memcpy((NvU8 *)pBbxTempSamples, (NvU8 *)pDmaBuf, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_memcpy((NvU8 *)params, (NvU8 *)pBbxTempSamples, sizeof(NVSWITCH_GET_TEMP_SAMPLES_PARAMS));
nvswitch_os_free(pBbxTempSamples);
}
else
{
NVSWITCH_PRINT(device, ERROR, "Unknown dataType %d", dataType);
goto nvswitch_bbx_get_data_ls10_unmap_and_exit;
}
nvswitch_bbx_get_data_ls10_unmap_and_exit:
nvswitch_os_unmap_dma_region(device->os_handle, pDmaBuf, dmaHandle,
transferSize, NVSWITCH_DMA_DIR_FROM_SYSMEM);
nvswitch_bbx_get_data_ls10_free_and_exit:
nvswitch_os_free_contig_memory(device->os_handle, pDmaBuf, transferSize);
return status;
}

523
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

File diff suppressed because it is too large Load Diff

162
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@ -98,6 +98,30 @@ _nvswitch_configure_reserved_throughput_counters
DRF_DEF(_NVLTLC_TX_LNK, _DEBUG_TP_CNTR_CTRL_0, _ENABLE, _ENABLE));
}
void
nvswitch_program_l1_scratch_reg_ls10
(
nvswitch_device *device,
NvU32 linkNumber
)
{
NvU32 scrRegVal;
NvU32 tempRegVal;
// Read L1 register and store initial/VBIOS L1 Threshold Value in Scratch register
tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD);
scrRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM);
// Update the scratch register value only if it has not been written to before
if (scrRegVal == NV_NVLIPT_LNK_SCRATCH_WARM_DATA_INIT)
{
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _SCRATCH_WARM, tempRegVal);
}
}
#define BUG_3797211_LS10_VBIOS_VERSION 0x9610410000
void
nvswitch_init_lpwr_regs_ls10
(
@ -110,42 +134,64 @@ nvswitch_init_lpwr_regs_ls10
NvU32 tempRegVal, lpEntryThreshold;
NvU8 softwareDesired;
NvBool bLpEnable;
NvU64 biosVersion;
if (device->regkeys.enable_pm == NV_SWITCH_REGKEY_ENABLE_PM_NO)
{
return;
}
// bios_config = nvswitch_get_bios_nvlink_config(device);
// IC Enter Threshold
if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT)
if (nvswitch_lib_get_bios_version(device, &biosVersion) != NVL_SUCCESS)
{
//
// TODO: get from bios. Refer Bug 3626523 for more info.
//
// The threshold is measured in 100us unit. So lpEntryThreshold = 1
// means the threshold is set to 100us in the register.
//
lpEntryThreshold = 1;
NVSWITCH_PRINT(device, WARN, "%s Get VBIOS version failed.\n",
__FUNCTION__);
biosVersion = 0;
}
// bios_config = nvswitch_get_bios_nvlink_config(device);
if (biosVersion >= BUG_3797211_LS10_VBIOS_VERSION)
{
// IC Enter Threshold
if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT)
{
//
// Do nothing since VBIOS (version 96.10.41.00.00 and above)
// sets the default L1 threshold.
// Refer Bug 3797211 for more info.
//
}
else
{
lpEntryThreshold = device->regkeys.lp_threshold;
tempRegVal = 0;
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal);
}
}
else
{
lpEntryThreshold = device->regkeys.lp_threshold;
}
// IC Enter Threshold
if (device->regkeys.lp_threshold == NV_SWITCH_REGKEY_SET_LP_THRESHOLD_DEFAULT)
{
lpEntryThreshold = 1;
}
else
{
lpEntryThreshold = device->regkeys.lp_threshold;
}
tempRegVal = 0;
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal);
tempRegVal = 0;
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_L1_ENTER_THRESHOLD, _THRESHOLD, lpEntryThreshold, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_L1_ENTER_THRESHOLD, tempRegVal);
}
//LP Entry Enable
bLpEnable = NV_TRUE;
softwareDesired = (bLpEnable) ? 0x1 : 0x0;
// TO-DO: The write to the AN1 register is not working. The logic here needs to be re-visited.
tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL);
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L1_ENABLE, softwareDesired, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, tempRegVal);
tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL);
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_CTRL, _L1_SOFTWARE_DESIRED, softwareDesired, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL, tempRegVal);
}
void
@ -1402,7 +1448,7 @@ nvswitch_load_link_disable_settings_ls10
nvswitch_device *device,
nvlink_link *link
)
{
{
NvU32 regVal;
// Read state from NVLIPT HW
@ -1411,7 +1457,7 @@ nvswitch_load_link_disable_settings_ls10
if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal))
{
// Set link to invalid and unregister from corelib
device->link[link->linkNumber].valid = NV_FALSE;
nvlink_lib_unregister_link(link);
@ -1452,7 +1498,7 @@ nvswitch_execute_unilateral_link_shutdown_ls10
// Status is explicitly ignored here since we are required to soldier-on
// in this scenario
//
status = nvswitch_request_tl_link_state_lr10(link,
status = nvswitch_request_tl_link_state_ls10(link,
NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN, NV_TRUE);
if (status == NVL_SUCCESS)
@ -1625,6 +1671,76 @@ nvswitch_are_link_clocks_on_ls10
return NV_TRUE;
}
NvlStatus
nvswitch_request_tl_link_state_ls10
(
nvlink_link *link,
NvU32 tlLinkState,
NvBool bSync
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvlStatus status = NVL_SUCCESS;
NvU32 linkStatus;
NvU32 lnkErrStatus;
NvU32 bit;
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,
"%s: link #%d invalid\n",
__FUNCTION__, link->linkNumber);
return -NVL_UNBOUND_DEVICE;
}
// Wait for the TL link state register to report ready
status = nvswitch_wait_for_tl_request_ready_lr10(link);
if (status != NVL_SUCCESS)
{
return status;
}
// Clear any pending FAILEDMINIONREQUEST status that maybe populated as it is stale now
bit = DRF_NUM(_NVLIPT_LNK, _ERR_STATUS_0, _FAILEDMINIONREQUEST, 1);
lnkErrStatus = NVSWITCH_LINK_RD32(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0);
if (nvswitch_test_flags(lnkErrStatus, bit))
{
NVSWITCH_LINK_WR32(device, link->linkNumber, NVLIPT_LNK, _NVLIPT_LNK, _ERR_STATUS_0,
bit);
}
// Request state through CTRL_LINK_STATE_REQUEST
NVSWITCH_LINK_WR32_LS10(device, link->linkNumber,
NVLIPT_LNK, _NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST,
DRF_NUM(_NVLIPT_LNK, _CTRL_LINK_STATE_REQUEST, _REQUEST, tlLinkState));
if (bSync)
{
// Wait for the TL link state register to complete
status = nvswitch_wait_for_tl_request_ready_lr10(link);
if (status != NVL_SUCCESS)
{
return status;
}
// Check for state requested
linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber,
NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS);
if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) !=
tlLinkState)
{
NVSWITCH_PRINT(device, ERROR,
"%s: TL link state request to state 0x%x for link #%d did not complete!\n",
__FUNCTION__, tlLinkState, link->linkNumber);
return -NVL_ERR_GENERIC;
}
}
return status;
}
NvBool
nvswitch_does_link_need_termination_enabled_ls10
(

191
src/common/nvswitch/kernel/ls10/ls10.c
View File

@ -41,6 +41,7 @@
#include "ls10/gfw_ls10.h"
#include "nvswitch/ls10/dev_nvs_top.h"
#include "nvswitch/ls10/ptop_discovery_ip.h"
#include "nvswitch/ls10/dev_pri_masterstation_ip.h"
#include "nvswitch/ls10/dev_pri_hub_sys_ip.h"
#include "nvswitch/ls10/dev_nvlw_ip.h"
@ -914,7 +915,7 @@ nvswitch_ctrl_get_sw_info_ls10
switch (p->index[i])
{
case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_NVL_SUPPORTED:
p->info[i] = NV_FALSE; //TODO: Enable once NVL support is present (CTK-4163)
p->info[i] = NV_TRUE;
break;
case NVSWITCH_GET_SW_INFO_INDEX_INFOROM_BBX_SUPPORTED:
p->info[i] = NV_TRUE;
@ -1350,7 +1351,53 @@ nvswitch_init_warm_reset_ls10
)
{
NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
}
}
//
// Helper funcction to query MINION to see if DL clocks are on
// return NV_TRUE if the clocks are on
// NV_FALSE if the clocks are off
static
NvBool
_nvswitch_are_dl_clocks_on
(
nvswitch_device *device,
NvU32 linkNumber
)
{
NvU32 link_state;
NvU32 stat_data;
NvlStatus status = NVL_SUCCESS;
nvlink_link * link= nvswitch_get_link(device, linkNumber);
if (link == NULL)
{
NVSWITCH_PRINT(device, ERROR, "%s: invalid link %d\n",
__FUNCTION__, linkNumber);
return NV_FALSE;
}
status = nvswitch_minion_get_dl_status(device, linkNumber,
NV_NVLSTAT_UC01, 0, &stat_data);
if (status != NVL_SUCCESS)
{
return NV_FALSE;
}
link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data);
switch(link_state)
{
case LINKSTATUS_RESET:
case LINKSTATUS_UNINIT:
return NV_FALSE;
case LINKSTATUS_LANESHUTDOWN:
case LINKSTATUS_ACTIVE_PENDING:
return nvswitch_are_link_clocks_on_ls10(device, link,
NVSWITCH_PER_LINK_CLOCK_SET(RXCLK) | NVSWITCH_PER_LINK_CLOCK_SET(TXCLK));
}
return NV_TRUE;
}
//
// Implement reset and drain sequence for ls10
@ -1582,10 +1629,10 @@ nvswitch_reset_and_drain_links_ls10
nvswitch_soe_restore_nport_state_ls10(device, link);
// Step 7.0 : Re-program the routing table for DBEs
// Step 8.0 : Reset NVLW and NPORT interrupt state
_nvswitch_link_reset_interrupts_ls10(device, link);
// Re-register links.
status = nvlink_lib_register_link(device->nvlink_device, link_info);
if (status != NVL_SUCCESS)
@ -1621,21 +1668,9 @@ nvswitch_reset_and_drain_links_ls10
do
{
bKeepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
bAreDlClocksOn = _nvswitch_are_dl_clocks_on(device, link);
status = nvswitch_minion_get_dl_status(device, link_info->linkNumber,
NV_NVLSTAT_UC01, 0, &stat_data);
if (status != NVL_SUCCESS)
{
continue;
}
link_state = DRF_VAL(_NVLSTAT, _UC01, _LINK_STATE, stat_data);
bAreDlClocksOn = (link_state != LINKSTATUS_INITPHASE1) ?
NV_TRUE:NV_FALSE;
if (bAreDlClocksOn == NV_TRUE)
if (bAreDlClocksOn)
{
break;
}
@ -2740,6 +2775,15 @@ nvswitch_get_num_links_ls10
return NVSWITCH_NUM_LINKS_LS10;
}
static NvU8
nvswitch_get_num_links_per_nvlipt_ls10
(
nvswitch_device *device
)
{
return NVSWITCH_LINKS_PER_NVLIPT_LS10;
}
NvlStatus
nvswitch_ctrl_get_fom_values_ls10
(
@ -3039,8 +3083,17 @@ NvlStatus nvswitch_get_link_public_id_ls10
NvU32 *publicId
)
{
NVSWITCH_PRINT(device, WARN, "%s: Function not implemented\n", __FUNCTION__);
return -NVL_ERR_NOT_IMPLEMENTED;
if (!device->hal.nvswitch_is_link_valid(device, linkId) ||
(publicId == NULL))
{
return -NVL_BAD_ARGS;
}
*publicId = NVSWITCH_NVLIPT_GET_PUBLIC_ID_LS10(linkId);
return (NVSWITCH_ENG_VALID_LS10(device, NVLIPT, *publicId)) ?
NVL_SUCCESS : -NVL_BAD_ARGS;
}
/*
@ -5744,6 +5797,104 @@ nvswitch_ctrl_get_nvlink_error_threshold_ls10
return NVL_SUCCESS;
}
NvlStatus
nvswitch_check_io_sanity_ls10
(
nvswitch_device *device
)
{
NvBool keepPolling;
NVSWITCH_TIMEOUT timeout;
NvU32 val;
NvBool error = NV_FALSE;
NvU32 sxid;
const char *sxid_desc = NULL;
//
// NOTE: MMIO discovery has not been performed so only constant BAR0 offset
// addressing can be performed.
//
// BAR0 offset 0 should always contain valid data -- unless it doesn't
val = NVSWITCH_OFF_RD32(device, 0);
if (val == 0)
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE;
sxid_desc = "Firmware recovery mode";
}
else if ((val == 0xFFFFFFFF) || ((val & 0xFFFF0000) == 0xBADF0000))
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_IO_FAILURE;
sxid_desc = "IO failure";
}
else if (!IS_FMODEL(device))
{
// check if FSP successfully started
nvswitch_timeout_create(10 * NVSWITCH_INTERVAL_1SEC_IN_NS, &timeout);
do
{
keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
if (FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
{
break;
}
nvswitch_os_sleep(1);
}
while (keepPolling);
if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, val))
{
error = NV_TRUE;
sxid = NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE;
sxid_desc = "Firmware initialization failure";
}
}
if (error)
{
NVSWITCH_RAW_ERROR_LOG_TYPE report = { 0, { 0 } };
NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
NvU32 report_idx = 0;
NvU32 i;
val = NVSWITCH_REG_RD32(device, _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS);
report.data[report_idx++] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
__FUNCTION__, val);
for (i = 0; i <= 15; i++)
{
val = NVSWITCH_OFF_RD32(device,
NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 + NV_NVLSAW_SW_SCRATCH(i));
report_saw.data[i] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
__FUNCTION__, i, val);
}
for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
{
val = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
report.data[report_idx++] = val;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
__FUNCTION__, i, val);
}
// Include useful scratch information for triage
NVSWITCH_PRINT_SXID_NO_BBX(device, sxid,
"Fatal, %s (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", sxid_desc,
report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
return -NVL_INITIALIZATION_TOTAL_FAILURE;
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_read_vbios_link_entries_ls10
(

91
src/common/nvswitch/kernel/nvswitch.c
View File

@ -30,6 +30,7 @@
#include "flcn/haldefs_flcnable_nvswitch.h"
#include "flcn/flcn_nvswitch.h"
#include "soe/soe_nvswitch.h"
#include "soe/soeififr.h"
#include "nvVer.h"
#include "nvlink_inband_msg.h"
@ -1511,10 +1512,17 @@ nvswitch_lib_initialize_device
nvswitch_reset_and_train_link(device, link);
}
//
// During Nvswitch initialization, the default L1 thresholds are programmed by the
// BIOS from the BIOS tables. Save these L1 Threshold Values in scratch registers
// for use when resetting the thresholds to default.
//
nvswitch_program_l1_scratch_reg(device, link_num);
//
// WAR : Initializing the L1 threshold registers at this point as a WAR for
// Bug 3963639 where is it was discussed that the L1 threshold register should have
// value the default value for all available links and not just for active links.
// Bug 3963639 where it was discussed that the L1 threshold register should have
// the default value for all available links and not just for active links.
//
nvswitch_init_lpwr_regs(link);
}
@ -3429,6 +3437,46 @@ _nvswitch_ctrl_get_inforom_bbx_sxid
return nvswitch_inforom_bbx_get_sxid(device, params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_sys_info
(
nvswitch_device *device,
NVSWITCH_GET_SYS_INFO_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_SYS_INFO, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_time_info
(
nvswitch_device *device,
NVSWITCH_GET_TIME_INFO_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TIME_INFO, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_temp_data
(
nvswitch_device *device,
NVSWITCH_GET_TEMP_DATA_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_DATA, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_inforom_bbx_temp_samples
(
nvswitch_device *device,
NVSWITCH_GET_TEMP_SAMPLES_PARAMS *params
)
{
return nvswitch_inforom_bbx_get_data(device, RM_SOE_IFR_BBX_GET_TEMP_SAMPLES, (void *)params);
}
static NvlStatus
_nvswitch_ctrl_get_nvlink_lp_counters
(
@ -4610,6 +4658,25 @@ nvswitch_init_lpwr_regs
device->hal.nvswitch_init_lpwr_regs(link);
}
void
nvswitch_program_l1_scratch_reg
(
nvswitch_device *device,
NvU32 linkNumber
)
{
device->hal.nvswitch_program_l1_scratch_reg(device, linkNumber);
}
NvlStatus
nvswitch_check_io_sanity
(
nvswitch_device *device
)
{
return device->hal.nvswitch_check_io_sanity(device);
}
NvlStatus
nvswitch_launch_ALI
(
@ -5123,6 +5190,26 @@ nvswitch_lib_ctrl
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_POWER,
_nvswitch_ctrl_therm_read_power,
NVSWITCH_GET_POWER_PARAMS);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SYS_INFO,
_nvswitch_ctrl_get_inforom_bbx_sys_info,
NVSWITCH_GET_SYS_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TIME_INFO,
_nvswitch_ctrl_get_inforom_bbx_time_info,
NVSWITCH_GET_TIME_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_DATA,
_nvswitch_ctrl_get_inforom_bbx_temp_data,
NVSWITCH_GET_TEMP_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_SAMPLES,
_nvswitch_ctrl_get_inforom_bbx_temp_samples,
NVSWITCH_GET_TEMP_SAMPLES_PARAMS,
osPrivate, flags);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "unknown ioctl %x\n", cmd);

3
src/common/sdk/nvidia/inc/class/cl2080_notification.h
View File

@ -201,7 +201,8 @@ extern "C" {
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (177)
#define NV2080_NOTIFIERS_MAXCOUNT (178)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (178)
#define NV2080_NOTIFIERS_MAXCOUNT (179)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))

53
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
View File

@ -208,11 +208,11 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
* guestMSIData
* This parameter indicates the MSI data set by the guest OS.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
* vgpuUuid
* This parameter specifies the uuid of vGPU assigned to VM.
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
* domainId
* This parameter specifies the unique guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
@ -225,11 +225,11 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMAPHORE_MEMORY_PARAMS {
typedef struct NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS {
NV_DECLARE_ALIGNED(NvU64 guestMSIAddr, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
NvU32 guestMSIData;
NvHandle hSemMemory;
NvBool isReset;
NvU8 vgpuUuid[VM_UUID_SIZE];
NV_DECLARE_ALIGNED(NvU64 domainId, 8);
} NV2080_CTRL_EVENT_SET_GUEST_MSI_PARAMS;
@ -266,41 +266,6 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
NvBool isSemaMemValidationEnabled;
} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
NvHandle hSemMemory;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
*

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@ -837,6 +837,7 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
/*
* NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES

1
src/common/sdk/nvidia/inc/nv-hypervisor.h
View File

@ -57,6 +57,7 @@ typedef struct
void *waitQueue;
void *nv;
NvU32 *vgpuTypeIds;
NvU8 **vgpuNames;
NvU32 numVgpuTypes;
NvU32 domain;
NvU8 bus;

4
src/common/sdk/nvidia/inc/nverror.h
View File

@ -118,7 +118,9 @@
#define SPI_PMU_RPC_ERASE_FAIL (124)
#define INFOROM_FS_ERROR (125)
#define ALI_TRAINING_FAIL (136)
#define ROBUST_CHANNEL_LAST_ERROR (ALI_TRAINING_FAIL)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define GPU_INIT_ERROR (143)
#define ROBUST_CHANNEL_LAST_ERROR (GPU_INIT_ERROR)

3
src/common/unix/nvidia-3d/src/nvidia-3d-surface.c
View File

@ -189,6 +189,9 @@ NvBool nv3dAllocChannelSurface(Nv3dChannelPtr p3dChannel)
void nv3dFreeChannelSurface(Nv3dChannelPtr p3dChannel)
{
if (p3dChannel->p3dDevice == NULL) {
return;
}
if (p3dChannel->surface.gpuAddress != 0) {
/*

6
src/nvidia-modeset/include/nvkms-types.h
View File

@ -1328,6 +1328,12 @@ typedef struct _NVHwModeTimingsEvo {
} stereo;
} NVHwModeTimingsEvo;
static inline NvBool nvIsAdaptiveSyncDpyVrrType(enum NvKmsDpyVRRType type)
{
return ((type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_DEFAULTLISTED) ||
(type == NVKMS_DPY_VRR_TYPE_ADAPTIVE_SYNC_NON_DEFAULTLISTED));
}
static inline NvU64 nvEvoFrametimeUsFromTimings(const NVHwModeTimingsEvo *pTimings)
{
NvU64 pixelsPerFrame = pTimings->rasterSize.x * pTimings->rasterSize.y;

2
src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
View File

@ -112,6 +112,8 @@ typedef struct {
NvBool nvkms_output_rounding_fix(void);
NvBool nvkms_disable_vrr_memclk_switch(void);
void nvkms_call_rm (void *ops);
void* nvkms_alloc (size_t size,
NvBool zero);

27
src/nvidia-modeset/src/dp/nvdp-connector.cpp
View File

@ -267,6 +267,10 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_PARAMS *msaParams,
const NVHwModeTimingsEvo *pTimings)
{
NV0073_CTRL_DP_MSA_PROPERTIES_MASK *featureMask = &msaParams->featureMask;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *featureValues =
&msaParams->featureValues;
nvkms_memset(msaParams, 0, sizeof(*msaParams));
/*
@ -279,12 +283,16 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
msaParams->subDeviceInstance = pDispEvo->displayOwner;
msaParams->displayId = displayId;
if ((pTimings->yuv420Mode == NV_YUV420_MODE_SW) && displayId != 0) {
NV0073_CTRL_DP_MSA_PROPERTIES_MASK *featureMask = &msaParams->featureMask;
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES *featureValues = &msaParams->featureValues;
if ((displayId == 0x0) ||
((pTimings->yuv420Mode != NV_YUV420_MODE_SW) &&
!nvIsAdaptiveSyncDpyVrrType(pTimings->vrr.type))) {
return;
}
msaParams->bEnableMSA = 1;
msaParams->bCacheMsaOverrideForNextModeset = 1;
msaParams->bEnableMSA = 1;
msaParams->bCacheMsaOverrideForNextModeset = 1;
if (pTimings->yuv420Mode == NV_YUV420_MODE_SW) {
featureMask->bRasterTotalHorizontal = true;
featureMask->bActiveStartHorizontal = true;
featureMask->bSurfaceTotalHorizontal = true;
@ -294,6 +302,15 @@ static void SetDPMSATiming(const NVDispEvoRec *pDispEvo,
featureValues->surfaceTotalHorizontal = 2 * nvEvoVisibleWidth(pTimings);
featureValues->syncWidthHorizontal = 2 * (pTimings->rasterSyncEnd.x + 1);
}
/*
* In case of Adaptive-Sync VRR, override VTotal field of MSA (Main Stream
* Attributes) to workaround bug 4164132.
*/
if (nvIsAdaptiveSyncDpyVrrType(pTimings->vrr.type)) {
featureMask->bRasterTotalVertical = true;
featureValues->rasterTotalVertical = pTimings->rasterSize.y;
}
}
static void InitDpModesetParams(

2
src/nvidia-modeset/src/nvkms-evo.c
View File

@ -5486,6 +5486,8 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo,
} else {
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444;
}
} else {
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444;
}
} else {
/* TMDS default */

3
src/nvidia/arch/nvalloc/common/inc/flcnretval.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -262,6 +262,7 @@ typedef NvU8 FLCN_STATUS;
// Warnings.
#define FLCN_WARN_NOTHING_TO_DO (0xD0U)
#define FLCN_WARN_NOT_QUERIED (0xD1U)
#define FLCN_WARN_DATA_NOT_AVAILABLE (0xD2U)
// Queue handling Errors
#define FLCN_ERR_QUEUE_MGMT_INVALID_UNIT_ID (0xE0U)

1271
src/nvidia/arch/nvalloc/common/inc/inforom/ifrnvl.h Normal file
View File

File diff suppressed because it is too large Load Diff

3
src/nvidia/arch/nvalloc/common/inc/inforom/ifrstruct.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@ -26,6 +26,7 @@
#include "inforom/types.h"
#include "inforom/ifrnvl.h"
#include "inforom/ifrecc.h"
#include "inforom/ifrdem.h"
#include "inforom/omsdef.h"

40
src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
View File

@ -225,7 +225,6 @@ NV_STATUS NV_API_CALL nv_vgpu_get_type_info(
{
THREAD_STATE_NODE threadState;
OBJSYS *pSys = SYS_GET_INSTANCE();
OBJGPU *pGpu = NULL;
KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys);
NV_STATUS rmStatus = NV_OK;
VGPU_TYPE *vgpuTypeInfo;
@ -238,14 +237,6 @@ NV_STATUS NV_API_CALL nv_vgpu_get_type_info(
// LOCK: acquire API lock
if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_HYPERVISOR)) == NV_OK)
{
pGpu = NV_GET_NV_PRIV_PGPU(pNv);
if (pGpu == NULL)
{
NV_PRINTF(LEVEL_ERROR, "%s GPU handle is not valid \n", __FUNCTION__);
rmStatus = NV_ERR_INVALID_STATE;
goto exit;
}
if ((rmStatus = kvgpumgrGetPgpuIndex(pKernelVgpuMgr, pNv->gpu_id, &pgpuIndex)) ==
NV_OK)
{
@ -912,7 +903,7 @@ NV_STATUS osVgpuRegisterMdev
)
{
NV_STATUS status = NV_OK;
vgpu_vfio_info vgpu_info;
vgpu_vfio_info vgpu_info = {0};
OBJSYS *pSys = SYS_GET_INSTANCE();
KernelVgpuMgr *pKernelVgpuMgr = SYS_GET_KERNEL_VGPUMGR(pSys);
KERNEL_PHYS_GPU_INFO *pPhysGpuInfo;
@ -930,12 +921,22 @@ NV_STATUS osVgpuRegisterMdev
status = os_alloc_mem((void **)&vgpu_info.vgpuTypeIds,
((vgpu_info.numVgpuTypes) * sizeof(NvU32)));
if (status != NV_OK)
return status;
goto free_mem;
status = os_alloc_mem((void **)&vgpu_info.vgpuNames,
((vgpu_info.numVgpuTypes) * sizeof(char *)));
if (status != NV_OK)
goto free_mem;
vgpu_info.nv = pOsGpuInfo;
for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++)
{
status = os_alloc_mem((void *)&vgpu_info.vgpuNames[i], (VGPU_STRING_BUFFER_SIZE * sizeof(char)));
if (status != NV_OK)
goto free_mem;
vgpu_info.vgpuTypeIds[i] = pPhysGpuInfo->vgpuTypes[i]->vgpuTypeId;
os_snprintf((char *) vgpu_info.vgpuNames[i], VGPU_STRING_BUFFER_SIZE, "%s\n", pPhysGpuInfo->vgpuTypes[i]->vgpuName);
}
if ((!pPhysGpuInfo->sriovEnabled) ||
@ -965,7 +966,22 @@ NV_STATUS osVgpuRegisterMdev
}
}
os_free_mem(vgpu_info.vgpuTypeIds);
free_mem:
if (vgpu_info.vgpuTypeIds)
os_free_mem(vgpu_info.vgpuTypeIds);
if (vgpu_info.vgpuNames)
{
for (i = 0; i < pPhysGpuInfo->numVgpuTypes; i++)
{
if (vgpu_info.vgpuNames[i])
{
os_free_mem(vgpu_info.vgpuNames[i]);
}
}
os_free_mem(vgpu_info.vgpuNames);
}
return status;
}

5
src/nvidia/arch/nvalloc/unix/src/osapi.c
View File

@ -337,6 +337,11 @@ RmLogGpuCrash(OBJGPU *pGpu)
"NVRM: A GPU crash dump has been created. If possible, please run\n"
"NVRM: nvidia-bug-report.sh as root to collect this data before\n"
"NVRM: the NVIDIA kernel module is unloaded.\n");
if (hypervisorIsVgxHyper())
{
nv_printf(NV_DBG_ERRORS, "NVRM: Dumping nvlogs buffers\n");
nvlogDumpToKernelLog(NV_FALSE);
}
}
// Restore the disconnected properties, if they were reset

24
src/nvidia/generated/g_client_resource_nvoc.c
View File

@ -313,12 +313,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
#endif
},
{ /* [8] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCaps_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
/*flags=*/ 0x811u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*flags=*/ 0x810u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x127u,
/*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS),
@ -328,12 +328,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
#endif
},
{ /* [9] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsV2_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
/*flags=*/ 0x811u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*flags=*/ 0x810u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x12bu,
/*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS),
@ -478,12 +478,12 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_RmClient
#endif
},
{ /* [19] */
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*pFunc=*/ (void (*)(void)) NULL,
#else
/*pFunc=*/ (void (*)(void)) cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
/*flags=*/ 0x11u,
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
/*flags=*/ 0x810u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x13au,
/*paramSize=*/ sizeof(NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS),
@ -1556,15 +1556,15 @@ static void __nvoc_init_funcTable_RmClientResource_1(RmClientResource *pThis) {
pThis->__cliresCtrlCmdSystemGetHwbcInfo__ = &cliresCtrlCmdSystemGetHwbcInfo_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
pThis->__cliresCtrlCmdSystemGetP2pCaps__ = &cliresCtrlCmdSystemGetP2pCaps_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x811u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
pThis->__cliresCtrlCmdSystemGetP2pCapsV2__ = &cliresCtrlCmdSystemGetP2pCapsV2_IMPL;
#endif
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x11u)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x810u)
pThis->__cliresCtrlCmdSystemGetP2pCapsMatrix__ = &cliresCtrlCmdSystemGetP2pCapsMatrix_IMPL;
#endif

11
src/nvidia/generated/g_gpu_nvoc.c
View File

@ -427,6 +427,17 @@ static void __nvoc_init_funcTable_OBJGPU_1(OBJGPU *pThis) {
pThis->__gpuWriteFunctionConfigRegEx__ = &gpuWriteFunctionConfigRegEx_5baef9;
}
// Hal function -- gpuReadVgpuConfigReg
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_GH100;
}
// default
else
{
pThis->__gpuReadVgpuConfigReg__ = &gpuReadVgpuConfigReg_46f6a7;
}
// Hal function -- gpuGetIdInfo
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0ffe0UL) )) /* ChipHal: TU102 | TU104 | TU106 | TU116 | TU117 | GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{

29
src/nvidia/generated/g_gpu_nvoc.h
View File

@ -823,6 +823,7 @@ struct OBJGPU {
NV_STATUS (*__gpuReadFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32 *);
NV_STATUS (*__gpuWriteFunctionConfigReg__)(struct OBJGPU *, NvU32, NvU32, NvU32);
NV_STATUS (*__gpuWriteFunctionConfigRegEx__)(struct OBJGPU *, NvU32, NvU32, NvU32, THREAD_STATE_NODE *);
NV_STATUS (*__gpuReadVgpuConfigReg__)(struct OBJGPU *, NvU32, NvU32 *);
void (*__gpuGetIdInfo__)(struct OBJGPU *);
void (*__gpuHandleSanityCheckRegReadError__)(struct OBJGPU *, NvU32, NvU32);
void (*__gpuHandleSecFault__)(struct OBJGPU *);
@ -934,6 +935,9 @@ struct OBJGPU {
NvU32 subdeviceInstance;
NvS32 numaNodeId;
_GPU_UUID gpuUuid;
NvU32 gpuPhysicalId;
NvU32 gpuTerminatedLinkMask;
NvBool gpuLinkTerminationEnabled;
_GPU_PCIE_PEER_CLIQUE pciePeerClique;
NvU32 i2cPortForExtdev;
GPUIDINFO idInfo;
@ -1316,6 +1320,8 @@ NV_STATUS __nvoc_objCreate_OBJGPU(OBJGPU**, Dynamic*, NvU32,
#define gpuWriteFunctionConfigReg_HAL(pGpu, function, reg, data) gpuWriteFunctionConfigReg_DISPATCH(pGpu, function, reg, data)
#define gpuWriteFunctionConfigRegEx(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState)
#define gpuWriteFunctionConfigRegEx_HAL(pGpu, function, reg, data, pThreadState) gpuWriteFunctionConfigRegEx_DISPATCH(pGpu, function, reg, data, pThreadState)
#define gpuReadVgpuConfigReg(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data)
#define gpuReadVgpuConfigReg_HAL(pGpu, index, data) gpuReadVgpuConfigReg_DISPATCH(pGpu, index, data)
#define gpuGetIdInfo(pGpu) gpuGetIdInfo_DISPATCH(pGpu)
#define gpuGetIdInfo_HAL(pGpu) gpuGetIdInfo_DISPATCH(pGpu)
#define gpuHandleSanityCheckRegReadError(pGpu, addr, value) gpuHandleSanityCheckRegReadError_DISPATCH(pGpu, addr, value)
@ -2157,6 +2163,19 @@ static inline void gpuDestroyDefaultClientShare(struct OBJGPU *pGpu) {
#define gpuDestroyDefaultClientShare_HAL(pGpu) gpuDestroyDefaultClientShare(pGpu)
void gpuGetTerminatedLinkMask_GA100(struct OBJGPU *pGpu, NvU32 arg0);
#ifdef __nvoc_gpu_h_disabled
static inline void gpuGetTerminatedLinkMask(struct OBJGPU *pGpu, NvU32 arg0) {
NV_ASSERT_FAILED_PRECOMP("OBJGPU was disabled!");
}
#else //__nvoc_gpu_h_disabled
#define gpuGetTerminatedLinkMask(pGpu, arg0) gpuGetTerminatedLinkMask_GA100(pGpu, arg0)
#endif //__nvoc_gpu_h_disabled
#define gpuGetTerminatedLinkMask_HAL(pGpu, arg0) gpuGetTerminatedLinkMask(pGpu, arg0)
NvU32 gpuGetActiveFBIOs_FWCLIENT(struct OBJGPU *pGpu);
NvU32 gpuGetActiveFBIOs_GM107(struct OBJGPU *pGpu);
@ -2535,6 +2554,16 @@ static inline NV_STATUS gpuWriteFunctionConfigRegEx_DISPATCH(struct OBJGPU *pGpu
return pGpu->__gpuWriteFunctionConfigRegEx__(pGpu, function, reg, data, pThreadState);
}
NV_STATUS gpuReadVgpuConfigReg_GH100(struct OBJGPU *pGpu, NvU32 index, NvU32 *data);
static inline NV_STATUS gpuReadVgpuConfigReg_46f6a7(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
return NV_ERR_NOT_SUPPORTED;
}
static inline NV_STATUS gpuReadVgpuConfigReg_DISPATCH(struct OBJGPU *pGpu, NvU32 index, NvU32 *data) {
return pGpu->__gpuReadVgpuConfigReg__(pGpu, index, data);
}
void gpuGetIdInfo_GM107(struct OBJGPU *pGpu);
void gpuGetIdInfo_GH100(struct OBJGPU *pGpu);

14
src/nvidia/generated/g_kern_fsp_nvoc.c
View File

@ -161,10 +161,14 @@ void __nvoc_dtor_KernelFsp(KernelFsp *pThis) {
void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) {
ChipHal *chipHal = &pRmhalspecowner->chipHal;
const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(chipHal);
PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
// NVOC Property Hal field -- PDB_PROP_KFSP_IS_MISSING
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
@ -176,6 +180,12 @@ void __nvoc_init_dataField_KernelFsp(KernelFsp *pThis, RmHalspecOwner *pRmhalspe
{
pThis->setProperty(pThis, PDB_PROP_KFSP_IS_MISSING, ((NvBool)(0 == 0)));
}
// NVOC Property Hal field -- PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000002UL) )) /* RmVariantHal: PF_KERNEL_ONLY */
{
pThis->setProperty(pThis, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM, ((NvBool)(0 == 0)));
}
}
NV_STATUS __nvoc_ctor_OBJENGSTATE(OBJENGSTATE* );
@ -195,10 +205,14 @@ __nvoc_ctor_KernelFsp_exit:
static void __nvoc_init_funcTable_KernelFsp_1(KernelFsp *pThis, RmHalspecOwner *pRmhalspecowner) {
ChipHal *chipHal = &pRmhalspecowner->chipHal;
const unsigned long chipHal_HalVarIdx = (unsigned long)chipHal->__nvoc_HalVarIdx;
RmVariantHal *rmVariantHal = &pRmhalspecowner->rmVariantHal;
const unsigned long rmVariantHal_HalVarIdx = (unsigned long)rmVariantHal->__nvoc_HalVarIdx;
PORT_UNREFERENCED_VARIABLE(pThis);
PORT_UNREFERENCED_VARIABLE(pRmhalspecowner);
PORT_UNREFERENCED_VARIABLE(chipHal);
PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
PORT_UNREFERENCED_VARIABLE(rmVariantHal);
PORT_UNREFERENCED_VARIABLE(rmVariantHal_HalVarIdx);
pThis->__kfspConstructEngine__ = &kfspConstructEngine_IMPL;

22
src/nvidia/generated/g_kern_mem_sys_nvoc.c
View File

@ -396,6 +396,28 @@ static void __nvoc_init_funcTable_KernelMemorySystem_1(KernelMemorySystem *pThis
pThis->__kmemsysSwizzIdToVmmuSegmentsRange__ = &kmemsysSwizzIdToVmmuSegmentsRange_GH100;
}
// Hal function -- kmemsysCheckEccCounts
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_GH100;
}
// default
else
{
pThis->__kmemsysCheckEccCounts__ = &kmemsysCheckEccCounts_b3696a;
}
// Hal function -- kmemsysClearEccCounts
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x10000000UL) )) /* ChipHal: GH100 */
{
pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_GH100;
}
// default
else
{
pThis->__kmemsysClearEccCounts__ = &kmemsysClearEccCounts_56cd7a;
}
pThis->__nvoc_base_OBJENGSTATE.__engstateConstructEngine__ = &__nvoc_thunk_KernelMemorySystem_engstateConstructEngine;
pThis->__nvoc_base_OBJENGSTATE.__engstateStateInitLocked__ = &__nvoc_thunk_KernelMemorySystem_engstateStateInitLocked;

26
src/nvidia/generated/g_kern_mem_sys_nvoc.h
View File

@ -215,6 +215,8 @@ struct KernelMemorySystem {
NV_STATUS (*__kmemsysReadMIGMemoryCfg__)(OBJGPU *, struct KernelMemorySystem *);
NV_STATUS (*__kmemsysInitMIGMemoryPartitionTable__)(OBJGPU *, struct KernelMemorySystem *);
NV_STATUS (*__kmemsysSwizzIdToVmmuSegmentsRange__)(OBJGPU *, struct KernelMemorySystem *, NvU32, NvU32, NvU32);
void (*__kmemsysCheckEccCounts__)(OBJGPU *, struct KernelMemorySystem *);
NV_STATUS (*__kmemsysClearEccCounts__)(OBJGPU *, struct KernelMemorySystem *);
NV_STATUS (*__kmemsysReconcileTunableState__)(POBJGPU, struct KernelMemorySystem *, void *);
NV_STATUS (*__kmemsysStateLoad__)(POBJGPU, struct KernelMemorySystem *, NvU32);
NV_STATUS (*__kmemsysStateUnload__)(POBJGPU, struct KernelMemorySystem *, NvU32);
@ -311,6 +313,10 @@ NV_STATUS __nvoc_objCreate_KernelMemorySystem(KernelMemorySystem**, Dynamic*, Nv
#define kmemsysInitMIGMemoryPartitionTable_HAL(pGpu, pKernelMemorySystem) kmemsysInitMIGMemoryPartitionTable_DISPATCH(pGpu, pKernelMemorySystem)
#define kmemsysSwizzIdToVmmuSegmentsRange(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments)
#define kmemsysSwizzIdToVmmuSegmentsRange_HAL(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments) kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments)
#define kmemsysCheckEccCounts(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem)
#define kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysCheckEccCounts_DISPATCH(pGpu, pKernelMemorySystem)
#define kmemsysClearEccCounts(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem)
#define kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem) kmemsysClearEccCounts_DISPATCH(pGpu, pKernelMemorySystem)
#define kmemsysReconcileTunableState(pGpu, pEngstate, pTunableState) kmemsysReconcileTunableState_DISPATCH(pGpu, pEngstate, pTunableState)
#define kmemsysStateLoad(pGpu, pEngstate, arg0) kmemsysStateLoad_DISPATCH(pGpu, pEngstate, arg0)
#define kmemsysStateUnload(pGpu, pEngstate, arg0) kmemsysStateUnload_DISPATCH(pGpu, pEngstate, arg0)
@ -653,6 +659,26 @@ static inline NV_STATUS kmemsysSwizzIdToVmmuSegmentsRange_DISPATCH(OBJGPU *pGpu,
return pKernelMemorySystem->__kmemsysSwizzIdToVmmuSegmentsRange__(pGpu, pKernelMemorySystem, swizzId, vmmuSegmentSize, totalVmmuSegments);
}
void kmemsysCheckEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem);
static inline void kmemsysCheckEccCounts_b3696a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) {
return;
}
static inline void kmemsysCheckEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) {
pKernelMemorySystem->__kmemsysCheckEccCounts__(pGpu, pKernelMemorySystem);
}
NV_STATUS kmemsysClearEccCounts_GH100(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem);
static inline NV_STATUS kmemsysClearEccCounts_56cd7a(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) {
return NV_OK;
}
static inline NV_STATUS kmemsysClearEccCounts_DISPATCH(OBJGPU *pGpu, struct KernelMemorySystem *pKernelMemorySystem) {
return pKernelMemorySystem->__kmemsysClearEccCounts__(pGpu, pKernelMemorySystem);
}
static inline NV_STATUS kmemsysReconcileTunableState_DISPATCH(POBJGPU pGpu, struct KernelMemorySystem *pEngstate, void *pTunableState) {
return pEngstate->__kmemsysReconcileTunableState__(pGpu, pEngstate, pTunableState);
}

19
src/nvidia/generated/g_kernel_gsp_nvoc.h
View File

@ -335,12 +335,15 @@ struct KernelGsp {
RM_LIBOS_LOG_MEM rmLibosLogMem[3];
RM_LIBOS_LOG_MEM gspPluginInitTaskLogMem[32];
RM_LIBOS_LOG_MEM gspPluginVgpuTaskLogMem[32];
NvBool bHasVgpuLogs;
void *pLogElf;
NvU64 logElfDataSize;
PORT_MUTEX *pNvlogFlushMtx;
NvBool bLibosLogsPollingEnabled;
NvBool bInInit;
NvBool bInLockdown;
NvBool bPollingForRpcResponse;
NvBool bFatalError;
MEMORY_DESCRIPTOR *pMemDesc_simAccessBuf;
SimAccessBuffer *pSimAccessBuf;
NvP64 pSimAccessBufPriv;
@ -1075,14 +1078,24 @@ static inline NV_STATUS kgspStartLogPolling(struct OBJGPU *pGpu, struct KernelGs
#define kgspStartLogPolling(pGpu, pKernelGsp) kgspStartLogPolling_IMPL(pGpu, pKernelGsp)
#endif //__nvoc_kernel_gsp_h_disabled
void kgspDumpGspLogs_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvBool arg0);
void kgspDumpGspLogs_IMPL(struct KernelGsp *pKernelGsp, NvBool arg0);
#ifdef __nvoc_kernel_gsp_h_disabled
static inline void kgspDumpGspLogs(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, NvBool arg0) {
static inline void kgspDumpGspLogs(struct KernelGsp *pKernelGsp, NvBool arg0) {
NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!");
}
#else //__nvoc_kernel_gsp_h_disabled
#define kgspDumpGspLogs(pGpu, pKernelGsp, arg0) kgspDumpGspLogs_IMPL(pGpu, pKernelGsp, arg0)
#define kgspDumpGspLogs(pKernelGsp, arg0) kgspDumpGspLogs_IMPL(pKernelGsp, arg0)
#endif //__nvoc_kernel_gsp_h_disabled
void kgspDumpGspLogsUnlocked_IMPL(struct KernelGsp *pKernelGsp, NvBool arg0);
#ifdef __nvoc_kernel_gsp_h_disabled
static inline void kgspDumpGspLogsUnlocked(struct KernelGsp *pKernelGsp, NvBool arg0) {
NV_ASSERT_FAILED_PRECOMP("KernelGsp was disabled!");
}
#else //__nvoc_kernel_gsp_h_disabled
#define kgspDumpGspLogsUnlocked(pKernelGsp, arg0) kgspDumpGspLogsUnlocked_IMPL(pKernelGsp, arg0)
#endif //__nvoc_kernel_gsp_h_disabled
NV_STATUS kgspExecuteSequencerBuffer_IMPL(struct OBJGPU *pGpu, struct KernelGsp *pKernelGsp, void *pRunCpuSeqParams);

5
src/nvidia/generated/g_kernel_vgpu_mgr_nvoc.h
View File

@ -326,9 +326,8 @@ kvgpumgrGetHostVgpuDeviceFromMdevUuid(NvU32 gpuPciId, const NvU8 *pMdevUuid,
KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice);
NV_STATUS
kvgpumgrGetHostVgpuDeviceFromVmId(NvU32 gpuPciId, VM_ID guestVmId,
KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice,
VM_ID_TYPE vmIdType);
kvgpumgrGetHostVgpuDeviceFromVgpuUuid(NvU32 gpuPciId, NvU8 *vgpuUuid,
KERNEL_HOST_VGPU_DEVICE **ppKernelHostVgpuDevice);
NV_STATUS
kvgpumgrGetCreatableVgpuTypes(struct OBJGPU *pGpu, struct KernelVgpuMgr *pKernelVgpuMgr, NvU32 pgpuIndex, NvU32* numVgpuTypes, NvU32* vgpuTypes);

7
src/nvidia/generated/g_nv_name_released.h
View File

@ -808,12 +808,15 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" },
{ 0x20B2, 0x1625, 0x10de, "NVIDIA PG509-210" },
{ 0x20B3, 0x14a7, 0x10de, "NVIDIA A100-SXM-64GB" },
{ 0x20B3, 0x14a8, 0x10de, "NVIDIA A100-SXM-64GB" },
{ 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" },
{ 0x20B5, 0x1642, 0x10de, "NVIDIA A100 80GB PCIe" },
{ 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" },
{ 0x20B7, 0x1532, 0x10de, "NVIDIA A30" },
{ 0x20B7, 0x1804, 0x10de, "NVIDIA A30" },
{ 0x20B7, 0x1852, 0x10de, "NVIDIA A30" },
{ 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" },
{ 0x20F3, 0x179b, 0x10de, "NVIDIA A800-SXM4-80GB" },
{ 0x20F3, 0x179c, 0x10de, "NVIDIA A800-SXM4-80GB" },
@ -985,6 +988,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" },
{ 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2770, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Embedded GPU" },
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" },
{ 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
@ -998,14 +1002,17 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x27BB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Laptop GPU" },
{ 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x2803, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" },
{ 0x2805, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" },
{ 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2838, 0x0000, 0x0000, "NVIDIA RTX 3000 Ada Generation Laptop GPU" },
{ 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2882, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060" },
{ 0x28A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28A1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28B8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Laptop GPU" },
{ 0x28E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Laptop GPU" },
{ 0x28E1, 0x0000, 0x0000, "NVIDIA GeForce RTX 4050 Laptop GPU" },
{ 0x28F8, 0x0000, 0x0000, "NVIDIA RTX 2000 Ada Generation Embedded GPU" },
{ 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },
{ 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" },
{ 0x13BD, 0x11ce, 0x10DE, "GRID M10-0Q" },

2
src/nvidia/generated/g_subdevice_nvoc.h
View File

@ -606,7 +606,7 @@ struct Subdevice {
struct Device *pDevice;
NvBool bMaxGrTickFreqRequested;
NvU64 P2PfbMappedBytes;
NvU32 notifyActions[178];
NvU32 notifyActions[179];
NvHandle hNotifierMemory;
struct Memory *pNotifierMemory;
NvHandle hSemMemory;

2
src/nvidia/inc/libraries/mmu/mmu_walk.h
View File

@ -834,7 +834,7 @@ mmuWalkGetUserCtx
/*!
* Set the user context of a walker state.
*/
void
NV_STATUS
mmuWalkSetUserCtx
(
MMU_WALK *pWalk,

21
src/nvidia/inc/libraries/nvlog/nvlog.h
View File

@ -328,6 +328,27 @@ NvU32 nvlogGetFileLineFilterRules(NVLOG_FILELINE_FILTER *pFileLineFilter, NvU32
*/
void nvlogDumpToKernelLogIfEnabled(void);
/**
* @param[in] pCb callback function to be called when nvlog buffers need to be flushed
* @param[in] pData argument to pass to pCb
* @param[out] ppCb output callback data pointer
*
* @return NV_OK on success
*/
NV_STATUS nvlogRegisterFlushCb(void (*pCb)(void*), void *pData);
/**
* @param[in] pCb callback pCb to be deregistered
* @param[in] pData argument that pCb was registered with
*/
void nvlogDeregisterFlushCb(void (*pCb)(void*), void *pData);
//
// Run registered callbacks.
// All callback list accesses are synchronised.
//
void nvlogRunFlushCbs(void);
#ifdef __cplusplus
} // extern "C"
#endif

1
src/nvidia/kernel/vgpu/nv/rpc.c
View File

@ -147,6 +147,7 @@ static NV_STATUS _issueRpcAndWait(OBJGPU *pGpu, OBJRPC *pRpc)
// should not be called in broadcast mode
NV_ASSERT_OR_RETURN(!gpumgrGetBcEnabledStatus(pGpu), NV_ERR_INVALID_STATE);
NV_CHECK(LEVEL_ERROR, rmDeviceGpuLockIsOwner(pGpu->gpuInstance));
if (bProfileRPC)
{

76
src/nvidia/src/kernel/diagnostics/nvlog.c
View File

@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include "nvlimits.h"
#include "nvlog/nvlog.h"
#include "nvrm_registry.h"
#include "os/os.h"
@ -78,6 +79,19 @@ NVLOG_LOGGER NvLogLogger =
#define NVLOG_IS_VALID_BUFFER_HANDLE(hBuffer) \
((hBuffer < NVLOG_MAX_BUFFERS) && (NvLogLogger.pBuffers[hBuffer] != NULL))
typedef struct
{
void (*pCb)(void *);
void *pData;
} NvlogFlushCb;
#define NVLOG_MAX_FLUSH_CBS 32
// At least one callback for each OBJGPU's KernelGsp
ct_assert(NVLOG_MAX_FLUSH_CBS >= NV_MAX_DEVICES);
static NvlogFlushCb nvlogFlushCbs[NVLOG_MAX_FLUSH_CBS];
NV_STATUS
nvlogInit(void *pData)
{
@ -95,7 +109,14 @@ nvlogInit(void *pData)
{
return NV_ERR_INSUFFICIENT_RESOURCES;
}
NvLogLogger.flushCbsLock = portSyncRwLockCreate(portMemAllocatorGetGlobalNonPaged());
if (NvLogLogger.flushCbsLock == NULL)
{
return NV_ERR_INSUFFICIENT_RESOURCES;
}
tlsInitialize();
portMemSet(nvlogFlushCbs, '\0', sizeof(nvlogFlushCbs));
return status;
}
@ -123,6 +144,11 @@ nvlogDestroy(void)
portSyncMutexDestroy(NvLogLogger.buffersLock);
NvLogLogger.buffersLock = NULL;
}
if (NvLogLogger.flushCbsLock != NULL)
{
portSyncRwLockDestroy(NvLogLogger.flushCbsLock);
NvLogLogger.flushCbsLock = NULL;
}
tlsShutdown();
/// @todo Destructor should return void.
@ -752,3 +778,53 @@ void nvlogDumpToKernelLogIfEnabled(void)
nvlogDumpToKernelLog(NV_FALSE);
}
NV_STATUS nvlogRegisterFlushCb(void (*pCb)(void*), void *pData)
{
NV_STATUS status = NV_ERR_INSUFFICIENT_RESOURCES;
portSyncRwLockAcquireWrite(NvLogLogger.flushCbsLock);
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(nvlogFlushCbs); i++)
{
// The same callback should not be registered twice
NV_ASSERT(nvlogFlushCbs[i].pCb != pCb || nvlogFlushCbs[i].pData != pData);
if (nvlogFlushCbs[i].pCb == NULL)
{
nvlogFlushCbs[i].pCb = pCb;
nvlogFlushCbs[i].pData = pData;
status = NV_OK;
goto done;
}
}
done:
portSyncRwLockReleaseWrite(NvLogLogger.flushCbsLock);
return status;
}
void nvlogDeregisterFlushCb(void (*pCb)(void*), void *pData)
{
portSyncRwLockAcquireWrite(NvLogLogger.flushCbsLock);
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(nvlogFlushCbs); i++)
{
if (nvlogFlushCbs[i].pCb == pCb && nvlogFlushCbs[i].pData == pData)
{
nvlogFlushCbs[i] = (NvlogFlushCb){0};
goto done;
}
}
done:
portSyncRwLockReleaseWrite(NvLogLogger.flushCbsLock);
}
void nvlogRunFlushCbs(void)
{
portSyncRwLockAcquireRead(NvLogLogger.flushCbsLock);
for (NvU32 i = 0; i < NV_ARRAY_ELEMENTS(nvlogFlushCbs); i++)
if (nvlogFlushCbs[i].pCb != NULL)
nvlogFlushCbs[i].pCb(nvlogFlushCbs[i].pData);
portSyncRwLockReleaseRead(NvLogLogger.flushCbsLock);
}

23
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
View File

@ -30,6 +30,7 @@
#include "published/hopper/gh100/dev_pmc.h"
#include "published/hopper/gh100/dev_xtl_ep_pcfg_gpu.h"
#include "published/hopper/gh100/pri_nv_xal_ep.h"
#include "published/hopper/gh100/dev_xtl_ep_pri.h"
#include "gpu/gsp/gsp_static_config.h"
@ -73,6 +74,28 @@ gpuReadBusConfigReg_GH100
return gpuReadBusConfigCycle(pGpu, index, pData);
}
/*!
* @brief Read the non-private registers on vGPU through mirror space
*
* @param[in] pGpu GPU object pointer
* @param[in] index Register offset in PCIe config space
* @param[out] pData Value of the register
*
* @returns NV_OK on success
*/
NV_STATUS
gpuReadVgpuConfigReg_GH100
(
OBJGPU *pGpu,
NvU32 index,
NvU32 *pData
)
{
*pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
return NV_OK;
}
/*!
* @brief Get GPU ID based on PCIE config reads.
* Also determine other properties of the PCIE capabilities.

16
src/nvidia/src/kernel/gpu/bus/arch/maxwell/kern_bus_gm107.c
View File

@ -1428,7 +1428,7 @@ kbusSetupBar2GpuVaSpace_GM107
NV_ASSERT_OR_RETURN(pWalk != NULL, NV_ERR_INVALID_STATE);
// Pre-reserve and init 4K tables through BAR0 window (bBootstrap) mode.
mmuWalkSetUserCtx(pWalk, &userCtx);
NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pWalk, &userCtx));
if (pKernelBus->bar2[gfid].cpuVisibleLimit != 0)
{
@ -1580,7 +1580,7 @@ kbusTeardownBar2GpuVaSpace_GM107
userCtx.pGpu = pGpu;
mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx);
NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx));
if (kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus) || IS_GFID_VF(gfid))
{
@ -1608,7 +1608,7 @@ kbusTeardownBar2GpuVaSpace_GM107
kbusRestoreBar0WindowAfterBar2Bootstrap_HAL(pGpu, pKernelBus, origVidOffset);
}
mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, NULL);
NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, NULL));
mmuWalkDestroy(pKernelBus->bar2[gfid].pWalk);
pKernelBus->bar2[gfid].pWalk = NULL;
@ -2119,8 +2119,6 @@ kbusUpdateRmAperture_GM107
}
}
pFmt = pKernelBus->bar2[gfid].pFmt;
// Math below requires page-sized va.
if (vaSize == 0 || vaSize & RM_PAGE_MASK)
{
@ -2153,7 +2151,7 @@ kbusUpdateRmAperture_GM107
dmaPageArrayInitFromMemDesc(&pageArray, pSubDevMemDesc, addressTranslation);
userCtx.pGpu = pGpu;
userCtx.gfid = gfid;
mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx);
NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, &userCtx));
if (bSparsify)
{
@ -2171,6 +2169,10 @@ kbusUpdateRmAperture_GM107
}
else
{
pFmt = pKernelBus->bar2[gfid].pFmt;
NV_CHECK_OR_RETURN(LEVEL_ERROR, pFmt != NULL, NV_ERR_INVALID_ARGUMENT);
// MMU_MAP_CTX
mapTarget.pLevelFmt = mmuFmtFindLevelWithPageShift(pFmt->pRoot,
BIT_IDX_32(pageSize));
@ -2253,7 +2255,7 @@ kbusUpdateRmAperture_GM107
NV_ASSERT(NV_OK == status);
}
mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, NULL);
NV_ASSERT_OK_OR_RETURN(mmuWalkSetUserCtx(pKernelBus->bar2[gfid].pWalk, NULL));
if (pKernelBus->bar2[gfid].bBootstrap &&
!kbusIsPhysicalBar2InitPagetableEnabled(pKernelBus))

15
src/nvidia/src/kernel/gpu/fsp/arch/hopper/kern_fsp_gh100.c
View File

@ -38,6 +38,7 @@
#include "published/hopper/gh100/dev_therm_addendum.h"
#include "os/os.h"
#include "nvRmReg.h"
#include "nverror.h"
#if RMCFG_MODULE_ENABLED (FSP)
#include "hopper/gh100/dev_gsp.h"
@ -625,9 +626,13 @@ kfspWaitForSecureBoot_GH100
status = gpuCheckTimeout(pGpu, &timeout);
if (status == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR,
"Timout while polling for FSP boot complete I2CS_SCRATCH : %x\n",
GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE));
nvErrorLog_va((void*) pGpu, GPU_INIT_ERROR, "Timeout while polling for FSP boot complete, "
"0x%x, 0x%x, 0x%x, 0x%x, 0x%x",
GPU_REG_RD32(pGpu, NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE),
GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(0)),
GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(1)),
GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(2)),
GPU_REG_RD32(pGpu, NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(3)));
break;
}
}
@ -808,7 +813,7 @@ kfspSetupGspImages
pGspImageMapSize = NV_ALIGN_UP(pGspImageSize, 0x1000);
status = memdescCreate(&pKernelFsp->pGspFmcMemdesc, pGpu, pGspImageMapSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED,
MEMDESC_FLAGS_NONE);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);
@ -1083,7 +1088,7 @@ kfspSendBootCommands_GH100
if (!pKernelFsp->getProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_SYSMEM))
{
status = memdescCreate(&pKernelFsp->pSysmemFrtsMemdesc, pGpu, frtsSize,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_UNCACHED,
0, NV_TRUE, ADDR_SYSMEM, NV_MEMORY_CACHED,
MEMDESC_FLAGS_NONE);
NV_ASSERT_OR_GOTO(status == NV_OK, failed);

6
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@ -103,8 +103,10 @@ kfspInitRegistryOverrides
}
}
// Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken.
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM))
// Inst-in-sys must only set up FRTS in SYSMEM. This includes FB broken and cache only.
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) ||
pGpu->getProperty(pGpu, PDB_PROP_GPU_BROKEN_FB) ||
gpuIsCacheOnlyModeEnabled(pGpu))
{
pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_DISABLE_FRTS_VIDMEM, NV_TRUE);
}

22
src/nvidia/src/kernel/gpu/gpu.c
View File

@ -4696,17 +4696,25 @@ gpuReadBusConfigCycle_IMPL
NvU32 *pData
)
{
NvU32 domain = gpuGetDomain(pGpu);
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU8 function = 0;
NvU32 domain = gpuGetDomain(pGpu);
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU8 function = 0;
NvBool bIsCCFeatureEnabled = NV_FALSE;
if (pGpu->hPci == NULL)
if (IS_PASSTHRU(pGpu) && !bIsCCFeatureEnabled)
{
pGpu->hPci = osPciInitHandle(domain, bus, device, function, NULL, NULL);
gpuReadVgpuConfigReg_HAL(pGpu, index, pData);
}
else
{
if (pGpu->hPci == NULL)
{
pGpu->hPci = osPciInitHandle(domain, bus, device, function, NULL, NULL);
}
*pData = osPciReadDword(pGpu->hPci, index);
*pData = osPciReadDword(pGpu->hPci, index);
}
return NV_OK;
}

20
src/nvidia/src/kernel/gpu/gpu_registry.c
View File

@ -222,25 +222,6 @@ gpuInitInstLocOverrides_IMPL
pGpu->instLocOverrides2 = NV_REG_STR_RM_INST_LOC_ALL_COH;
pGpu->instLocOverrides3 = NV_REG_STR_RM_INST_LOC_ALL_COH;
// Leave instLocOverrides4 as _DEFAULT until all flavors are tested.
if (gpuIsCacheOnlyModeEnabled(pGpu))
{
//
// If cache only mode is enabled then we will override
// userD and bar page tables to vidmem(l2 cache).
// This is to avoid deadlocks on platforms
// that don't support reflected accesses.
// Such platforms will need to enable cache only mode to
// run test zeroFb
// NOTE: Since this puts USERD in vidmem, you probably also want to
// reduce the number of channels to allocate, or else
// fifoPreAllocUserD_GF100 will fail due to the limited amount of
// L2 available as "vidmem". (Use the RmNumFifos regkey.)
//
pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _BAR_PTE, _VID, pGpu->instLocOverrides);
pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _USERD, _VID, pGpu->instLocOverrides);
pGpu->instLocOverrides = FLD_SET_DRF(_REG, _STR_RM_INST_LOC, _BAR_PDE, _VID, pGpu->instLocOverrides);
}
}
//
@ -287,6 +268,7 @@ gpuInitInstLocOverrides_IMPL
// SMs) are fine.
//
if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_ALL_INST_IN_SYSMEM) &&
!gpuIsCacheOnlyModeEnabled(pGpu) &&
!(FLD_TEST_DRF(_REG_STR_RM, _INST_LOC, _BAR_PTE, _DEFAULT, pGpu->instLocOverrides) &&
FLD_TEST_DRF(_REG_STR_RM, _INST_LOC, _BAR_PDE, _DEFAULT, pGpu->instLocOverrides)))
{

24
src/nvidia/src/kernel/gpu/gsp/arch/hopper/kernel_gsp_gh100.c
View File

@ -28,6 +28,7 @@
#include "rmconfig.h"
#include "gpu/fsp/kern_fsp.h"
#include "gpu/gsp/kernel_gsp.h"
#include "gpu/mem_sys/kern_mem_sys.h"
#include "gsp/gspifpub.h"
#include "vgpu/rpc.h"
@ -502,6 +503,7 @@ kgspBootstrapRiscvOSEarly_GH100
{
KernelFalcon *pKernelFalcon = staticCast(pKernelGsp, KernelFalcon);
KernelFsp *pKernelFsp = GPU_GET_KERNEL_FSP(pGpu);
KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
NV_STATUS status = NV_OK;
// Only for GSP client builds
@ -511,8 +513,16 @@ kgspBootstrapRiscvOSEarly_GH100
return NV_ERR_NOT_SUPPORTED;
}
// Clear ECC errors before attempting to load GSP
status = kmemsysClearEccCounts_HAL(pGpu, pKernelMemorySystem);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Issue clearing ECC counts! Status:0x%x\n", status);
}
// Setup the descriptors that GSP-FMC needs to boot GSP-RM
NV_ASSERT_OK_OR_RETURN(kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw));
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,
kgspSetupGspFmcArgs_HAL(pGpu, pKernelGsp, pGspFw), exit);
kgspSetupLibosInitArgs(pGpu, pKernelGsp);
@ -541,7 +551,8 @@ kgspBootstrapRiscvOSEarly_GH100
{
NV_PRINTF(LEVEL_ERROR, "Starting to boot GSP via FSP.\n");
pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_GSP_MODE_GSPRM, NV_TRUE);
NV_ASSERT_OK_OR_RETURN(kfspSendBootCommands_HAL(pGpu, pKernelFsp));
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR,
kfspSendBootCommands_HAL(pGpu, pKernelFsp), exit);
}
else
{
@ -562,7 +573,7 @@ kgspBootstrapRiscvOSEarly_GH100
kfspDumpDebugState_HAL(pGpu, pKernelFsp);
}
return status;
goto exit;
}
// Wait for lockdown to be released.
@ -582,7 +593,7 @@ kgspBootstrapRiscvOSEarly_GH100
kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX0));
NV_PRINTF(LEVEL_ERROR, "NV_PGSP_FALCON_MAILBOX1 = 0x%x\n",
kflcnRegRead_HAL(pGpu, pKernelFalcon, NV_PFALCON_FALCON_MAILBOX1));
return status;
goto exit;
}
// Start polling for libos logs now that lockdown is released
@ -616,6 +627,11 @@ kgspBootstrapRiscvOSEarly_GH100
NV_PRINTF(LEVEL_INFO, "GSP FW RM ready.\n");
exit:
// If GSP fails to boot, check if there's any DED error.
if (status != NV_OK)
{
kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem);
}
NV_ASSERT(status == NV_OK);
return status;

37
src/nvidia/src/kernel/gpu/gsp/arch/turing/kernel_gsp_tu102.c
View File

@ -774,31 +774,46 @@ kgspHealthCheck_TU102
NvU32 mb0 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(0));
//
// Check for an error message in the GSP mailbox. Any error here is severe
// enough that it should be reported as an Xid. Clear the error so more can
// potentially be reported by GSP, if it was able to recover. In that case,
// it's possible that GSP will skip reporting some more errors that happened
// before the clear, and it will just update the "skipped" count.
// Check for an error message in the GSP mailbox. Any error reported here is
// almost certainly fatal.
//
if (FLD_TEST_DRF(_GSP, _ERROR, _TAG, _VAL, mb0))
{
NvU32 mb1 = GPU_REG_RD32(pGpu, NV_PGSP_MAILBOX(1));
NvU32 skipped = DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0);
pKernelGsp->bFatalError = NV_TRUE;
// Clear the mailbox
GPU_REG_WR32(pGpu, NV_PGSP_MAILBOX(0), 0);
NV_PRINTF(LEVEL_NOTICE,
NV_PRINTF(LEVEL_ERROR,
"********************************* GSP Failure **********************************\n");
nvErrorLog_va((void*)pGpu, GSP_ERROR,
"GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x (%d more errors skipped)",
"GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x. The GPU likely needs to be reset.",
DRF_VAL(_GSP, _ERROR, _TASK, mb0),
DRF_VAL(_GSP, _ERROR, _CODE, mb0),
DRF_VAL(_GSP, _ERROR, _REASON, mb0),
mb1,
DRF_VAL(_GSP, _ERROR, _SKIPPED, mb0));
mb1);
NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX
("GSP Error: Task %d raised error code 0x%x for reason 0x%x at 0x%x"),
DRF_VAL(_GSP, _ERROR, _TASK, mb0),
DRF_VAL(_GSP, _ERROR, _CODE, mb0),
DRF_VAL(_GSP, _ERROR, _REASON, mb0),
mb1);
NV_PRINTF(LEVEL_NOTICE,
// Check if GSP had more errors to report (unlikely)
if (skipped)
{
NV_PRINTF(LEVEL_ERROR, "%d more errors skipped\n", skipped);
}
NV_PRINTF(LEVEL_ERROR,
"********************************************************************************\n");
KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
kmemsysCheckEccCounts_HAL(pGpu, pKernelMemorySystem);
}
}
@ -844,7 +859,7 @@ kgspService_TU102
// provides RM a chance to handle it so we have better debugability
// into GSP-RISCV issues.
//
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
kgspHealthCheck_HAL(pGpu, pKernelGsp);
}
if (intrStatus & DRF_DEF(_PFALCON, _FALCON_IRQSTAT, _SWGEN0, _TRUE))

222
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@ -162,6 +162,43 @@ _kgspGetActiveRpcDebugData
}
}
static NV_STATUS
_kgspRpcSanityCheck(OBJGPU *pGpu)
{
if (API_GPU_IN_RESET_SANITY_CHECK(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"GPU in reset, skipping RPC\n");
return NV_ERR_GPU_IN_FULLCHIP_RESET;
}
if (!API_GPU_ATTACHED_SANITY_CHECK(pGpu) ||
pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST))
{
NV_PRINTF(LEVEL_INFO,
"GPU lost, skipping RPC\n");
return NV_ERR_GPU_IS_LOST;
}
if (osIsGpuShutdown(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"GPU shutdown, skipping RPC\n");
return NV_ERR_GPU_IS_LOST;
}
if (!gpuIsGpuFullPowerForPmResume(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"GPU not full power, skipping RPC\n");
return NV_ERR_GPU_NOT_FULL_POWER;
}
if (!gpuCheckSysmemAccess(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"GPU has no sysmem access, skipping RPC\n");
return NV_ERR_INVALID_ACCESS_TYPE;
}
return NV_OK;
}
/*!
* GSP client RM RPC send routine
*/
@ -177,7 +214,7 @@ _kgspRpcSendMessage
NV_ASSERT(rmDeviceGpuLockIsOwner(pGpu->gpuInstance));
NV_ASSERT_OR_RETURN(!osIsGpuShutdown(pGpu), NV_ERR_GPU_IS_LOST);
NV_CHECK_OK_OR_RETURN(LEVEL_SILENT, _kgspRpcSanityCheck(pGpu));
nvStatus = GspMsgQueueSendCommand(pRpc->pMessageQueueInfo, pGpu);
if (nvStatus != NV_OK)
@ -1073,7 +1110,7 @@ _kgspRpcDrainEvents
while (nvStatus == NV_OK)
{
nvStatus = _kgspRpcDrainOneEvent(pGpu, pRpc, expectedFunc);
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
}
kgspHealthCheck_HAL(pGpu, pKernelGsp);
@ -1115,6 +1152,12 @@ _kgspLogXid119
_getRpcName(expectedFunc),
pRpc->rpcHistory[historyEntry].data[0],
pRpc->rpcHistory[historyEntry].data[1]);
NVLOG_PRINTF(NV_PRINTF_MODULE, NVLOG_ROUTE_RM, LEVEL_ERROR, NV_PRINTF_ADD_PREFIX
("Timeout waiting for RPC from GSP%d! Expected function %d (0x%x 0x%x)"),
gpuGetInstance(pGpu),
expectedFunc,
pRpc->rpcHistory[historyEntry].data[0],
pRpc->rpcHistory[historyEntry].data[1]);
if (pRpc->timeoutCount == 1)
{
@ -1162,8 +1205,17 @@ _kgspRpcIncrementTimeoutCountAndRateLimitPrints
OBJRPC *pRpc
)
{
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
pRpc->timeoutCount++;
if (pKernelGsp->bFatalError)
{
// in case of a fatal GSP error, don't bother printing RPC errors at all
pRpc->bQuietPrints = NV_TRUE;
return;
}
if ((pRpc->timeoutCount == (RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH + 1)) &&
(RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP > 0))
{
@ -1198,7 +1250,8 @@ _kgspRpcRecvPoll
)
{
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
NV_STATUS nvStatus;
NV_STATUS rpcStatus = NV_OK;
NV_STATUS timeoutStatus = NV_OK;
RMTIMEOUT timeout;
NvU32 timeoutUs;
NvU32 timeoutFlags;
@ -1260,11 +1313,17 @@ _kgspRpcRecvPoll
for (;;)
{
nvStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc);
//
// Check for GPU timeout, save that information, and then verify if the RPC is completed.
// Otherwise if the CPU thread goes to sleep immediately after the RPC check, it may result in hitting a timeout.
//
timeoutStatus = gpuCheckTimeout(pGpu, &timeout);
switch (nvStatus) {
rpcStatus = _kgspRpcDrainEvents(pGpu, pKernelGsp, expectedFunc);
switch (rpcStatus) {
case NV_WARN_MORE_PROCESSING_REQUIRED:
nvStatus = NV_OK;
rpcStatus = NV_OK;
goto done;
case NV_OK:
// Check timeout and continue outer loop.
@ -1273,11 +1332,12 @@ _kgspRpcRecvPoll
goto done;
}
osSpinLoop();
NV_CHECK_OK_OR_GOTO(rpcStatus, LEVEL_SILENT, _kgspRpcSanityCheck(pGpu), done);
nvStatus = gpuCheckTimeout(pGpu, &timeout);
if (nvStatus == NV_ERR_TIMEOUT)
if (timeoutStatus == NV_ERR_TIMEOUT)
{
rpcStatus = timeoutStatus;
_kgspRpcIncrementTimeoutCountAndRateLimitPrints(pGpu, pRpc);
if (!pRpc->bQuietPrints)
@ -1287,12 +1347,15 @@ _kgspRpcRecvPoll
goto done;
}
if (osIsGpuShutdown(pGpu))
else if (timeoutStatus != NV_OK)
{
nvStatus = NV_ERR_GPU_IS_LOST;
NV_PRINTF(LEVEL_ERROR, "gpuCheckTimeout() returned unexpected error (0x%08x)\n",
timeoutStatus);
rpcStatus = timeoutStatus;
goto done;
}
osSpinLoop();
}
pRpc->timeoutCount = 0;
@ -1306,7 +1369,7 @@ done:
threadStateResetTimeout(pGpu);
}
return nvStatus;
return rpcStatus;
}
/*!
@ -1466,7 +1529,7 @@ kgspFreeVgpuPartitionLogging_IMPL
else
{
// Make sure there is no lingering debug output.
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
_kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid);
return NV_OK;
@ -1498,6 +1561,8 @@ kgspInitVgpuPartitionLogging_IMPL
return NV_ERR_INVALID_ARGUMENT;
}
portSyncMutexAcquire(pKernelGsp->pNvlogFlushMtx);
// Source name is used to generate a tag that is a unique identifier for nvlog buffers.
// As the source name 'GSP' is already in use, we will need a custom source name.
nvDbgSnprintf(sourceName, SOURCE_NAME_MAX_LENGTH, "V%02d", gfid);
@ -1602,13 +1667,23 @@ kgspInitVgpuPartitionLogging_IMPL
"GSP", SOURCE_NAME_MAX_LENGTH);
}
pKernelGsp->bHasVgpuLogs = NV_TRUE;
error_cleanup:
portSyncMutexRelease(pKernelGsp->pNvlogFlushMtx);
if (nvStatus != NV_OK)
_kgspFreeLibosVgpuPartitionLoggingStructures(pGpu, pKernelGsp, gfid);
return nvStatus;
}
void kgspNvlogFlushCb(void *pKernelGsp)
{
if (pKernelGsp != NULL)
kgspDumpGspLogs((KernelGsp*)pKernelGsp, NV_TRUE);
}
/*!
* Free LIBOS task logging structures
*/
@ -1624,7 +1699,15 @@ _kgspFreeLibosLoggingStructures
_kgspStopLogPolling(pGpu, pKernelGsp);
// Make sure there is no lingering debug output.
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
if (pKernelGsp->pNvlogFlushMtx != NULL)
{
nvlogDeregisterFlushCb(kgspNvlogFlushCb, pKernelGsp);
portSyncMutexDestroy(pKernelGsp->pNvlogFlushMtx);
pKernelGsp->pNvlogFlushMtx = NULL;
}
libosLogDestroy(&pKernelGsp->logDecode);
@ -1691,6 +1774,13 @@ _kgspInitLibosLoggingStructures
NV_STATUS nvStatus = NV_OK;
NvU8 idx;
pKernelGsp->pNvlogFlushMtx = portSyncMutexCreate(portMemAllocatorGetGlobalNonPaged());
if (pKernelGsp->pNvlogFlushMtx == NULL)
{
nvStatus = NV_ERR_INSUFFICIENT_RESOURCES;
goto error_cleanup;
}
libosLogCreate(&pKernelGsp->logDecode);
for (idx = 0; idx < LOGIDX_SIZE; idx++)
@ -2053,7 +2143,26 @@ kgspInitRm_IMPL
goto done;
}
status = kgspCalculateFbLayout(pGpu, pKernelGsp, pGspFw);
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspInitLogging(pGpu, pKernelGsp, pGspFw), done);
// If live decoding is enabled, do not register flush callback to avoid racing with ioctl
if (pKernelGsp->pLogElf == NULL)
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, nvlogRegisterFlushCb(kgspNvlogFlushCb, pKernelGsp), done);
// Wait for GFW_BOOT OK status
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp), done);
// Fail early if WPR2 is up
if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp))
{
NV_PRINTF(LEVEL_ERROR, "unexpected WPR2 already up, cannot proceed with booting gsp\n");
NV_PRINTF(LEVEL_ERROR, "(the GPU is likely in a bad state and may need to be reset)\n");
status = NV_ERR_INVALID_STATE;
goto done;
}
// Calculate FB layout (requires knowing FB size which depends on GFW_BOOT)
status = kgspCalculateFbLayout_HAL(pGpu, pKernelGsp, pGspFw);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Error calculating FB layout\n");
@ -2088,20 +2197,6 @@ kgspInitRm_IMPL
}
}
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspInitLogging(pGpu, pKernelGsp, pGspFw), done);
// Wait for GFW_BOOT OK status
NV_CHECK_OK_OR_GOTO(status, LEVEL_ERROR, kgspWaitForGfwBootOk_HAL(pGpu, pKernelGsp), done);
// Fail early if WPR2 is up
if (kgspIsWpr2Up_HAL(pGpu, pKernelGsp))
{
NV_PRINTF(LEVEL_ERROR, "unexpected WPR2 already up, cannot proceed with booting gsp\n");
NV_PRINTF(LEVEL_ERROR, "(the GPU is likely in a bad state and may need to be reset)\n");
status = NV_ERR_INVALID_STATE;
goto done;
}
// bring up ucode with RM offload task
status = kgspBootstrapRiscvOSEarly_HAL(pGpu, pKernelGsp, pGspFw);
if (status != NV_OK)
@ -2193,7 +2288,7 @@ kgspUnloadRm_IMPL
kgspWaitForProcessorSuspend_HAL(pGpu, pKernelGsp);
// Dump GSP-RM logs and reset before invoking FWSEC-SB
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogs(pKernelGsp, NV_FALSE);
//
// Avoid cascading timeouts when attempting to invoke the below ucodes if
@ -2268,10 +2363,32 @@ kgspDestruct_IMPL
_kgspFreeSimAccessBuffer(pGpu, pKernelGsp);
}
void
kgspDumpGspLogsUnlocked_IMPL
(
KernelGsp *pKernelGsp,
NvBool bSyncNvLog
)
{
if (pKernelGsp->bInInit || pKernelGsp->pLogElf || bSyncNvLog)
{
libosExtractLogs(&pKernelGsp->logDecode, bSyncNvLog);
if (pKernelGsp->bHasVgpuLogs)
{
// Dump logs from vGPU partition
for (NvU32 i = 0; i < MAX_PARTITIONS_WITH_GFID; i++)
{
libosExtractLogs(&pKernelGsp->logDecodeVgpuPartition[i], bSyncNvLog);
}
}
}
}
/*!
* Dump logs coming from GSP-RM
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelGsp KernelGsp pointer
* @param[in] bSyncNvLog NV_TRUE: Copy a snapshot of the libos logs
* into the nvLog wrap buffers.
@ -2279,30 +2396,20 @@ kgspDestruct_IMPL
void
kgspDumpGspLogs_IMPL
(
OBJGPU *pGpu,
KernelGsp *pKernelGsp,
NvBool bSyncNvLog
)
{
if (!IS_GSP_CLIENT(pGpu))
{
return;
}
if (pKernelGsp->bInInit || pKernelGsp->pLogElf || bSyncNvLog)
{
libosExtractLogs(&pKernelGsp->logDecode, bSyncNvLog);
}
if (pKernelGsp->pNvlogFlushMtx != NULL)
portSyncMutexAcquire(pKernelGsp->pNvlogFlushMtx);
if (IS_VGPU_GSP_PLUGIN_OFFLOAD_ENABLED(pGpu))
{
// Dump logs from vGPU partition
for (NvU32 i = 0; i < MAX_PARTITIONS_WITH_GFID; i++)
{
libosExtractLogs(&pKernelGsp->logDecodeVgpuPartition[i], bSyncNvLog);
}
}
kgspDumpGspLogsUnlocked(pKernelGsp, bSyncNvLog);
if (pKernelGsp->pNvlogFlushMtx != NULL)
portSyncMutexRelease(pKernelGsp->pNvlogFlushMtx);
}
}
/*!
@ -3135,8 +3242,12 @@ _kgspLogPollingCallback
void *data
)
{
//
// Do not take any locks in kgspDumpGspLogs. As this callback only fires when kgspNvlogFlushCb
// is not registered, there is no possibility of data race.
//
KernelGsp *pKernelGsp = GPU_GET_KERNEL_GSP(pGpu);
kgspDumpGspLogs(pGpu, pKernelGsp, NV_FALSE);
kgspDumpGspLogsUnlocked(pKernelGsp, NV_FALSE);
}
NV_STATUS
@ -3146,8 +3257,14 @@ kgspStartLogPolling_IMPL
KernelGsp *pKernelGsp
)
{
NV_STATUS status;
status = osSchedule1SecondCallback(pGpu, _kgspLogPollingCallback, NULL, NV_OS_1HZ_REPEAT);
NV_STATUS status = NV_OK;
//
// Only enable the 1 Hz poll if we can live decode logs in dmesg. Else we'll flush it on demand
// by nvidia-debugdump.
//
if (pKernelGsp->pLogElf != NULL)
status = osSchedule1SecondCallback(pGpu, _kgspLogPollingCallback, NULL, NV_OS_1HZ_REPEAT);
return status;
}
@ -3158,7 +3275,8 @@ _kgspStopLogPolling
KernelGsp *pKernelGsp
)
{
osRemove1SecondRepeatingCallback(pGpu, _kgspLogPollingCallback, NULL);
if (pKernelGsp->pLogElf != NULL)
osRemove1SecondRepeatingCallback(pGpu, _kgspLogPollingCallback, NULL);
}
#else // LIBOS_LOG_DECODE_ENABLE

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