2022-05-09 23:18:59 +03:00
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/*
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2022-10-11 00:59:24 +03:00
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* SPDX-FileCopyrightText: Copyright (c) 2013-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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2022-05-09 23:18:59 +03:00
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* nv_gpu_ops.h
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*
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* This file defines the interface between the common RM layer
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* and the OS specific platform layers. (Currently supported
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* are Linux and KMD)
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*
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*/
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#ifndef _NV_GPU_OPS_H_
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#define _NV_GPU_OPS_H_
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#include "nvgputypes.h"
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#include "nv_uvm_types.h"
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typedef struct gpuSession *gpuSessionHandle;
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typedef struct gpuDevice *gpuDeviceHandle;
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typedef struct gpuAddressSpace *gpuAddressSpaceHandle;
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typedef struct gpuChannel *gpuChannelHandle;
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typedef struct gpuObject *gpuObjectHandle;
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typedef struct gpuRetainedChannel_struct gpuRetainedChannel;
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NV_STATUS nvGpuOpsCreateSession(struct gpuSession **session);
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NV_STATUS nvGpuOpsDestroySession(struct gpuSession *session);
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NV_STATUS nvGpuOpsDeviceCreate(struct gpuSession *session,
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const gpuInfo *pGpuInfo,
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const NvProcessorUuid *gpuGuid,
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struct gpuDevice **device,
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NvBool bCreateSmcPartition);
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NV_STATUS nvGpuOpsDeviceDestroy(struct gpuDevice *device);
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NV_STATUS nvGpuOpsAddressSpaceCreate(struct gpuDevice *device,
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NvU64 vaBase,
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NvU64 vaSize,
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gpuAddressSpaceHandle *vaSpace,
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UvmGpuAddressSpaceInfo *vaSpaceInfo);
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NV_STATUS nvGpuOpsGetP2PCaps(gpuDeviceHandle device1,
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gpuDeviceHandle device2,
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getP2PCapsParams *p2pCaps);
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void nvGpuOpsAddressSpaceDestroy(gpuAddressSpaceHandle vaSpace);
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NV_STATUS nvGpuOpsMemoryAllocFb (gpuAddressSpaceHandle vaSpace,
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NvLength length, NvU64 *gpuOffset, gpuAllocInfo * allocInfo);
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NV_STATUS nvGpuOpsMemoryAllocSys (gpuAddressSpaceHandle vaSpace,
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NvLength length, NvU64 *gpuOffset, gpuAllocInfo * allocInfo);
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NV_STATUS nvGpuOpsPmaAllocPages(void *pPma,
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NvLength pageCount,
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NvU32 pageSize,
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gpuPmaAllocationOptions *pPmaAllocOptions,
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NvU64 *pPages);
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void nvGpuOpsPmaFreePages(void *pPma,
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NvU64 *pPages,
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NvLength pageCount,
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NvU32 pageSize,
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NvU32 flags);
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NV_STATUS nvGpuOpsPmaPinPages(void *pPma,
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NvU64 *pPages,
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NvLength pageCount,
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NvU32 pageSize,
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NvU32 flags);
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NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma,
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NvU64 *pPages,
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NvLength pageCount,
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NvU32 pageSize);
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NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace,
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const gpuChannelAllocParams *params,
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gpuChannelHandle *channelHandle,
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gpuChannelInfo *channelInfo);
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NV_STATUS nvGpuOpsMemoryReopen(struct gpuAddressSpace *vaSpace,
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NvHandle hSrcClient, NvHandle hSrcAllocation, NvLength length, NvU64 *gpuOffset);
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void nvGpuOpsChannelDestroy(struct gpuChannel *channel);
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void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace,
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NvU64 pointer);
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NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace,
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NvU64 memory, NvLength length,
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void **cpuPtr, NvU32 pageSize);
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void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace,
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void* cpuPtr);
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NV_STATUS nvGpuOpsQueryCaps(struct gpuDevice *device,
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gpuCaps *caps);
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NV_STATUS nvGpuOpsQueryCesCaps(struct gpuDevice *device,
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gpuCesCaps *caps);
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NV_STATUS nvGpuOpsDupAllocation(struct gpuAddressSpace *srcVaSpace,
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NvU64 srcAddress,
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struct gpuAddressSpace *dstVaSpace,
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NvU64 dstVaAlignment,
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NvU64 *dstAddress);
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NV_STATUS nvGpuOpsDupMemory(struct gpuDevice *device,
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NvHandle hClient,
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NvHandle hPhysMemory,
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NvHandle *hDupMemory,
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gpuMemoryInfo *pGpuMemoryInfo);
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NV_STATUS nvGpuOpsGetGuid(NvHandle hClient, NvHandle hDevice,
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NvHandle hSubDevice, NvU8 *gpuGuid,
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unsigned guidLength);
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NV_STATUS nvGpuOpsGetClientInfoFromPid(unsigned pid,
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const NvU8 *gpuUuid,
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NvHandle *hClient,
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NvHandle *hDevice,
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NvHandle *hSubDevice);
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NV_STATUS nvGpuOpsFreeDupedHandle(struct gpuDevice *device,
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NvHandle hPhysHandle);
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NV_STATUS nvGpuOpsGetAttachedGpus(NvU8 *guidList, unsigned *numGpus);
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NV_STATUS nvGpuOpsGetGpuInfo(const NvProcessorUuid *gpuUuid,
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const gpuClientInfo *pGpuClientInfo,
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gpuInfo *pGpuInfo);
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NV_STATUS nvGpuOpsGetGpuIds(const NvU8 *pUuid, unsigned uuidLength, NvU32 *pDeviceId,
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NvU32 *pSubdeviceId);
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NV_STATUS nvGpuOpsOwnPageFaultIntr(struct gpuDevice *device, NvBool bOwnInterrupts);
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NV_STATUS nvGpuOpsServiceDeviceInterruptsRM(struct gpuDevice *device);
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NV_STATUS nvGpuOpsCheckEccErrorSlowpath(struct gpuChannel * channel, NvBool *bEccDbeSet);
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NV_STATUS nvGpuOpsSetPageDirectory(struct gpuAddressSpace * vaSpace,
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NvU64 physAddress, unsigned numEntries,
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NvBool bVidMemAperture, NvU32 pasid);
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NV_STATUS nvGpuOpsUnsetPageDirectory(struct gpuAddressSpace * vaSpace);
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NV_STATUS nvGpuOpsGetGmmuFmt(struct gpuAddressSpace * vaSpace, void ** pFmt);
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NV_STATUS nvGpuOpsInvalidateTlb(struct gpuAddressSpace * vaSpace);
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NV_STATUS nvGpuOpsGetFbInfo(struct gpuDevice *device, gpuFbInfo * fbInfo);
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NV_STATUS nvGpuOpsGetEccInfo(struct gpuDevice *device, gpuEccInfo * eccInfo);
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NV_STATUS nvGpuOpsInitFaultInfo(struct gpuDevice *device, gpuFaultInfo *pFaultInfo);
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NV_STATUS nvGpuOpsDestroyFaultInfo(struct gpuDevice *device,
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gpuFaultInfo *pFaultInfo);
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NV_STATUS nvGpuOpsHasPendingNonReplayableFaults(gpuFaultInfo *pFaultInfo, NvBool *hasPendingFaults);
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NV_STATUS nvGpuOpsGetNonReplayableFaults(gpuFaultInfo *pFaultInfo, void *faultBuffer, NvU32 *numFaults);
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NV_STATUS nvGpuOpsDupAddressSpace(struct gpuDevice *device,
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NvHandle hUserClient,
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NvHandle hUserVASpace,
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struct gpuAddressSpace **vaSpace,
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UvmGpuAddressSpaceInfo *vaSpaceInfo);
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NV_STATUS nvGpuOpsGetPmaObject(struct gpuDevice *device,
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void **pPma,
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const UvmPmaStatistics **pPmaPubStats);
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NV_STATUS nvGpuOpsInitAccessCntrInfo(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo);
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NV_STATUS nvGpuOpsDestroyAccessCntrInfo(struct gpuDevice *device,
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gpuAccessCntrInfo *pAccessCntrInfo);
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NV_STATUS nvGpuOpsOwnAccessCntrIntr(struct gpuSession *session,
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gpuAccessCntrInfo *pAccessCntrInfo,
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NvBool bOwnInterrupts);
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NV_STATUS nvGpuOpsEnableAccessCntr(struct gpuDevice *device,
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gpuAccessCntrInfo *pAccessCntrInfo,
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gpuAccessCntrConfig *pAccessCntrConfig);
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NV_STATUS nvGpuOpsDisableAccessCntr(struct gpuDevice *device, gpuAccessCntrInfo *pAccessCntrInfo);
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NV_STATUS nvGpuOpsP2pObjectCreate(struct gpuDevice *device1,
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struct gpuDevice *device2,
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NvHandle *hP2pObject);
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NV_STATUS nvGpuOpsP2pObjectDestroy(struct gpuSession *session,
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NvHandle hP2pObject);
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NV_STATUS nvGpuOpsGetExternalAllocPtes(struct gpuAddressSpace *vaSpace,
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NvHandle hDupedMemory,
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NvU64 offset,
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NvU64 size,
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gpuExternalMappingInfo *pGpuExternalMappingInfo);
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NV_STATUS nvGpuOpsRetainChannel(struct gpuAddressSpace *vaSpace,
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NvHandle hClient,
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NvHandle hChannel,
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gpuRetainedChannel **retainedChannel,
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gpuChannelInstanceInfo *channelInstanceInfo);
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void nvGpuOpsReleaseChannel(gpuRetainedChannel *retainedChannel);
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NV_STATUS nvGpuOpsBindChannelResources(gpuRetainedChannel *retainedChannel,
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gpuChannelResourceBindParams *channelResourceBindParams);
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void nvGpuOpsStopChannel(gpuRetainedChannel *retainedChannel, NvBool bImmediate);
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NV_STATUS nvGpuOpsGetChannelResourcePtes(struct gpuAddressSpace *vaSpace,
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NvP64 resourceDescriptor,
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NvU64 offset,
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NvU64 size,
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gpuExternalMappingInfo *pGpuExternalMappingInfo);
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NV_STATUS nvGpuOpsReportNonReplayableFault(struct gpuDevice *device,
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const void *pFaultPacket);
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// Private interface used for windows only
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#if defined(NV_WINDOWS)
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NV_STATUS nvGpuOpsGetRmHandleForSession(gpuSessionHandle hSession, NvHandle *hRmClient);
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NV_STATUS nvGpuOpsGetRmHandleForChannel(gpuChannelHandle hChannel, NvHandle *hRmChannel);
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#endif // WINDOWS
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// Interface used for SR-IOV heavy
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NV_STATUS nvGpuOpsPagingChannelAllocate(struct gpuDevice *device,
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const gpuPagingChannelAllocParams *params,
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gpuPagingChannelHandle *channelHandle,
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gpuPagingChannelInfo *channelinfo);
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void nvGpuOpsPagingChannelDestroy(UvmGpuPagingChannel *channel);
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NV_STATUS nvGpuOpsPagingChannelsMap(struct gpuAddressSpace *srcVaSpace,
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NvU64 srcAddress,
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struct gpuDevice *device,
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NvU64 *dstAddress);
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void nvGpuOpsPagingChannelsUnmap(struct gpuAddressSpace *srcVaSpace,
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NvU64 srcAddress,
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struct gpuDevice *device);
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NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel,
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char *methodStream,
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NvU32 methodStreamSize);
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#endif /* _NV_GPU_OPS_H_*/
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