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1281779330
in our memory model, all atomics are supposed to be full barriers;
stores are not release-only. this is important because store is used
as an unlock operation in places where it needs to acquire the waiter
count to determine if a futex wake is needed. at least in the
malloc-internal locks, but possibly elsewhere, soft deadlocks from
missing futex wake (breakable by poking the threads to restart the
syscall, e.g. by attaching a tracer) were reported to occur.
once the malloc lock is replaced with Jens Gustedt's new lock
implementation (see commit 47d0bcd476),
malloc will not be affected by the issue, but it's not clear that
other uses won't be. reducing the strength of the ordering properties
required from a_store would require a thorough analysis of how it's
used.
to fix the problem, I'm removing the powerpc[64]-specific a_store
definition; now, the top-level atomic.h will implement a_store using
a_barrier on both sides of the store.
it's not clear to me yet whether there might be issues with the other
atomics. it's possible that a_post_llsc needs to be replaced with a
full barrier to guarantee the formal semanics we want, but either way
I think the difference is unlikely to impact the way we use them.
39 lines
799 B
C
39 lines
799 B
C
#define a_ll a_ll
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static inline int a_ll(volatile int *p)
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{
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int v;
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__asm__ __volatile__ ("lwarx %0, 0, %2" : "=r"(v) : "m"(*p), "r"(p));
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return v;
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}
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#define a_sc a_sc
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static inline int a_sc(volatile int *p, int v)
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{
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int r;
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__asm__ __volatile__ (
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"stwcx. %2, 0, %3 ; mfcr %0"
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: "=r"(r), "=m"(*p) : "r"(v), "r"(p) : "memory", "cc");
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return r & 0x20000000; /* "bit 2" of "cr0" (backwards bit order) */
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}
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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#define a_pre_llsc a_barrier
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#define a_post_llsc a_post_llsc
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static inline void a_post_llsc()
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{
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__asm__ __volatile__ ("isync" : : : "memory");
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}
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#define a_clz_32 a_clz_32
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static inline int a_clz_32(uint32_t x)
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{
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__asm__ ("cntlzw %0, %1" : "=r"(x) : "r"(x));
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return x;
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}
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