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1315596b51
rather than having each arch provide its own atomic.h, there is a new shared atomic.h in src/internal which pulls arch-specific definitions from arc/$(ARCH)/atomic_arch.h. the latter can be extremely minimal, defining only a_cas or new ll/sc type primitives which the shared atomic.h will use to construct everything else. this commit avoids making heavy changes to the individual archs' atomic implementations. definitions which are identical or near-identical to what the new shared atomic.h would produce have been removed, but otherwise the changes made are just hooking up the arch-specific files to the new infrastructure. major changes to take advantage of the new system will come in subsequent commits.
169 lines
2.9 KiB
C
169 lines
2.9 KiB
C
#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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__asm__ __volatile__("dmb ish");
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}
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#define a_cas a_cas
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static inline int a_cas(volatile int *p, int t, int s)
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{
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int old;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%3\n"
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" cmp %0,%1\n"
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" bne 1f\n"
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" strex %0,%2,%3\n"
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" cmp %0, #0\n"
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" bne 1b\n"
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" mov %0, %1\n"
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"1: dmb ish\n"
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: "=&r"(old)
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: "r"(t), "r"(s), "Q"(*p)
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: "memory", "cc" );
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return old;
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}
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#define a_swap a_swap
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static inline int a_swap(volatile int *x, int v)
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{
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int old, tmp;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%3\n"
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" strex %1,%2,%3\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(old), "=&r"(tmp)
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: "r"(v), "Q"(*x)
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: "memory", "cc" );
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return old;
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}
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#define a_fetch_add a_fetch_add
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static inline int a_fetch_add(volatile int *x, int v)
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{
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int old, tmp;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%3\n"
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" add %0,%0,%2\n"
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" strex %1,%0,%3\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(old), "=&r"(tmp)
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: "r"(v), "Q"(*x)
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: "memory", "cc" );
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return old-v;
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}
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#define a_inc a_inc
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static inline void a_inc(volatile int *x)
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{
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int tmp, tmp2;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%2\n"
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" add %0,%0,#1\n"
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" strex %1,%0,%2\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(tmp), "=&r"(tmp2)
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: "Q"(*x)
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: "memory", "cc" );
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}
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#define a_dec a_dec
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static inline void a_dec(volatile int *x)
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{
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int tmp, tmp2;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%2\n"
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" sub %0,%0,#1\n"
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" strex %1,%0,%2\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(tmp), "=&r"(tmp2)
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: "Q"(*x)
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: "memory", "cc" );
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}
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#define a_and a_and
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static inline void a_and(volatile int *x, int v)
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{
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int tmp, tmp2;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%3\n"
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" and %0,%0,%2\n"
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" strex %1,%0,%3\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(tmp), "=&r"(tmp2)
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: "r"(v), "Q"(*x)
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: "memory", "cc" );
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}
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#define a_or a_or
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static inline void a_or(volatile int *x, int v)
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{
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int tmp, tmp2;
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__asm__ __volatile__(
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" dmb ish\n"
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"1: ldrex %0,%3\n"
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" orr %0,%0,%2\n"
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" strex %1,%0,%3\n"
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" cmp %1, #0\n"
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" bne 1b\n"
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" dmb ish\n"
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: "=&r"(tmp), "=&r"(tmp2)
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: "r"(v), "Q"(*x)
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: "memory", "cc" );
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}
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#define a_store a_store
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static inline void a_store(volatile int *p, int x)
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{
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__asm__ __volatile__(
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" dmb ish\n"
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" str %1,%0\n"
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" dmb ish\n"
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: "=m"(*p)
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: "r"(x)
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: "memory", "cc" );
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}
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#else
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int __a_cas(int, int, volatile int *) __attribute__((__visibility__("hidden")));
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#define __k_cas __a_cas
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#define a_barrier a_barrier
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static inline void a_barrier()
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{
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__asm__ __volatile__("bl __a_barrier"
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: : : "memory", "cc", "ip", "lr" );
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}
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#define a_cas a_cas
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static inline int a_cas(volatile int *p, int t, int s)
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{
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int old;
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for (;;) {
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if (!__k_cas(t, s, p))
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return t;
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if ((old=*p) != t)
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return old;
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}
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}
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#endif
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