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fix tabs/spaces in memcpy.s
this file had been a mess that went unnoticed ever since it was imported. some lines used spaces for indention while others used tabs, and tabs were used for alignment.
This commit is contained in:
Rich Felker
parent
921c26e0e7
commit
9911754b19
@ -49,113 +49,113 @@ memcpy:
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* ARM ABI. Since we have to save R0, we might as well save R4
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* which we can use for better pipelining of the reads below
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*/
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.fnstart
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.save {r0, r4, lr}
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stmfd sp!, {r0, r4, lr}
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/* Making room for r5-r11 which will be spilled later */
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.pad #28
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sub sp, sp, #28
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.fnstart
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.save {r0, r4, lr}
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stmfd sp!, {r0, r4, lr}
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/* Making room for r5-r11 which will be spilled later */
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.pad #28
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sub sp, sp, #28
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/* it simplifies things to take care of len<4 early */
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cmp r2, #4
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blo copy_last_3_and_return
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/* it simplifies things to take care of len<4 early */
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cmp r2, #4
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blo copy_last_3_and_return
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/* compute the offset to align the source
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* offset = (4-(src&3))&3 = -src & 3
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*/
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rsb r3, r1, #0
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ands r3, r3, #3
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beq src_aligned
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/* compute the offset to align the source
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* offset = (4-(src&3))&3 = -src & 3
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*/
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rsb r3, r1, #0
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ands r3, r3, #3
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beq src_aligned
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/* align source to 32 bits. We need to insert 2 instructions between
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* a ldr[b|h] and str[b|h] because byte and half-word instructions
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* stall 2 cycles.
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*/
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movs r12, r3, lsl #31
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sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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.word 0x44d13001 /* ldrbmi r3, [r1], #1 */
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.word 0x24d14001 /* ldrbcs r4, [r1], #1 */
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.word 0x24d1c001 /* ldrbcs r12,[r1], #1 */
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.word 0x44c03001 /* strbmi r3, [r0], #1 */
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.word 0x24c04001 /* strbcs r4, [r0], #1 */
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.word 0x24c0c001 /* strbcs r12,[r0], #1 */
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/* align source to 32 bits. We need to insert 2 instructions between
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* a ldr[b|h] and str[b|h] because byte and half-word instructions
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* stall 2 cycles.
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*/
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movs r12, r3, lsl #31
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sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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.word 0x44d13001 /* ldrbmi r3, [r1], #1 */
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.word 0x24d14001 /* ldrbcs r4, [r1], #1 */
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.word 0x24d1c001 /* ldrbcs r12,[r1], #1 */
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.word 0x44c03001 /* strbmi r3, [r0], #1 */
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.word 0x24c04001 /* strbcs r4, [r0], #1 */
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.word 0x24c0c001 /* strbcs r12,[r0], #1 */
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src_aligned:
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/* see if src and dst are aligned together (congruent) */
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eor r12, r0, r1
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tst r12, #3
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bne non_congruent
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eor r12, r0, r1
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tst r12, #3
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bne non_congruent
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* align the destination to a cache-line */
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rsb r3, r0, #0
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ands r3, r3, #0x1C
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beq congruent_aligned32
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cmp r3, r2
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andhi r3, r2, #0x1C
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/* align the destination to a cache-line */
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rsb r3, r0, #0
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ands r3, r3, #0x1C
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beq congruent_aligned32
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cmp r3, r2
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andhi r3, r2, #0x1C
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/* conditionnaly copies 0 to 7 words (length in r3) */
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movs r12, r3, lsl #28
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ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmi r1!, {r8, r9} /* 8 bytes */
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stmcs r0!, {r4, r5, r6, r7}
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stmmi r0!, {r8, r9}
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tst r3, #0x4
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ldrne r10,[r1], #4 /* 4 bytes */
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strne r10,[r0], #4
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sub r2, r2, r3
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/* conditionnaly copies 0 to 7 words (length in r3) */
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movs r12, r3, lsl #28
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ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmi r1!, {r8, r9} /* 8 bytes */
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stmcs r0!, {r4, r5, r6, r7}
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stmmi r0!, {r8, r9}
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tst r3, #0x4
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ldrne r10,[r1], #4 /* 4 bytes */
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strne r10,[r0], #4
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sub r2, r2, r3
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congruent_aligned32:
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/*
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* here source is aligned to 32 bytes.
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*/
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* here source is aligned to 32 bytes.
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*/
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cached_aligned32:
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subs r2, r2, #32
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blo less_than_32_left
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subs r2, r2, #32
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blo less_than_32_left
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/*
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* We preload a cache-line up to 64 bytes ahead. On the 926, this will
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* stall only until the requested world is fetched, but the linefill
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* continues in the the background.
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* While the linefill is going, we write our previous cache-line
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* into the write-buffer (which should have some free space).
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* When the linefill is done, the writebuffer will
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* start dumping its content into memory
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*
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* While all this is going, we then load a full cache line into
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* 8 registers, this cache line should be in the cache by now
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* (or partly in the cache).
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*
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* This code should work well regardless of the source/dest alignment.
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*
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*/
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/*
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* We preload a cache-line up to 64 bytes ahead. On the 926, this will
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* stall only until the requested world is fetched, but the linefill
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* continues in the the background.
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* While the linefill is going, we write our previous cache-line
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* into the write-buffer (which should have some free space).
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* When the linefill is done, the writebuffer will
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* start dumping its content into memory
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*
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* While all this is going, we then load a full cache line into
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* 8 registers, this cache line should be in the cache by now
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* (or partly in the cache).
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*
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* This code should work well regardless of the source/dest alignment.
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*
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*/
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/* Align the preload register to a cache-line because the cpu does
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* "critical word first" (the first word requested is loaded first).
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*/
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@ bic r12, r1, #0x1F
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@ add r12, r12, #64
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/* Align the preload register to a cache-line because the cpu does
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* "critical word first" (the first word requested is loaded first).
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*/
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@ bic r12, r1, #0x1F
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@ add r12, r12, #64
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1: ldmia r1!, { r4-r11 }
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subs r2, r2, #32
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1: ldmia r1!, { r4-r11 }
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subs r2, r2, #32
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/*
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* NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
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* for ARM9 preload will not be safely guarded by the preceding subs.
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* When it is safely guarded the only possibility to have SIGSEGV here
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* is because the caller overstates the length.
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*/
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@ ldrhi r3, [r12], #32 /* cheap ARM9 preload */
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stmia r0!, { r4-r11 }
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bhs 1b
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/*
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* NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
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* for ARM9 preload will not be safely guarded by the preceding subs.
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* When it is safely guarded the only possibility to have SIGSEGV here
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* is because the caller overstates the length.
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*/
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@ ldrhi r3, [r12], #32 /* cheap ARM9 preload */
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stmia r0!, { r4-r11 }
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bhs 1b
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add r2, r2, #32
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add r2, r2, #32
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less_than_32_left:
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/*
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@ -166,30 +166,30 @@ less_than_32_left:
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* be a common case (if not executed the code below takes
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* about 16 cycles)
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*/
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tst r2, #0x1F
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beq 1f
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tst r2, #0x1F
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beq 1f
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/* conditionnaly copies 0 to 31 bytes */
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movs r12, r2, lsl #28
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ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmi r1!, {r8, r9} /* 8 bytes */
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stmcs r0!, {r4, r5, r6, r7}
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stmmi r0!, {r8, r9}
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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.word 0x40d140b2 /* ldrhmi r4, [r1], #2 */ /* 2 bytes */
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strcs r3, [r0], #4
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.word 0x40c040b2 /* strhmi r4, [r0], #2 */
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tst r2, #0x1
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.word 0x15d13000 /* ldrbne r3, [r1] */ /* last byte */
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.word 0x15c03000 /* strbne r3, [r0] */
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/* conditionnaly copies 0 to 31 bytes */
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movs r12, r2, lsl #28
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ldmcs r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmi r1!, {r8, r9} /* 8 bytes */
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stmcs r0!, {r4, r5, r6, r7}
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stmmi r0!, {r8, r9}
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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.word 0x40d140b2 /* ldrhmi r4, [r1], #2 */ /* 2 bytes */
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strcs r3, [r0], #4
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.word 0x40c040b2 /* strhmi r4, [r0], #2 */
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tst r2, #0x1
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.word 0x15d13000 /* ldrbne r3, [r1] */ /* last byte */
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.word 0x15c03000 /* strbne r3, [r0] */
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/* we're done! restore everything and return */
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1: ldmfd sp!, {r5-r11}
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ldmfd sp!, {r0, r4, lr}
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tst lr, #1
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moveq pc, lr
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bx lr
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/* we're done! restore everything and return */
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1: ldmfd sp!, {r5-r11}
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ldmfd sp!, {r0, r4, lr}
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tst lr, #1
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moveq pc, lr
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bx lr
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/********************************************************************/
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@ -202,180 +202,180 @@ non_congruent:
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* (the number of bytes written is always smaller, because we have
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* partial words in the shift queue)
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*/
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cmp r2, #4
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blo copy_last_3_and_return
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cmp r2, #4
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blo copy_last_3_and_return
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* compute shifts needed to align src to dest */
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rsb r5, r0, #0
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and r5, r5, #3 /* r5 = # bytes in partial words */
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mov r12, r5, lsl #3 /* r12 = right */
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rsb lr, r12, #32 /* lr = left */
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/* compute shifts needed to align src to dest */
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rsb r5, r0, #0
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and r5, r5, #3 /* r5 = # bytes in partial words */
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mov r12, r5, lsl #3 /* r12 = right */
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rsb lr, r12, #32 /* lr = left */
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/* read the first word */
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ldr r3, [r1], #4
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sub r2, r2, #4
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/* read the first word */
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ldr r3, [r1], #4
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sub r2, r2, #4
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/* write a partial word (0 to 3 bytes), such that destination
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* becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
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*/
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movs r5, r5, lsl #31
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.word 0x44c03001 /* strbmi r3, [r0], #1 */
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movmi r3, r3, lsr #8
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.word 0x24c03001 /* strbcs r3, [r0], #1 */
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movcs r3, r3, lsr #8
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.word 0x24c03001 /* strbcs r3, [r0], #1 */
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movcs r3, r3, lsr #8
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/* write a partial word (0 to 3 bytes), such that destination
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* becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
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*/
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movs r5, r5, lsl #31
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.word 0x44c03001 /* strbmi r3, [r0], #1 */
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movmi r3, r3, lsr #8
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.word 0x24c03001 /* strbcs r3, [r0], #1 */
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movcs r3, r3, lsr #8
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.word 0x24c03001 /* strbcs r3, [r0], #1 */
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movcs r3, r3, lsr #8
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cmp r2, #4
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blo partial_word_tail
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cmp r2, #4
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blo partial_word_tail
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/* Align destination to 32 bytes (cache line boundary) */
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1: tst r0, #0x1c
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beq 2f
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ldr r5, [r1], #4
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sub r2, r2, #4
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orr r4, r3, r5, lsl lr
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mov r3, r5, lsr r12
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str r4, [r0], #4
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cmp r2, #4
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bhs 1b
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blo partial_word_tail
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/* Align destination to 32 bytes (cache line boundary) */
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1: tst r0, #0x1c
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beq 2f
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ldr r5, [r1], #4
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sub r2, r2, #4
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orr r4, r3, r5, lsl lr
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mov r3, r5, lsr r12
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str r4, [r0], #4
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cmp r2, #4
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bhs 1b
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blo partial_word_tail
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/* copy 32 bytes at a time */
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2: subs r2, r2, #32
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blo less_than_thirtytwo
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2: subs r2, r2, #32
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blo less_than_thirtytwo
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/* Use immediate mode for the shifts, because there is an extra cycle
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* for register shifts, which could account for up to 50% of
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* performance hit.
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*/
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/* Use immediate mode for the shifts, because there is an extra cycle
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* for register shifts, which could account for up to 50% of
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* performance hit.
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*/
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cmp r12, #24
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beq loop24
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cmp r12, #8
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beq loop8
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cmp r12, #24
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beq loop24
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cmp r12, #8
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beq loop8
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loop16:
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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subs r2, r2, #32
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ldrhs r12, [r1], #4
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orr r3, r3, r4, lsl #16
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mov r4, r4, lsr #16
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orr r4, r4, r5, lsl #16
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mov r5, r5, lsr #16
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orr r5, r5, r6, lsl #16
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mov r6, r6, lsr #16
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orr r6, r6, r7, lsl #16
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mov r7, r7, lsr #16
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orr r7, r7, r8, lsl #16
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mov r8, r8, lsr #16
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orr r8, r8, r9, lsl #16
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mov r9, r9, lsr #16
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orr r9, r9, r10, lsl #16
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mov r10, r10, lsr #16
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orr r10, r10, r11, lsl #16
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stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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mov r3, r11, lsr #16
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bhs 1b
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b less_than_thirtytwo
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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subs r2, r2, #32
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ldrhs r12, [r1], #4
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orr r3, r3, r4, lsl #16
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mov r4, r4, lsr #16
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orr r4, r4, r5, lsl #16
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mov r5, r5, lsr #16
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orr r5, r5, r6, lsl #16
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mov r6, r6, lsr #16
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orr r6, r6, r7, lsl #16
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mov r7, r7, lsr #16
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orr r7, r7, r8, lsl #16
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mov r8, r8, lsr #16
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orr r8, r8, r9, lsl #16
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mov r9, r9, lsr #16
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orr r9, r9, r10, lsl #16
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mov r10, r10, lsr #16
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orr r10, r10, r11, lsl #16
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stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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mov r3, r11, lsr #16
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bhs 1b
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b less_than_thirtytwo
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loop8:
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
|
||||
subs r2, r2, #32
|
||||
ldrhs r12, [r1], #4
|
||||
orr r3, r3, r4, lsl #24
|
||||
mov r4, r4, lsr #8
|
||||
orr r4, r4, r5, lsl #24
|
||||
mov r5, r5, lsr #8
|
||||
orr r5, r5, r6, lsl #24
|
||||
mov r6, r6, lsr #8
|
||||
orr r6, r6, r7, lsl #24
|
||||
mov r7, r7, lsr #8
|
||||
orr r7, r7, r8, lsl #24
|
||||
mov r8, r8, lsr #8
|
||||
orr r8, r8, r9, lsl #24
|
||||
mov r9, r9, lsr #8
|
||||
orr r9, r9, r10, lsl #24
|
||||
mov r10, r10, lsr #8
|
||||
orr r10, r10, r11, lsl #24
|
||||
stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
|
||||
mov r3, r11, lsr #8
|
||||
bhs 1b
|
||||
b less_than_thirtytwo
|
||||
ldr r12, [r1], #4
|
||||
1: mov r4, r12
|
||||
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
|
||||
subs r2, r2, #32
|
||||
ldrhs r12, [r1], #4
|
||||
orr r3, r3, r4, lsl #24
|
||||
mov r4, r4, lsr #8
|
||||
orr r4, r4, r5, lsl #24
|
||||
mov r5, r5, lsr #8
|
||||
orr r5, r5, r6, lsl #24
|
||||
mov r6, r6, lsr #8
|
||||
orr r6, r6, r7, lsl #24
|
||||
mov r7, r7, lsr #8
|
||||
orr r7, r7, r8, lsl #24
|
||||
mov r8, r8, lsr #8
|
||||
orr r8, r8, r9, lsl #24
|
||||
mov r9, r9, lsr #8
|
||||
orr r9, r9, r10, lsl #24
|
||||
mov r10, r10, lsr #8
|
||||
orr r10, r10, r11, lsl #24
|
||||
stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
|
||||
mov r3, r11, lsr #8
|
||||
bhs 1b
|
||||
b less_than_thirtytwo
|
||||
|
||||
loop24:
|
||||
ldr r12, [r1], #4
|
||||
1: mov r4, r12
|
||||
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
|
||||
subs r2, r2, #32
|
||||
ldrhs r12, [r1], #4
|
||||
orr r3, r3, r4, lsl #8
|
||||
mov r4, r4, lsr #24
|
||||
orr r4, r4, r5, lsl #8
|
||||
mov r5, r5, lsr #24
|
||||
orr r5, r5, r6, lsl #8
|
||||
mov r6, r6, lsr #24
|
||||
orr r6, r6, r7, lsl #8
|
||||
mov r7, r7, lsr #24
|
||||
orr r7, r7, r8, lsl #8
|
||||
mov r8, r8, lsr #24
|
||||
orr r8, r8, r9, lsl #8
|
||||
mov r9, r9, lsr #24
|
||||
orr r9, r9, r10, lsl #8
|
||||
mov r10, r10, lsr #24
|
||||
orr r10, r10, r11, lsl #8
|
||||
stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
|
||||
mov r3, r11, lsr #24
|
||||
bhs 1b
|
||||
ldr r12, [r1], #4
|
||||
1: mov r4, r12
|
||||
ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
|
||||
subs r2, r2, #32
|
||||
ldrhs r12, [r1], #4
|
||||
orr r3, r3, r4, lsl #8
|
||||
mov r4, r4, lsr #24
|
||||
orr r4, r4, r5, lsl #8
|
||||
mov r5, r5, lsr #24
|
||||
orr r5, r5, r6, lsl #8
|
||||
mov r6, r6, lsr #24
|
||||
orr r6, r6, r7, lsl #8
|
||||
mov r7, r7, lsr #24
|
||||
orr r7, r7, r8, lsl #8
|
||||
mov r8, r8, lsr #24
|
||||
orr r8, r8, r9, lsl #8
|
||||
mov r9, r9, lsr #24
|
||||
orr r9, r9, r10, lsl #8
|
||||
mov r10, r10, lsr #24
|
||||
orr r10, r10, r11, lsl #8
|
||||
stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
|
||||
mov r3, r11, lsr #24
|
||||
bhs 1b
|
||||
|
||||
less_than_thirtytwo:
|
||||
/* copy the last 0 to 31 bytes of the source */
|
||||
rsb r12, lr, #32 /* we corrupted r12, recompute it */
|
||||
add r2, r2, #32
|
||||
cmp r2, #4
|
||||
blo partial_word_tail
|
||||
rsb r12, lr, #32 /* we corrupted r12, recompute it */
|
||||
add r2, r2, #32
|
||||
cmp r2, #4
|
||||
blo partial_word_tail
|
||||
|
||||
1: ldr r5, [r1], #4
|
||||
sub r2, r2, #4
|
||||
orr r4, r3, r5, lsl lr
|
||||
mov r3, r5, lsr r12
|
||||
str r4, [r0], #4
|
||||
cmp r2, #4
|
||||
bhs 1b
|
||||
1: ldr r5, [r1], #4
|
||||
sub r2, r2, #4
|
||||
orr r4, r3, r5, lsl lr
|
||||
mov r3, r5, lsr r12
|
||||
str r4, [r0], #4
|
||||
cmp r2, #4
|
||||
bhs 1b
|
||||
|
||||
partial_word_tail:
|
||||
/* we have a partial word in the input buffer */
|
||||
movs r5, lr, lsl #(31-3)
|
||||
movs r5, lr, lsl #(31-3)
|
||||
.word 0x44c03001 /* strbmi r3, [r0], #1 */
|
||||
movmi r3, r3, lsr #8
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
movcs r3, r3, lsr #8
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
movmi r3, r3, lsr #8
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
movcs r3, r3, lsr #8
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
|
||||
/* Refill spilled registers from the stack. Don't update sp. */
|
||||
ldmfd sp, {r5-r11}
|
||||
/* Refill spilled registers from the stack. Don't update sp. */
|
||||
ldmfd sp, {r5-r11}
|
||||
|
||||
copy_last_3_and_return:
|
||||
movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
|
||||
.word 0x44d12001 /* ldrbmi r2, [r1], #1 */
|
||||
.word 0x24d13001 /* ldrbcs r3, [r1], #1 */
|
||||
.word 0x25d1c000 /* ldrbcs r12,[r1] */
|
||||
.word 0x44c02001 /* strbmi r2, [r0], #1 */
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
.word 0x25c0c000 /* strbcs r12,[r0] */
|
||||
movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
|
||||
.word 0x44d12001 /* ldrbmi r2, [r1], #1 */
|
||||
.word 0x24d13001 /* ldrbcs r3, [r1], #1 */
|
||||
.word 0x25d1c000 /* ldrbcs r12,[r1] */
|
||||
.word 0x44c02001 /* strbmi r2, [r0], #1 */
|
||||
.word 0x24c03001 /* strbcs r3, [r0], #1 */
|
||||
.word 0x25c0c000 /* strbcs r12,[r0] */
|
||||
|
||||
/* we're done! restore sp and spilled registers and return */
|
||||
add sp, sp, #28
|
||||
ldmfd sp!, {r0, r4, lr}
|
||||
tst lr, #1
|
||||
moveq pc, lr
|
||||
bx lr
|
||||
/* we're done! restore sp and spilled registers and return */
|
||||
add sp, sp, #28
|
||||
ldmfd sp!, {r0, r4, lr}
|
||||
tst lr, #1
|
||||
moveq pc, lr
|
||||
bx lr
|
||||
|
||||
Loading…
Reference in New Issue
Block a user