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add thumb2 support to arm assembler memcpy

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For Thumb2 compatibility, replace two instances of a single
instruction "orr with a variable shift" with the two instruction
equivalent. Neither of the replacements are in a performance critical
loop.
This commit is contained in:
Andre McCurdy 2019-09-13 11:44:31 -07:00 committed by Rich Felker
parent 0ff18be208
commit 91e662d1d9
2 changed files with 9 additions and 6 deletions
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2
src/string/arm/memcpy.c
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@ -1,3 +1,3 @@
#if __ARMEB__ || __thumb__ #if __ARMEB__
#include "../memcpy.c" #include "../memcpy.c"
#endif #endif

13
src/string/arm/memcpy_le.S
View File

@ -1,4 +1,4 @@
#if !__ARMEB__ && !__thumb__ #if !__ARMEB__
/* /*
* Copyright (C) 2008 The Android Open Source Project * Copyright (C) 2008 The Android Open Source Project
@ -40,8 +40,9 @@
* This file has been modified from the original for use in musl libc. * This file has been modified from the original for use in musl libc.
* The main changes are: addition of .type memcpy,%function to make the * The main changes are: addition of .type memcpy,%function to make the
* code safely callable from thumb mode, adjusting the return * code safely callable from thumb mode, adjusting the return
* instructions to be compatible with pre-thumb ARM cpus, and removal * instructions to be compatible with pre-thumb ARM cpus, removal of
* of prefetch code that is not compatible with older cpus. * prefetch code that is not compatible with older cpus and support for
* building as thumb 2.
*/ */
.syntax unified .syntax unified
@ -241,7 +242,8 @@ non_congruent:
beq 2f beq 2f
ldr r5, [r1], #4 ldr r5, [r1], #4
sub r2, r2, #4 sub r2, r2, #4
orr r4, r3, r5, lsl lr mov r4, r5, lsl lr
orr r4, r4, r3
mov r3, r5, lsr r12 mov r3, r5, lsr r12
str r4, [r0], #4 str r4, [r0], #4
cmp r2, #4 cmp r2, #4
@ -348,7 +350,8 @@ less_than_thirtytwo:
1: ldr r5, [r1], #4 1: ldr r5, [r1], #4
sub r2, r2, #4 sub r2, r2, #4
orr r4, r3, r5, lsl lr mov r4, r5, lsl lr
orr r4, r4, r3
mov r3, r5, lsr r12 mov r3, r5, lsr r12
str r4, [r0], #4 str r4, [r0], #4
cmp r2, #4 cmp r2, #4