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mitigate performance regression in libc-internal locks on x86_64

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commit 3c43c0761e fixed missing
synchronization in the atomic store operation for i386 and x86_64, but
opted to use mfence for the barrier on x86_64 where it's always
available. however, in practice mfence is significantly slower than
the barrier approach used on i386 (a nop-like lock orl operation).
this commit changes x86_64 (and x32) to use the faster barrier.
This commit is contained in:
Rich Felker 2015-08-16 18:15:18 +00:00
parent c13f2af1fe
commit 5a9c8c05a5
2 changed files with 2 additions and 2 deletions
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2
arch/x32/atomic.h
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@ -83,7 +83,7 @@ static inline void a_dec(volatile int *x)
static inline void a_store(volatile int *p, int x)
{
__asm__( "mov %1, %0 ; mfence" : "=m"(*p) : "r"(x) : "memory" );
__asm__( "mov %1, %0 ; lock ; orl $0,(%%rsp)" : "=m"(*p) : "r"(x) : "memory" );
}
static inline void a_spin()

2
arch/x86_64/atomic.h
View File

@ -83,7 +83,7 @@ static inline void a_dec(volatile int *x)
static inline void a_store(volatile int *p, int x)
{
__asm__( "mov %1, %0 ; mfence" : "=m"(*p) : "r"(x) : "memory" );
__asm__( "mov %1, %0 ; lock ; orl $0,(%%rsp)" : "=m"(*p) : "r"(x) : "memory" );
}
static inline void a_spin()