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stm32: Add low-level hardware I2C slave driver.

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This commit is contained in:
Damien George 2018-05-24 23:07:29 +10:00
parent 4200018a05
commit f47eeab0ad
2 changed files with 161 additions and 0 deletions
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101
ports/stm32/i2cslave.c Normal file
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "i2cslave.h"
#if defined(STM32F4)
void i2c_slave_init_helper(i2c_slave_t *i2c, int addr) {
i2c->CR2 = I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN | 4 << I2C_CR2_FREQ_Pos;
i2c->OAR1 = 1 << 14 | addr << 1;
i2c->OAR2 = 0;
i2c->CR1 = I2C_CR1_ACK | I2C_CR1_PE;
}
void i2c_slave_ev_irq_handler(i2c_slave_t *i2c) {
uint32_t sr1 = i2c->SR1;
if (sr1 & I2C_SR1_ADDR) {
// Address matched
// Read of SR1, SR2 needed to clear ADDR bit
sr1 = i2c->SR1;
uint32_t sr2 = i2c->SR2;
i2c_slave_process_addr_match((sr2 >> I2C_SR2_TRA_Pos) & 1);
}
if (sr1 & I2C_SR1_STOPF) {
// STOPF only set at end of RX mode (in TX mode AF is set on NACK)
// Read of SR1, write CR1 needed to clear STOPF bit
sr1 = i2c->SR1;
i2c->CR1 &= ~I2C_CR1_ACK;
i2c_slave_process_rx_end();
i2c->CR1 |= I2C_CR1_ACK;
}
if (sr1 & I2C_SR1_TXE) {
i2c->DR = i2c_slave_process_tx_byte();
}
if (sr1 & I2C_SR1_RXNE) {
i2c_slave_process_rx_byte(i2c->DR);
}
}
#elif defined(STM32F7)
void i2c_slave_init_helper(i2c_slave_t *i2c, int addr) {
i2c->CR1 = I2C_CR1_STOPIE | I2C_CR1_ADDRIE | I2C_CR1_RXIE | I2C_CR1_TXIE;
i2c->CR2 = 0;
i2c->OAR1 = I2C_OAR1_OA1EN | addr << 1;
i2c->OAR2 = 0;
i2c->CR1 |= I2C_CR1_PE;
}
void i2c_slave_ev_irq_handler(i2c_slave_t *i2c) {
uint32_t isr = i2c->ISR;
if (isr & I2C_ISR_ADDR) {
// Address matched
// Set TXE so that TXDR is flushed and ready for the first byte
i2c->ISR = I2C_ISR_TXE;
i2c->ICR = I2C_ICR_ADDRCF;
i2c_slave_process_addr_match(0);
}
if (isr & I2C_ISR_STOPF) {
// STOPF only set for STOP condition, not a repeated START
i2c->ICR = I2C_ICR_STOPCF;
i2c->OAR1 &= ~I2C_OAR1_OA1EN;
if (i2c->ISR & I2C_ISR_DIR) {
//i2c_slave_process_tx_end();
} else {
i2c_slave_process_rx_end();
}
i2c->OAR1 |= I2C_OAR1_OA1EN;
}
if (isr & I2C_ISR_TXIS) {
i2c->TXDR = i2c_slave_process_tx_byte();
}
if (isr & I2C_ISR_RXNE) {
i2c_slave_process_rx_byte(i2c->RXDR);
}
}
#endif

60
ports/stm32/i2cslave.h Normal file
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/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2018 Damien P. George
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef MICROPY_INCLUDED_STM32_I2CSLAVE_H
#define MICROPY_INCLUDED_STM32_I2CSLAVE_H
#include STM32_HAL_H
typedef I2C_TypeDef i2c_slave_t;
void i2c_slave_init_helper(i2c_slave_t *i2c, int addr);
static inline void i2c_slave_init(i2c_slave_t *i2c, int irqn, int irq_pri, int addr) {
int en_bit = RCC_APB1ENR_I2C1EN_Pos + ((uintptr_t)i2c - I2C1_BASE) / (I2C2_BASE - I2C1_BASE);
RCC->APB1ENR |= 1 << en_bit;
volatile uint32_t tmp = RCC->APB1ENR; // Delay after enabling clock
(void)tmp;
i2c_slave_init_helper(i2c, addr);
NVIC_SetPriority(irqn, irq_pri);
NVIC_EnableIRQ(irqn);
}
static inline void i2c_slave_shutdown(i2c_slave_t *i2c, int irqn) {
i2c->CR1 = 0;
NVIC_DisableIRQ(irqn);
}
void i2c_slave_ev_irq_handler(i2c_slave_t *i2c);
// These should be provided externally
int i2c_slave_process_addr_match(int rw);
int i2c_slave_process_rx_byte(uint8_t val);
void i2c_slave_process_rx_end(void);
uint8_t i2c_slave_process_tx_byte(void);
#endif // MICROPY_INCLUDED_STM32_I2CSLAVE_H