stm32/powerctrl: Improve support for changing system freq on H7 MCUs.
This commit improves pllvalues.py to generate PLL values for H7 MCUs that are valid (VCO in and out are in range) and extend for the entire range of SYSCLK values up to 400MHz (up to 480MHz is currently unsupported).
This commit is contained in:
Damien George
parent
03b73ce329
commit
2c8c2b935e
@ -649,7 +649,7 @@ CMSIS_MCU_HDR = $(CMSIS_DIR)/$(CMSIS_MCU_LOWER).h
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modmachine.c: $(GEN_PLLFREQTABLE_HDR)
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$(GEN_PLLFREQTABLE_HDR): $(PLLVALUES) | $(HEADER_BUILD)
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$(ECHO) "GEN $@"
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$(Q)$(PYTHON) $(PLLVALUES) -c $(if $(filter $(MCU_SERIES),f7),--relax-pll48,) file:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h > $@
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$(Q)$(PYTHON) $(PLLVALUES) -c -m $(MCU_SERIES) file:$(BOARD_DIR)/stm32$(MCU_SERIES)xx_hal_conf.h > $@
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$(BUILD)/modstm.o: $(GEN_STMCONST_HDR)
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# Use a pattern rule here so that make will only call make-stmconst.py once to
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@ -7,6 +7,36 @@ for the machine.freq() function.
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from __future__ import print_function
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import re
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class MCU:
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def __init__(self, range_sysclk, range_m, range_n, range_p, range_q, range_vco_in, range_vco_out):
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self.range_sysclk = range_sysclk
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self.range_m = range_m
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self.range_n = range_n
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self.range_p = range_p
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self.range_q = range_q
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self.range_vco_in = range_vco_in
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self.range_vco_out = range_vco_out
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mcu_default = MCU(
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range_sysclk=range(2, 216 + 1, 2),
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range_m=range(2, 63 + 1),
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range_n=range(192, 432 + 1),
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range_p=range(2, 8 + 1, 2),
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range_q=range(2, 15 + 1),
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range_vco_in=range(1, 2 + 1),
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range_vco_out=range(192, 432 + 1),
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)
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mcu_h7 = MCU(
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range_sysclk=range(2, 400 + 1, 2), # above 400MHz currently unsupported
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range_m=range(1, 63 + 1),
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range_n=range(4, 512 + 1),
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range_p=range(2, 128 + 1, 2),
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range_q=range(1, 128 + 1),
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range_vco_in=range(1, 16 + 1),
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range_vco_out=range(150, 960 + 1), # 150-420=medium, 192-960=wide
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)
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def close_int(x):
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return abs(x - round(x)) < 0.01
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@ -42,41 +72,40 @@ def compute_pll(hse, sys):
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# improved version that doesn't require N/M to be an integer
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def compute_pll2(hse, sys, relax_pll48):
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# Loop over the allowed values of P, looking for a valid PLL configuration
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# that gives the desired "sys" frequency. We use floats for P to force
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# floating point arithmetic on Python 2.
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# that gives the desired "sys" frequency.
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fallback = None
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for P in (2.0, 4.0, 6.0, 8.0):
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NbyM = sys * P / hse
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for P in mcu.range_p:
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# VCO_OUT must be between 192MHz and 432MHz
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if not (192 <= hse * NbyM <= 432):
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if not sys * P in mcu.range_vco_out:
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continue
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NbyM = float(sys * P) / hse # float for Python 2
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# scan M
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M = int(192 // NbyM) # starting value
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while 2 * M < hse:
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M += 1
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# VCO_IN must be between 1MHz and 2MHz (2MHz recommended)
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for M in range(M, hse + 1):
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if NbyM * M < 191.99 or not close_int(NbyM * M):
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continue
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M_min = mcu.range_n[0] // int(round(NbyM)) # starting value
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while mcu.range_vco_in[-1] * M_min < hse:
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M_min += 1
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# VCO_IN must be >=1MHz, but higher is better for stability so start high (low M)
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for M in range(M_min, hse + 1):
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# compute N
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N = NbyM * M
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# N must be an integer
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if not close_int(N):
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continue
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N = round(N)
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# N is restricted
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if not (192 <= N <= 432):
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if N not in mcu.range_n:
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continue
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Q = (sys * P / 48)
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Q = float(sys * P) / 48 # float for Python 2
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# Q must be an integer in a set range
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if not (2 <= Q <= 15):
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if close_int(Q) and round(Q) in mcu.range_q:
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# found valid values
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return (M, N, P, Q)
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# Re-try Q to get at most 48MHz
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Q = (sys * P + 47) // 48
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if Q not in mcu.range_q:
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continue
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if not close_int(Q):
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if int(M) == int(hse) and fallback is None:
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# the values don't give 48MHz on PLL48 but are otherwise OK
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fallback = M, N, P, int(Q)
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continue
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# found valid values
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return (M, N, P, Q)
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if fallback is None:
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# the values don't give 48MHz on PLL48 but are otherwise OK
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fallback = M, N, P, Q
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if relax_pll48:
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# might have found values which don't give 48MHz on PLL48
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return fallback
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@ -85,6 +114,7 @@ def compute_pll2(hse, sys, relax_pll48):
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return None
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def compute_derived(hse, pll):
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hse = float(hse) # float for Python 2
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M, N, P, Q = pll
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vco_in = hse / M
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vco_out = hse * N / M
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@ -103,16 +133,16 @@ def verify_pll(hse, pll):
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assert close_int(Q)
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# verify range
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assert 2 <= M <= 63
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assert 192 <= N <= 432
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assert P in (2, 4, 6, 8)
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assert 2 <= Q <= 15
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assert 1 <= vco_in <= 2
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assert 192 <= vco_out <= 432
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assert M in mcu.range_m
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assert N in mcu.range_n
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assert P in mcu.range_p
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assert Q in mcu.range_q
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assert mcu.range_vco_in[0] <= vco_in <= mcu.range_vco_in[-1]
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assert mcu.range_vco_out[0] <= vco_out <= mcu.range_vco_out[-1]
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def compute_pll_table(source_clk, relax_pll48):
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valid_plls = []
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for sysclk in range(2, 217, 2):
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for sysclk in mcu.range_sysclk:
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pll = compute_pll2(source_clk, sysclk, relax_pll48)
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if pll is not None:
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verify_pll(source_clk, pll)
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@ -121,10 +151,34 @@ def compute_pll_table(source_clk, relax_pll48):
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def generate_c_table(hse, valid_plls):
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valid_plls.sort()
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if mcu.range_sysclk[-1] <= 0xff and mcu.range_m[-1] <= 0x3f and mcu.range_p[-1] // 2 - 1 <= 0x3:
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typedef = 'uint16_t'
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sys_mask = 0xff
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m_shift = 10
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m_mask = 0x3f
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p_shift = 8
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p_mask = 0x3
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else:
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typedef = 'uint32_t'
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sys_mask = 0xffff
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m_shift = 24
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m_mask = 0xff
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p_shift = 16
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p_mask = 0xff
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print("#define PLL_FREQ_TABLE_SYS(pll) ((pll) & %d)" % (sys_mask,))
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print("#define PLL_FREQ_TABLE_M(pll) (((pll) >> %d) & %d)" % (m_shift, m_mask))
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print("#define PLL_FREQ_TABLE_P(pll) (((((pll) >> %d) & %d) + 1) * 2)" % (p_shift, p_mask))
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print("typedef %s pll_freq_table_t;" % (typedef,))
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print("// (M, P/2-1, SYS) values for %u MHz source" % hse)
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print("static const uint16_t pll_freq_table[%u] = {" % len(valid_plls))
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print("static const pll_freq_table_t pll_freq_table[%u] = {" % (len(valid_plls),))
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for sys, (M, N, P, Q) in valid_plls:
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print(" (%u << 10) | (%u << 8) | %u," % (M, P // 2 - 1, sys))
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print(" (%u << %u) | (%u << %u) | %u," % (M, m_shift, P // 2 - 1, p_shift, sys), end='')
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if M >= 2:
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vco_in, vco_out, pllck, pll48ck = compute_derived(hse, (M, N, P, Q))
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print(" // M=%u N=%u P=%u Q=%u vco_in=%.2f vco_out=%.2f pll48=%.2f"
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% (M, N, P, Q, vco_in, vco_out, pll48ck), end=''
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)
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print()
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print("};")
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def print_table(hse, valid_plls):
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@ -157,6 +211,7 @@ def search_header_for_hsx_values(filename, vals):
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return vals
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def main():
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global mcu
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global out_format
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# parse input args
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@ -164,7 +219,7 @@ def main():
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argv = sys.argv[1:]
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c_table = False
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relax_pll48 = False
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mcu_series = 'f4'
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hse = None
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hsi = None
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@ -172,14 +227,14 @@ def main():
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if argv[0] == '-c':
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c_table = True
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argv.pop(0)
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elif argv[0] == '--relax-pll48':
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relax_pll48 = True
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elif argv[0] == '-m':
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argv.pop(0)
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mcu_series = argv.pop(0).lower()
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else:
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break
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if len(argv) != 1:
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print("usage: pllvalues.py [-c] <hse in MHz>")
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print("usage: pllvalues.py [-c] [-m <mcu_series>] <hse in MHz>")
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sys.exit(1)
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if argv[0].startswith("file:"):
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@ -194,6 +249,15 @@ def main():
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# HSE given directly as an integer
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hse = int(argv[0])
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# Select MCU parameters
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if mcu_series == 'h7':
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mcu = mcu_h7
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else:
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mcu = mcu_default
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# Relax constraight on PLLQ being 48MHz on F7 and H7 MCUs, which have separate PLLs for 48MHz
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relax_pll48 = mcu_series in ('f7', 'h7')
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hse_valid_plls = compute_pll_table(hse, relax_pll48)
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if hsi is not None:
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hsi_valid_plls = compute_pll_table(hsi, relax_pll48)
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@ -310,6 +310,11 @@ STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) {
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#else
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mp_int_t sysclk = mp_obj_get_int(args[0]);
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mp_int_t ahb = sysclk;
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#if defined (STM32H7)
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if (ahb > 200000000) {
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ahb /= 2;
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}
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#endif
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mp_int_t apb1 = ahb / 4;
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mp_int_t apb2 = ahb / 2;
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if (n_args > 1) {
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@ -93,12 +93,48 @@ void powerctrl_check_enter_bootloader(void) {
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#if !defined(STM32F0) && !defined(STM32L0) && !defined(STM32WB)
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typedef struct _sysclk_scaling_table_entry_t {
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uint16_t mhz;
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uint16_t value;
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} sysclk_scaling_table_entry_t;
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#if defined(STM32F7)
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STATIC const sysclk_scaling_table_entry_t volt_scale_table[] = {
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{ 151, PWR_REGULATOR_VOLTAGE_SCALE3 },
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{ 180, PWR_REGULATOR_VOLTAGE_SCALE2 },
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// Above 180MHz uses default PWR_REGULATOR_VOLTAGE_SCALE1
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};
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#elif defined(STM32H7)
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STATIC const sysclk_scaling_table_entry_t volt_scale_table[] = {
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// See table 55 "Kernel clock distribution overview" of RM0433.
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{200, PWR_REGULATOR_VOLTAGE_SCALE3},
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{300, PWR_REGULATOR_VOLTAGE_SCALE2},
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// Above 300MHz uses default PWR_REGULATOR_VOLTAGE_SCALE1
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// (above 400MHz needs special handling for overdrive, currently unsupported)
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};
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#endif
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STATIC int powerctrl_config_vos(uint32_t sysclk_mhz) {
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#if defined(STM32F7) || defined(STM32H7)
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uint32_t volt_scale = PWR_REGULATOR_VOLTAGE_SCALE1;
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for (int i = 0; i < MP_ARRAY_SIZE(volt_scale_table); ++i) {
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if (sysclk_mhz <= volt_scale_table[i].mhz) {
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volt_scale = volt_scale_table[i].value;
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break;
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}
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}
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if (HAL_PWREx_ControlVoltageScaling(volt_scale) != HAL_OK) {
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return -MP_EIO;
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}
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#endif
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return 0;
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}
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// Assumes that PLL is used as the SYSCLK source
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int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk_mhz, bool need_pllsai) {
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uint32_t flash_latency;
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#if defined(STM32F7)
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if (need_pllsai) {
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// Configure PLLSAI at 48MHz for those peripherals that need this freq
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// (calculation assumes it can get an integral value of PLLSAIN)
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@ -118,20 +154,16 @@ int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk
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}
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RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
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}
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#endif
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// If possible, scale down the internal voltage regulator to save power
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uint32_t volt_scale;
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if (sysclk_mhz <= 151) {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE3;
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} else if (sysclk_mhz <= 180) {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE2;
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} else {
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volt_scale = PWR_REGULATOR_VOLTAGE_SCALE1;
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}
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if (HAL_PWREx_ControlVoltageScaling(volt_scale) != HAL_OK) {
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return -MP_EIO;
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int ret = powerctrl_config_vos(sysclk_mhz);
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if (ret) {
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return ret;
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}
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#if defined(STM32F7)
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// These flash_latency values assume a supply voltage between 2.7V and 3.6V
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if (sysclk_mhz <= 30) {
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flash_latency = FLASH_LATENCY_0;
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@ -172,6 +204,17 @@ int powerctrl_rcc_clock_config_pll(RCC_ClkInitTypeDef *rcc_init, uint32_t sysclk
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#if !defined(STM32F0) && !defined(STM32L0) && !defined(STM32L4) && !defined(STM32WB)
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STATIC uint32_t calc_ahb_div(uint32_t wanted_div) {
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#if defined(STM32H7)
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if (wanted_div <= 1) { return RCC_HCLK_DIV1; }
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else if (wanted_div <= 2) { return RCC_HCLK_DIV2; }
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else if (wanted_div <= 4) { return RCC_HCLK_DIV4; }
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else if (wanted_div <= 8) { return RCC_HCLK_DIV8; }
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else if (wanted_div <= 16) { return RCC_HCLK_DIV16; }
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else if (wanted_div <= 64) { return RCC_HCLK_DIV64; }
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else if (wanted_div <= 128) { return RCC_HCLK_DIV128; }
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else if (wanted_div <= 256) { return RCC_HCLK_DIV256; }
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else { return RCC_HCLK_DIV512; }
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#else
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if (wanted_div <= 1) { return RCC_SYSCLK_DIV1; }
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else if (wanted_div <= 2) { return RCC_SYSCLK_DIV2; }
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else if (wanted_div <= 4) { return RCC_SYSCLK_DIV4; }
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@ -181,14 +224,35 @@ STATIC uint32_t calc_ahb_div(uint32_t wanted_div) {
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else if (wanted_div <= 128) { return RCC_SYSCLK_DIV128; }
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else if (wanted_div <= 256) { return RCC_SYSCLK_DIV256; }
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else { return RCC_SYSCLK_DIV512; }
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#endif
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}
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STATIC uint32_t calc_apb_div(uint32_t wanted_div) {
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STATIC uint32_t calc_apb1_div(uint32_t wanted_div) {
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#if defined(STM32H7)
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if (wanted_div <= 1) { return RCC_APB1_DIV1; }
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else if (wanted_div <= 2) { return RCC_APB1_DIV2; }
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else if (wanted_div <= 4) { return RCC_APB1_DIV4; }
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else if (wanted_div <= 8) { return RCC_APB1_DIV8; }
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else { return RCC_APB1_DIV16; }
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#else
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if (wanted_div <= 1) { return RCC_HCLK_DIV1; }
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else if (wanted_div <= 2) { return RCC_HCLK_DIV2; }
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else if (wanted_div <= 4) { return RCC_HCLK_DIV4; }
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else if (wanted_div <= 8) { return RCC_HCLK_DIV8; }
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else { return RCC_SYSCLK_DIV16; }
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else { return RCC_HCLK_DIV16; }
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#endif
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}
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STATIC uint32_t calc_apb2_div(uint32_t wanted_div) {
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#if defined(STM32H7)
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if (wanted_div <= 1) { return RCC_APB2_DIV1; }
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else if (wanted_div <= 2) { return RCC_APB2_DIV2; }
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else if (wanted_div <= 4) { return RCC_APB2_DIV4; }
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else if (wanted_div <= 8) { return RCC_APB2_DIV8; }
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else { return RCC_APB2_DIV16; }
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#else
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return calc_apb1_div(wanted_div);
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#endif
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}
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int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t apb2) {
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@ -207,11 +271,11 @@ int powerctrl_set_sysclk(uint32_t sysclk, uint32_t ahb, uint32_t apb1, uint32_t
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// Search for a valid PLL configuration that keeps USB at 48MHz
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uint32_t sysclk_mhz = sysclk / 1000000;
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for (const uint16_t *pll = &pll_freq_table[MP_ARRAY_SIZE(pll_freq_table) - 1]; pll >= &pll_freq_table[0]; --pll) {
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uint32_t sys = *pll & 0xff;
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for (const pll_freq_table_t *pll = &pll_freq_table[MP_ARRAY_SIZE(pll_freq_table) - 1]; pll >= &pll_freq_table[0]; --pll) {
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||||
uint32_t sys = PLL_FREQ_TABLE_SYS(*pll);
|
||||
if (sys <= sysclk_mhz) {
|
||||
m = (*pll >> 10) & 0x3f;
|
||||
p = ((*pll >> 7) & 0x6) + 2;
|
||||
m = PLL_FREQ_TABLE_M(*pll);
|
||||
p = PLL_FREQ_TABLE_P(*pll);
|
||||
if (m == 0) {
|
||||
// special entry for using HSI directly
|
||||
sysclk_source = RCC_SYSCLKSOURCE_HSI;
|
||||
@ -259,8 +323,13 @@ set_clk:
|
||||
#if !defined(STM32H7)
|
||||
ahb = sysclk >> AHBPrescTable[RCC_ClkInitStruct.AHBCLKDivider >> RCC_CFGR_HPRE_Pos];
|
||||
#endif
|
||||
RCC_ClkInitStruct.APB1CLKDivider = calc_apb_div(ahb / apb1);
|
||||
RCC_ClkInitStruct.APB2CLKDivider = calc_apb_div(ahb / apb2);
|
||||
RCC_ClkInitStruct.APB1CLKDivider = calc_apb1_div(ahb / apb1);
|
||||
RCC_ClkInitStruct.APB2CLKDivider = calc_apb2_div(ahb / apb2);
|
||||
#if defined(STM32H7)
|
||||
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
||||
#endif
|
||||
|
||||
#if MICROPY_HW_CLK_LAST_FREQ
|
||||
// Save the bus dividers for use later
|
||||
@ -294,6 +363,26 @@ set_clk:
|
||||
RCC_OscInitStruct.PLL.PLLN = n;
|
||||
RCC_OscInitStruct.PLL.PLLP = p;
|
||||
RCC_OscInitStruct.PLL.PLLQ = q;
|
||||
|
||||
#if defined(STM32H7)
|
||||
RCC_OscInitStruct.PLL.PLLR = 0;
|
||||
if (MICROPY_HW_CLK_VALUE / 1000000 <= 2 * m) {
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; // 1-2MHz
|
||||
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 4 * m) {
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; // 2-4MHz
|
||||
} else if (MICROPY_HW_CLK_VALUE / 1000000 <= 8 * m) {
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; // 4-8MHz
|
||||
} else {
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; // 8-16MHz
|
||||
}
|
||||
if (MICROPY_HW_CLK_VALUE / 1000000 * n <= 420 * m) {
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; // 150-420MHz
|
||||
} else {
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; // 192-960MHz
|
||||
}
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
#endif
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return -MP_EIO;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user