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stm32/mpu: Rename MPU_CONFIG_DISABLE to MPU_CONFIG_NOACCESS.

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The existing MPU_CONFIG_DISABLE macro enables the MPU region but disables
all access to it.

The rename is necessary to support an MPU_CONFIG_DISABLE macro that
actually disables the MPU region entirely.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
This commit is contained in:
Angus Gratton 2024-02-21 12:31:11 +11:00 committed by Damien George
parent 5fe99013b6
commit 2345c1a04e
2 changed files with 23 additions and 18 deletions
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7
ports/stm32/mpu.h
View File

@ -37,7 +37,12 @@
#define MPU_REGION_SDRAM1 (MPU_REGION_NUMBER4) #define MPU_REGION_SDRAM1 (MPU_REGION_NUMBER4)
#define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5) #define MPU_REGION_SDRAM2 (MPU_REGION_NUMBER5)
#define MPU_CONFIG_DISABLE(srd, size) ( \ // Attribute value to disable a region entirely, remove it from the MPU
// (i.e. the MPU_REGION_ENABLE bit is unset.)
#define MPU_CONFIG_DISABLE 0
// Configure a region with all access disabled. Can also set a Subregion Disable mask.
#define MPU_CONFIG_NOACCESS(srd, size) ( \
MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \ MPU_INSTRUCTION_ACCESS_DISABLE << MPU_RASR_XN_Pos \
| MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos \ | MPU_REGION_NO_ACCESS << MPU_RASR_AP_Pos \
| MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos \ | MPU_TEX_LEVEL0 << MPU_RASR_TEX_Pos \

34
ports/stm32/qspi.c
View File

@ -68,7 +68,7 @@ static inline void qspi_mpu_disable_all(void) {
// Configure MPU to disable access to entire QSPI region, to prevent CPU // Configure MPU to disable access to entire QSPI region, to prevent CPU
// speculative execution from accessing this region and modifying QSPI registers. // speculative execution from accessing this region and modifying QSPI registers.
uint32_t irq_state = mpu_config_start(); uint32_t irq_state = mpu_config_start();
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x00, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x00, MPU_REGION_SIZE_256MB));
mpu_config_end(irq_state); mpu_config_end(irq_state);
} }
@ -84,30 +84,30 @@ static inline void qspi_mpu_enable_mapped(void) {
// unprivileged or the background region is disabled, the MPU issues a fault. // unprivileged or the background region is disabled, the MPU issues a fault.
uint32_t irq_state = mpu_config_start(); uint32_t irq_state = mpu_config_start();
#if MICROPY_HW_QSPI_MPU_REGION_SIZE > 128 #if MICROPY_HW_QSPI_MPU_REGION_SIZE > 128
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0xFF, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0xFF, MPU_REGION_SIZE_256MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 64 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 64
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_256MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 32 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 32
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_256MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 16 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 16
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 8 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 8
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 4 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 4
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_32MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 2 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 2
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB));
#elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 1 #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 1
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x0F, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB));
mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_16MB)); mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_16MB));
#else #else
mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_256MB)); mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB));
mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x01, MPU_REGION_SIZE_32MB)); mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB));
mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_DISABLE(0x03, MPU_REGION_SIZE_4MB)); mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_4MB));
#endif #endif
mpu_config_end(irq_state); mpu_config_end(irq_state);
} }