mirrors
/
micropython
mirror of https://github.com/micropython/micropython.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

stmhal: Add stm32f401_af.csv, for AF definitions of F401 MCUs.

This commit is contained in:
Damien George 2015-04-18 16:33:53 +01:00
parent 9253e7bdf7
commit 03ec6e4d01
1 changed files with 83 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
stmhal/boards/stm32f401_af.csv Normal file
View File

@ -0,0 +1,83 @@
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM9/TIM10/TIM11,I2C1/I2C2/I2C3,SPI1/SPI2/I2S2/SPI3/I2S3/SPI4,SPI2/I2S2/SPI3/I2S3,SPI3/I2S3/USART1/USART2,USART6,I2C2/I2C3,OTG1_FS,,SDIO,,,,
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,,,,,USART2_CTS,,,,,,,,EVENTOUT,
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,,,,,,,,EVENTOUT,
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,,,,,,,,EVENTOUT,
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,,,,,,EVENTOUT,
PortA,PA4,,,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT,
PortA,PA5,,TIM2_CH1/TIM2_ETR,,,,SPI1_SCK,,,,,,,,,,EVENTOUT,
PortA,PA6,,TIM1_BKIN,TIM3_CH1,,,SPI1_MISO,,,,,,,,,,EVENTOUT,
PortA,PA7,,TIM1_CH1N,TIM3_CH2,,,SPI1_MOSI,,,,,,,,,,EVENTOUT,
PortA,PA8,MCO_1,TIM1_CH1,,,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,,EVENTOUT,
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,,,USART1_TX,,,OTG_FS_VBUS,,,,,EVENTOUT,
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,,,EVENTOUT,
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,USART6_TX,,OTG_FS_DM,,,,,EVENTOUT,
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,USART6_RX,,OTG_FS_DP,,,,,EVENTOUT,
PortA,PA13,JTMS_SWDIO,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA14,JTCK_SWCLK,,,,,,,,,,,,,,,EVENTOUT,
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS,SPI3_NSS/I2S3_WS,,,,,,,,,EVENTOUT,
PortB,PB0,,TIM1_CH2N,TIM3_CH3,,,,,,,,,,,,,EVENTOUT,
PortB,PB1,,TIM1_CH3N,TIM3_CH4,,,,,,,,,,,,,EVENTOUT,
PortB,PB2,,,,,,,,,,,,,,,,EVENTOUT,
PortB,PB3,JTDO_SWO,TIM2_CH2,,,,SPI1_SCK,SPI3_SCK/I2S3_CK,,,I2C2_SDA,,,,,,EVENTOUT,
PortB,PB4,JTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,,I2C3_SDA,,,,,,EVENTOUT,
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,,,,,,,,,EVENTOUT,
PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT,
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT,
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,,,,SDIO_D4,,,EVENTOUT,
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,,,,SDIO_D5,,,EVENTOUT,
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT,
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,,,,,,,,,EVENTOUT,
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,,,,,,,,,EVENTOUT,
PortB,PB14,,TIM1_CH2N,,,,SPI2_MISO,I2S2ext_SD,,,,,,,,,EVENTOUT,
PortB,PB15,RTC_REFIN,TIM1_CH3N,,,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT,
PortC,PC0,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC1,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,,,,,,,,,EVENTOUT,
PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT,
PortC,PC4,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC5,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC6,,,TIM3_CH1,,,I2S2_MCK,,,USART6_TX,,,,SDIO_D6,,,EVENTOUT,
PortC,PC7,,,TIM3_CH2,,,,I2S3_MCK,,USART6_RX,,,,SDIO_D7,,,EVENTOUT,
PortC,PC8,,,TIM3_CH3,,,,,,USART6_CK,,,,SDIO_D0,,,EVENTOUT,
PortC,PC9,MCO_2,,TIM3_CH4,,I2C3_SDA,I2S_CKIN,,,,,,,SDIO_D1,,,EVENTOUT,
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,,,,,,SDIO_D2,,,EVENTOUT,
PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,,,,,,SDIO_D3,,,EVENTOUT,
PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,,,,,,SDIO_CK,,,EVENTOUT,
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD0,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD1,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD2,,,TIM3_ETR,,,,,,,,,,SDIO_CMD,,,EVENTOUT,
PortD,PD3,,,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,,,,EVENTOUT,
PortD,PD4,,,,,,,,USART2_RTS,,,,,,,,EVENTOUT,
PortD,PD5,,,,,,,,USART2_TX,,,,,,,,EVENTOUT,
PortD,PD6,,,,,,SPI3_MOSI/I2S3_SD,,USART2_RX,,,,,,,,EVENTOUT,
PortD,PD7,,,,,,,,USART2_CK,,,,,,,,EVENTOUT,
PortD,PD8,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD9,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD10,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD11,,,,,,,,,,,,,,,,EVENTOUT,
PortD,PD12,,,TIM4_CH1,,,,,,,,,,,,,EVENTOUT,
PortD,PD13,,,TIM4_CH2,,,,,,,,,,,,,EVENTOUT,
PortD,PD14,,,TIM4_CH3,,,,,,,,,,,,,EVENTOUT,
PortD,PD15,,,TIM4_CH4,,,,,,,,,,,,,EVENTOUT,
PortE,PE0,,,TIM4_ETR,,,,,,,,,,,,,EVENTOUT,
PortE,PE1,,TIM1_CH2N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE2,TRACECLK,,,,,SPI4_SCK,,,,,,,,,,EVENTOUT,
PortE,PE3,TRACED0,,,,,,,,,,,,,,,EVENTOUT,
PortE,PE4,TRACED1,,,,,SPI4_NSS,,,,,,,,,,EVENTOUT,
PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,,,,,,,,,,EVENTOUT,
PortE,PE6,TRACED3,,,TIM9_CH2,,SPI4_MOSI,,,,,,,,,,EVENTOUT,
PortE,PE7,,TIM1_ETR,,,,,,,,,,,,,,EVENTOUT,
PortE,PE8,,TIM1_CH1N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE9,,TIM1_CH1,,,,,,,,,,,,,,EVENTOUT,
PortE,PE10,,TIM1_CH2N,,,,,,,,,,,,,,EVENTOUT,
PortE,PE11,,TIM1_CH2,,,,SPI4_NSS,,,,,,,,,,EVENTOUT,
PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK,,,,,,,,,,EVENTOUT,
PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,,,,,,,,,,EVENTOUT,
PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,,,,,,EVENTOUT,
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,,,,EVENTOUT,
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,
1 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
2 SYS_AF TIM1/TIM2 TIM3/TIM4/TIM5 TIM9/TIM10/TIM11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2/SPI3/I2S3/SPI4 SPI2/I2S2/SPI3/I2S3 SPI3/I2S3/USART1/USART2 USART6 I2C2/I2C3 OTG1_FS SDIO
3 PortA PA0 TIM2_CH1/TIM2_ETR TIM5_CH1 USART2_CTS EVENTOUT
4 PortA PA1 TIM2_CH2 TIM5_CH2 USART2_RTS EVENTOUT
5 PortA PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX EVENTOUT
6 PortA PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX EVENTOUT
7 PortA PA4 SPI1_NSS SPI3_NSS/I2S3_WS USART2_CK EVENTOUT
8 PortA PA5 TIM2_CH1/TIM2_ETR SPI1_SCK EVENTOUT
9 PortA PA6 TIM1_BKIN TIM3_CH1 SPI1_MISO EVENTOUT
10 PortA PA7 TIM1_CH1N TIM3_CH2 SPI1_MOSI EVENTOUT
11 PortA PA8 MCO_1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT
12 PortA PA9 TIM1_CH2 I2C3_SMBA USART1_TX OTG_FS_VBUS EVENTOUT
13 PortA PA10 TIM1_CH3 USART1_RX OTG_FS_ID EVENTOUT
14 PortA PA11 TIM1_CH4 USART1_CTS USART6_TX OTG_FS_DM EVENTOUT
15 PortA PA12 TIM1_ETR USART1_RTS USART6_RX OTG_FS_DP EVENTOUT
16 PortA PA13 JTMS_SWDIO EVENTOUT
17 PortA PA14 JTCK_SWCLK EVENTOUT
18 PortA PA15 JTDI TIM2_CH1/TIM2_ETR SPI1_NSS SPI3_NSS/I2S3_WS EVENTOUT
19 PortB PB0 TIM1_CH2N TIM3_CH3 EVENTOUT
20 PortB PB1 TIM1_CH3N TIM3_CH4 EVENTOUT
21 PortB PB2 EVENTOUT
22 PortB PB3 JTDO_SWO TIM2_CH2 SPI1_SCK SPI3_SCK/I2S3_CK I2C2_SDA EVENTOUT
23 PortB PB4 JTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD I2C3_SDA EVENTOUT
24 PortB PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI SPI3_MOSI/I2S3_SD EVENTOUT
25 PortB PB6 TIM4_CH1 I2C1_SCL USART1_TX EVENTOUT
26 PortB PB7 TIM4_CH2 I2C1_SDA USART1_RX EVENTOUT
27 PortB PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL SDIO_D4 EVENTOUT
28 PortB PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/I2S2_WS SDIO_D5 EVENTOUT
29 PortB PB10 TIM2_CH3 I2C2_SCL SPI2_SCK/I2S2_CK EVENTOUT
30 PortB PB12 TIM1_BKIN I2C2_SMBA SPI2_NSS/I2S2_WS EVENTOUT
31 PortB PB13 TIM1_CH1N SPI2_SCK/I2S2_CK EVENTOUT
32 PortB PB14 TIM1_CH2N SPI2_MISO I2S2ext_SD EVENTOUT
33 PortB PB15 RTC_REFIN TIM1_CH3N SPI2_MOSI/I2S2_SD EVENTOUT
34 PortC PC0 EVENTOUT
35 PortC PC1 EVENTOUT
36 PortC PC2 SPI2_MISO I2S2ext_SD EVENTOUT
37 PortC PC3 SPI2_MOSI/I2S2_SD EVENTOUT
38 PortC PC4 EVENTOUT
39 PortC PC5 EVENTOUT
40 PortC PC6 TIM3_CH1 I2S2_MCK USART6_TX SDIO_D6 EVENTOUT
41 PortC PC7 TIM3_CH2 I2S3_MCK USART6_RX SDIO_D7 EVENTOUT
42 PortC PC8 TIM3_CH3 USART6_CK SDIO_D0 EVENTOUT
43 PortC PC9 MCO_2 TIM3_CH4 I2C3_SDA I2S_CKIN SDIO_D1 EVENTOUT
44 PortC PC10 SPI3_SCK/I2S3_CK SDIO_D2 EVENTOUT
45 PortC PC11 I2S3ext_SD SPI3_MISO SDIO_D3 EVENTOUT
46 PortC PC12 SPI3_MOSI/I2S3_SD SDIO_CK EVENTOUT
47 PortC PC13 EVENTOUT
48 PortC PC14 EVENTOUT
49 PortC PC15 EVENTOUT
50 PortD PD0 EVENTOUT
51 PortD PD1 EVENTOUT
52 PortD PD2 TIM3_ETR SDIO_CMD EVENTOUT
53 PortD PD3 SPI2_SCK/I2S2_CK USART2_CTS EVENTOUT
54 PortD PD4 USART2_RTS EVENTOUT
55 PortD PD5 USART2_TX EVENTOUT
56 PortD PD6 SPI3_MOSI/I2S3_SD USART2_RX EVENTOUT
57 PortD PD7 USART2_CK EVENTOUT
58 PortD PD8 EVENTOUT
59 PortD PD9 EVENTOUT
60 PortD PD10 EVENTOUT
61 PortD PD11 EVENTOUT
62 PortD PD12 TIM4_CH1 EVENTOUT
63 PortD PD13 TIM4_CH2 EVENTOUT
64 PortD PD14 TIM4_CH3 EVENTOUT
65 PortD PD15 TIM4_CH4 EVENTOUT
66 PortE PE0 TIM4_ETR EVENTOUT
67 PortE PE1 TIM1_CH2N EVENTOUT
68 PortE PE2 TRACECLK SPI4_SCK EVENTOUT
69 PortE PE3 TRACED0 EVENTOUT
70 PortE PE4 TRACED1 SPI4_NSS EVENTOUT
71 PortE PE5 TRACED2 TIM9_CH1 SPI4_MISO EVENTOUT
72 PortE PE6 TRACED3 TIM9_CH2 SPI4_MOSI EVENTOUT
73 PortE PE7 TIM1_ETR EVENTOUT
74 PortE PE8 TIM1_CH1N EVENTOUT
75 PortE PE9 TIM1_CH1 EVENTOUT
76 PortE PE10 TIM1_CH2N EVENTOUT
77 PortE PE11 TIM1_CH2 SPI4_NSS EVENTOUT
78 PortE PE12 TIM1_CH3N SPI4_SCK EVENTOUT
79 PortE PE13 TIM1_CH3 SPI4_MISO EVENTOUT
80 PortE PE14 TIM1_CH4 SPI4_MOSI EVENTOUT
81 PortE PE15 TIM1_BKIN EVENTOUT
82 PortH PH0 EVENTOUT
83 PortH PH1 EVENTOUT